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BernardXiongBernardXiong
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Merge pull request #2666 from Zero-Free/pm_dev
[pm]add pm example and support for stm32l475-atk-pandora
2 parents c4cd2a1 + 598f2d3 commit 1dd364b

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5 files changed

+309
-44
lines changed

5 files changed

+309
-44
lines changed

‎bsp/stm32/stm32l475-atk-pandora/board/CubeMX_Config/Inc/stm32l4xx_hal_conf.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@
6969
#define HAL_IWDG_MODULE_ENABLED
7070
/*#define HAL_LTDC_MODULE_ENABLED */
7171
/*#define HAL_LCD_MODULE_ENABLED */
72-
/*#define HAL_LPTIM_MODULE_ENABLED */
72+
#define HAL_LPTIM_MODULE_ENABLED
7373
/*#define HAL_NAND_MODULE_ENABLED */
7474
/*#define HAL_NOR_MODULE_ENABLED */
7575
/*#define HAL_OPAMP_MODULE_ENABLED */

‎bsp/stm32/stm32l475-atk-pandora/board/board.c‎

Lines changed: 210 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -10,55 +10,222 @@
1010
* Change Logs:
1111
* Date Author Notes
1212
* 2009-01-05 Bernard first implementation
13+
* 2019-05-09 Zero-Free Adding multiple configurations for system clock frequency
1314
*/
1415

1516
#include <board.h>
17+
#include <rtthread.h>
1618

1719
void SystemClock_Config(void)
1820
{
19-
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
20-
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
21-
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
21+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
22+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
23+
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
2224

23-
/**Initializes the CPU, AHB and APB busses clocks
24-
*/
25-
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
26-
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
27-
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
28-
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
29-
RCC_OscInitStruct.PLL.PLLM = 1;
30-
RCC_OscInitStruct.PLL.PLLN = 20;
31-
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
32-
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
33-
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
34-
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
35-
{
36-
Error_Handler();
37-
}
38-
/**Initializes the CPU, AHB and APB busses clocks
39-
*/
40-
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
41-
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
42-
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
43-
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
44-
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
45-
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
46-
47-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
48-
{
49-
Error_Handler();
50-
}
51-
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_USART2;
52-
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
53-
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
54-
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
55-
{
56-
Error_Handler();
57-
}
58-
/**Configure the main internal regulator output voltage
25+
/**Initializes the CPU, AHB and APB busses clocks
26+
*/
27+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
28+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
29+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
30+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
31+
RCC_OscInitStruct.PLL.PLLM = 1;
32+
RCC_OscInitStruct.PLL.PLLN = 20;
33+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
34+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
35+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
36+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
37+
{
38+
Error_Handler();
39+
}
40+
/**Initializes the CPU, AHB and APB busses clocks
41+
*/
42+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
43+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
44+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
45+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
46+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
47+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
48+
49+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
50+
{
51+
Error_Handler();
52+
}
53+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2;
54+
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
55+
PeriphClkInit.Usart2ClockSelection = RCC_USART2CLKSOURCE_PCLK1;
56+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
57+
{
58+
Error_Handler();
59+
}
60+
/**Configure the main internal regulator output voltage
61+
*/
62+
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
63+
{
64+
Error_Handler();
65+
}
66+
}
67+
68+
#ifdef RT_USING_PM
69+
70+
void SystemClock_MSI_ON(void)
71+
{
72+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
73+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
74+
75+
/* Initializes the CPU, AHB and APB busses clocks */
76+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
77+
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
78+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
79+
{
80+
RT_ASSERT(0);
81+
}
82+
83+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
84+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
85+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
86+
{
87+
Error_Handler();
88+
}
89+
}
90+
91+
void SystemClock_MSI_OFF(void)
92+
{
93+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
94+
95+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
96+
RCC_OscInitStruct.HSIState = RCC_MSI_OFF;
97+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; /* No update on PLL */
98+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
99+
{
100+
Error_Handler();
101+
}
102+
}
103+
104+
void SystemClock_80M(void)
105+
{
106+
RCC_OscInitTypeDef RCC_OscInitStruct;
107+
RCC_ClkInitTypeDef RCC_ClkInitStruct;
108+
109+
/**Initializes the CPU, AHB and APB busses clocks */
110+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
111+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
112+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
113+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
114+
RCC_OscInitStruct.PLL.PLLM = 1;
115+
RCC_OscInitStruct.PLL.PLLN = 20;
116+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
117+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
118+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
119+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
120+
{
121+
Error_Handler();
122+
}
123+
124+
/**Initializes the CPU, AHB and APB busses clocks
125+
*/
126+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
127+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
128+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
129+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
130+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
131+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
132+
133+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
134+
{
135+
Error_Handler();
136+
}
137+
}
138+
139+
void SystemClock_24M(void)
140+
{
141+
RCC_OscInitTypeDef RCC_OscInitStruct;
142+
RCC_ClkInitTypeDef RCC_ClkInitStruct;
143+
144+
/** Initializes the CPU, AHB and APB busses clocks */
145+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
146+
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
147+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
148+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
149+
RCC_OscInitStruct.PLL.PLLM = 1;
150+
RCC_OscInitStruct.PLL.PLLN = 12;
151+
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
152+
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
153+
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV4;
154+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
155+
{
156+
Error_Handler();
157+
}
158+
/** Initializes the CPU, AHB and APB busses clocks */
159+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
160+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
161+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
162+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
163+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
164+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
165+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
166+
{
167+
Error_Handler();
168+
}
169+
}
170+
171+
void SystemClock_2M(void)
172+
{
173+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
174+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
175+
176+
/* MSI is enabled after System reset, update MSI to 2Mhz (RCC_MSIRANGE_5) */
177+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
178+
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
179+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_5;
180+
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
181+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
182+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
183+
{
184+
/* Initialization Error */
185+
Error_Handler();
186+
}
187+
188+
/* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
189+
clocks dividers */
190+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
191+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
192+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
193+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
194+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
195+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
196+
{
197+
/* Initialization Error */
198+
Error_Handler();
199+
}
200+
}
201+
202+
/**
203+
* @brief Configures system clock after wake-up from STOP: enable HSI, PLL
204+
* and select PLL as system clock source.
205+
* @param None
206+
* @retval None
59207
*/
60-
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
61-
{
62-
Error_Handler();
63-
}
208+
void SystemClock_ReConfig(uint8_t mode)
209+
{
210+
SystemClock_MSI_ON();
211+
212+
switch (mode)
213+
{
214+
case PM_RUN_MODE_HIGH_SPEED:
215+
case PM_RUN_MODE_NORMAL_SPEED:
216+
SystemClock_80M();
217+
break;
218+
case PM_RUN_MODE_MEDIUM_SPEED:
219+
SystemClock_24M();
220+
break;
221+
case PM_RUN_MODE_LOW_SPEED:
222+
SystemClock_2M();
223+
break;
224+
default:
225+
break;
226+
}
227+
228+
// SystemClock_MSI_OFF();
64229
}
230+
231+
#endif

‎bsp/stm32/stm32l475-atk-pandora/board/board.h‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,12 @@ extern "C" {
3232
#define HEAP_END STM32_SRAM1_END
3333

3434
void SystemClock_Config(void);
35+
void SystemClock_MSI_ON(void);
36+
void SystemClock_MSI_OFF(void);
37+
void SystemClock_80M(void);
38+
void SystemClock_24M(void);
39+
void SystemClock_2M(void);
40+
void SystemClock_ReConfig(uint8_t mode);
3541

3642
#ifdef __cplusplus
3743
}

‎components/drivers/pm/pm.c‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
static struct rt_pm _pm;
2020
static uint8_t _pm_default_sleep = RT_PM_DEFAULT_SLEEP_MODE;
2121
static struct rt_pm_notify _pm_notify;
22+
static uint8_t _pm_init_flag = 0;
2223

2324
#define RT_PM_TICKLESS_THRESH (2)
2425

@@ -215,6 +216,9 @@ void rt_system_power_manager(void)
215216
{
216217
uint8_t mode;
217218

219+
if (_pm_init_flag == 0)
220+
return;
221+
218222
/* CPU frequency scaling according to the runing mode settings */
219223
_pm_frequency_scaling(&_pm);
220224

@@ -234,6 +238,9 @@ void rt_pm_request(uint8_t mode)
234238
rt_base_t level;
235239
struct rt_pm *pm;
236240

241+
if (_pm_init_flag == 0)
242+
return;
243+
237244
if (mode > (PM_SLEEP_MODE_MAX - 1))
238245
return;
239246

@@ -256,6 +263,9 @@ void rt_pm_release(uint8_t mode)
256263
rt_ubase_t level;
257264
struct rt_pm *pm;
258265

266+
if (_pm_init_flag == 0)
267+
return;
268+
259269
if (mode > (PM_SLEEP_MODE_MAX - 1))
260270
return;
261271

@@ -423,6 +433,9 @@ int rt_pm_run_enter(uint8_t mode)
423433
rt_base_t level;
424434
struct rt_pm *pm;
425435

436+
if (_pm_init_flag == 0)
437+
return -RT_EIO;
438+
426439
if (mode > PM_RUN_MODE_MAX)
427440
return -RT_EINVAL;
428441

@@ -486,6 +499,8 @@ void rt_system_pm_init(const struct rt_pm_ops *ops,
486499

487500
pm->device_pm = RT_NULL;
488501
pm->device_pm_number = 0;
502+
503+
_pm_init_flag = 1;
489504
}
490505

491506
#ifdef RT_USING_FINSH

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