[cpu_cache] fix function replaced by macro

wirano · Rbb666 · commit 2d18f033a496 · 2024-04-19T15:36:08.000+08:00
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c
@@ -17,6 +17,8 @@
 /* The L1-caches on all CortexÂ®-M7s are divided into lines of 32 bytes. */
 #define L1CACHE_LINESIZE_BYTE       (32)
 
+#ifdef RT_USING_CACHE
+
 void rt_hw_cpu_icache_enable(void)
 {
     SCB_EnableICache();
@@ -89,3 +91,6 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
         RT_ASSERT(0);
     }
 }
+
+#endif /* RT_USING_CACHE */
+

Original file line number	Diff line number	Diff line change
`@@ -17,6 +17,8 @@`
`17`	`17`	`/* The L1-caches on all CortexÂ®-M7s are divided into lines of 32 bytes. */`
`18`	`18`	`#define L1CACHE_LINESIZE_BYTE (32)`
`19`	`19`
	`20`	`+#ifdef RT_USING_CACHE`
	`21`	`+`
`20`	`22`	`void rt_hw_cpu_icache_enable(void)`
`21`	`23`	`{`
`22`	`24`	`SCB_EnableICache();`
`@@ -89,3 +91,6 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)`
`89`	`91`	`RT_ASSERT(0);`
`90`	`92`	`}`
`91`	`93`	`}`
	`94`	`+`
	`95`	`+#endif /* RT_USING_CACHE */`
	`96`	`+`