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liangyongxiangliangyongxiang
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[libcpu] add risc-v e310 porting
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‎libcpu/risc-v/e310/SConscript‎

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Import('rtconfig')
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from building import *
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cwd = GetCurrentDir()
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src = Glob('*.c')
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CPPPATH = [cwd]
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if rtconfig.PLATFORM == 'gcc':
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src += Glob('*_gcc.S')
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group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')

‎libcpu/risc-v/e310/context_gcc.S‎

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;/*
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; * File : context_gcc.S
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; * This file is part of RT-Thread RTOS
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; * COPYRIGHT (C) 2018, RT-Thread Development Team
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; *
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; * This program is free software; you can redistribute it and/or modify
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; * it under the terms of the GNU General Public License as published by
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; * the Free Software Foundation; either version 2 of the License, or
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; * (at your option) any later version.
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; *
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; * This program is distributed in the hope that it will be useful,
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; * but WITHOUT ANY WARRANTY; without even the implied warranty of
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; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; * GNU General Public License for more details.
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; *
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; * You should have received a copy of the GNU General Public License along
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; * with this program; if not, write to the Free Software Foundation, Inc.,
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; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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; *
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; * Change Logs:
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; * Date Author Notes
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; * 2017-07-16 zhangjun for hifive1
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; * 2018-05-29 tanek optimize rt_hw_interrupt_*
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; * 2018-05-29 tanek add mie register to context
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; */
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/*
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* rt_base_t rt_hw_interrupt_disable(void);
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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csrrci a0, mstatus, 8
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ret
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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csrw mstatus, a0
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ret
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* a0 --> from
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* a1 --> to
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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/* saved from thread context
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* x1/ra -> sp(0)
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* x1/ra -> sp(1)
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* mstatus.mie -> sp(2)
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* x(i) -> sp(i-4)
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*/
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addi sp, sp, -32 * 4
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sw sp, (a0)
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sw x1, 0 * 4(sp)
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sw x1, 1 * 4(sp)
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csrr a0, mstatus
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andi a0, a0, 8
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beqz a0, save_mpie
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li a0, 0x80
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save_mpie:
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sw a0, 2 * 4(sp)
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sw x4, 4 * 4(sp)
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sw x5, 5 * 4(sp)
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sw x6, 6 * 4(sp)
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sw x7, 7 * 4(sp)
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sw x8, 8 * 4(sp)
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sw x9, 9 * 4(sp)
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sw x10, 10 * 4(sp)
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sw x11, 11 * 4(sp)
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sw x12, 12 * 4(sp)
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sw x13, 13 * 4(sp)
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sw x14, 14 * 4(sp)
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sw x15, 15 * 4(sp)
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sw x16, 16 * 4(sp)
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sw x17, 17 * 4(sp)
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sw x18, 18 * 4(sp)
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sw x19, 19 * 4(sp)
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sw x20, 20 * 4(sp)
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sw x21, 21 * 4(sp)
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sw x22, 22 * 4(sp)
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sw x23, 23 * 4(sp)
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sw x24, 24 * 4(sp)
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sw x25, 25 * 4(sp)
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sw x26, 26 * 4(sp)
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sw x27, 27 * 4(sp)
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sw x28, 28 * 4(sp)
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sw x29, 29 * 4(sp)
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sw x30, 30 * 4(sp)
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sw x31, 31 * 4(sp)
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/* restore to thread context
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* sp(0) -> epc;
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* sp(1) -> ra;
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* sp(i) -> x(i+2)
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*/
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lw sp, (a1)
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/* resw ra to mepc */
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lw a1, 0 * 4(sp)
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csrw mepc, a1
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lw x1, 1 * 4(sp)
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/* force to machin mode(MPP=11) */
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li a1, 0x00001800;
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csrs mstatus, a1
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lw a1, 2 * 4(sp)
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csrs mstatus, a1
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lw x4, 4 * 4(sp)
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lw x5, 5 * 4(sp)
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lw x6, 6 * 4(sp)
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lw x7, 7 * 4(sp)
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lw x8, 8 * 4(sp)
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lw x9, 9 * 4(sp)
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lw x10, 10 * 4(sp)
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lw x11, 11 * 4(sp)
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lw x12, 12 * 4(sp)
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lw x13, 13 * 4(sp)
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lw x14, 14 * 4(sp)
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lw x15, 15 * 4(sp)
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lw x16, 16 * 4(sp)
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lw x17, 17 * 4(sp)
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lw x18, 18 * 4(sp)
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lw x19, 19 * 4(sp)
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lw x20, 20 * 4(sp)
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lw x21, 21 * 4(sp)
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lw x22, 22 * 4(sp)
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lw x23, 23 * 4(sp)
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lw x24, 24 * 4(sp)
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lw x25, 25 * 4(sp)
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lw x26, 26 * 4(sp)
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lw x27, 27 * 4(sp)
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lw x28, 28 * 4(sp)
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lw x29, 29 * 4(sp)
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lw x30, 30 * 4(sp)
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lw x31, 31 * 4(sp)
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addi sp, sp, 32 * 4
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mret
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* a0 --> to
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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lw sp, (a0)
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/* load epc from stack */
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lw a0, 0 * 4(sp)
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csrw mepc, a0
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lw x1, 1 * 4(sp)
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/* load mstatus from stack */
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lw a0, 2 * 4(sp)
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csrw mstatus, a0
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lw x4, 4 * 4(sp)
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lw x5, 5 * 4(sp)
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lw x6, 6 * 4(sp)
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lw x7, 7 * 4(sp)
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lw x8, 8 * 4(sp)
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lw x9, 9 * 4(sp)
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lw x10, 10 * 4(sp)
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lw x11, 11 * 4(sp)
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lw x12, 12 * 4(sp)
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lw x13, 13 * 4(sp)
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lw x14, 14 * 4(sp)
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lw x15, 15 * 4(sp)
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lw x16, 16 * 4(sp)
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lw x17, 17 * 4(sp)
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lw x18, 18 * 4(sp)
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lw x19, 19 * 4(sp)
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lw x20, 20 * 4(sp)
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lw x21, 21 * 4(sp)
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lw x22, 22 * 4(sp)
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lw x23, 23 * 4(sp)
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lw x24, 24 * 4(sp)
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lw x25, 25 * 4(sp)
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lw x26, 26 * 4(sp)
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lw x27, 27 * 4(sp)
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lw x28, 28 * 4(sp)
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lw x29, 29 * 4(sp)
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lw x30, 30 * 4(sp)
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lw x31, 31 * 4(sp)
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addi sp, sp, 32 * 4
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mret
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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*/
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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addi sp, sp, -16
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sw s0, 12(sp)
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sw a0, 8(sp)
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sw a5, 4(sp)
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la a0, rt_thread_switch_interrupt_flag
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lw a5, (a0)
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bnez a5, _reswitch
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li a5, 1
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sw a5, (a0)
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la a5, rt_interrupt_from_thread
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lw a0, 8(sp)
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sw a0, (a5)
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_reswitch:
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la a5, rt_interrupt_to_thread
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sw a1, (a5)
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lw a5, 4(sp)
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lw a0, 8(sp)
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lw s0, 12(sp)
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addi sp, sp, 16
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ret

‎libcpu/risc-v/e310/entry_gcc.S‎

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/*
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* File : context_gcc.S
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2018, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2018-05-29 tanek first implementation
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*/
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.section .text.entry
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.align 2
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.global trap_entry
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trap_entry:
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// save all from thread context
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addi sp, sp, -32 * 4
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sw x1, 1 * 4(sp)
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li t0, 0x80
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sw t0, 2 * 4(sp)
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sw x4, 4 * 4(sp)
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sw x5, 5 * 4(sp)
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sw x6, 6 * 4(sp)
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sw x7, 7 * 4(sp)
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sw x8, 8 * 4(sp)
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sw x9, 9 * 4(sp)
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sw x10, 10 * 4(sp)
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sw x11, 11 * 4(sp)
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sw x12, 12 * 4(sp)
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sw x13, 13 * 4(sp)
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sw x14, 14 * 4(sp)
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sw x15, 15 * 4(sp)
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sw x16, 16 * 4(sp)
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sw x17, 17 * 4(sp)
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sw x18, 18 * 4(sp)
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sw x19, 19 * 4(sp)
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sw x20, 20 * 4(sp)
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sw x21, 21 * 4(sp)
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sw x22, 22 * 4(sp)
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sw x23, 23 * 4(sp)
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sw x24, 24 * 4(sp)
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sw x25, 25 * 4(sp)
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sw x26, 26 * 4(sp)
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sw x27, 27 * 4(sp)
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sw x28, 28 * 4(sp)
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sw x29, 29 * 4(sp)
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sw x30, 30 * 4(sp)
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sw x31, 31 * 4(sp)
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// switch to interrupt stack
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move s0, sp
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la sp, _sp
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// interrupt handle
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call rt_interrupt_enter
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csrr a0, mcause
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csrr a1, mepc
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mv a2, sp
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call handle_trap
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call rt_interrupt_leave
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// switch to from thread stack
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move sp, s0
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// need to switch new thread
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la s0, rt_thread_switch_interrupt_flag
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lw s2, 0(s0)
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beqz s2, spurious_interrupt
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sw zero, 0(s0)
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csrr a0, mepc
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sw a0, 0 * 4(sp)
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la s0, rt_interrupt_from_thread
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lw s1, 0(s0)
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sw sp, 0(s1)
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la s0, rt_interrupt_to_thread
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lw s1, 0(s0)
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lw sp, 0(s1)
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lw a0, 0 * 4(sp)
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csrw mepc, a0
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spurious_interrupt:
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lw x1, 1 * 4(sp)
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// Remain in M-mode after mret
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li t0, 0x00001800
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csrs mstatus, t0
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lw t0, 2 * 4(sp)
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csrs mstatus, t0
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lw x4, 4 * 4(sp)
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lw x5, 5 * 4(sp)
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lw x6, 6 * 4(sp)
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lw x7, 7 * 4(sp)
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lw x8, 8 * 4(sp)
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lw x9, 9 * 4(sp)
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lw x10, 10 * 4(sp)
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lw x11, 11 * 4(sp)
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lw x12, 12 * 4(sp)
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lw x13, 13 * 4(sp)
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lw x14, 14 * 4(sp)
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lw x15, 15 * 4(sp)
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lw x16, 16 * 4(sp)
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lw x17, 17 * 4(sp)
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lw x18, 18 * 4(sp)
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lw x19, 19 * 4(sp)
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lw x20, 20 * 4(sp)
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lw x21, 21 * 4(sp)
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lw x22, 22 * 4(sp)
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lw x23, 23 * 4(sp)
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lw x24, 24 * 4(sp)
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lw x25, 25 * 4(sp)
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lw x26, 26 * 4(sp)
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lw x27, 27 * 4(sp)
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lw x28, 28 * 4(sp)
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lw x29, 29 * 4(sp)
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lw x30, 30 * 4(sp)
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lw x31, 31 * 4(sp)
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addi sp, sp, 32 * 4
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mret
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.weak handle_trap
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handle_trap:
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1:
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j 1b

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