[dm][clk] refactoring the CLK framework

The old CLK is can't link all hardware clock cell in system that the
API of layout such as 'set_parent' can't work as expected.

Some hareware clock cell need some flags to prevent some dangerous behaviors, eg:
When a clock cell is link to the PMU, the SoC will power-down if the cell is
disable.

The new CLK can do it, and make the CLK drivers implemented easier from
TRM/DataSheet.

Signed-off-by: GuEe-GUI <[email protected]>

Author: GuEe-GUI

components/drivers/clk/SConscript

@@ -1,7 +1,6 @@
 from building import *
 
 group = []
-objs = []
 
 if not GetDepend(['RT_USING_CLK']):
     Return('group')
@@ -15,12 +14,7 @@ src = ['clk.c']
 if GetDepend(['RT_USING_OFW']):
     src += ['clk-fixed-rate.c']
 
-group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
 
-for d in list:
-    path = os.path.join(cwd, d)
-    if os.path.isfile(os.path.join(path, 'SConscript')):
-        objs = objs + SConscript(os.path.join(d, 'SConscript'))
-objs = objs + group
+group = DefineGroup('DeviceDrivers', src, depend = [''], CPPPATH = CPPPATH)
 
-Return('objs')
+Return('group')

components/drivers/clk/clk-fixed-rate.c

@@ -6,66 +6,72 @@
  * Change Logs:
  * Date           Author       Notes
  * 2022-11-26     GuEe-GUI     first version
+ * 2024-05-01     GuEe-GUI     update for new clk
  */
 
 #include <rtthread.h>
 #include <rtdevice.h>
 
-#include <drivers/platform.h>
-
-static rt_err_t fixed_clk_ofw_init(struct rt_platform_device *pdev, struct rt_clk_fixed_rate *clk_fixed)
+struct clk_fixed
 {
-    rt_err_t err = RT_EOK;
-    rt_uint32_t rate, accuracy;
-    struct rt_ofw_node *np = pdev->parent.ofw_node;
-    const char *clk_name = np->name;
-
-    if (!rt_ofw_prop_read_u32(np, "clock-frequency", &rate))
-    {
-        rt_ofw_prop_read_u32(np, "clock-accuracy", &accuracy);
-        rt_ofw_prop_read_string(np, "clock-output-names", &clk_name);
+    struct rt_clk_node parent;
 
-        clk_fixed->clk.name = clk_name;
-        clk_fixed->clk.rate = rate;
-        clk_fixed->clk.min_rate = rate;
-        clk_fixed->clk.max_rate = rate;
-        clk_fixed->fixed_rate = rate;
-        clk_fixed->fixed_accuracy = accuracy;
+    struct rt_clk_fixed_rate fcell;
+    struct rt_clk_cell *cells[1];
+};
 
-        rt_ofw_data(np) = &clk_fixed->clk;
-    }
-    else
-    {
-        err = -RT_EIO;
-    }
+static rt_ubase_t fixed_clk_recalc_rate(struct rt_clk_cell *cell, rt_ubase_t parent_rate)
+{
+    struct rt_clk_fixed_rate *fr = rt_container_of(cell, struct rt_clk_fixed_rate, cell);
 
-    return err;
+    return fr->fixed_rate;
 }
 
+static struct rt_clk_ops fixed_clk_ops =
+{
+    .recalc_rate = fixed_clk_recalc_rate,
+};
+
 static rt_err_t fixed_clk_probe(struct rt_platform_device *pdev)
 {
-    rt_err_t err = RT_EOK;
-    struct rt_clk_fixed_rate *clk_fixed = rt_calloc(1, sizeof(*clk_fixed));
+    rt_err_t err;
+    rt_uint32_t val;
+    struct rt_device *dev = &pdev->parent;
+    struct clk_fixed *cf = rt_calloc(1, sizeof(*cf));
 
-    if (clk_fixed)
+    if (!cf)
     {
-        err = fixed_clk_ofw_init(pdev, clk_fixed);
-    }
-    else
-    {
-        err = -RT_ENOMEM;
+        return -RT_ENOMEM;
     }
 
-    if (!err)
+    if ((err = rt_dm_dev_prop_read_u32(dev, "clock-frequency", &val)))
     {
-        err = rt_clk_register(&clk_fixed->clk, RT_NULL);
+        goto _fail;
     }
+    cf->fcell.fixed_rate = val;
+
+    val = 0;
+    rt_dm_dev_prop_read_u32(dev, "clock-accuracy", &val);
+    cf->fcell.fixed_accuracy = val;
 
-    if (err && clk_fixed)
+    rt_dm_dev_prop_read_string(dev, "clock-output-names", &cf->fcell.cell.name);
+
+    cf->parent.dev = dev;
+    cf->parent.cells_nr = 1;
+    cf->parent.cells = cf->cells;
+    cf->cells[0] = &cf->fcell.cell;
+    cf->fcell.cell.ops = &fixed_clk_ops;
+
+    if ((err = rt_clk_register(&cf->parent)))
     {
-        rt_free(clk_fixed);
+        goto _fail;
     }
 
+    return RT_EOK;
+
+_fail:
+    rt_free(cf);
+
     return err;
 }