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+ /* Copyright (c) 2023, Canaan Bright Sight Co., Ltd
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions are met:
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+ * 1. Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * 2. Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in the
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+ * documentation and/or other materials provided with the distribution.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
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+ * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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+ */
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+
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+ #ifndef __SYSCTL_BOOT_H__
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+ #define __SYSCTL_BOOT_H__
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+
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+ #include <stdint.h>
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+ #include <stdbool.h>
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+
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+ typedef struct pll {
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+ volatile uint32_t cfg0 ;
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+ volatile uint32_t cfg1 ;
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+ volatile uint32_t ctl ;
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+ volatile uint32_t state ;
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+ } pll_t ;
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+
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+ /*
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+ * pll related registers see TRM 2.2.4 Table 2-2-8
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+ * soc_glb_rst: see TRM 2.1.4 Table 2-2-1
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+ * Others: see TRM 2.3.4 Table 2-3-2
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+ */
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+ typedef struct sysctl_boot {
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+ pll_t pll [4 ];
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+ volatile uint32_t soc_boot_ctl ; /* 0x40 */
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+ volatile uint32_t reserved0 [7 ]; /* 0x44 0x48 0x4c 0x50 0x54 0x58 0x5c*/
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+ volatile uint32_t soc_glb_rst ; /* 0x60 */
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+ volatile uint32_t soc_rst_tim ; /* 0x64 */
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+ volatile uint32_t soc_slp_tim ; /* 0x68 */
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+ volatile uint32_t soc_slp_ctl ; /* 0x6c */
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+ volatile uint32_t clk_stable_tim ; /* 0x70 */
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+ volatile uint32_t cpu_wakeup_tim ; /* 0x74 */
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+ volatile uint32_t soc_wakeup_src ; /* 0x78 */
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+ volatile uint32_t cpu_wakeup_cfg ; /* 0x7c */
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+ volatile uint32_t timer_pause_ctl ; /* 0x80 */
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+ volatile uint32_t reserved1 [3 ]; /* 0x84 0x88 0x8c */
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+ volatile uint32_t sysctl_int0_raw ; /* 0x90 */
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+ volatile uint32_t sysctl_int0_en ; /* 0x94 */
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+ volatile uint32_t sysctl_int0_state ; /* 0x98 */
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+ volatile uint32_t reserved2 ; /* 0x9c */
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+ volatile uint32_t sysctl_int1_raw ; /* 0xa0 */
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+ volatile uint32_t sysctl_int1_en ; /* 0xa4 */
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+ volatile uint32_t sysctl_int1_state ; /* 0xa8 */
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+ volatile uint32_t reserved3 ; /* 0xac */
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+ volatile uint32_t sysctl_int2_raw ; /* 0xb0 */
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+ volatile uint32_t sysctl_int2_en ; /* 0xb4 */
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+ volatile uint32_t sysctl_int2_state ; /* 0xb8 */
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+ volatile uint32_t reserved4 [17 ]; /* 0xbc 0xc0-0xcc 0xd0-0xdc 0xe0-0xec 0xf0-0xfc*/
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+ volatile uint32_t cpu0_hart_rstvec ; /* 0x100 */
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+ volatile uint32_t cpu1_hart_rstvec ; /* 0x104 */
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+ volatile uint32_t reserved5 [4 ]; /* 0x108 0x10c 0x110 0x114 */
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+ volatile uint32_t soc_sleep_mask ; /* 0x118 */
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+ } sysctl_boot_t ;
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+
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+
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+ /* See TRM 1.4.1 Boot media Selection */
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+ typedef enum
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+ {
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+ SYSCTL_BOOT_NORFLASH = 0 ,
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+ SYSCTL_BOOT_NANDFLASH = 1 ,
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+ SYSCTL_BOOT_EMMC = 2 ,
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+ SYSCTL_BOOT_SDCARD = 3 ,
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+ SYSCTL_BOOT_MAX ,
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+ } sysctl_boot_mode_e ;
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+
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+ sysctl_boot_mode_e sysctl_boot_get_boot_mode (void );
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+ bool sysctl_boot_get_otp_bypass (void );
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+ void sysctl_boot_set_pll_lock (void );
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+ void sysctl_boot_set_spi2axi (void );
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+ void sysctl_boot_reset_soc (void );
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+
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+ int sysctl_boot_read_is_boot_wakeup (void );
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+ void sysctl_boot_soc_sleep_ctl (void );
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+
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+ #endif
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