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BernardXiongBernardXiong
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Merge pull request #3159 from enkiller/pr
[WIP][libcpu][cm33] support cortex-m33
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‎libcpu/arm/cortex-m33/SConscript‎

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# RT-Thread building script for component
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from building import *
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Import('rtconfig')
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cwd = GetCurrentDir()
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src = Glob('*.c') + Glob('*.cpp')
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CPPPATH = [cwd]
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if rtconfig.PLATFORM == 'armcc':
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src += Glob('*_rvds.S')
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if rtconfig.PLATFORM == 'gcc':
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src += Glob('*_init.S')
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src += Glob('*_gcc.S')
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if rtconfig.PLATFORM == 'iar':
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src += Glob('*_iar.S')
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group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH)
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Return('group')

‎libcpu/arm/cortex-m33/context_gcc.S‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2009-10-11 Bernard first version
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* 2012-01-01 aozima support context switch load/store FPU register.
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* 2013-06-18 aozima add restore MSP feature.
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* 2013-06-23 aozima support lazy stack optimized.
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* 2018-07-24 aozima enhancement hard fault exception handler.
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*/
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/**
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* @addtogroup cortex-m4
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*/
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/*@{*/
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.cpu cortex-m4
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.syntax unified
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.thumb
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.text
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.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */
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.equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */
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.equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */
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.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */
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.equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.global rt_hw_interrupt_disable
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.type rt_hw_interrupt_disable, %function
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rt_hw_interrupt_disable:
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MRS r0, PRIMASK
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CPSID I
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BX LR
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.global rt_hw_interrupt_enable
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.type rt_hw_interrupt_enable, %function
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rt_hw_interrupt_enable:
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MSR PRIMASK, r0
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BX LR
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
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* r0 --> from
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* r1 --> to
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*/
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.global rt_hw_context_switch_interrupt
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.type rt_hw_context_switch_interrupt, %function
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.global rt_hw_context_switch
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.type rt_hw_context_switch, %function
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rt_hw_context_switch_interrupt:
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rt_hw_context_switch:
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/* set rt_thread_switch_interrupt_flag to 1 */
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LDR r2, =rt_thread_switch_interrupt_flag
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LDR r3, [r2]
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CMP r3, #1
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BEQ _reswitch
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MOV r3, #1
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STR r3, [r2]
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LDR r2, =rt_interrupt_from_thread /* set rt_interrupt_from_thread */
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STR r0, [r2]
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_reswitch:
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LDR r2, =rt_interrupt_to_thread /* set rt_interrupt_to_thread */
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STR r1, [r2]
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LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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BX LR
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/* r0 --> switch from thread stack
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* r1 --> switch to thread stack
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* psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
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*/
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.global PendSV_Handler
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.type PendSV_Handler, %function
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PendSV_Handler:
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/* disable interrupt to protect context switch */
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MRS r2, PRIMASK
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CPSID I
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/* get rt_thread_switch_interrupt_flag */
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LDR r0, =rt_thread_switch_interrupt_flag /* r0 = &rt_thread_switch_interrupt_flag */
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LDR r1, [r0] /* r1 = *r1 */
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CMP r1, #0x00 /* compare r1 == 0x00 */
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BNE schedule
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MSR PRIMASK, r2 /* if r1 == 0x00, do msr PRIMASK, r2 */
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BX lr /* if r1 == 0x00, do bx lr */
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schedule
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PUSH {r2} /* store interrupt state */
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/* clear rt_thread_switch_interrupt_flag to 0 */
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MOV r1, #0x00 /* r1 = 0x00 */
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STR r1, [r0] /* *r0 = r1 */
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/* skip register save at the first time */
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LDR r0, =rt_interrupt_from_thread /* r0 = &rt_interrupt_from_thread */
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LDR r1, [r0] /* r1 = *r0 */
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CBZ r1, switch_to_thread /* if r1 == 0, goto switch_to_thread */
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/* Whether TrustZone thread stack exists */
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LDR r1, =rt_trustzone_current_context /* r1 = &rt_secure_current_context */
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LDR r1, [r1] /* r1 = *r1 */
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CBZ r1, contex_ns_store /* if r1 == 0, goto contex_ns_store */
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/*call TrustZone fun, Save TrustZone stack */
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STMFD sp!, {r0-r1, lr} /* push register */
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MOV r0, r1 /* r0 = rt_secure_current_context */
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BL rt_trustzone_context_store /* call TrustZone store fun */
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LDMFD sp!, {r0-r1, lr} /* pop register */
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/* check break from TrustZone */
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MOV r2, lr /* r2 = lr */
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TST r2, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */
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BEQ contex_ns_store /* if r2 & 0x40 == 0, goto contex_ns_store */
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/* push PSPLIM CONTROL PSP LR current_context to stack */
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MRS r3, psplim /* r3 = psplim */
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MRS r4, control /* r4 = control */
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MRS r5, psp /* r5 = psp */
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STMFD r5!, {r1-r4} /* push to thread stack */
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/* update from thread stack pointer */
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LDR r0, [r0] /* r0 = rt_thread_switch_interrupt_flag */
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STR r5, [r0] /* *r0 = r5 */
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b switch_to_thread /* goto switch_to_thread */
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contex_ns_store:
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MRS r1, psp /* get from thread stack pointer */
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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TST lr, #0x10 /* if(!EXC_RETURN[4]) */
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VSTMDBEQ r1!, {d8 - d15} /* push FPU register s16~s31 */
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#endif
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STMFD r1!, {r4 - r11} /* push r4 - r11 register */
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LDR r2, =rt_trustzone_current_context /* r2 = &rt_secure_current_context */
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LDR r2, [r2] /* r2 = *r2 */
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MOV r3, lr /* r3 = lr */
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MRS r4, psplim /* r4 = psplim */
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MRS r5, control /* r5 = control */
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STMFD r1!, {r2-r5} /* push to thread stack */
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LDR r0, [r0]
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STR r1, [r0] /* update from thread stack pointer */
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switch_to_thread:
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LDR r1, =rt_interrupt_to_thread
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LDR r1, [r1]
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LDR r1, [r1] /* load thread stack pointer */
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/* update current TrustZone context */
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LDMFD r1!, {r2-r5} /* pop thread stack */
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MSR psplim, r4 /* psplim = r4 */
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MSR control, r5 /* control = r5 */
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MOV lr, r3 /* lr = r3 */
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LDR r6, =rt_trustzone_current_context /* r6 = &rt_secure_current_context */
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STR r2, [r6] /* *r6 = r2 */
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MOV r0, r2 /* r0 = r2 */
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/* Whether TrustZone thread stack exists */
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CBZ r0, contex_ns_load /* if r0 == 0, goto contex_ns_load */
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PUSH {r1, r3} /* push lr, thread_stack */
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BL rt_trustzone_context_load /* call TrustZone load fun */
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POP {r1, r3} /* pop lr, thread_stack */
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MOV lr, r3 /* lr = r1 */
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TST r3, #0x40 /* if EXC_RETURN[6] is 1, TrustZone stack was used */
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BEQ contex_ns_load /* if r1 & 0x40 == 0, goto contex_ns_load */
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B pendsv_exit
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contex_ns_load:
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LDMFD r1!, {r4 - r11} /* pop r4 - r11 register */
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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TST lr, #0x10 /* if(!EXC_RETURN[4]) */
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VLDMIAEQ r1!, {d8 - d15} /* pop FPU register s16~s31 */
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#endif
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pendsv_exit:
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MSR psp, r1 /* update stack pointer */
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/* restore interrupt */
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POP {r2}
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MSR PRIMASK, r2
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BX lr
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/*
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* void rt_hw_context_switch_to(rt_uint32 to);
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* r0 --> to
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*/
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.global rt_hw_context_switch_to
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.type rt_hw_context_switch_to, %function
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rt_hw_context_switch_to:
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LDR r1, =rt_interrupt_to_thread
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STR r0, [r1]
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#if defined (__VFP_FP__) && !defined(__SOFTFP__)
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/* CLEAR CONTROL.FPCA */
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MRS r2, CONTROL /* read */
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BIC r2, #0x04 /* modify */
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MSR CONTROL, r2 /* write-back */
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#endif
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/* set from thread to 0 */
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LDR r1, =rt_interrupt_from_thread
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MOV r0, #0x0
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STR r0, [r1]
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/* set interrupt flag to 1 */
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LDR r1, =rt_thread_switch_interrupt_flag
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MOV r0, #1
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STR r0, [r1]
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/* set the PendSV exception priority */
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LDR r0, =NVIC_SYSPRI2
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LDR r1, =NVIC_PENDSV_PRI
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LDR.W r2, [r0,#0x00] /* read */
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ORR r1,r1,r2 /* modify */
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STR r1, [r0] /* write-back */
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LDR r0, =NVIC_INT_CTRL /* trigger the PendSV exception (causes context switch) */
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LDR r1, =NVIC_PENDSVSET
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STR r1, [r0]
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/* restore MSP */
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LDR r0, =SCB_VTOR
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LDR r0, [r0]
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LDR r0, [r0]
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NOP
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MSR msp, r0
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/* enable interrupts at processor level */
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CPSIE F
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CPSIE I
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/* never reach here! */
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/* compatible with old version */
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.global rt_hw_interrupt_thread_switch
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.type rt_hw_interrupt_thread_switch, %function
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rt_hw_interrupt_thread_switch:
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BX lr
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NOP
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.global HardFault_Handler
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.type HardFault_Handler, %function
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HardFault_Handler:
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/* get current context */
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MRS r0, msp /* get fault context from handler. */
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TST lr, #0x04 /* if(!EXC_RETURN[2]) */
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BEQ get_sp_done
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MRS r0, psp /* get fault context from thread. */
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get_sp_done:
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STMFD r0!, {r4 - r11} /* push r4 - r11 register */
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LDR r2, =rt_trustzone_current_context /* r2 = &rt_secure_current_context */
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LDR r2, [r2] /* r2 = *r2 */
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MOV r3, lr /* r3 = lr */
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MRS r4, psplim /* r4 = psplim */
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MRS r5, control /* r5 = control */
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STMFD r0!, {r2-r5} /* push to thread stack */
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STMFD r0!, {lr} /* push exec_return register */
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TST lr, #0x04 /* if(!EXC_RETURN[2]) */
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BEQ update_msp
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MSR psp, r0 /* update stack pointer to PSP. */
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B update_done
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update_msp:
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MSR msp, r0 /* update stack pointer to MSP. */
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update_done:
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PUSH {LR}
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BL rt_hw_hard_fault_exception
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POP {LR}
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ORR lr, lr, #0x04
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BX lr

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