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[stm32][eth] beautify codes
1 parent c255c49 commit 3cb13b4

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2 files changed

+20
-16
lines changed

2 files changed

+20
-16
lines changed

bsp/stm32/libraries/HAL_Drivers/drv_eth.c

Lines changed: 16 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -41,9 +41,9 @@ struct rt_stm32_eth
4141
/* interface address info, hw address */
4242
rt_uint8_t dev_addr[MAX_ADDR_LEN];
4343
/* ETH_Speed */
44-
uint32_t ETH_Speed;
44+
rt_uint32_t ETH_Speed;
4545
/* ETH_Duplex_Mode */
46-
uint32_t ETH_Mode;
46+
rt_uint32_t ETH_Mode;
4747
};
4848

4949
static ETH_DMADescTypeDef *DMARxDscrTab, *DMATxDscrTab;
@@ -167,8 +167,14 @@ static rt_err_t rt_stm32_eth_control(rt_device_t dev, int cmd, void *args)
167167
{
168168
case NIOCTL_GADDR:
169169
/* get mac address */
170-
if (args) rt_memcpy(args, stm32_eth_device.dev_addr, 6);
171-
else return -RT_ERROR;
170+
if (args)
171+
{
172+
rt_memcpy(args, stm32_eth_device.dev_addr, 6);
173+
}
174+
else
175+
{
176+
return -RT_ERROR;
177+
}
172178
break;
173179

174180
default :
@@ -214,7 +220,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
214220
while ((byteslefttocopy + bufferoffset) > ETH_TX_BUF_SIZE)
215221
{
216222
/* Copy data to Tx buffer*/
217-
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
223+
rt_memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), (ETH_TX_BUF_SIZE - bufferoffset));
218224

219225
/* Point to next descriptor */
220226
DmaTxDesc = (ETH_DMADescTypeDef *)(DmaTxDesc->Buffer2NextDescAddr);
@@ -236,7 +242,7 @@ rt_err_t rt_stm32_eth_tx(rt_device_t dev, struct pbuf *p)
236242
}
237243

238244
/* Copy the remaining bytes */
239-
memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
245+
rt_memcpy((uint8_t *)((uint8_t *)buffer + bufferoffset), (uint8_t *)((uint8_t *)q->payload + payloadoffset), byteslefttocopy);
240246
bufferoffset = bufferoffset + byteslefttocopy;
241247
framelength = framelength + byteslefttocopy;
242248
}
@@ -327,7 +333,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
327333
while ((byteslefttocopy + bufferoffset) > ETH_RX_BUF_SIZE)
328334
{
329335
/* Copy data to pbuf */
330-
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
336+
rt_memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), (ETH_RX_BUF_SIZE - bufferoffset));
331337

332338
/* Point to next descriptor */
333339
dmarxdesc = (ETH_DMADescTypeDef *)(dmarxdesc->Buffer2NextDescAddr);
@@ -338,7 +344,7 @@ struct pbuf *rt_stm32_eth_rx(rt_device_t dev)
338344
bufferoffset = 0;
339345
}
340346
/* Copy remaining data in pbuf */
341-
memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
347+
rt_memcpy((uint8_t *)((uint8_t *)q->payload + payloadoffset), (uint8_t *)((uint8_t *)buffer + bufferoffset), byteslefttocopy);
342348
bufferoffset = bufferoffset + byteslefttocopy;
343349
}
344350
}
@@ -385,7 +391,9 @@ void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth)
385391
rt_err_t result;
386392
result = eth_device_ready(&(stm32_eth_device.parent));
387393
if (result != RT_EOK)
394+
{
388395
LOG_I("RxCpltCallback err = %d", result);
396+
}
389397
}
390398

391399
void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)

bsp/stm32/libraries/HAL_Drivers/drv_eth.h

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -28,13 +28,12 @@
2828

2929
/* The PHY ID one register */
3030
#define PHY_ID1_REG 0x02U
31-
3231
/* The PHY ID two register */
3332
#define PHY_ID2_REG 0x03U
34-
3533
/* The PHY auto-negotiate advertise register */
3634
#define PHY_AUTONEG_ADVERTISE_REG 0x04U
3735

36+
3837
#ifdef PHY_USING_LAN8720A
3938
/* The PHY interrupt source flag register. */
4039
#define PHY_INTERRUPT_FLAG_REG 0x1DU
@@ -51,9 +50,8 @@
5150
#define PHY_Status_SPEED_10M(sr) ((sr) & PHY_10M_MASK)
5251
#define PHY_Status_SPEED_100M(sr) ((sr) & PHY_100M_MASK)
5352
#define PHY_Status_FULL_DUPLEX(sr) ((sr) & PHY_FULL_DUPLEX_MASK)
54-
#endif /* PHY_USING_LAN8720A */
5553

56-
#ifdef PHY_USING_DM9161CEP
54+
#elif defined(PHY_USING_DM9161CEP)
5755
#define PHY_Status_REG 0x11U
5856
#define PHY_10M_MASK ((1<<12) || (1<<13))
5957
#define PHY_100M_MASK ((1<<14) || (1<<15))
@@ -69,9 +67,7 @@
6967
#define PHY_LINK_CHANGE_MASK (1<<9)
7068
#define PHY_INT_MASK 0
7169

72-
#endif /* PHY_USING_DM9161CEP */
73-
74-
#ifdef PHY_USING_DP83848C
70+
#elif defined(PHY_USING_DP83848C)
7571
#define PHY_Status_REG 0x10U
7672
#define PHY_10M_MASK (1<<1)
7773
#define PHY_FULL_DUPLEX_MASK (1<<2)
@@ -87,6 +83,6 @@
8783
/* The PHY interrupt mask register. */
8884
#define PHY_INTERRUPT_MASK_REG 0x12U
8985
#define PHY_INT_MASK (1<<5)
90-
#endif /* PHY_USING_DP83848C */
86+
#endif
9187

9288
#endif /* __DRV_ETH_H__ */

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