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hywingRbb666
hywing
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Rbb666
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[bsp][nxp][mcxa153] add hardware timer driver
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4 files changed

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‎bsp/nxp/mcx/mcxa/Libraries/drivers/drv_hwtimer.c‎

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/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-11-26 hywing the first version.
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*
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*/
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#include <rtthread.h>
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#ifdef BSP_USING_HWTIMER
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#define LOG_TAG "drv.hwtimer"
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#include <drv_log.h>
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#include <rtdevice.h>
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#include "drv_hwtimer.h"
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#include "fsl_ctimer.h"
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enum
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{
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#ifdef BSP_USING_CTIMER0
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TIM0_INDEX,
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#endif
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#ifdef BSP_USING_CTIMER1
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TIM1_INDEX,
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#endif
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#ifdef BSP_USING_CTIMER2
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TIM2_INDEX,
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#endif
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};
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#ifdef BSP_USING_CTIMER0
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#define TIM0_CONFIG \
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{ \
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.tim_handle = CTIMER0, \
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.tim_irqn = CTIMER0_IRQn, \
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.name = "timer0", \
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}
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#endif /* TIM0_CONFIG */
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#ifdef BSP_USING_CTIMER1
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#define TIM1_CONFIG \
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{ \
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.tim_handle = CTIMER1, \
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.tim_irqn = CTIMER1_IRQn, \
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.name = "timer1", \
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}
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#endif /* TIM1_CONFIG */
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#ifdef BSP_USING_CTIMER2
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#define TIM2_CONFIG \
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{ \
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.tim_handle = CTIMER2, \
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.tim_irqn = CTIMER2_IRQn, \
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.name = "timer2", \
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}
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#endif /* TIM2_CONFIG */
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struct mcxa_hwtimer
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{
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rt_hwtimer_t time_device;
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CTIMER_Type* tim_handle;
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enum IRQn tim_irqn;
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char* name;
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};
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static struct mcxa_hwtimer mcxa_hwtimer_obj[] =
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{
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#ifdef BSP_USING_CTIMER0
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TIM0_CONFIG,
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#endif
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#ifdef BSP_USING_CTIMER1
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TIM1_CONFIG,
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#endif
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#ifdef BSP_USING_CTIMER2
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TIM2_CONFIG,
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#endif
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};
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static void NVIC_Configuration(void)
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{
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#ifdef BSP_USING_CTIMER0
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EnableIRQ(CTIMER0_IRQn);
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#endif
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#ifdef BSP_USING_CTIMER1
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EnableIRQ(CTIMER1_IRQn);
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#endif
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#ifdef BSP_USING_CTIMER2
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EnableIRQ(CTIMER2_IRQn);
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#endif
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}
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static rt_err_t mcxa_ctimer_control(rt_hwtimer_t *timer, rt_uint32_t cmd, void *args)
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{
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rt_err_t err = RT_EOK;
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CTIMER_Type *hwtimer_dev;
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hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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uint32_t clk;
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uint32_t pre;
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if(hwtimer_dev == CTIMER0) clk = CLOCK_GetCTimerClkFreq(0U);
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if(hwtimer_dev == CTIMER1) clk = CLOCK_GetCTimerClkFreq(1U);
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if(hwtimer_dev == CTIMER2) clk = CLOCK_GetCTimerClkFreq(2U);
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pre = clk / *((uint32_t *)args) - 1;
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hwtimer_dev->PR = pre;
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}
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break;
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default:
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err = -RT_ENOSYS;
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break;
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}
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return err;
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}
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static rt_uint32_t mcxa_ctimer_count_get(rt_hwtimer_t *timer)
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{
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rt_uint32_t CurrentTimer_Count;
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CTIMER_Type *hwtimer_dev;
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hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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CurrentTimer_Count = hwtimer_dev->TC;
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return CurrentTimer_Count;
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}
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static void mcxa_ctimer_init(rt_hwtimer_t *timer, rt_uint32_t state)
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{
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CTIMER_Type *hwtimer_dev;
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ctimer_config_t cfg;
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hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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/* Use Main clock for some of the Ctimers */
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if(hwtimer_dev == CTIMER0) CLOCK_AttachClk(kFRO_HF_to_CTIMER0);
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if(hwtimer_dev == CTIMER1) CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
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if(hwtimer_dev == CTIMER2) CLOCK_AttachClk(kFRO_HF_to_CTIMER2);
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CTIMER_Init(hwtimer_dev, &cfg);
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if (state == 1)
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{
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NVIC_Configuration();
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CTIMER_GetDefaultConfig(&cfg);
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CTIMER_Init(hwtimer_dev, &cfg);
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}
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}
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static rt_err_t mcxa_ctimer_start(rt_hwtimer_t *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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{
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CTIMER_Type *hwtimer_dev;
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hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
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/* Match Configuration for Channel 0 */
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ctimer_match_config_t matchCfg;
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RT_ASSERT(timer != RT_NULL);
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/* Configuration*/
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matchCfg.enableCounterReset = true;
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matchCfg.enableCounterStop = (mode == HWTIMER_MODE_ONESHOT) ? true : false;;
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matchCfg.matchValue = cnt;
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matchCfg.outControl = kCTIMER_Output_NoAction;
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matchCfg.outPinInitState = false;
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matchCfg.enableInterrupt = true;
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CTIMER_SetupMatch(hwtimer_dev, kCTIMER_Match_1, &matchCfg);
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NVIC_Configuration();
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CTIMER_StartTimer(hwtimer_dev);
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return RT_EOK;
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}
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static void mcxa_ctimer_stop(rt_hwtimer_t *timer)
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{
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CTIMER_Type *hwtimer_dev;
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hwtimer_dev = (CTIMER_Type *)timer->parent.user_data;
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RT_ASSERT(timer != RT_NULL);
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CTIMER_StopTimer(hwtimer_dev);
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}
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static const struct rt_hwtimer_ops mcxa_hwtimer_ops =
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{
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.init = mcxa_ctimer_init,
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.start = mcxa_ctimer_start,
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.stop = mcxa_ctimer_stop,
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.count_get = mcxa_ctimer_count_get,
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.control = mcxa_ctimer_control,
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};
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static const struct rt_hwtimer_info mcxa_hwtimer_info =
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{
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96000000, /* the maximum count frequency can be set */
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6103, /* the minimum count frequency can be set */
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0xFFFFFFFF,
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HWTIMER_CNTMODE_UP,
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};
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int rt_hw_hwtimer_init(void)
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{
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int i = 0;
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int result = RT_EOK;
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for (i = 0; i < sizeof(mcxa_hwtimer_obj) / sizeof(mcxa_hwtimer_obj[0]); i++)
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{
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mcxa_hwtimer_obj[i].time_device.info = &mcxa_hwtimer_info;
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mcxa_hwtimer_obj[i].time_device.ops = &mcxa_hwtimer_ops;
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if (rt_device_hwtimer_register(&mcxa_hwtimer_obj[i].time_device,
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mcxa_hwtimer_obj[i].name, mcxa_hwtimer_obj[i].tim_handle) == RT_EOK)
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{
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LOG_D("%s register success", mcxa_hwtimer_obj[i].name);
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}
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else
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{
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LOG_E("%s register failed", mcxa_hwtimer_obj[i].name);
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result = -RT_ERROR;
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}
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}
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return result;
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}
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INIT_DEVICE_EXPORT(rt_hw_hwtimer_init);
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#ifdef BSP_USING_CTIMER0
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void CTIMER0_IRQHandler(void)
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{
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uint32_t int_stat;
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/* Get Interrupt status flags */
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int_stat = CTIMER_GetStatusFlags(CTIMER0);
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/* Clear the status flags that were set */
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CTIMER_ClearStatusFlags(CTIMER0, int_stat);
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rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM0_INDEX].time_device);
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}
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#endif /* BSP_USING_HWTIMER0 */
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#ifdef BSP_USING_CTIMER1
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void CTIMER1_IRQHandler(void)
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{
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uint32_t int_stat;
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/* Get Interrupt status flags */
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int_stat = CTIMER_GetStatusFlags(CTIMER1);
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/* Clear the status flags that were set */
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CTIMER_ClearStatusFlags(CTIMER1, int_stat);
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rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM1_INDEX].time_device);
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}
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#endif /* BSP_USING_HWTIMER1 */
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#ifdef BSP_USING_CTIMER2
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void CTIMER2_IRQHandler(void)
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{
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uint32_t int_stat;
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/* Get Interrupt status flags */
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int_stat = CTIMER_GetStatusFlags(CTIMER2);
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/* Clear the status flags that were set */
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CTIMER_ClearStatusFlags(CTIMER2, int_stat);
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rt_device_hwtimer_isr(&mcxa_hwtimer_obj[TIM2_INDEX].time_device);
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}
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#endif /* BSP_USING_HWTIMER2 */
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#endif /* BSP_USING_HWTIMER */

‎bsp/nxp/mcx/mcxa/Libraries/drivers/drv_hwtimer.h‎

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/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-11-26 hywing the first version.
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*/
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#ifndef DRV_HWTIMER_H__
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#define DRV_HWTIMER_H__
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int rt_hw_hwtimer_init(void);
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#endif /* __DRV_HWTIMER_H__ */
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‎bsp/nxp/mcx/mcxa/frdm-mcxa153/board/Kconfig‎

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@@ -103,7 +103,7 @@ menu "On-chip Peripheral Drivers"
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menuconfig BSP_USING_HWTIMER
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config BSP_USING_HWTIMER
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bool "Enable Timer"
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bool "Enable Hardware Timer"
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select RT_USING_HWTIMER
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default y
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bool "Enable CIMER1"
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default n
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config BSP_USING_CTIMER3
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bool "Enable CIMER3"
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default n
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config BSP_USING_CTIMER4
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bool "Enable CIMER4"
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config BSP_USING_CTIMER2
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bool "Enable CIMER2"
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default n
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endif
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‎bsp/nxp/mcx/mcxa/frdm-mcxa153/board/MCUX_Config/board/pin_mux.c‎

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@@ -44,8 +44,12 @@ void BOARD_InitPins(void)
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CLOCK_EnableClock(kCLOCK_GateGPIO2);
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CLOCK_EnableClock(kCLOCK_GateGPIO3);
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CLOCK_SetClockDiv(kCLOCK_DivCTIMER0, 1u);
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CLOCK_AttachClk(kFRO_HF_to_CTIMER0);
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CLOCK_SetClockDiv(kCLOCK_DivCTIMER1, 1u);
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CLOCK_AttachClk(kFRO_HF_to_CTIMER1);
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CLOCK_SetClockDiv(kCLOCK_DivCTIMER2, 1u);
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CLOCK_AttachClk(kFRO_HF_to_CTIMER2);
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RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
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RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);

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