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BernardXiongBernardXiong
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Merge pull request #3963 from Dozingfiretruck/master
stm32wb
2 parents b809c02 + 49fb0a9 commit 577f215

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‎.travis.yml‎

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@@ -126,6 +126,7 @@ env:
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- RTT_BSP='stm32/stm32mp157a-st-ev1' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32f20x' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='swm320-lq100' RTT_TOOL_CHAIN='sourcery-arm'
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- RTT_BSP='stm32/stm32wb55-st-nucleo' RTT_TOOL_CHAIN='sourcery-arm'
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# - RTT_BSP='taihu' RTT_TOOL_CHAIN='sourcery-ppc'
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# - RTT_BSP='upd70f3454' # iar
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# - RTT_BSP='x86' # x86

‎bsp/stm32/libraries/HAL_Drivers/SConscript‎

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@@ -82,6 +82,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
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if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32H7']):
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src += ['drv_flash/drv_flash_h7.c']
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if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32WB']):
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src += ['drv_flash/drv_flash_wb.c']
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if GetDepend('RT_USING_HWCRYPTO'):
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src += ['drv_crypto.c']
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‎bsp/stm32/libraries/HAL_Drivers/config/wb/adc_config.h‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-10-14 Dozingfiretruck first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.DMAContinuousRequests = DISABLE, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef BSP_USING_ADC2
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#ifndef ADC2_CONFIG
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#define ADC2_CONFIG \
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{ \
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.Instance = ADC2, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.DMAContinuousRequests = DISABLE, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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}
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#endif /* ADC2_CONFIG */
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#endif /* BSP_USING_ADC2 */
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#ifdef BSP_USING_ADC3
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#ifndef ADC3_CONFIG
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#define ADC3_CONFIG \
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{ \
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.Instance = ADC3, \
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.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
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.Init.Resolution = ADC_RESOLUTION_12B, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.EOCSelection = ADC_EOC_SINGLE_CONV, \
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.Init.LowPowerAutoWait = DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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.Init.DMAContinuousRequests = DISABLE, \
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.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN, \
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}
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#endif /* ADC3_CONFIG */
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#endif /* BSP_USING_ADC3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/wb/dma_config.h‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* Date Author Notes
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* 2020-10-14 Dozingfiretruck first version
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 channel1 */
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/* DMA1 channel2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#if defined(DMAMUX1) /* for L4+ */
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#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
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#else /* for L4 */
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#define SPI1_RX_DMA_REQUEST DMA_REQUEST_1
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#endif /* DMAMUX1 */
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#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
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#endif
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/* DMA1 channel3 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
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#if defined(DMAMUX1) /* for L4+ */
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#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
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#else /* for L4 */
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#define SPI1_TX_DMA_REQUEST DMA_REQUEST_1
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#endif /* DMAMUX1 */
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#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
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#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
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#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
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#define UART3_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART3_RX_DMA_INSTANCE DMA1_Channel3
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#if defined(DMAMUX1) /* for L4+ */
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#define UART3_RX_DMA_REQUEST DMA_REQUEST_USART3_RX
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#else /* for L4 */
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#define UART3_RX_DMA_REQUEST DMA_REQUEST_2
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#endif /* DMAMUX1 */
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#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
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#endif
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/* DMA1 channel4 */
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#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
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#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART1_TX_DMA_INSTANCE DMA1_Channel4
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#if defined(DMAMUX1) /* for L4+ */
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#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
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#else /* for L4 */
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#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
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#endif /* DMAMUX1 */
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#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
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#elif defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
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#if defined(DMAMUX1) /* for L4+ */
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#define SPI2_RX_DMA_REQUEST DMA_REQUEST_SPI2_RX
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#else /* for L4 */
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#define SPI2_RX_DMA_REQUEST DMA_REQUEST_1
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#endif /* DMAMUX1 */
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#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
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#endif
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/* DMA1 channel5 */
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#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART1_RX_DMA_INSTANCE DMA1_Channel5
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#if defined(DMAMUX1) /* for L4+ */
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#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
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#else /* for L4 */
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#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
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#endif /* DMAMUX1 */
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#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
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#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
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#define QSPI_DMA_IRQHandler DMA1_Channel5_IRQHandler
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#define QSPI_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define QSPI_DMA_INSTANCE DMA1_Channel5
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#if defined(DMAMUX1) /* for L4+ */
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#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1
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#else /* for L4 */
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#define QSPI_DMA_REQUEST DMA_REQUEST_5
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#endif /* DMAMUX1 */
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#define QSPI_DMA_IRQ DMA1_Channel5_IRQn
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#elif defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
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#if defined(DMAMUX1) /* for L4+ */
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#define SPI2_TX_DMA_REQUEST DMA_REQUEST_SPI2_TX
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#else /* for L4 */
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#define SPI2_TX_DMA_REQUEST DMA_REQUEST_1
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#endif /* DMAMUX1 */
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#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
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#endif
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/* DMA1 channel6 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHB1ENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Channel6
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#if defined(DMAMUX1) /* for L4+ */
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX
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#else /* for L4 */
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#define UART2_RX_DMA_REQUEST DMA_REQUEST_2
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#endif /* DMAMUX1 */
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#define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn
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#endif
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/* DMA1 channel7 */
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/* DMA2 channel1 */
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#if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE)
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#define UART5_DMA_TX_IRQHandler DMA2_Channel1_IRQHandler
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#define UART5_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define UART5_TX_DMA_INSTANCE DMA2_Channel1
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#if defined(DMAMUX1) /* for L4+ */
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#define UART5_TX_DMA_REQUEST DMA_REQUEST_UART5_TX
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#else /* for L4 */
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#define UART5_TX_DMA_REQUEST DMA_REQUEST_2
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#endif /* DMAMUX1 */
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#define UART5_TX_DMA_IRQ DMA2_Channel1_IRQn
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#endif
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/* DMA2 channel2 */
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#if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE)
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#define UART5_DMA_RX_IRQHandler DMA2_Channel2_IRQHandler
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#define UART5_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define UART5_RX_DMA_INSTANCE DMA2_Channel2
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#if defined(DMAMUX1) /* for L4+ */
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#define UART5_RX_DMA_REQUEST DMA_REQUEST_UART5_RX
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#else /* for L4 */
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#define UART5_RX_DMA_REQUEST DMA_REQUEST_2
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#endif /* DMAMUX1 */
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#define UART5_RX_DMA_IRQ DMA2_Channel2_IRQn
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#endif
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/* DMA2 channel3 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define SPI1_RX_DMA_INSTANCE DMA2_Channel3
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#if defined(DMAMUX1) /* for L4+ */
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#define SPI1_RX_DMA_REQUEST DMA_REQUEST_SPI1_RX
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#else /* for L4 */
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#define SPI1_RX_DMA_REQUEST DMA_REQUEST_4
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#endif /* DMAMUX1 */
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#define SPI1_RX_DMA_IRQ DMA2_Channel3_IRQn
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#endif
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/* DMA2 channel4 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
171+
#define SPI1_DMA_TX_IRQHandler DMA2_Channel4_IRQHandler
172+
#define SPI1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
173+
#define SPI1_TX_DMA_INSTANCE DMA2_Channel4
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#if defined(DMAMUX1) /* for L4+ */
175+
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_SPI1_TX
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#else /* for L4 */
177+
#define SPI1_TX_DMA_REQUEST DMA_REQUEST_4
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#endif /* DMAMUX1 */
179+
#define SPI1_TX_DMA_IRQ DMA2_Channel4_IRQn
180+
#endif
181+
182+
/* DMA2 channel5 */
183+
184+
/* DMA2 channel6 */
185+
#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
186+
#define UART1_DMA_TX_IRQHandler DMA2_Channel6_IRQHandler
187+
#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA2EN
188+
#define UART1_TX_DMA_INSTANCE DMA2_Channel6
189+
#if defined(DMAMUX1) /* for L4+ */
190+
#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX
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#else /* for L4 */
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#define UART1_TX_DMA_REQUEST DMA_REQUEST_2
193+
#endif /* DMAMUX1 */
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#define UART1_TX_DMA_IRQ DMA2_Channel6_IRQn
195+
#endif
196+
197+
/* DMA2 channel7 */
198+
#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
199+
#define UART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler
200+
#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
201+
#define UART1_RX_DMA_INSTANCE DMA2_Channel7
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#if defined(DMAMUX1) /* for L4+ */
203+
#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX
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#else /* for L4 */
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#define UART1_RX_DMA_REQUEST DMA_REQUEST_2
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#endif /* DMAMUX1 */
207+
#define UART1_RX_DMA_IRQ DMA2_Channel7_IRQn
208+
#elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE)
209+
#define QSPI_DMA_IRQHandler DMA2_Channel7_IRQHandler
210+
#define QSPI_DMA_RCC RCC_AHB1ENR_DMA2EN
211+
#define QSPI_DMA_INSTANCE DMA2_Channel7
212+
#if defined(DMAMUX1) /* for L4+ */
213+
#define QSPI_DMA_REQUEST DMA_REQUEST_OCTOSPI1
214+
#else /* for L4 */
215+
#define QSPI_DMA_REQUEST DMA_REQUEST_3
216+
#endif /* DMAMUX1 */
217+
#define QSPI_DMA_IRQ DMA2_Channel7_IRQn
218+
#elif defined(BSP_LPUART1_RX_USING_DMA) && !defined(LPUART1_RX_DMA_INSTANCE)
219+
#define LPUART1_DMA_RX_IRQHandler DMA2_Channel7_IRQHandler
220+
#define LPUART1_RX_DMA_RCC RCC_AHB1ENR_DMA2EN
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#define LPUART1_RX_DMA_INSTANCE DMA2_Channel7
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#if defined(DMAMUX1) /* for L4+ */
223+
#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_LPUART1_RX
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#else /* for L4 */
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#define LPUART1_RX_DMA_REQUEST DMA_REQUEST_4
226+
#endif /* DMAMUX1 */
227+
#define LPUART1_RX_DMA_IRQ DMA2_Channel7_IRQn
228+
#endif
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#ifdef __cplusplus
231+
}
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#endif
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#endif /* __DMA_CONFIG_H__ */

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