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kylepengchnkylepengchn
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[components][drivers][spi]: 基于SPI总线驱动框架添加模拟SPI总线扩展 (#5656)
* add soft-spi * add spi-bit-ops.c/h to components/drivers/spi * add a drv_soft_spi example for gd32303e-eval Signed-off-by: kyle <[email protected]> * Fixed the format and the certificate. Signed-off-by: kyle <[email protected]> * Update the certificate data. Signed-off-by: kyle <[email protected]>
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‎bsp/gd32303e-eval/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -64,6 +64,12 @@ config RT_USING_SPI2
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select RT_USING_SPI
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default n
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config RT_USING_SPI3
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bool "Using SPI2 BUS (software simulation)"
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select RT_USING_SPI
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select RT_USING_SPI_BITOPS
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default n
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config RT_USING_I2C0
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bool "Using I2C0"
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select RT_USING_I2C

‎bsp/gd32303e-eval/drivers/SConscript‎

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@@ -15,7 +15,11 @@ CPPPATH = [cwd]
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# add spi drivers.
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if GetDepend('RT_USING_SPI'):
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src += ['drv_spi.c']
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# add softspi drivers.
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if GetDepend('RT_USING_SPI_BITOPS'):
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src += ['drv_soft_spi.c']
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# add i2c drivers.
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if GetDepend('RT_USING_I2C'):
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src += ['drv_i2c.c']

‎bsp/gd32303e-eval/drivers/drv_soft_spi.c‎

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@@ -0,0 +1,303 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-10-11 kyle first implementation.
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*/
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#include "drv_soft_spi.h"
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#include <board.h>
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#include <rtthread.h>
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#if defined(RT_USING_SPI) && defined(RT_USING_SPI_BITOPS) && defined(RT_USING_PIN)
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#include <rtdevice.h>
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#include "spi-bit-ops.h"
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#define DBG_TAG "drv.SPI"
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#ifdef RT_SPI_DEBUG
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#define DBG_LVL DBG_LOG
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#else
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#define DBG_LVL DBG_WARNING
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#endif
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#include <rtdbg.h>
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#ifndef ITEM_NUM
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#define ITEM_NUM(items) sizeof(items) / sizeof(items[0])
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#endif
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struct gd32_spi_bit_data
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{
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struct
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{
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rcu_periph_enum clk;
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rt_uint32_t port;
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rt_uint32_t pin;
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} sclk, mosi, miso;
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};
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rt_inline FlagStatus GPIO_OUTPUT_BIT_GET(uint32_t gpio_periph, uint32_t pin)
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{
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if((uint32_t)RESET !=(GPIO_OCTL(gpio_periph)&(pin))){
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return SET;
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}else{
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return RESET;
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}
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}
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rt_inline void GPIO_BIT_RESET(uint32_t gpio_periph, uint32_t pin)
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{
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GPIO_BC(gpio_periph) = (uint32_t)pin;
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}
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rt_inline void GPIO_BIT_SET(uint32_t gpio_periph, uint32_t pin)
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{
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GPIO_BOP(gpio_periph) = (uint32_t)pin;
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}
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rt_inline FlagStatus GPIO_INPUT_BIT_GET(uint32_t gpio_periph,uint32_t pin)
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{
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if((uint32_t)RESET != (GPIO_ISTAT(gpio_periph)&(pin))){
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return SET;
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}else{
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return RESET;
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}
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}
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rt_inline void GPIO_INIT(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin)
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{
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uint16_t i;
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uint32_t temp_mode = 0U;
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uint32_t reg = 0U;
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/* GPIO mode configuration */
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temp_mode = (uint32_t)(mode & ((uint32_t)0x0FU));
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/* GPIO speed configuration */
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if(((uint32_t)0x00U) != ((uint32_t)mode & ((uint32_t)0x10U))){
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/* output mode max speed:10MHz,2MHz,50MHz */
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temp_mode |= (uint32_t)speed;
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}
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/* configure the eight low port pins with GPIO_CTL0 */
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for(i = 0U;i < 8U;i++){
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if((1U << i) & pin){
88+
reg = GPIO_CTL0(gpio_periph);
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/* clear the specified pin mode bits */
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reg &= ~GPIO_MODE_MASK(i);
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/* set the specified pin mode bits */
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reg |= GPIO_MODE_SET(i, temp_mode);
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/* set IPD or IPU */
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if(GPIO_MODE_IPD == mode){
97+
/* reset the corresponding OCTL bit */
98+
GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
99+
}else{
100+
/* set the corresponding OCTL bit */
101+
if(GPIO_MODE_IPU == mode){
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GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
103+
}
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}
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/* set GPIO_CTL0 register */
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GPIO_CTL0(gpio_periph) = reg;
107+
}
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}
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/* configure the eight high port pins with GPIO_CTL1 */
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for(i = 8U;i < 16U;i++){
111+
if((1U << i) & pin){
112+
reg = GPIO_CTL1(gpio_periph);
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/* clear the specified pin mode bits */
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reg &= ~GPIO_MODE_MASK(i - 8U);
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/* set the specified pin mode bits */
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reg |= GPIO_MODE_SET(i - 8U, temp_mode);
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/* set IPD or IPU */
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if(GPIO_MODE_IPD == mode){
121+
/* reset the corresponding OCTL bit */
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GPIO_BC(gpio_periph) = (uint32_t)((1U << i) & pin);
123+
}else{
124+
/* set the corresponding OCTL bit */
125+
if(GPIO_MODE_IPU == mode){
126+
GPIO_BOP(gpio_periph) = (uint32_t)((1U << i) & pin);
127+
}
128+
}
129+
/* set GPIO_CTL1 register */
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GPIO_CTL1(gpio_periph) = reg;
131+
}
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}
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}
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#define GPIO_SET_OUTPUT(port, pin) GPIO_INIT(port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, pin)
136+
#define GPIO_SET_INPUT(port, pin) GPIO_INIT(port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, pin)
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static void gpio_tog_sclk(void *data)
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{
141+
struct gd32_spi_bit_data *bd = data;
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if (GPIO_OUTPUT_BIT_GET(bd->sclk.port, bd->sclk.pin) == SET)
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{
145+
GPIO_BIT_RESET(bd->sclk.port, bd->sclk.pin);
146+
}
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else
148+
{
149+
GPIO_BIT_SET(bd->sclk.port, bd->sclk.pin);
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}
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}
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static void gpio_set_sclk(void *data, rt_int32_t state)
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{
155+
struct gd32_spi_bit_data *bd = data;
156+
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if (state)
158+
{
159+
GPIO_BIT_SET(bd->sclk.port, bd->sclk.pin);
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}
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else
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{
163+
GPIO_BIT_RESET(bd->sclk.port, bd->sclk.pin);
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}
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}
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static void gpio_set_mosi(void *data, rt_int32_t state)
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{
169+
struct gd32_spi_bit_data *bd = data;
170+
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if (state)
172+
{
173+
GPIO_BIT_SET(bd->mosi.port, bd->mosi.pin);
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}
175+
else
176+
{
177+
GPIO_BIT_RESET(bd->mosi.port, bd->mosi.pin);
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}
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}
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static void gpio_set_miso(void *data, rt_int32_t state)
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{
183+
struct gd32_spi_bit_data *bd = data;
184+
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if (state)
186+
{
187+
GPIO_BIT_SET(bd->miso.port, bd->miso.pin);
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}
189+
else
190+
{
191+
GPIO_BIT_RESET(bd->miso.port, bd->miso.pin);
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}
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}
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static rt_int32_t gpio_get_sclk(void *data)
196+
{
197+
struct gd32_spi_bit_data *bd = data;
198+
199+
return GPIO_INPUT_BIT_GET(bd->sclk.port, bd->sclk.pin);
200+
}
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static rt_int32_t gpio_get_mosi(void *data)
203+
{
204+
struct gd32_spi_bit_data *bd = data;
205+
206+
return GPIO_INPUT_BIT_GET(bd->mosi.port, bd->mosi.pin);
207+
}
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static rt_int32_t gpio_get_miso(void *data)
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{
211+
struct gd32_spi_bit_data *bd = data;
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213+
return GPIO_INPUT_BIT_GET(bd->miso.port, bd->miso.pin);
214+
}
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static void gpio_dir_mosi(void *data, rt_int32_t state)
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{
218+
struct gd32_spi_bit_data *bd = data;
219+
220+
if (state)
221+
{
222+
GPIO_SET_INPUT(bd->mosi.port, bd->mosi.pin);
223+
}
224+
else
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{
226+
GPIO_SET_OUTPUT(bd->mosi.port, bd->mosi.pin);
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}
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}
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static void gpio_dir_miso(void *data, rt_int32_t state)
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{
232+
struct gd32_spi_bit_data *bd = data;
233+
234+
if (state)
235+
{
236+
GPIO_SET_INPUT(bd->miso.port, bd->miso.pin);
237+
}
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else
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{
240+
GPIO_SET_OUTPUT(bd->miso.port, bd->miso.pin);
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}
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}
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static void gpio_udelay(rt_uint32_t us)
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{
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int i = ((rcu_clock_freq_get(CK_SYS) / 4000000) * us);
247+
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while (i)
249+
{
250+
i--;
251+
}
252+
}
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static void soft_spi_gpio_init(const struct gd32_spi_bit_data *bd)
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{
256+
rcu_periph_clock_enable(bd->sclk.clk);
257+
rcu_periph_clock_enable(bd->mosi.clk);
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rcu_periph_clock_enable(bd->miso.clk);
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gpio_init(bd->sclk.port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, bd->sclk.pin);
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gpio_init(bd->mosi.port, GPIO_MODE_OUT_PP, GPIO_OSPEED_50MHZ, bd->mosi.pin);
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gpio_init(bd->miso.port, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_50MHZ, bd->miso.pin);
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GPIO_BIT_SET(bd->sclk.port, bd->sclk.pin);
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GPIO_BIT_SET(bd->mosi.port, bd->mosi.pin);
266+
GPIO_BIT_SET(bd->miso.port, bd->miso.pin);
267+
}
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int rt_soft_spi_init(void)
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{
271+
int result = 0;
272+
273+
{
274+
static const struct gd32_spi_bit_data spi1_bdata =
275+
{
276+
.sclk = { RCU_GPIOB, GPIOB, GPIO_PIN_13},
277+
.mosi = { RCU_GPIOB, GPIOB, GPIO_PIN_15},
278+
.miso = { RCU_GPIOB, GPIOB, GPIO_PIN_14},
279+
};
280+
static struct rt_spi_bit_ops spi1_bops =
281+
{
282+
.data = (void *)&spi1_bdata,
283+
.tog_sclk = gpio_tog_sclk,
284+
.set_sclk = gpio_set_sclk,
285+
.set_mosi = gpio_set_mosi,
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.set_miso = gpio_set_miso,
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.get_sclk = gpio_get_sclk,
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.get_mosi = gpio_get_mosi,
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.get_miso = gpio_get_miso,
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.dir_mosi = gpio_dir_mosi,
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.dir_miso = gpio_dir_miso,
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.udelay = gpio_udelay,
293+
};
294+
struct rt_spi_bit_obj spi1_obj;
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296+
soft_spi_gpio_init(&spi1_bdata);
297+
rt_spi_bit_add_bus(&spi1_obj, "spi3", &spi1_bops);
298+
}
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300+
return result;
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}
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INIT_BOARD_EXPORT(rt_soft_spi_init);
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#endif

‎bsp/gd32303e-eval/drivers/drv_soft_spi.h‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2021-10-11 kyle first implementation.
9+
*/
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11+
#ifndef __DRV_SOFT_SPI_H__
12+
#define __DRV_SOFT_SPI_H__
13+
14+
#ifdef __cplusplus
15+
extern "C" {
16+
#endif
17+
18+
int rt_soft_spi_init(void);
19+
20+
#ifdef __cplusplus
21+
}
22+
#endif
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#endif // __DRV_SPI_H__

‎components/drivers/Kconfig‎

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -228,7 +228,18 @@ config RT_USING_SPI
228228
bool "Using SPI Bus/Device device drivers"
229229
default n
230230

231-
if RT_USING_SPI
231+
if RT_USING_SPI
232+
config RT_USING_SPI_BITOPS
233+
select RT_USING_PIN
234+
bool "Use GPIO to simulate SPI"
235+
default n
236+
237+
if RT_USING_SPI_BITOPS
238+
config RT_SPI_BITOPS_DEBUG
239+
bool "Use simulate SPI debug message"
240+
default n
241+
endif
242+
232243
config RT_USING_QSPI
233244
bool "Enable QSPI mode"
234245
default n

‎components/drivers/spi/SConscript‎

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Original file line numberDiff line numberDiff line change
@@ -6,6 +6,9 @@ src = ['spi_core.c', 'spi_dev.c']
66
CPPPATH = [cwd, cwd + '/../include']
77
LOCAL_CFLAGS = ''
88

9+
if GetDepend('RT_USING_SPI_BITOPS'):
10+
src += ['spi-bit-ops.c']
11+
912
if GetDepend('RT_USING_QSPI'):
1013
src += ['qspi_core.c']
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