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BernardXiongBernardXiong
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Merge pull request #4294 from Michael0066/ls1b-dev
bsp:ls1b:rework uart driver and fix some bugs to make it work. tested on ls1b dev board
2 parents 17ee3d2 + 97de1e7 commit 6420c27

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21 files changed

+1989
-396
lines changed

21 files changed

+1989
-396
lines changed

‎bsp/ls1bdev/Kconfig‎

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,6 @@ config PKGS_DIR
1616
default "packages"
1717

1818
source "$RTT_DIR/Kconfig"
19-
source "$RTT_DIR/libcpu/mips/common/Kconfig"
2019
source "$PKGS_DIR/Kconfig"
2120

2221
config SOC_LS1B
@@ -25,16 +24,33 @@ config SOC_LS1B
2524
select RT_USING_USER_MAIN
2625
default y
2726

27+
config RT_MEM_SIZE
28+
int "Memory Size (MByte)"
29+
default 256
30+
31+
config RT_OSC_CLK
32+
int "Oscillator Clock (Hz)"
33+
default 25000000
34+
2835
if RT_USING_SERIAL
2936
config RT_USING_UART0
3037
bool "Using RT_USING_UART0"
31-
default y
38+
default n
3239
config RT_USING_UART1
3340
bool "Using RT_USING_UART1"
3441
default n
42+
config RT_USING_UART2
43+
bool "Using RT_USING_UART2"
44+
default n
3545
config RT_USING_UART3
3646
bool "Using RT_USING_UART3"
3747
default n
48+
config RT_USING_UART4
49+
bool "Using RT_USING_UART4"
50+
default n
51+
config RT_USING_UART5
52+
bool "Using RT_USING_UART5"
53+
default y
3854

3955
config RT_UART_RX_BUFFER_SIZE
4056
int "The rx buffer size"

‎bsp/ls1bdev/drivers/board.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
#include <mips_fpu.h>
2020

2121
#include "board.h"
22-
#include "uart.h"
22+
#include "drv_uart.h"
2323
#include "ls1b.h"
2424

2525
#ifdef RT_USING_RTGUI
@@ -84,6 +84,6 @@ void rt_hw_board_init(void)
8484
#ifdef RT_USING_COMPONENTS_INIT
8585
rt_components_board_init();
8686
#endif
87-
87+
rt_kprintf("current sr: 0x%08x\n", read_c0_status());
8888
}
8989
/*@}*/

‎bsp/ls1bdev/drivers/board.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@
1919
void rt_hw_board_init(void);
2020

2121
/* 64M SDRAM */
22-
#define RT_HW_HEAP_END (0x80000000 + 64 * 1024 * 1024)
22+
#define RT_HW_HEAP_END (0x80000000 + RT_MEM_SIZE * 1024 * 1024)
2323
#define CPU_HZ (125 * 1000000)
2424

2525
#endif

‎bsp/ls1bdev/drivers/drv_uart.c‎

Lines changed: 222 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,222 @@
1+
/*
2+
* Copyright (c) 2006-2018, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-05-08 zhuangwei the first version
9+
* 2021-02-02 [email protected] adapt to ls1b
10+
*/
11+
#include <rtthread.h>
12+
#include <rtdevice.h>
13+
#include <rthw.h>
14+
#include "drv_uart.h"
15+
#include "ls1b_pin.h"
16+
#include "ls1b_uart.h"
17+
18+
/* STM32 uart driver */
19+
struct rt_uart_ls1b
20+
{
21+
ls1b_uart_t UARTx;
22+
rt_uint32_t IRQ;
23+
};
24+
25+
static rt_err_t ls1b_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
26+
{
27+
struct rt_uart_ls1b *uart_dev = RT_NULL;
28+
ls1b_uart_info_t uart_info = {0};
29+
30+
RT_ASSERT(serial != RT_NULL);
31+
RT_ASSERT(cfg != RT_NULL);
32+
33+
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
34+
35+
// 初始化串口
36+
uart_info.UARTx = uart_dev->UARTx;
37+
uart_info.baudrate = cfg->baud_rate;
38+
uart_info.rx_enable = TRUE;
39+
uart_init(&uart_info);
40+
41+
return RT_EOK;
42+
43+
}
44+
45+
static rt_err_t ls1b_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
46+
{
47+
struct rt_uart_ls1b *uart_dev = RT_NULL;
48+
49+
RT_ASSERT(serial != RT_NULL);
50+
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
51+
52+
switch (cmd)
53+
{
54+
case RT_DEVICE_CTRL_CLR_INT: /* disable rx irq */
55+
rt_hw_interrupt_mask(uart_dev->IRQ);
56+
break;
57+
58+
case RT_DEVICE_CTRL_SET_INT: /* enable rx irq */
59+
rt_hw_interrupt_umask(uart_dev->IRQ);
60+
break;
61+
62+
default:
63+
break;
64+
}
65+
66+
return RT_EOK;
67+
68+
}
69+
70+
static int ls1b_uart_putc(struct rt_serial_device *serial, char c)
71+
{
72+
struct rt_uart_ls1b *uart_dev = RT_NULL;
73+
74+
RT_ASSERT(serial != RT_NULL);
75+
76+
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
77+
uart_putc(uart_dev->UARTx, c);
78+
79+
return 1;
80+
}
81+
82+
static int ls1b_uart_getc(struct rt_serial_device *serial)
83+
{
84+
struct rt_uart_ls1b *uart_dev = RT_NULL;
85+
86+
RT_ASSERT(serial != RT_NULL);
87+
88+
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
89+
void *uart_base = uart_get_base(uart_dev->UARTx);
90+
91+
if (LSR_RXRDY & reg_read_8(uart_base + LS1B_UART_LSR_OFFSET))
92+
{
93+
return reg_read_8(uart_base + LS1B_UART_DAT_OFFSET);
94+
}
95+
96+
return -1;
97+
}
98+
99+
/* UART interrupt handler */
100+
static void uart_irq_handler(int vector, void *param)
101+
{
102+
struct rt_serial_device *serial = (struct rt_serial_device *)param;
103+
struct rt_uart_ls1b *uart_dev = RT_NULL;
104+
105+
RT_ASSERT(serial != RT_NULL);
106+
107+
uart_dev = (struct rt_uart_ls1b *)serial->parent.user_data;
108+
void *uart_base = uart_get_base(uart_dev->UARTx);
109+
unsigned char iir = reg_read_8(uart_base + LS1B_UART_IIR_OFFSET);
110+
111+
// 判断是否为接收超时或接收到有效数据
112+
if ((IIR_RXTOUT & iir) || (IIR_RXRDY & iir))
113+
{
114+
rt_interrupt_enter();
115+
rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
116+
rt_interrupt_leave();
117+
}
118+
119+
}
120+
121+
static const struct rt_uart_ops ls1b_uart_ops =
122+
{
123+
ls1b_uart_configure,
124+
ls1b_uart_control,
125+
ls1b_uart_putc,
126+
ls1b_uart_getc,
127+
};
128+
129+
130+
#if defined(RT_USING_UART1)
131+
struct rt_uart_ls1b uart1 =
132+
{
133+
LS1B_UART1,
134+
LS1B_UART1_IRQ,
135+
};
136+
struct rt_serial_device serial1;
137+
#endif /* RT_USING_UART1 */
138+
139+
#if defined(RT_USING_UART2)
140+
struct rt_uart_ls1b uart2 =
141+
{
142+
LS1B_UART2,
143+
LS1B_UART2_IRQ,
144+
};
145+
struct rt_serial_device serial2;
146+
#endif /* RT_USING_UART2 */
147+
148+
149+
#if defined(RT_USING_UART3)
150+
struct rt_uart_ls1b uart3 =
151+
{
152+
LS1B_UART3,
153+
LS1B_UART3_IRQ,
154+
};
155+
struct rt_serial_device serial3;
156+
#endif /* RT_USING_UART3 */
157+
158+
#if defined(RT_USING_UART4)
159+
struct rt_uart_ls1b uart4 =
160+
{
161+
LS1B_UART4,
162+
LS1B_UART4_IRQ,
163+
};
164+
struct rt_serial_device serial4;
165+
#endif /* RT_USING_UART4 */
166+
167+
#if defined(RT_USING_UART5)
168+
struct rt_uart_ls1b uart5 =
169+
{
170+
LS1B_UART5,
171+
LS1B_UART5_IRQ,
172+
};
173+
struct rt_serial_device serial5;
174+
#endif /* RT_USING_UART5 */
175+
176+
177+
178+
void rt_hw_uart_init(void)
179+
{
180+
struct rt_uart_ls1b *uart;
181+
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
182+
183+
#ifdef RT_USING_UART5
184+
uart = &uart5;
185+
186+
serial5.ops = &ls1b_uart_ops;
187+
serial5.config = config;
188+
189+
rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial5, "UART5");
190+
191+
/* register UART5 device */
192+
rt_hw_serial_register(&serial5,
193+
"uart5",
194+
//RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
195+
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
196+
uart);
197+
#endif /* RT_USING_UART5 */
198+
199+
200+
#ifdef RT_USING_UART2
201+
uart = &uart2;
202+
203+
serial2.ops = &ls1b_uart_ops;
204+
serial2.config = config;
205+
206+
pin_set_purpose(36, PIN_PURPOSE_OTHER);
207+
pin_set_purpose(37, PIN_PURPOSE_OTHER);
208+
pin_set_remap(36, PIN_REMAP_SECOND);
209+
pin_set_remap(37, PIN_REMAP_SECOND);
210+
211+
rt_hw_interrupt_install(uart->IRQ, uart_irq_handler, &serial2, "UART2");
212+
213+
/* register UART2 device */
214+
rt_hw_serial_register(&serial2,
215+
"uart2",
216+
//RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_DMA_RX,
217+
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
218+
uart);
219+
#endif /* RT_USING_UART2 */
220+
221+
}
222+

‎bsp/ls1bdev/drivers/drv_uart.h‎

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,100 @@
1+
/*
2+
* Copyright (c) 2006-2018, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-05-08 zhuangwei the first version
9+
*/
10+
11+
#ifndef __DRV_UART_H__
12+
#define __DRV_UART_H__
13+
14+
#include "ls1b.h"
15+
#include <rthw.h>
16+
17+
#define DEV_CLK 252000000 // 252MHz
18+
#define UART_BAUDRATE 115200
19+
20+
#define UART0_BASE 0xBFE40000
21+
//#define UART0_1_BASE 0xBFE41000
22+
#define UART1_BASE 0xBFE44000
23+
#define UART2_BASE 0xBFE48000
24+
#define UART3_BASE 0xBFE4C000
25+
#define UART4_BASE 0xBFE4C400
26+
#define UART5_BASE 0xBFE4C500
27+
#define UART6_BASE 0xBFE4C600
28+
#define UART7_BASE 0xBFE4C700
29+
#define UART8_BASE 0xBFE4C800
30+
#define UART9_BASE 0xBFE4C900
31+
#define UART10_BASE 0xBFE4Ca00
32+
#define UART11_BASE 0xBFE4Cb00
33+
34+
/* UART registers */
35+
#define UART_DAT(base) HWREG8(base + 0x00)
36+
#define UART_IER(base) HWREG8(base + 0x01)
37+
#define UART_IIR(base) HWREG8(base + 0x02)
38+
#define UART_FCR(base) HWREG8(base + 0x02)
39+
#define UART_LCR(base) HWREG8(base + 0x03)
40+
#define UART_MCR(base) HWREG8(base + 0x04)
41+
#define UART_LSR(base) HWREG8(base + 0x05)
42+
#define UART_MSR(base) HWREG8(base + 0x06)
43+
44+
#define UART_LSB(base) HWREG8(base + 0x00)
45+
#define UART_MSB(base) HWREG8(base + 0x01)
46+
47+
/* UART0 registers */
48+
#define UART0_DAT HWREG8(UART0_BASE + 0x00)
49+
#define UART0_IER HWREG8(UART0_BASE + 0x01)
50+
#define UART0_IIR HWREG8(UART0_BASE + 0x02)
51+
#define UART0_FCR HWREG8(UART0_BASE + 0x02)
52+
#define UART0_LCR HWREG8(UART0_BASE + 0x03)
53+
#define UART0_MCR HWREG8(UART0_BASE + 0x04)
54+
#define UART0_LSR HWREG8(UART0_BASE + 0x05)
55+
#define UART0_MSR HWREG8(UART0_BASE + 0x06)
56+
57+
#define UART0_LSB HWREG8(UART0_BASE + 0x00)
58+
#define UART0_MSB HWREG8(UART0_BASE + 0x01)
59+
60+
/* UART1 registers */
61+
#define UART1_DAT HWREG8(UART1_BASE + 0x00)
62+
#define UART1_IER HWREG8(UART1_BASE + 0x01)
63+
#define UART1_IIR HWREG8(UART1_BASE + 0x02)
64+
#define UART1_FCR HWREG8(UART1_BASE + 0x02)
65+
#define UART1_LCR HWREG8(UART1_BASE + 0x03)
66+
#define UART1_MCR HWREG8(UART1_BASE + 0x04)
67+
#define UART1_LSR HWREG8(UART1_BASE + 0x05)
68+
#define UART1_MSR HWREG8(UART1_BASE + 0x06)
69+
70+
#define UART1_LSB HWREG8(UART1_BASE + 0x00)
71+
#define UART1_MSB HWREG8(UART1_BASE + 0x01)
72+
73+
/* UART interrupt enable register value */
74+
#define UARTIER_IME (1 << 3)
75+
#define UARTIER_ILE (1 << 2)
76+
#define UARTIER_ITXE (1 << 1)
77+
#define UARTIER_IRXE (1 << 0)
78+
79+
/* UART line control register value */
80+
#define UARTLCR_DLAB (1 << 7)
81+
#define UARTLCR_BCB (1 << 6)
82+
#define UARTLCR_SPB (1 << 5)
83+
#define UARTLCR_EPS (1 << 4)
84+
#define UARTLCR_PE (1 << 3)
85+
#define UARTLCR_SB (1 << 2)
86+
87+
/* UART line status register value */
88+
#define UARTLSR_ERROR (1 << 7)
89+
#define UARTLSR_TE (1 << 6)
90+
#define UARTLSR_TFE (1 << 5)
91+
#define UARTLSR_BI (1 << 4)
92+
#define UARTLSR_FE (1 << 3)
93+
#define UARTLSR_PE (1 << 2)
94+
#define UARTLSR_OE (1 << 1)
95+
#define UARTLSR_DR (1 << 0)
96+
97+
void rt_hw_uart_init(void);
98+
99+
100+
#endif

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