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[bsp][renesas][ra4m1-ek] bsp code format
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-5132
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112 files changed

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‎bsp/renesas/ra4m1-ek/board/board.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2021, RT-Thread Development Team
2+
* Copyright (c) 2006-2025 RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -35,4 +35,4 @@ extern int __ddsc_RAM_END;
3535
}
3636
#endif
3737

38-
#endif
38+
#endif

‎bsp/renesas/ra4m1-ek/board/ports/fal_cfg.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2024, RT-Thread Development Team
2+
* Copyright (c) 2006-2025 RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -28,4 +28,4 @@ extern const struct fal_flash_dev _onchip_flash_lp;
2828
{FAL_PART_MAGIC_WROD, "app", "onchip_flash_lp", 128*1024, 128*1024, 0}, \
2929
}
3030
#endif /* FAL_PART_HAS_TABLE_CFG */
31-
#endif /* _FAL_CFG_H_ */
31+
#endif /* _FAL_CFG_H_ */

‎bsp/renesas/ra4m1-ek/board/ports/gpio_cfg.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2021, RT-Thread Development Team
2+
* Copyright (c) 2006-2025 RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/renesas/ra4m1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -258,9 +258,9 @@ __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
258258
uint32_t result;
259259
__ASM volatile(
260260
"MRS %0, cpsr \n"
261-
"CPS #0x1F \n" // no effect in USR mode
261+
"CPS #0x1F \n" /* no effect in USR mode*/
262262
"MOV %1, sp \n"
263-
"MSR cpsr_c, %0 \n" // no effect in USR mode
263+
"MSR cpsr_c, %0 \n" /* no effect in USR mode*/
264264
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
265265
);
266266
return result;
@@ -274,9 +274,9 @@ __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
274274
uint32_t cpsr;
275275
__ASM volatile(
276276
"MRS %0, cpsr \n"
277-
"CPS #0x1F \n" // no effect in USR mode
277+
"CPS #0x1F \n" /* no effect in USR mode*/
278278
"MOV sp, %1 \n"
279-
"MSR cpsr_c, %0 \n" // no effect in USR mode
279+
"MSR cpsr_c, %0 \n" /* no effect in USR mode*/
280280
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
281281
);
282282
}
@@ -326,23 +326,23 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
326326
__STATIC_INLINE void __FPU_Enable(void)
327327
{
328328
__ASM volatile(
329-
// Permit access to VFP/NEON, registers by modifying CPACR
329+
/* Permit access to VFP/NEON, registers by modifying CPACR*/
330330
" MRC p15,0,R1,c1,c0,2 \n"
331331
" ORR R1,R1,#0x00F00000 \n"
332332
" MCR p15,0,R1,c1,c0,2 \n"
333333

334-
// Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
334+
/* Ensure that subsequent instructions occur in the context of VFP/NEON access permitted*/
335335
" ISB \n"
336336

337-
// Enable VFP/NEON
337+
/* Enable VFP/NEON*/
338338
" VMRS R1,FPEXC \n"
339339
" ORR R1,R1,#0x40000000 \n"
340340
" VMSR FPEXC,R1 \n"
341341

342-
// Initialise VFP/NEON registers to 0
342+
/* Initialise VFP/NEON registers to 0*/
343343
" MOV R2,#0 \n"
344344

345-
// Initialise D16 registers to 0
345+
/* Initialise D16 registers to 0*/
346346
" VMOV D0, R2,R2 \n"
347347
" VMOV D1, R2,R2 \n"
348348
" VMOV D2, R2,R2 \n"
@@ -361,7 +361,7 @@ __STATIC_INLINE void __FPU_Enable(void)
361361
" VMOV D15,R2,R2 \n"
362362

363363
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
364-
// Initialise D32 registers to 0
364+
/* Initialise D32 registers to 0*/
365365
" VMOV D16,R2,R2 \n"
366366
" VMOV D17,R2,R2 \n"
367367
" VMOV D18,R2,R2 \n"
@@ -380,9 +380,9 @@ __STATIC_INLINE void __FPU_Enable(void)
380380
" VMOV D31,R2,R2 \n"
381381
#endif
382382

383-
// Initialise FPSCR to a known state
383+
/* Initialise FPSCR to a known state*/
384384
" VMRS R1,FPSCR \n"
385-
" LDR R2,=0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
385+
" LDR R2,=0x00086060 \n" /*Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.*/
386386
" AND R1,R1,R2 \n"
387387
" VMSR FPSCR,R1 "
388388
: : : "cc", "r1", "r2"

‎bsp/renesas/ra4m1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -254,9 +254,9 @@ __STATIC_FORCEINLINE uint32_t __get_SP_usr(void)
254254
uint32_t result;
255255
__ASM volatile(
256256
"MRS %0, cpsr \n"
257-
"CPS #0x1F \n" // no effect in USR mode
257+
"CPS #0x1F \n" /* no effect in USR mode*/
258258
"MOV %1, sp \n"
259-
"MSR cpsr_c, %0 \n" // no effect in USR mode
259+
"MSR cpsr_c, %0 \n" /* no effect in USR mode*/
260260
"ISB" : "=r"(cpsr), "=r"(result) : : "memory"
261261
);
262262
return result;
@@ -270,9 +270,9 @@ __STATIC_FORCEINLINE void __set_SP_usr(uint32_t topOfProcStack)
270270
uint32_t cpsr;
271271
__ASM volatile(
272272
"MRS %0, cpsr \n"
273-
"CPS #0x1F \n" // no effect in USR mode
273+
"CPS #0x1F \n" /* no effect in USR mode*/
274274
"MOV sp, %1 \n"
275-
"MSR cpsr_c, %0 \n" // no effect in USR mode
275+
"MSR cpsr_c, %0 \n" /* no effect in USR mode*/
276276
"ISB" : "=r"(cpsr) : "r" (topOfProcStack) : "memory"
277277
);
278278
}
@@ -321,20 +321,20 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
321321
*/
322322
__STATIC_INLINE void __FPU_Enable(void)
323323
{
324-
// Permit access to VFP/NEON, registers by modifying CPACR
324+
/* Permit access to VFP/NEON, registers by modifying CPACR*/
325325
const uint32_t cpacr = __get_CPACR();
326326
__set_CPACR(cpacr | 0x00F00000ul);
327327
__ISB();
328328

329-
// Enable VFP/NEON
329+
/* Enable VFP/NEON*/
330330
const uint32_t fpexc = __get_FPEXC();
331331
__set_FPEXC(fpexc | 0x40000000ul);
332332

333333
__ASM volatile(
334-
// Initialise VFP/NEON registers to 0
334+
/* Initialise VFP/NEON registers to 0*/
335335
" MOV R2,#0 \n"
336336

337-
// Initialise D16 registers to 0
337+
/* Initialise D16 registers to 0*/
338338
" VMOV D0, R2,R2 \n"
339339
" VMOV D1, R2,R2 \n"
340340
" VMOV D2, R2,R2 \n"
@@ -353,7 +353,7 @@ __STATIC_INLINE void __FPU_Enable(void)
353353
" VMOV D15,R2,R2 \n"
354354

355355
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
356-
// Initialise D32 registers to 0
356+
/* Initialise D32 registers to 0*/
357357
" VMOV D16,R2,R2 \n"
358358
" VMOV D17,R2,R2 \n"
359359
" VMOV D18,R2,R2 \n"
@@ -374,7 +374,7 @@ __STATIC_INLINE void __FPU_Enable(void)
374374
: : : "cc", "r2"
375375
);
376376

377-
// Initialise FPSCR to a known state
377+
/* Initialise FPSCR to a known state*/
378378
const uint32_t fpscr = __get_FPSCR();
379379
__set_FPSCR(fpscr & 0x00086060ul);
380380
}

‎bsp/renesas/ra4m1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -158,20 +158,20 @@ __STATIC_FORCEINLINE void __set_FPEXC(uint32_t fpexc)
158158
*/
159159
__STATIC_INLINE void __FPU_Enable(void)
160160
{
161-
// Permit access to VFP/NEON, registers by modifying CPACR
161+
/* Permit access to VFP/NEON, registers by modifying CPACR*/
162162
const uint32_t cpacr = __get_CPACR();
163163
__set_CPACR(cpacr | 0x00F00000ul);
164164
__ISB();
165165

166-
// Enable VFP/NEON
166+
/* Enable VFP/NEON*/
167167
const uint32_t fpexc = __get_FPEXC();
168168
__set_FPEXC(fpexc | 0x40000000ul);
169169

170170
__ASM volatile(
171-
// Initialise VFP/NEON registers to 0
171+
/* Initialise VFP/NEON registers to 0*/
172172
" MOV R2,#0 \n"
173173

174-
// Initialise D16 registers to 0
174+
/* Initialise D16 registers to 0*/
175175
" VMOV D0, R2,R2 \n"
176176
" VMOV D1, R2,R2 \n"
177177
" VMOV D2, R2,R2 \n"
@@ -190,7 +190,7 @@ __STATIC_INLINE void __FPU_Enable(void)
190190
" VMOV D15,R2,R2 \n"
191191

192192
#if (defined(__ARM_NEON) && (__ARM_NEON == 1))
193-
// Initialise D32 registers to 0
193+
/* Initialise D32 registers to 0*/
194194
" VMOV D16,R2,R2 \n"
195195
" VMOV D17,R2,R2 \n"
196196
" VMOV D18,R2,R2 \n"
@@ -211,7 +211,7 @@ __STATIC_INLINE void __FPU_Enable(void)
211211
: : : "cc", "r2"
212212
);
213213

214-
// Initialise FPSCR to a known state
214+
/* Initialise FPSCR to a known state*/
215215
const uint32_t fpscr = __get_FPSCR();
216216
__set_FPSCR(fpscr & 0x00086060ul);
217217
}

‎bsp/renesas/ra4m1-ek/ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -458,9 +458,9 @@ __IAR_FT uint32_t __get_SP_usr(void)
458458
uint32_t result;
459459
__ASM volatile(
460460
"MRS %0, cpsr \n"
461-
"CPS #0x1F \n" // no effect in USR mode
461+
"CPS #0x1F \n" /* no effect in USR mode*/
462462
"MOV %1, sp \n"
463-
"MSR cpsr_c, %2 \n" // no effect in USR mode
463+
"MSR cpsr_c, %2 \n" /* no effect in USR mode*/
464464
"ISB" : "=r"(cpsr), "=r"(result) : "r"(cpsr) : "memory"
465465
);
466466
return result;
@@ -471,9 +471,9 @@ __IAR_FT void __set_SP_usr(uint32_t topOfProcStack)
471471
uint32_t cpsr;
472472
__ASM volatile(
473473
"MRS %0, cpsr \n"
474-
"CPS #0x1F \n" // no effect in USR mode
474+
"CPS #0x1F \n" /* no effect in USR mode*/
475475
"MOV sp, %1 \n"
476-
"MSR cpsr_c, %2 \n" // no effect in USR mode
476+
"MSR cpsr_c, %2 \n" /* no effect in USR mode*/
477477
"ISB" : "=r"(cpsr) : "r" (topOfProcStack), "r"(cpsr) : "memory"
478478
);
479479
}
@@ -484,23 +484,23 @@ __STATIC_INLINE
484484
void __FPU_Enable(void)
485485
{
486486
__ASM volatile(
487-
//Permit access to VFP/NEON, registers by modifying CPACR
487+
/*Permit access to VFP/NEON, registers by modifying CPACR*/
488488
" MRC p15,0,R1,c1,c0,2 \n"
489489
" ORR R1,R1,#0x00F00000 \n"
490490
" MCR p15,0,R1,c1,c0,2 \n"
491491

492-
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
492+
/*Ensure that subsequent instructions occur in the context of VFP/NEON access permitted*/
493493
" ISB \n"
494494

495-
//Enable VFP/NEON
495+
/*Enable VFP/NEON*/
496496
" VMRS R1,FPEXC \n"
497497
" ORR R1,R1,#0x40000000 \n"
498498
" VMSR FPEXC,R1 \n"
499499

500-
//Initialise VFP/NEON registers to 0
500+
/*Initialise VFP/NEON registers to 0*/
501501
" MOV R2,#0 \n"
502502

503-
//Initialise D16 registers to 0
503+
/*Initialise D16 registers to 0*/
504504
" VMOV D0, R2,R2 \n"
505505
" VMOV D1, R2,R2 \n"
506506
" VMOV D2, R2,R2 \n"
@@ -519,7 +519,7 @@ void __FPU_Enable(void)
519519
" VMOV D15,R2,R2 \n"
520520

521521
#ifdef __ARM_ADVANCED_SIMD__
522-
//Initialise D32 registers to 0
522+
/*Initialise D32 registers to 0*/
523523
" VMOV D16,R2,R2 \n"
524524
" VMOV D17,R2,R2 \n"
525525
" VMOV D18,R2,R2 \n"
@@ -538,9 +538,9 @@ void __FPU_Enable(void)
538538
" VMOV D31,R2,R2 \n"
539539
#endif
540540

541-
//Initialise FPSCR to a known state
541+
/*Initialise FPSCR to a known state*/
542542
" VMRS R1,FPSCR \n"
543-
" MOV32 R2,#0x00086060 \n" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
543+
" MOV32 R2,#0x00086060 \n" /*Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.*/
544544
" AND R1,R1,R2 \n"
545545
" VMSR FPSCR,R1 \n"
546546
: : : "cc", "r1", "r2"

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