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33 | 33 | #include "io.h" |
34 | 34 | #include <assert.h> |
35 | 35 |
|
36 | | -#define MX6UL_PAD_UART1_TX_DATA__UART1_TX1 (IOMUXC_BASE_ADDR+0x084) |
37 | | -#define MX6UL_PAD_UART1_RX_DATA__UART1_RX1 (IOMUXC_BASE_ADDR+0x088) |
| 36 | +#define MX6UL_PAD_UART1_TX_DATA__UART1_TX1 (IOMUXC_BASE_ADDR+0x084) |
| 37 | +#define MX6UL_PAD_UART1_RX_DATA__UART1_RX1 (IOMUXC_BASE_ADDR+0x088) |
38 | 38 | #define IOMUXC_UART1_UART_RXD_MUX_SELECT_INPUT1 (IOMUXC_BASE_ADDR+0x624) |
39 | 39 |
|
40 | 40 | #define PIN_CFG(mux_ctl_offset, pad_ctl_offset, select_input_offset, mux_mode, daisy, pad_setting) \ |
41 | | - do {\ |
42 | | - writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\ |
43 | | - if (select_input_offset != 0)\ |
44 | | - writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\ |
45 | | - writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\ |
46 | | - } while(0); |
| 41 | + do {\ |
| 42 | + writel(mux_mode, IOMUXC_BASE_ADDR + mux_ctl_offset);\ |
| 43 | + if (select_input_offset != 0)\ |
| 44 | + writel(daisy, IOMUXC_BASE_ADDR + select_input_offset);\ |
| 45 | + writel(pad_setting, IOMUXC_BASE_ADDR + pad_ctl_offset);\ |
| 46 | + } while(0); |
47 | 47 |
|
48 | 48 | #define MX6UL_PAD_UART1_TX_DATA__UART1_TX(p) PIN_CFG(0x0084, 0x0310, 0x0624, 0x0, 0x2, p) |
49 | 49 | #define MX6UL_PAD_UART1_RX_DATA__UART1_RX(p) PIN_CFG(0x0088, 0x0314, 0x0624, 0x0, 0x3, p) |
@@ -108,11 +108,11 @@ void uart_iomux_config(int instance) |
108 | 108 | return uart5_iomux_config(); |
109 | 109 |
|
110 | 110 | case HW_UART7: |
111 | | - return uart5_iomux_config(); |
| 111 | + return uart5_iomux_config(); |
112 | 112 |
|
113 | 113 | case HW_UART8: |
114 | | - return uart5_iomux_config(); |
115 | | - |
| 114 | + return uart5_iomux_config(); |
| 115 | + |
116 | 116 | default: |
117 | 117 | assert(false); |
118 | 118 | } |
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