bsp:

add support to zynqmp-r5 core and zynqmp-r5-axu4ev board

Author: Wang-Huachen

bsp/zynqmp-r5-axu4ev/.config

@@ -0,0 +1,27 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+
+config SOC_ZYNQMP_R5
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    default y
+
+source "$BSP_DIR/drivers/Kconfig"

bsp/zynqmp-r5-axu4ev/Kconfig

@@ -0,0 +1,112 @@
+# AXU4EV-E BSP (Board Support Package) Execution Instruction
+
+[中文页](README_zh.md) |
+
+## **Introduction**
+
+This document records the execution instruction of the BSP (board support package) for the AXU4EV-E development board.
+
+The document is covered in three parts:
+
+- AXU4EV-E Board Resources Introduction
+- Quickly Get Started
+- Advanced Features
+- BSP Migration
+
+By reading the Quickly Get Started section developers can quickly get their hands on this BSP and run RT-Thread on the board. More advanced features will be introduced in the Advanced Features section to help developers take advantage of RT-Thread to drive more on-board resources.
+
+## AXU4EV-E Resources Introduction
+
+ALINX AXU4EV-E: Xilinx Zynq UltraScale+ MPSOC XCZU4EV-1SFVC784I Ethernet FPGA development board, the SoM Core board is the smallest system, mainly composed of XCZU4EV-1SFVC784I + 5 DDR4 + eMMC + 1 QSPI FLASH. The Carrier board expands a wealth of peripheral interfaces for the core board, including 1 SATA M.2 interface, 1 DP output interface, 4 USB3.0 interfaces, 2 Gigabit Ethernet interfaces, 2 UART interfaces, 1 SD card interface, 2*40-pin Expansion Connectors for Modules, 2 CAN bus interfaces, 2 RS485 interfaces, 1 MIPI interface, Keys and LEDs. High-speed data exchange and transmission, data storage, pre-verification and post-application of data processing, video transmission processing, deep learning, artificial intelligence and industrial control, is a professional ZYNQ development platform. suitable for students, engineers and other groups engaged in the development of MPSoCs.
+
+For more details about this board, please refer to [Alinx Electronic Technology (Shanghai) Co.,Ltd.](http://www.alinx.com/en/)。
+
+## **Peripheral Condition**
+
+Each peripheral supporting condition for this BSP is as follows:
+
+| **Core**      | **Support** | **Remark**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| R5-CPU0   |     Support     | The R5-CPU0 is running the system |
+| **On-board Peripherals**      | **Support** | **Remark**                              |
+| None |          |  |
+| **On-chip Peripherals**      | **Support** | **Remark**                              |
+| GPIO              |     Support     |  |
+| UART              |     Support     | UART0                            |
+| TIMER     |     Support     |     TTC0 provides system clock         |
+| EMMC | Support | SD0 Controller |
+
+## Execution Instruction
+
+### Quickly Get Started
+
+This BSP only support the GCC development environment. Here's an example to introduce how to run the system.
+
+#### Compile and Download
+
+1. Open the env tool under BSP. Enter `scons` to compile.
+
+2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
+
+3. Use Xilinx Vitis to generate fsbl, and then create "Debug Configuration", select the `rtthread-zynqmp-r5.elf` file as the application.
+
+4. Use the debugger to connect the PC and the development board. Set the dial switch to JTAG to start. Then connect the power supply. Click start debugging or running.
+
+   Since the compiler has debugging information by default (see rtconfig.py In BUILD, so when debugging in Xilinx Vitis, you can also open source files to set breakpoints for debugging.
+
+#### Software Solidification
+
+1. Open the env tool under BSP. Enter `scons` to compile.
+
+2. After compiling, `rtthread-zynqmp-r5.elf` file will be generated in BSP directory.
+
+3. Use Xilinx Vitis or Xilinx SDK to generate fsbl, and then use the bootgen tool provided by Xilinx to make fsbl BOOT.bin Documents.
+
+   For example, use the command line:
+
+   ```
+    bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on
+   ```
+   
+   And the outpu.bif file could be：
+   ```
+   //arch = zynqmp; split = false; format = BIN
+   the_ROM_image:
+   {
+        [bootloader, destination_cpu = r5-0]./fsbl.elf
+        [destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf
+   }
+   ```
+   
+4. According to the document provided by Alinx, put BOOT.bin into SD card or burn to QSPI flash, set the startup mode through dial switch, and then connect the power supply to start.
+
+
+#### Running Results
+
+Once the project is successfully downloaded, the system runs automatically.
+
+Connect the serial port of the board to PC, communicate with it via a serial terminal tool (115200bps, 8N1). Restart the board and the startup information of RT-Thread will be observed:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Nov 27 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh />
+```
+
+### **Advanced Features**
+
+This BSP enables EMMC driver and DFS file system by default. If you need to use a file system, you can format and mount it by yourself.
+
+## BSP Migration
+
+If you need to ported the BSP to another development board of Xilinx Zynq UltraScale+ MPSOC development platform, it is also convenient. The main modifications are as follows:
+
+1. Memory: `psu_r5_ddr_0_MEM_0` in `zynqmp-r5.ld` (if DDR memory is less than 2G)
+2. Main Frequency: `XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ` in `zynqmp-r5.h`
+3. Pin and Frequency of Serial Port: `rxmio`, `txmio` and `XPAR_PSU_UART_0_UART_CLK_FREQ_HZ` in `drv_uart.c`
+4. Timer Frequency: `XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` in `drv_timer.c`
+5. SD Controller: Block device driver initialization in `drv_sdcard.c`
+
+The parameter macro definition in `xparameters.h` does not need to be modified manually. You can directly copy the `xparameters.h` file of the development board generated in Xilinx Vitis.

bsp/zynqmp-r5-axu4ev/README.md

@@ -0,0 +1,133 @@
+# AXU4EV-E 开发板 BSP 说明
+
+## 简介
+
+本文档是为 AXU4EV-E 开发板提供的 BSP (板级支持包) 说明。
+
+主要内容如下：
+
+- 开发板资源介绍
+- BSP 快速上手
+- 进阶使用方法
+
+通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。
+
+## 开发板介绍
+
+AXU4EV-E 开发板是 芯驿电子科技（上海）有限公司 推出的一款基于 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板。这款 MPSoCs 开发平台采用核心板加扩展板的模式，方便用户对核心板的二次开发利用。核心板使用 XILINX Zynq UltraScale+ EV 芯片 ZU4EV 的解决方案，它采用Processing System(PS)+Programmable Logic(PL)技术将四核ARM Cortex-A53 和FPGA 可编程逻辑集成在一颗芯片上。另外核心板上 PS 端带有 4 片共 4GB 高速 DDR4 SDRAM 芯片，1 片 8GB的 eMMC 存储芯片和 1 片 256Mb 的 QSPI FLASH 芯片；核心板上 PL 端带有 1 片 1GB 的DDR4 SDRAM 芯片 。
+
+开发板更多详细信息请参考[芯驿电子科技（上海）有限公司](http://www.alinx.cn/)。
+
+## 外设支持
+
+本 BSP 目前对外设的支持情况如下：
+
+| **核心**      | **支持情况** | **备注**                              |
+| :----------------- | :----------: | :------------------------------------- |
+| R5-CPU0   |     支持     | 运行系统的为R5核的CPU0 |
+| **板载外设**      | **支持情况** | **备注**                              |
+| 无 |          |  |
+| **片上外设**      | **支持情况** | **备注**                              |
+| GPIO              |     支持     |  |
+| UART              |     支持     | UART0                            |
+| TIMER     |     支持     |     TTC0提供系统时钟         |
+| EMMC | 支持 | SD0控制器 |
+
+## 使用说明
+
+使用说明分为如下两个章节：
+
+- 快速上手
+
+    本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。
+
+- 进阶使用
+
+    本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。
+
+
+### 快速上手
+
+本 BSP 为仅支持 GCC 开发环境，下面介绍如何将系统运行起来。
+
+#### 编译下载
+
+1. 在 bsp 下打开 env 工具，输入`scons`进行编译。
+
+2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。
+
+3. 使用 Xilinx Vitis 产生 FSBL，然后创建 “Debug Configuration”，Application 选择`rtthread-zynqmp-r5.elf` 文件。
+
+4. 使用调试器连接 PC 和开发板，通过拨码开关设置为 JTAG 启动，然后连接电源，点击开始调试或运行即可。
+
+   由于编译时默认带有调试信息（见 rtconfig.py 中 BUILD），所以在 Xilinx Vitis 中调试时同样可以打开源文件设断点进行调试。
+
+#### 固化程序
+
+1. 在 bsp 下打开 env 工具，输入`scons`进行编译。
+
+2. 编译完成后在 bsp 目录下会生成 `rtthread-zynqmp-r5.elf` 文件。
+
+3. 使用 Xilinx Vitis 或 Xilinx SDK 产生 FSBL，然后使用 Xilinx 提供的 bootgen 工具制作 BOOT.bin 文件。
+
+   例如使用命令行方式：
+
+   ```
+    bootgen -image ./output.bif -arch zynqmp -o ./BOOT.bin -w on
+   ```
+   
+   其中 output.bif 文件可以是：
+   ```
+   //arch = zynqmp; split = false; format = BIN
+   the_ROM_image:
+   {
+        [bootloader, destination_cpu = r5-0]./fsbl.elf
+        [destination_cpu = r5-0, exception_level = el-3]./rtthread-zynqmp-r5.elf
+   }
+   ```
+   
+4. 根据 ALINX 提供的文档将 BOOT.bin 放进SD卡或烧录到 QSPI FLASH 中，通过拨码开关设置启动方式，然后连接电源即可启动。
+
+
+#### 运行结果
+
+下载程序成功之后，系统会自动运行。
+
+连接开发板对应串口到 PC , 在终端工具里打开相应的串口（115200-8-1-N），复位设备后，可以看到 RT-Thread 的输出信息:
+
+```bash
+ \ | /
+- RT -     Thread Operating System
+ / | \     4.0.3 build Nov 27 2020
+ 2006 - 2020 Copyright by rt-thread team
+msh />
+```
+
+### 进阶使用
+
+此 BSP 默认开启了 EMMC 驱动和 DFS 文件系统，如果需要使用文件系统可以自行格式化并挂载。
+
+
+## 板级移植
+
+如果需要将BSP移植到其他 XILINX Zynq UltraScale+ MPSoCs 开发平台的开发板上也比较方便，主要修改的地方有以下几点：
+
+1. 内存： 如果 DDR memory 小于 2G，需要修改`zynqmp-r5.ld`链接文件中的`psu_r5_ddr_0_MEM_0` 
+2. 主频： `xparameters.h`中的`XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ`
+3. 串口引脚和频率：`drv_uart.c`中的`rxmio`, `txmio` 和`xparameters.h`中的`XPAR_PSU_UART_0_UART_CLK_FREQ_HZ`
+4. 定时器频率：`xparameters.h`中的`XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ` 
+5. SD控制器：`drv_sdcard.c`中的块设备驱动初始化
+
+以上需要修改的`xparameters.h`中的参数宏定义不需要手动修改，可以直接将Xilinx Vitis中产生的开发板的`xparameters.h`文件复制过来即可。
+
+
+
+## 注意事项
+
+- 无
+
+## 联系人信息
+
+维护人:
+
+-  [王华辰](https://github.com/Wang-Huachen/)

bsp/zynqmp-r5-axu4ev/README_zh.md

@@ -0,0 +1,14 @@
+# for module compiling
+import os
+Import('RTT_ROOT')
+
+cwd = str(Dir('#'))
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')

bsp/zynqmp-r5-axu4ev/SConscript

@@ -0,0 +1,30 @@
+import os
+import sys
+import rtconfig
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-zynqmp-r5.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# make a building
+DoBuilding(TARGET, objs)

bsp/zynqmp-r5-axu4ev/SConstruct

@@ -0,0 +1,11 @@
+Import('RTT_ROOT')
+Import('rtconfig')
+from building import *
+
+cwd     = os.path.join(str(Dir('#')), 'applications')
+src	= Glob('*.c')
+CPPPATH = [cwd, str(Dir('#'))]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')

bsp/zynqmp-r5-axu4ev/applications/SConscript

@@ -0,0 +1,18 @@
+#include <rtthread.h>
+#include <rtdevice.h>
+
+#define LED_PIN    40
+int main(void)
+{
+    rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
+
+    while (1)
+    {
+        rt_pin_write(LED_PIN, PIN_HIGH);
+        rt_thread_mdelay(500);
+        rt_pin_write(LED_PIN, PIN_LOW);
+        rt_thread_mdelay(500);
+    }
+
+    return RT_EOK;
+}

bsp/zynqmp-r5-axu4ev/applications/main.c

@@ -0,0 +1,35 @@
+menu "Hardware Drivers Config"
+
+    menu "Onboard Peripheral Drivers"
+
+    endmenu
+
+    menu "On-chip Peripheral Drivers"
+
+    menuconfig BSP_USING_UART
+        bool "Enable UART"
+        default y
+        select RT_USING_SERIAL
+        if BSP_USING_UART
+            config BSP_USING_UART0
+                bool "Enable UART0"
+                default y
+        endif
+
+    menuconfig BSP_USING_SDIO
+        bool "Enable SDIO"
+        default y
+        if BSP_USING_SDIO
+            config BSP_USING_SD0
+                bool "Enable SD0 EMMC"
+                default y
+        endif
+
+    endmenu
+
+    menu "Board extended module Drivers"
+
+    endmenu
+
+endmenu
+