[bsp/n32g452xx] Unified header file definition. "GPIO_H__" to "DRV_GPIO_H". "USART_H" to "DRV_USART_H"

[bsp/n32g452xx] In drv_pwm.c, variable meaning is different with RT-Thread interface definition. Fixed and tested.
[bsp/n32g452xx] Add support for UART4/UART5.
[bsp/n32g452xx] In drv_gpio.c Modify "N32F10X_PIN_NUMBERS" to "N32G45X_PIN_NUMBERS".

Author: Blues-Jiang

bsp/n32g452xx/Libraries/rt_drivers/SConscript

@@ -15,7 +15,7 @@ src += ['drv_clk.c']
 if GetDepend(['BSP_USING_GPIO']):
     src += ['drv_gpio.c']
 
-if GetDepend(['BSP_USING_UART']):
+if GetDepend(['RT_USING_WDT']):
     src += ['drv_wdt.c']
 
 if GetDepend(['BSP_USING_UART']):

bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.c

@@ -15,7 +15,7 @@
 
 #ifdef RT_USING_PIN
 
-#define N32F10X_PIN_NUMBERS 64 //[48, 64, 100, 144 ]
+#define N32G45X_PIN_NUMBERS 64 //[48, 64, 100, 144 ]
 
 #define __N32_PIN(index, rcc, gpio, gpio_index) \
 { \
@@ -37,7 +37,7 @@ struct pin_index
 
 static const struct pin_index pins[] =
 {
-#if (N32F10X_PIN_NUMBERS == 48)
+#if (N32G45X_PIN_NUMBERS == 48)
     __N32_PIN_DEFAULT,
     __N32_PIN_DEFAULT,
     __N32_PIN(2, APB2, C, 13),
@@ -89,7 +89,7 @@ static const struct pin_index pins[] =
     __N32_PIN_DEFAULT,
 
 #endif
-#if (N32F10X_PIN_NUMBERS == 64)
+#if (N32G45X_PIN_NUMBERS == 64)
     __N32_PIN_DEFAULT,
     __N32_PIN_DEFAULT,
     __N32_PIN(2, APB2, C, 13),
@@ -156,7 +156,7 @@ static const struct pin_index pins[] =
     __N32_PIN_DEFAULT,
     __N32_PIN_DEFAULT,
 #endif
-#if (N32F10X_PIN_NUMBERS == 100)
+#if (N32G45X_PIN_NUMBERS == 100)
     __N32_PIN_DEFAULT,
     __N32_PIN(1, APB2, E, 2),
     __N32_PIN(2, APB2, E, 3),
@@ -259,7 +259,7 @@ static const struct pin_index pins[] =
     __N32_PIN_DEFAULT,
     __N32_PIN_DEFAULT,
 #endif
-#if (N32F10X_PIN_NUMBERS == 144)
+#if (N32G45X_PIN_NUMBERS == 144)
     __N32_PIN_DEFAULT,
     __N32_PIN(1, APB2, E, 2),
     __N32_PIN(2, APB2, E, 3),

bsp/n32g452xx/Libraries/rt_drivers/drv_gpio.h

@@ -7,9 +7,10 @@
  * Date           Author       Notes
  * 2015-01-05     Bernard      the first version
  */
-#ifndef GPIO_H__
-#define GPIO_H__
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
 
 int n32_hw_pin_init(void);
 
-#endif
+
+#endif /* __DRV_GPIO_H__ */

bsp/n32g452xx/Libraries/rt_drivers/drv_pwm.c

@@ -29,6 +29,7 @@
 #endif /* RT_USING_PWM */
 
 #define MAX_PERIOD 65535
+#define MIN_PERIOD 3
 
 #ifdef BSP_USING_PWM
 
@@ -207,6 +208,9 @@ static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration
 {
     TIM_Module *TIMx = pwm_dev->tim_handle;
     rt_uint32_t channel = configuration->channel;
+    rt_uint32_t period;
+    rt_uint64_t psc;
+    rt_uint32_t pulse;
 
     /* Init timer pin and enable clock */
     void n32_msp_tim_init(void *Instance);
@@ -228,25 +232,33 @@ static rt_err_t drv_pwm_set(struct n32_pwm *pwm_dev, struct rt_pwm_configuration
             input_clock = RCC_Clock.Pclk1Freq * 2;
     }
 
+    input_clock /= 1000000UL;
     /* Convert nanosecond to frequency and duty cycle. */
-    rt_uint32_t period = (unsigned long long)configuration->period ;
-    rt_uint64_t psc = period / MAX_PERIOD + 1;
+    period = (unsigned long long)configuration->period * input_clock / 1000ULL;
+    psc = period / MAX_PERIOD + 1;
     period = period / psc;
-    psc = psc * (input_clock / 1000000);
-
+    if (period < MIN_PERIOD)
+    {
+        period = MIN_PERIOD;
+    }
     if ((pwm_dev->period != period) || (pwm_dev->psc != psc))
     {
-        /* TIMe base configuration */
+        /* Tim base configuration */
         TIM_TimeBaseInitType TIM_TIMeBaseStructure;
         TIM_InitTimBaseStruct(&TIM_TIMeBaseStructure);
-        TIM_TIMeBaseStructure.Period = period;
+        TIM_TIMeBaseStructure.Period = period - 1;
         TIM_TIMeBaseStructure.Prescaler = psc - 1;
         TIM_TIMeBaseStructure.ClkDiv = 0;
         TIM_TIMeBaseStructure.CntMode = TIM_CNT_MODE_UP;
         TIM_InitTimeBase(TIMx, &TIM_TIMeBaseStructure);
     }
 
-    rt_uint32_t pulse = (unsigned long long)configuration->pulse;
+    pulse = (unsigned long long)configuration->pulse * input_clock / psc / 1000ULL;
+    if (pulse > period)
+    {
+        pulse = period;
+    }
+
     /* PWM1 Mode configuration: Channel1 */
     OCInitType  TIM_OCInitStructure;
     TIM_InitOcStruct(&TIM_OCInitStructure);

bsp/n32g452xx/Libraries/rt_drivers/drv_usart.c

@@ -437,12 +437,46 @@ void DMA2_Channel3_IRQHandler(void)
     rt_interrupt_enter();
 
     dma_rx_done_isr(&serial4);
-
     /* leave interrupt */
     rt_interrupt_leave();
 }
 #endif /* BSP_USING_UART4 */
 
+#if defined(BSP_USING_UART5)
+/* UART5 device driver structure */
+struct n32_uart uart5 =
+{
+    UART5,
+    UART5_IRQn,
+    {
+        DMA1_CH8,
+        DMA1,
+        DMA1_FLAG_GL8,
+        DMA1_Channel8_IRQn,
+        0,
+    },
+};
+struct rt_serial_device serial5;
+
+void UART5_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    uart_isr(&serial5);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+
+void DMA1_Channel8_IRQHandler(void)
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+    dma_rx_done_isr(&serial5);
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif /* BSP_USING_UART5 */
+
 static void NVIC_Configuration(struct n32_uart *uart)
 {
     NVIC_InitType NVIC_InitStructure;
@@ -552,6 +586,31 @@ int rt_hw_usart_init(void)
                           uart);
 #endif /* BSP_USING_UART3 */
 
+    #if defined(BSP_USING_UART4)
+    uart = &uart4;
+    config.baud_rate = BAUD_RATE_115200;
+    serial4.ops    = &n32_uart_ops;
+    serial4.config = config;
+    NVIC_Configuration(uart);
+    /* register UART3 device */
+    rt_hw_serial_register(&serial4, "uart4",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+                          RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
+                          uart);
+    #endif /* BSP_USING_UART4 */
+
+    #if defined(BSP_USING_UART5)
+    uart = &uart5;
+    config.baud_rate = BAUD_RATE_115200;
+    serial5.ops    = &n32_uart_ops;
+    serial5.config = config;
+    NVIC_Configuration(uart);
+    /* register UART3 device */
+    rt_hw_serial_register(&serial5, "uart5",
+                          RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |
+                          RT_DEVICE_FLAG_INT_TX | RT_DEVICE_FLAG_DMA_RX,
+                          uart);
+    #endif /* BSP_USING_UART5 */
     return RT_EOK;
 }
 

bsp/n32g452xx/Libraries/rt_drivers/drv_usart.h

@@ -8,9 +8,9 @@
  * 2009-01-05     Bernard      the first version
  */
 
-#ifndef __USART_H__
-#define __USART_H__
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
 
 int rt_hw_usart_init(void);
 
-#endif
+#endif /* __DRV_USART_H__ */

bsp/n32g452xx/n32g452xx-mini-system/board/Kconfig

@@ -49,6 +49,15 @@ menu "On-chip Peripheral Drivers"
             config BSP_USING_UART3
                 bool "Enable UART3"
                 default n
+
+            config BSP_USING_UART4
+                bool "Enable UART4"
+                default n
+
+            config BSP_USING_UART5
+                bool "Enable UART5"
+                default n
+				
         endif
 
     menuconfig BSP_USING_PWM