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[update] add riscv toolchain for ci.
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.github/workflows/action.yml

Lines changed: 18 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@ jobs:
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- {RTT_BSP: "allwinner_tina", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "efm32", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32e230k-start", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32vf103v-eval", RTT_TOOL_CHAIN: "sourcery-riscv-none-embed"}
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- {RTT_BSP: "gd32303e-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "gd32450z-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "imx6sx/cortex-a9", RTT_TOOL_CHAIN: "sourcery-arm"}
@@ -138,7 +139,7 @@ jobs:
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- {RTT_BSP: "raspberry-pi/raspi4-32", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "hc32l196", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "tae32f5300", RTT_TOOL_CHAIN: "sourcery-arm"}
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- {RTT_BSP: "bluetrum/ab32vg1-ab-prougen", RTT_TOOL_CHAIN: "sourcery-riscv"}
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- {RTT_BSP: "bluetrum/ab32vg1-ab-prougen", RTT_TOOL_CHAIN: "sourcery-riscv64-unknown-elf"}
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steps:
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- uses: actions/checkout@v2
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- name: Set up Python
@@ -172,6 +173,22 @@ jobs:
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/opt/mips-2016.05/bin/mips-sde-elf-gcc --version
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echo "RTT_EXEC_PATH=/opt/mips-2016.05/bin" >> $GITHUB_ENV
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- name: Install Riscv64-unknown-elf ToolChains
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if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv64-unknown-elf' && success() }}
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run: |
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wget -q https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz
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sudo tar zxvf riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14.tar.gz -C /opt
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/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin/riscv64-unknown-elf-gcc --version
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echo "RTT_EXEC_PATH=/opt/riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14/bin" >> $GITHUB_ENV
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- name: Install Riscv-none-embed ToolChains
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if: ${{ matrix.legs.RTT_TOOL_CHAIN == 'sourcery-riscv-none-embed' && success() }}
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run: |
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wget -q https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v8.3.0-2.3/xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz
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sudo tar zxvf xpack-riscv-none-embed-gcc-8.3.0-2.3-linux-x64.tar.gz -C /opt
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/opt/xpack-riscv-none-embed-gcc-8.3.0-2.3/bin/riscv-none-embed-gcc --version
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echo "RTT_EXEC_PATH=/opt/xpack-riscv-none-embed-gcc-8.3.0-2.3/bin" >> $GITHUB_ENV
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- name: Bsp Scons Compile
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if: ${{ success() }}
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shell: bash

bsp/bluetrum/ab32vg1-ab-prougen/rtconfig.py

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
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import os
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import platform
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# toolchains options
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ARCH ='risc-v'
@@ -57,8 +59,10 @@
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DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
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POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
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POST_ACTION += './riscv32-elf-xmaker -b rtthread.xm\n'
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POST_ACTION += './riscv32-elf-xmaker -b download.xm\n'
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if "Windows" in platform.platform():
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POST_ACTION += './riscv32-elf-xmaker -b rtthread.xm\n'
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POST_ACTION += './riscv32-elf-xmaker -b download.xm\n'
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def dist_handle(BSP_ROOT, dist_dir):
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import sys

bsp/bluetrum/libraries/hal_libraries/ab32vg1_hal/SConscript

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -48,8 +48,8 @@ ASFLAGS = ""
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CPPDEFINES = []
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LOCAL_CPPDEFINES = []
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LIBS = []
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LIBPATH = []
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LIBS = ['hal']
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LIBPATH = [CWD]
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LINKFLAGS = ""
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