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charlowncharlown
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[bsp/wch/arm/Libraries/ch32_drivers]: support ch32f10x hwtimer.
[bsp/wch/arm/ch32f103c8-core]: add hwtimer1~4.
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‎bsp/wch/arm/Libraries/ch32_drivers/SConscript‎

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@@ -29,6 +29,9 @@ if GetDepend('SOC_ARM_SERIES_CH32F103'):
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if GetDepend(['RT_USING_WDT', 'BSP_USING_IWDT']):
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src += ['drv_iwdt_ch32f10x.c']
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if GetDepend(['RT_USING_HWTIMER', 'BSP_USING_HWTIMER']):
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src += ['drv_hwtimer_ch32f10x.c']
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src += ['drv_common.c']
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path = [cwd]

‎bsp/wch/arm/Libraries/ch32_drivers/drv_hwtimer_ch32f10x.c‎

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/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-08-10 charlown first version
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*/
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#include <rtthread.h>
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#include <rtdevice.h>
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#include <board.h>
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#ifdef BSP_USING_HWTIMER
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#define LOG_TAG "drv.hwtimer"
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#include <drv_log.h>
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struct hwtimer_device
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{
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struct rt_hwtimer_device parent;
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TIM_TypeDef *periph;
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IRQn_Type irqn;
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char *name;
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};
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#ifdef BSP_USING_TIM1_HWTIMER
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struct hwtimer_device hwtimer_device1 =
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{
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.periph = TIM1,
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.irqn = TIM1_UP_IRQn,
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.name = "timer1"};
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#endif
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#ifdef BSP_USING_TIM2_HWTIMER
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struct hwtimer_device hwtimer_device2 =
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{
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.periph = TIM2,
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.irqn = TIM2_IRQn,
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.name = "timer2"};
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#endif
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#ifdef BSP_USING_TIM3_HWTIMER
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struct hwtimer_device hwtimer_device3 =
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{
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.periph = TIM3,
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.irqn = TIM3_IRQn,
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.name = "timer3"};
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#endif
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#ifdef BSP_USING_TIM4_HWTIMER
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struct hwtimer_device hwtimer_device4 =
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{
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.periph = TIM4,
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.irqn = TIM4_IRQn,
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.name = "timer4"};
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#endif
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static void ch32f1_hwtimer_init(struct rt_hwtimer_device *device, rt_uint32_t state)
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{
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struct hwtimer_device *hwtimer_dev;
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struct rt_hwtimer_info *hwtimer_info;
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rt_uint32_t clk = 0;
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rt_uint16_t prescaler_value = 0;
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TIM_TimeBaseInitTypeDef TIM_TimeBaseInitType;
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NVIC_InitTypeDef NVIC_InitStructure;
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RT_ASSERT(device != RT_NULL);
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hwtimer_dev = (struct hwtimer_device *)device;
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if (state)
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{
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ch32f1_hwtimer_clock_init(hwtimer_dev->periph);
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hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_dev->periph);
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clk = ch32f1_hwtimer_clock_get(hwtimer_dev->periph);
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prescaler_value = (rt_uint16_t)(clk / hwtimer_info->minfreq) - 1;
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/*
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* set interrupt callback one or each time need total time =
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* (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
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*/
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TIM_TimeBaseInitType.TIM_Period = hwtimer_info->maxcnt - 1;
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TIM_TimeBaseInitType.TIM_Prescaler = prescaler_value;
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TIM_TimeBaseInitType.TIM_ClockDivision = TIM_CKD_DIV1;
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TIM_TimeBaseInitType.TIM_RepetitionCounter = 0;
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if (hwtimer_info == RT_NULL)
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{
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TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up;
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}
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else
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{
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if (hwtimer_info->cntmode == HWTIMER_CNTMODE_UP)
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{
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TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Up;
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}
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else
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{
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TIM_TimeBaseInitType.TIM_CounterMode = TIM_CounterMode_Down;
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}
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}
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TIM_TimeBaseInit(hwtimer_dev->periph, &TIM_TimeBaseInitType);
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NVIC_InitStructure.NVIC_IRQChannel = hwtimer_dev->irqn;
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NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 2;
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NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
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NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
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NVIC_Init(&NVIC_InitStructure);
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TIM_ITConfig(hwtimer_dev->periph, TIM_IT_Update, ENABLE);
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TIM_ClearITPendingBit(hwtimer_dev->periph, TIM_IT_Update);
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LOG_D("%s init success", hwtimer_dev->name);
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}
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}
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static rt_err_t ch32f1_hwtimer_start(struct rt_hwtimer_device *device, rt_uint32_t cnt, rt_hwtimer_mode_t mode)
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{
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struct hwtimer_device *hwtimer_dev;
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RT_ASSERT(device != RT_NULL);
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hwtimer_dev = (struct hwtimer_device *)device;
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/*
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* interrupt callback one or each time need total time =
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* (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
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*/
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TIM_SetCounter(hwtimer_dev->periph, 0);
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TIM_SetAutoreload(hwtimer_dev->periph, cnt - 1);
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if (mode == HWTIMER_MODE_ONESHOT)
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{
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TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Single);
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}
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else
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{
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TIM_SelectOnePulseMode(hwtimer_dev->periph, TIM_OPMode_Repetitive);
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}
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TIM_Cmd(hwtimer_dev->periph, ENABLE);
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LOG_D("%s start, cnt = %d", hwtimer_dev->name, cnt);
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return RT_EOK;
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}
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static void ch32f1_hwtimer_stop(struct rt_hwtimer_device *device)
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{
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struct hwtimer_device *hwtimer_dev;
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RT_ASSERT(device != RT_NULL);
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hwtimer_dev = (struct hwtimer_device *)device;
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TIM_Cmd(hwtimer_dev->periph, DISABLE);
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TIM_SetCounter(hwtimer_dev->periph, 0);
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}
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static rt_uint32_t ch32f1_hwtimer_counter_get(struct rt_hwtimer_device *device)
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{
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struct hwtimer_device *hwtimer_dev;
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RT_ASSERT(device != RT_NULL);
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hwtimer_dev = (struct hwtimer_device *)device;
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return hwtimer_dev->periph->CNT;
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}
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static rt_err_t ch32f1_hwtimer_control(struct rt_hwtimer_device *device, rt_uint32_t cmd, void *arg)
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{
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struct hwtimer_device *hwtimer_dev;
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rt_err_t result = RT_EOK;
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RT_ASSERT(device != RT_NULL);
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hwtimer_dev = (struct hwtimer_device *)device;
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switch (cmd)
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{
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case HWTIMER_CTRL_FREQ_SET:
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{
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rt_uint32_t freq = 0;
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rt_uint32_t clk = 0;
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rt_uint16_t prescaler_value = 0;
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/*
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*set interrupt callback one or each time need total time =
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* (cnt + 1) * (1 / (clk/(prescaler_value + 1) ) )
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*/
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if (arg != RT_NULL)
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{
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freq = *((rt_uint32_t *)arg);
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clk = ch32f1_hwtimer_clock_get(hwtimer_dev->periph);
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prescaler_value = (rt_uint16_t)(clk / freq) - 1;
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TIM_PrescalerConfig(hwtimer_dev->periph, prescaler_value, TIM_PSCReloadMode_Immediate);
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}
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else
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{
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result = RT_EINVAL;
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}
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}
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break;
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default:
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result = RT_ENOSYS;
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break;
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}
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return result;
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}
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static const struct rt_hwtimer_ops hwtimer_ops =
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{
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.init = ch32f1_hwtimer_init,
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.start = ch32f1_hwtimer_start,
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.stop = ch32f1_hwtimer_stop,
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.count_get = ch32f1_hwtimer_counter_get,
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.control = ch32f1_hwtimer_control,
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};
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static int rt_hw_hwtimer_init(void)
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{
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rt_err_t ret;
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struct rt_hwtimer_info *hwtimer_info;
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#ifdef BSP_USING_TIM1_HWTIMER
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hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device1.periph);
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hwtimer_device1.parent.info = hwtimer_info;
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hwtimer_device1.parent.ops = &hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer_device1.parent, hwtimer_device1.name, RT_NULL);
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if (ret == RT_EOK)
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{
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LOG_D("hwtimer: %s register success.", hwtimer_device1.name);
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}
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else
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{
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LOG_D("hwtimer: %s register failed.", hwtimer_device1.name);
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}
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#endif
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#ifdef BSP_USING_TIM2_HWTIMER
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hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device2.periph);
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hwtimer_device2.parent.info = hwtimer_info;
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hwtimer_device2.parent.ops = &hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer_device2.parent, hwtimer_device2.name, RT_NULL);
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if (ret == RT_EOK)
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{
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LOG_D("hwtimer: %s register success.", hwtimer_device2.name);
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}
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else
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{
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LOG_D("hwtimer: %s register failed.", hwtimer_device2.name);
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}
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#endif
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#ifdef BSP_USING_TIM3_HWTIMER
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hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device3.periph);
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hwtimer_device3.parent.info = hwtimer_info;
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hwtimer_device3.parent.ops = &hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer_device3.parent, hwtimer_device3.name, RT_NULL);
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if (ret == RT_EOK)
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{
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LOG_D("hwtimer: %s register success.", hwtimer_device3.name);
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}
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else
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{
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LOG_D("hwtimer: %s register failed.", hwtimer_device3.name);
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}
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#endif
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#ifdef BSP_USING_TIM4_HWTIMER
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hwtimer_info = ch32f1_hwtimer_info_config_get(hwtimer_device4.periph);
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hwtimer_device4.parent.info = hwtimer_info;
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hwtimer_device4.parent.ops = &hwtimer_ops;
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ret = rt_device_hwtimer_register(&hwtimer_device4.parent, hwtimer_device4.name, RT_NULL);
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if (ret == RT_EOK)
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{
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LOG_D("hwtimer: %s register success.", hwtimer_device4.name);
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}
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else
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{
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LOG_D("hwtimer: %s register failed.", hwtimer_device4.name);
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}
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#endif
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return RT_EOK;
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}
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INIT_DEVICE_EXPORT(rt_hw_hwtimer_init);
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#ifdef BSP_USING_TIM1_HWTIMER
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void TIM1_UP_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetITStatus(hwtimer_device1.periph, TIM_IT_Update) == SET)
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{
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TIM_ClearITPendingBit(hwtimer_device1.periph, TIM_IT_Update);
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rt_device_hwtimer_isr(&hwtimer_device1.parent);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM2_HWTIMER
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void TIM2_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetITStatus(hwtimer_device2.periph, TIM_IT_Update) == SET)
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{
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TIM_ClearITPendingBit(hwtimer_device2.periph, TIM_IT_Update);
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rt_device_hwtimer_isr(&hwtimer_device2.parent);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM3_HWTIMER
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void TIM3_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetITStatus(hwtimer_device3.periph, TIM_IT_Update) == SET)
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{
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TIM_ClearITPendingBit(hwtimer_device3.periph, TIM_IT_Update);
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rt_device_hwtimer_isr(&hwtimer_device3.parent);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#ifdef BSP_USING_TIM4_HWTIMER
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void TIM4_IRQHandler(void)
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{
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/* enter interrupt */
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rt_interrupt_enter();
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if (TIM_GetITStatus(hwtimer_device4.periph, TIM_IT_Update) == SET)
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{
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TIM_ClearITPendingBit(hwtimer_device4.periph, TIM_IT_Update);
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rt_device_hwtimer_isr(&hwtimer_device4.parent);
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}
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/* leave interrupt */
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rt_interrupt_leave();
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}
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#endif
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#endif /* BSP_USING_HWTIMER */
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