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Merge pull request #3466 from gyd0317/dev
add STM32L1 HAL DRIVER
2 parents d1ba07a + 588bda5 commit 88eafe7

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‎bsp/stm32/libraries/HAL_Drivers/config/l1/adc_config.h‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-07 zylx first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_ADC1
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#ifndef ADC1_CONFIG
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#define ADC1_CONFIG \
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{ \
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.Instance = ADC1, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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}
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#endif /* ADC1_CONFIG */
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#endif /* BSP_USING_ADC1 */
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#ifdef BSP_USING_ADC2
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#ifndef ADC2_CONFIG
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#define ADC2_CONFIG \
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{ \
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.Instance = ADC2, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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}
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#endif /* ADC2_CONFIG */
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#endif /* BSP_USING_ADC2 */
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#ifdef BSP_USING_ADC3
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#ifndef ADC3_CONFIG
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#define ADC3_CONFIG \
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{ \
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.Instance = ADC3, \
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.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
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.Init.ScanConvMode = ADC_SCAN_DISABLE, \
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.Init.ContinuousConvMode = DISABLE, \
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.Init.NbrOfConversion = 1, \
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.Init.DiscontinuousConvMode = DISABLE, \
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.Init.NbrOfDiscConversion = 1, \
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.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
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}
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#endif /* ADC3_CONFIG */
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#endif /* BSP_USING_ADC3 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ADC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/l1/dma_config.h‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-01-02 SummerGift first version
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* 2019-01-08 SummerGift clean up the code
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*/
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#ifndef __DMA_CONFIG_H__
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#define __DMA_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* DMA1 channel1 */
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/* DMA1 channel2 */
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#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE)
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#define SPI1_DMA_RX_IRQHandler DMA1_Channel2_IRQHandler
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#define SPI1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_RX_DMA_INSTANCE DMA1_Channel2
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#define SPI1_RX_DMA_IRQ DMA1_Channel2_IRQn
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#elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE)
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#define UART3_DMA_TX_IRQHandler DMA1_Channel2_IRQHandler
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#define UART3_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART3_TX_DMA_INSTANCE DMA1_Channel2
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#define UART3_TX_DMA_IRQ DMA1_Channel2_IRQn
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#endif
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/* DMA1 channel3 */
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#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE)
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#define SPI1_DMA_TX_IRQHandler DMA1_Channel3_IRQHandler
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#define SPI1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI1_TX_DMA_INSTANCE DMA1_Channel3
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#define SPI1_TX_DMA_IRQ DMA1_Channel3_IRQn
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#elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE)
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#define UART3_DMA_RX_IRQHandler DMA1_Channel3_IRQHandler
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#define UART3_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART3_RX_DMA_INSTANCE DMA1_Channel3
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#define UART3_RX_DMA_IRQ DMA1_Channel3_IRQn
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#endif
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/* DMA1 channel4 */
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#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE)
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#define SPI2_DMA_RX_IRQHandler DMA1_Channel4_IRQHandler
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#define SPI2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_RX_DMA_INSTANCE DMA1_Channel4
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#define SPI2_RX_DMA_IRQ DMA1_Channel4_IRQn
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#elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE)
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#define UART1_DMA_TX_IRQHandler DMA1_Channel4_IRQHandler
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#define UART1_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_TX_DMA_INSTANCE DMA1_Channel4
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#define UART1_TX_DMA_IRQ DMA1_Channel4_IRQn
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#endif
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/* DMA1 channel5 */
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#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE)
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#define SPI2_DMA_TX_IRQHandler DMA1_Channel5_IRQHandler
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#define SPI2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define SPI2_TX_DMA_INSTANCE DMA1_Channel5
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#define SPI2_TX_DMA_IRQ DMA1_Channel5_IRQn
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#elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE)
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#define UART1_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
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#define UART1_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART1_RX_DMA_INSTANCE DMA1_Channel5
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#define UART1_RX_DMA_IRQ DMA1_Channel5_IRQn
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#endif
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/* DMA1 channel6 */
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#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
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#define UART2_DMA_RX_IRQHandler DMA1_Channel6_IRQHandler
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#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_RX_DMA_INSTANCE DMA1_Channel6
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#define UART2_RX_DMA_IRQ DMA1_Channel6_IRQn
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#endif
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/* DMA1 channel7 */
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#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
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#define UART2_DMA_TX_IRQHandler DMA1_Channel7_IRQHandler
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#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
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#define UART2_TX_DMA_INSTANCE DMA1_Channel7
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#define UART2_TX_DMA_IRQ DMA1_Channel7_IRQn
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#endif
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/* DMA2 channel1 */
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#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE)
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#define SPI3_DMA_RX_IRQHandler DMA2_Channel1_IRQHandler
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#define SPI3_RX_DMA_RCC RCC_AHBENR_DMA2EN
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#define SPI3_RX_DMA_INSTANCE DMA2_Channel1
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#define SPI3_RX_DMA_IRQ DMA2_Channel1_IRQn
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#endif
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/* DMA2 channel2 */
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#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE)
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#define SPI3_DMA_TX_IRQHandler DMA2_Channel2_IRQHandler
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#define SPI3_TX_DMA_RCC RCC_AHBENR_DMA2EN
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#define SPI3_TX_DMA_INSTANCE DMA2_Channel2
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#define SPI3_TX_DMA_IRQ DMA2_Channel2_IRQn
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#endif
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/* DMA2 channel3 */
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#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE)
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#define UART4_DMA_RX_IRQHandler DMA2_Channel3_IRQHandler
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#define UART4_RX_DMA_RCC RCC_AHBENR_DMA2EN
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#define UART4_RX_DMA_INSTANCE DMA2_Channel3
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#define UART4_RX_DMA_IRQ DMA2_Channel3_IRQn
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#endif
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/* DMA2 channel4 */
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/* DMA2 channel5 */
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#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE)
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#define UART4_DMA_TX_IRQHandler DMA2_Channel4_5_IRQHandler
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#define UART4_TX_DMA_RCC RCC_AHBENR_DMA2EN
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#define UART4_TX_DMA_INSTANCE DMA2_Channel5
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#define UART4_TX_DMA_IRQ DMA2_Channel4_5_IRQn
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* __DMA_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/l1/pulse_encoder_config.h‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2019-08-23 balanceTWK first version
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*/
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#ifndef __PULSE_ENCODER_CONFIG_H__
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#define __PULSE_ENCODER_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_PULSE_ENCODER1
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#ifndef PULSE_ENCODER1_CONFIG
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#define PULSE_ENCODER1_CONFIG \
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{ \
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.tim_handler.Instance = TIM1, \
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.encoder_irqn = TIM1_UP_IRQn, \
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.name = "pulse1" \
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}
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#endif /* PULSE_ENCODER1_CONFIG */
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#endif /* BSP_USING_PULSE_ENCODER1 */
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#ifdef BSP_USING_PULSE_ENCODER2
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#ifndef PULSE_ENCODER2_CONFIG
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#define PULSE_ENCODER2_CONFIG \
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{ \
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.tim_handler.Instance = TIM2, \
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.encoder_irqn = TIM2_IRQn, \
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.name = "pulse2" \
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}
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#endif /* PULSE_ENCODER2_CONFIG */
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#endif /* BSP_USING_PULSE_ENCODER2 */
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#ifdef BSP_USING_PULSE_ENCODER3
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#ifndef PULSE_ENCODER3_CONFIG
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#define PULSE_ENCODER3_CONFIG \
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{ \
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.tim_handler.Instance = TIM3, \
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.encoder_irqn = TIM3_IRQn, \
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.name = "pulse3" \
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}
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#endif /* PULSE_ENCODER3_CONFIG */
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#endif /* BSP_USING_PULSE_ENCODER3 */
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#ifdef BSP_USING_PULSE_ENCODER4
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#ifndef PULSE_ENCODER4_CONFIG
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#define PULSE_ENCODER4_CONFIG \
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{ \
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.tim_handler.Instance = TIM4, \
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.encoder_irqn = TIM4_IRQn, \
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.name = "pulse4" \
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}
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#endif /* PULSE_ENCODER4_CONFIG */
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#endif /* BSP_USING_PULSE_ENCODER4 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PULSE_ENCODER_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/l1/pwm_config.h‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-13 zylx first version
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*/
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#ifndef __PWM_CONFIG_H__
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#define __PWM_CONFIG_H__
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#include <rtthread.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_PWM2
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#ifndef PWM2_CONFIG
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#define PWM2_CONFIG \
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{ \
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.tim_handle.Instance = TIM2, \
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.name = "pwm2", \
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.channel = 0 \
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}
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#endif /* PWM2_CONFIG */
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#endif /* BSP_USING_PWM2 */
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#ifdef BSP_USING_PWM3
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#ifndef PWM3_CONFIG
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#define PWM3_CONFIG \
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{ \
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.tim_handle.Instance = TIM3, \
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.name = "pwm3", \
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.channel = 0 \
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}
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#endif /* PWM3_CONFIG */
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#endif /* BSP_USING_PWM3 */
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#ifdef BSP_USING_PWM4
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#ifndef PWM4_CONFIG
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#define PWM4_CONFIG \
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{ \
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.tim_handle.Instance = TIM4, \
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.name = "pwm4", \
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.channel = 0 \
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}
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#endif /* PWM4_CONFIG */
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#endif /* BSP_USING_PWM4 */
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#ifdef BSP_USING_PWM5
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#ifndef PWM5_CONFIG
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#define PWM5_CONFIG \
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{ \
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.tim_handle.Instance = TIM5, \
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.name = "pwm5", \
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.channel = 0 \
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}
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#endif /* PWM5_CONFIG */
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#endif /* BSP_USING_PWM5 */
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PWM_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/l1/sdio_config.h‎

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/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2018-12-13 BalanceTWK first version
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*/
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#ifndef __SDIO_CONFIG_H__
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#define __SDIO_CONFIG_H__
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#include <rtthread.h>
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#include "stm32l1xx_hal.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifdef BSP_USING_SDIO
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#define SDIO_BUS_CONFIG \
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{ \
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.Instance = SDIO, \
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.dma_rx.dma_rcc = RCC_AHBENR_DMA2EN, \
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.dma_tx.dma_rcc = RCC_AHBENR_DMA2EN, \
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.dma_rx.Instance = DMA2_Channel4, \
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.dma_rx.dma_irq = DMA2_Channel4_IRQn, \
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.dma_tx.Instance = DMA2_Channel4, \
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.dma_tx.dma_irq = DMA2_Channel4_IRQn, \
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}
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /*__SDIO_CONFIG_H__ */
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