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BernardXiongBernardXiong
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Merge pull request #3295 from ChazJin/patch-3
Fix bug for synopsys_emac.c
2 parents 38cb953 + 728e1d9 commit 891e479

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‎bsp/gd32450z-eval/drivers/synopsys_emac.c‎

Lines changed: 12 additions & 132 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,10 @@
1818
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
1919
*/
2020
#include "synopsys_emac.h"
21+
#include "gd32f4xx_enet.h"
22+
23+
/* The state of enet initialization */
24+
volatile uint32_t enet_init_state = 0;
2125

2226
/* Global pointers on Tx and Rx descriptor used to track transmit and receive descriptors */
2327
extern EMAC_DMADESCTypeDef *DMATxDescToSet;
@@ -28,139 +32,15 @@ extern EMAC_DMADESCTypeDef *DMARxDescToGet;
2832
*/
2933
rt_uint32_t EMAC_init(struct rt_synopsys_eth * ETHERNET_MAC, rt_uint32_t SystemCoreClock)
3034
{
31-
rt_uint32_t value = 0;
32-
33-
/*-------------------------------- MAC Config ------------------------------*/
34-
/*---------------------- ETHERNET MACMIIAR Configuration -------------------*/
35-
/* Get the ETHERNET MACMIIAR value */
36-
value = ETHERNET_MAC->GAR;
37-
/* Clear CSR Clock Range CR[2:0] bits */
38-
value &= MACMIIAR_CR_MASK;
39-
40-
/* Get hclk frequency value */
41-
/* Set CR bits depending on hclk value */
42-
if((SystemCoreClock >= 20000000)&&(SystemCoreClock < 35000000))
43-
{
44-
/* CSR Clock Range between 20-35 MHz */
45-
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div16;
46-
}
47-
else if((SystemCoreClock >= 35000000)&&(SystemCoreClock < 60000000))
48-
{
49-
/* CSR Clock Range between 35-60 MHz */
50-
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div26;
51-
}
52-
else if((SystemCoreClock >= 60000000)&&(SystemCoreClock <= 100000000))
53-
{
54-
/* CSR Clock Range between 60-100 MHz */
55-
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div42;
56-
}
57-
else if((SystemCoreClock >= 100000000)&&(SystemCoreClock <= 150000000))
58-
{
59-
/* CSR Clock Range between 100-150 MHz */
60-
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div62;
61-
}
62-
else if((SystemCoreClock >= 150000000)&&(SystemCoreClock <= 250000000))
63-
{
64-
/* CSR Clock Range between 150-250 MHz */
65-
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div102;
66-
}
67-
else /* if((SystemCoreClock >= 250000000)&&(SystemCoreClock <= 300000000)) */
68-
{
69-
/* CSR Clock Range between 250-300 MHz */
70-
value |= (rt_uint32_t)EMAC_MACMIIAR_CR_Div122;
71-
}
72-
/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
73-
ETHERNET_MAC->GAR = (rt_uint32_t)value;
74-
75-
/*------------------------ ETHERNET MACCR Configuration --------------------*/
76-
/* Get the ETHERNET MACCR value */
77-
value = ETHERNET_MAC->MCR;
78-
/* Clear WD, PCE, PS, TE and RE bits */
79-
value &= MACCR_CLEAR_MASK;
80-
81-
value |= (rt_uint32_t)(EMAC_Watchdog_Enable |
82-
EMAC_Jabber_Enable |
83-
EMAC_InterFrameGap_96Bit |
84-
EMAC_CarrierSense_Enable |
85-
EMAC_Speed_100M |
86-
EMAC_ReceiveOwn_Enable |
87-
EMAC_LoopbackMode_Disable |
88-
EMAC_Mode_FullDuplex |
89-
EMAC_ChecksumOffload_Enable |
90-
EMAC_RetryTransmission_Disable |
91-
EMAC_AutomaticPadCRCStrip_Disable |
92-
EMAC_BackOffLimit_10 |
93-
EMAC_DeferralCheck_Disable);
94-
95-
/* Write to ETHERNET MACCR */
96-
value |= (1<<15);
97-
value &= ~(1<<25);
98-
value &= ~(1<<24);
99-
ETHERNET_MAC->MCR = (rt_uint32_t)value;
100-
101-
/*----------------------- ETHERNET MACFFR Configuration --------------------*/
102-
/* Write to ETHERNET MACFFR */
103-
ETHERNET_MAC->MFFR = (rt_uint32_t)(EMAC_ReceiveAll_Enable |
104-
EMAC_SourceAddrFilter_Disable |
105-
EMAC_PassControlFrames_BlockAll |
106-
EMAC_BroadcastFramesReception_Disable |
107-
EMAC_DestinationAddrFilter_Normal |
108-
EMAC_PromiscuousMode_Disable |
109-
EMAC_MulticastFramesFilter_Perfect |
110-
EMAC_UnicastFramesFilter_Perfect);
111-
112-
/*--------------- ETHERNET MACHTHR and MACHTLR Configuration ---------------*/
113-
/* Write to ETHERNET MACHTHR */
114-
ETHERNET_MAC->MHTRH = 0;
115-
/* Write to ETHERNET MACHTLR */
116-
ETHERNET_MAC->MHTRL = 0;
117-
/*----------------------- ETHERNET MACFCR Configuration --------------------*/
118-
/* Get the ETHERNET MACFCR value */
119-
value = ETHERNET_MAC->FCR;
120-
/* Clear xx bits */
121-
value &= MACFCR_CLEAR_MASK;
122-
123-
value |= (rt_uint32_t)((0 << 16) |
124-
EMAC_ZeroQuantaPause_Disable |
125-
EMAC_PauseLowThreshold_Minus4 |
126-
EMAC_UnicastPauseFrameDetect_Disable |
127-
EMAC_ReceiveFlowControl_Disable |
128-
EMAC_TransmitFlowControl_Disable);
129-
130-
/* Write to ETHERNET MACFCR */
131-
ETHERNET_MAC->FCR = (rt_uint32_t)value;
132-
/*----------------------- ETHERNET MACVLANTR Configuration -----------------*/
133-
ETHERNET_MAC->VTR = (rt_uint32_t)(EMAC_VLANTagComparison_16Bit |
134-
0);
135-
136-
/*-------------------------------- DMA Config ------------------------------*/
137-
/*----------------------- ETHERNET DMAOMR Configuration --------------------*/
138-
/* Get the ETHERNET DMAOMR value */
139-
value = ETHERNET_MAC->OMR;
140-
/* Clear xx bits */
141-
value &= DMAOMR_CLEAR_MASK;
142-
143-
value |= (rt_uint32_t)(EMAC_DropTCPIPChecksumErrorFrame_Disable |
144-
EMAC_ReceiveStoreForward_Enable |
145-
EMAC_FlushReceivedFrame_Enable |
146-
EMAC_TransmitStoreForward_Enable |
147-
EMAC_TransmitThresholdControl_64Bytes |
148-
EMAC_ForwardErrorFrames_Disable |
149-
EMAC_ForwardUndersizedGoodFrames_Disable |
150-
EMAC_ReceiveThresholdControl_64Bytes |
151-
EMAC_SecondFrameOperate_Disable);
35+
/*-------------------------------- Reset ethernet -------------------------------*/
36+
enet_deinit();
37+
enet_software_reset();
15238

153-
/* Write to ETHERNET DMAOMR */
154-
ETHERNET_MAC->OMR = (rt_uint32_t)value;
39+
/* configure the parameters which are usually less cared for enet initialization */
40+
enet_initpara_config(HALFDUPLEX_OPTION, ENET_CARRIERSENSE_DISABLE|ENET_RECEIVEOWN_ENABLE|ENET_RETRYTRANSMISSION_DISABLE|ENET_BACKOFFLIMIT_10|ENET_DEFERRALCHECK_DISABLE);
15541

156-
/*----------------------- ETHERNET DMABMR Configuration --------------------*/
157-
ETHERNET_MAC->BMR = (rt_uint32_t)(EMAC_AddressAlignedBeats_Enable |
158-
EMAC_FixedBurst_Enable |
159-
EMAC_RxDMABurstLength_32Beat | /* !! if 4xPBL is selected for Tx or Rx it is applied for the other */
160-
EMAC_TxDMABurstLength_32Beat |
161-
(0 << 2) |
162-
EMAC_DMAArbitration_RoundRobin_RxTx_2_1 |
163-
EMAC_DMABMR_USP); /* Enable use of separate PBL for Rx and Tx */
42+
/*-------------------------------- Initialize ENET ------------------------------*/
43+
enet_init_state = enet_init(ENET_AUTO_NEGOTIATION, ENET_AUTOCHECKSUM_DROP_FAILFRAMES, ENET_BROADCAST_FRAMES_PASS);
16444

16545
/* Return Ethernet configuration success */
16646
return EMAC_SUCCESS;
@@ -288,7 +168,7 @@ void EMAC_start(struct rt_synopsys_eth * ETHERNET_MAC)
288168
/* Enable transmit state machine of the MAC for transmission on the MII */
289169
EMAC_MACTransmissionCmd(ETHERNET_MAC, RT_TRUE);
290170
/* Flush Transmit FIFO */
291-
EMAC_FlushTransmitFIFO(ETHERNET_MAC);
171+
enet_txfifo_flush();
292172
/* Enable receive state machine of the MAC for reception from the MII */
293173
EMAC_MACReceptionCmd(ETHERNET_MAC, RT_TRUE);
294174

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