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HuangboNo2HuangboNo2
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修改汇编rt_hw_context_switch_to处关于时间槽的使用；修改格式
1 parent bed7dac commit 8ab19db

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4 files changed

+63
-65
lines changed

4 files changed

+63
-65
lines changed

‎libcpu/ti-dsp/c6x/context.asm‎

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -136,15 +136,14 @@ rt_hw_context_switch_to:
136136
;
137137
; this maybe do better
138138
;
139-
MVC .S2 B11,RILC ; Restore RILC
140-
MVC .S2 B10,ILC ; Restore ILC
141-
MV B13,B3 ; Restore PC
142-
MVC .S2 B12,CSR ; Restore CSR
143-
144139
LDDW .D2T2 *++SP[1],B11:B10
140+
|| MVC .S2 B11,RILC ; Restore RILC
145141
LDDW .D2T2 *++SP[1],B13:B12
142+
|| MVC .S2 B10,ILC ; Restore ILC
146143
LDDW .D2T1 *++SP[1],A11:A10
144+
|| MV B13,B3 ; Restore PC
147145
LDDW .D2T1 *++SP[1],A13:A12
146+
|| MVC .S2 B12,CSR ; Restore CSR
148147
LDDW .D2T1 *++SP[1],A15:A14
149148
B B3 ; Return to caller
150149
ADDAW .D2 SP,2,SP
@@ -236,7 +235,6 @@ _reswitch:
236235
.global rt_interrupt_context_restore
237236
rt_interrupt_context_restore:
238237
;{
239-
; if rt_switch_interrupt_flag set, jump to rt_hw_context_switch_interrupt and don't return
240238
MVKL rt_thread_switch_interrupt_flag,A3
241239
MVKH rt_thread_switch_interrupt_flag,A3
242240
LDW *A3,A1

‎libcpu/ti-dsp/c6x/contextinc.asm‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ SAVE_ALL .macro __rp, __tsr
1919

2020
NOP 3
2121
STW .D2T2 B1,*+SP[1] ; save original B1
22-
XOR .D2 SP,B1,B0 ; (SP ^ KSP, check current stack types)
22+
XOR .D2 SP,B1,B0 ; check current stack types
2323
LDW .D2T2 *+SP[1],B1 ; restore B0/B1
2424
LDW .D2T2 *++SP[2],B0
2525
SHR .S2 B0,12,B0 ; 0 if already using system stack
@@ -75,7 +75,7 @@ SAVE_ALL .macro __rp, __tsr
7575

7676
STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
7777
STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
78-
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4
78+
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
7979
.endm
8080

8181
RESTORE_ALL .macro __rp, __tsr
@@ -183,5 +183,5 @@ THREAD_SAVE_ALL .macro __rp, __tsr
183183

184184
STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
185185
STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
186-
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4
186+
STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4(stack type)
187187
.endm

‎libcpu/ti-dsp/c6x/intexc.asm‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
;
1010

1111
;-----------------------------------------------------------
12-
; interrupt and execption handler for C000 DSP
12+
; interrupt and execption handler for C6000 DSP
1313
;-----------------------------------------------------------
1414

1515
;-----------------------------------------------------------
@@ -94,7 +94,7 @@ RT_EXECPTION_ENTRY .macro
9494

9595
RT_EXECPTION_EXIT .macro
9696
RESTORE_ALL NRP,NTSR
97-
B .S2 NRP ; return from interruption
97+
B .S2 NRP ; return from execption
9898
NOP 5
9999
.endm
100100

@@ -137,7 +137,7 @@ ret_from_trap:
137137
[!B0] MVKH .S2 ret_from_exception,B3
138138
[!B0] BNOP .S2 B3,5
139139
;
140-
; return from trap£¬restore exception context
140+
; return from trap restore exception context
141141
;
142142
ret_from_exception:
143143
RT_EXECPTION_EXIT

‎libcpu/ti-dsp/c6x/stack.asm‎

Lines changed: 53 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -35,73 +35,73 @@ ADDRESS_MSK .set 0xFFFFFFF0
3535
;{
3636
.global rt_hw_stack_init
3737
rt_hw_stack_init:
38-
SUB A6,1,B1 ;
39-
MVKL ADDRESS_MSK,A1 ;
40-
MVKH ADDRESS_MSK,A1 ; Build address mask
41-
MVC CSR,B0 ;
42-
AND -2,B0,B0 ; Clear GIE bit
43-
OR 2,B0,B0 ; Set PGIE bit for interrupt return
44-
AND A1,B1,B1 ; Ensure alignment
38+
SUB A6,1,B1 ;
39+
MVKL .S1 ADDRESS_MSK,A1 ;
40+
MVKH .S1 ADDRESS_MSK,A1 ; Build address mask
41+
MVC .S2 CSR,B0 ;
42+
AND -2,B0,B0 ; Clear GIE bit
43+
OR 2,B0,B0 ; Set PGIE bit for interrupt return
44+
AND A1,B1,B1 ; Ensure alignment
4545
;
4646
; Actually build the stack frame.
4747
;
48-
MV B1,A3
49-
MV B14,A2
50-
STDW A3:A2,*--B1[1] ; Initial B15:B14
48+
MV .S1 B1,A3
49+
MV .S1 B14,A2
50+
STDW .D2T1 A3:A2,*--B1[1] ; Initial B15:B14
5151
SUBAW .D2 B1,2,B1
5252
ZERO A2
53-
ZERO A3 ; Clear value
54-
STDW A3:A2,*B1--[1] ; Initial A15:A14
55-
STDW A3:A2,*B1--[1] ; Initial A13:A12
56-
STDW A3:A2,*B1--[1] ; Initial A11:A10
57-
STDW A3:A2,*B1--[1] ; Initial A9:A8
58-
STDW A3:A2,*B1--[1] ; Initial A7:A6
59-
MV B4,A2
60-
STDW A3:A2,*B1--[1] ; Initial A5:A4
53+
ZERO A3 ; Clear value
54+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A15:A14
55+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A13:A12
56+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A11:A10
57+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A9:A8
58+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A7:A6
59+
MV .S1 B4,A2
60+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A5:A4
6161
ZERO A2
62-
STDW A3:A2,*B1--[1] ; Initial A3:A2
63-
STDW A3:A2,*B1--[1] ; Initial A1:A0
62+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A3:A2
63+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A1:A0
6464

65-
STDW A3:A2,*B1--[1] ; Initial A31:A30
66-
STDW A3:A2,*B1--[1] ; Initial A29:A28
67-
STDW A3:A2,*B1--[1] ; Initial A27:A26
68-
STDW A3:A2,*B1--[1] ; Initial A25:A24
69-
STDW A3:A2,*B1--[1] ; Initial A23:A22
70-
STDW A3:A2,*B1--[1] ; Initial A21:A20
71-
STDW A3:A2,*B1--[1] ; Initial A19:A18
72-
STDW A3:A2,*B1--[1] ; Initial A17:A16
65+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A31:A30
66+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A29:A28
67+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A27:A26
68+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A25:A24
69+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A23:A22
70+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A21:A20
71+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A19:A18
72+
STDW .D2T1 A3:A2,*B1--[1] ; Initial A17:A16
7373

74-
STDW A3:A2,*B1--[1] ; Initial B13:B12
75-
STDW A3:A2,*B1--[1] ; Initial B11:B10
76-
STDW A3:A2,*B1--[1] ; Initial B9:B8
77-
STDW A3:A2,*B1--[1] ; Initial B7:B6
78-
STDW A3:A2,*B1--[1] ; Initial B5:B4
79-
MV B6,A3
80-
STDW A3:A2,*B1--[1] ; Initial B3:B2
74+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B13:B12
75+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B11:B10
76+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B9:B8
77+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B7:B6
78+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B5:B4
79+
MV .S1 B6,A3
80+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B3:B2
8181
ZERO A3
82-
STDW A3:A2,*B1--[1] ; Initial B1:B0
82+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B1:B0
8383

84-
STDW A3:A2,*B1--[1] ; Initial B31:B30
85-
STDW A3:A2,*B1--[1] ; Initial B29:B28
86-
STDW A3:A2,*B1--[1] ; Initial B27:B26
87-
STDW A3:A2,*B1--[1] ; Initial B25:B24
88-
STDW A3:A2,*B1--[1] ; Initial B23:B22
89-
STDW A3:A2,*B1--[1] ; Initial B21:B20
90-
STDW A3:A2,*B1--[1] ; Initial B19:B18
91-
STDW A3:A2,*B1--[1] ; Initial B17:B16
84+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B31:B30
85+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B29:B28
86+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B27:B26
87+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B25:B24
88+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B23:B22
89+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B21:B20
90+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B19:B18
91+
STDW .D2T1 A3:A2,*B1--[1] ; Initial B17:B16
9292

93-
MV A4,A3
94-
MV B0,A2
95-
STDW A3:A2,*B1--[1] ; Initial PC:CSR
93+
MV .S1 A4,A3
94+
MV .S1 B0,A2
95+
STDW .D2T1 A3:A2,*B1--[1] ; Initial PC:CSR
9696

9797
ZERO A2
9898
ZERO A3
99-
STDW A3:A2,*B1--[1] ; Initial ILC:RILC
99+
STDW .D2T1 A3:A2,*B1--[1] ; Initial ILC:RILC
100100
B B3
101-
MVKL 0x3,B0
102-
MV B0,A3
103-
MVKL 1,A2
104-
STDW A3:A2,*B1--[1] ; Initial TSR:stack type
105-
MV B1,A4 ; Save to TCB
101+
MVKL .S2 0x3,B0
102+
MV .S1 B0,A3
103+
MVKL .S1 1,A2
104+
STDW .D2T1 A3:A2,*B1--[1] ; Initial TSR:stack type
105+
MV .S1 B1,A4 ; Save to TCB
106106
;}
107107
.end

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