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| 1 | +/* |
| 2 | + * File : gpio.c |
| 3 | + * This file is part of RT-Thread RTOS |
| 4 | + * COPYRIGHT (C) 2015, RT-Thread Development Team |
| 5 | + * |
| 6 | + * The license and distribution terms for this file may be |
| 7 | + * found in the file LICENSE in this distribution or at |
| 8 | + * http://www.rt-thread.org/license/LICENSE |
| 9 | + * |
| 10 | + * Change Logs: |
| 11 | + * Date Author Notes |
| 12 | + * 2015-01-05 Bernard the first version |
| 13 | + */ |
| 14 | + |
| 15 | +#include <rthw.h> |
| 16 | +#include <rtdevice.h> |
| 17 | +#include <board.h> |
| 18 | + |
| 19 | +#ifdef RT_USING_PIN |
| 20 | + |
| 21 | +/* STM32 GPIO driver */ |
| 22 | +struct pin_index |
| 23 | +{ |
| 24 | + int index; |
| 25 | + uint32_t rcc; |
| 26 | + GPIO_TypeDef *gpio; |
| 27 | + uint32_t pin; |
| 28 | +}; |
| 29 | + |
| 30 | +static const struct pin_index pins[] = |
| 31 | +{ |
| 32 | + { 0, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_7}, |
| 33 | + { 1, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_6}, |
| 34 | + { 2, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_8}, |
| 35 | + { 3, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_11}, |
| 36 | + { 4, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_14}, |
| 37 | + { 5, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_13}, |
| 38 | + { 6, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_11}, |
| 39 | + { 7, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_9}, |
| 40 | + |
| 41 | + { 8, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_12}, |
| 42 | + { 9, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_13}, |
| 43 | + {10, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_14}, |
| 44 | + {11, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_15}, |
| 45 | + {12, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_6}, |
| 46 | + {13, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_5}, |
| 47 | + |
| 48 | + {14, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_8}, |
| 49 | + {15, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_9}, |
| 50 | + {16, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_5}, |
| 51 | + {17, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_6}, |
| 52 | + {18, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_6}, |
| 53 | + {19, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_7}, |
| 54 | + {20, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_9}, |
| 55 | + {21, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_8}, |
| 56 | + |
| 57 | + {22, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_12}, |
| 58 | + {23, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_2}, |
| 59 | + {24, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_1}, |
| 60 | + {25, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_0}, |
| 61 | + {26, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_9}, |
| 62 | + {27, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_13}, |
| 63 | + {28, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_15}, |
| 64 | + {29, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_12}, |
| 65 | + {30, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_10}, |
| 66 | + {31, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_8}, |
| 67 | + {32, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_7}, |
| 68 | + {33, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_4}, |
| 69 | + {34, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_3}, |
| 70 | + {35, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_2}, |
| 71 | + {36, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_1}, |
| 72 | + {37, RCC_AHB1Periph_GPIOE, GPIOE, GPIO_Pin_0}, |
| 73 | + {38, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_11}, |
| 74 | + {39, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_10}, |
| 75 | + {40, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_7}, |
| 76 | + {41, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_3}, |
| 77 | + {42, RCC_AHB1Periph_GPIOD, GPIOD, GPIO_Pin_4}, |
| 78 | + {43, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_8}, |
| 79 | + {44, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_15}, |
| 80 | + {45, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_14}, |
| 81 | + {46, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_11}, |
| 82 | + {47, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_5}, |
| 83 | + {48, RCC_AHB1Periph_GPIOC, GPIOC, GPIO_Pin_10}, |
| 84 | + {49, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_15}, |
| 85 | + {50, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_4}, |
| 86 | + {51, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_7}, |
| 87 | + {52, RCC_AHB1Periph_GPIOB, GPIOB, GPIO_Pin_3}, |
| 88 | + {53, RCC_AHB1Periph_GPIOA, GPIOA, GPIO_Pin_4}, |
| 89 | +}; |
| 90 | + |
| 91 | +#define ITEM_NUM(items) sizeof(items)/sizeof(items[0]) |
| 92 | +const struct pin_index * get_pin(uint8_t pin) |
| 93 | +{ |
| 94 | + const struct pin_index* index; |
| 95 | + |
| 96 | + if(pin < ITEM_NUM(pins)) |
| 97 | + { |
| 98 | + index = &pins[pin]; |
| 99 | + } |
| 100 | + else |
| 101 | + { |
| 102 | + index = RT_NULL; |
| 103 | + } |
| 104 | + |
| 105 | + return index; |
| 106 | +}; |
| 107 | + |
| 108 | +void stm32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) |
| 109 | +{ |
| 110 | + const struct pin_index *index; |
| 111 | + |
| 112 | + index = get_pin(pin); |
| 113 | + if(index == RT_NULL) |
| 114 | + { |
| 115 | + return; |
| 116 | + } |
| 117 | + |
| 118 | + if(value == PIN_LOW) |
| 119 | + { |
| 120 | + GPIO_ResetBits(index->gpio, index->pin); |
| 121 | + } |
| 122 | + else |
| 123 | + { |
| 124 | + GPIO_SetBits(index->gpio, index->pin); |
| 125 | + } |
| 126 | +} |
| 127 | + |
| 128 | +int stm32_pin_read(rt_device_t dev, rt_base_t pin) |
| 129 | +{ |
| 130 | + int value; |
| 131 | + const struct pin_index *index; |
| 132 | + |
| 133 | + value = PIN_LOW; |
| 134 | + |
| 135 | + index = get_pin(pin); |
| 136 | + if(index == RT_NULL) |
| 137 | + { |
| 138 | + return value; |
| 139 | + } |
| 140 | + |
| 141 | + if(GPIO_ReadInputDataBit(index->gpio, index->pin) == Bit_RESET) |
| 142 | + { |
| 143 | + value = PIN_LOW; |
| 144 | + } |
| 145 | + else |
| 146 | + { |
| 147 | + value = PIN_HIGH; |
| 148 | + } |
| 149 | + |
| 150 | + return value; |
| 151 | +} |
| 152 | + |
| 153 | +void stm32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) |
| 154 | +{ |
| 155 | + const struct pin_index *index; |
| 156 | + GPIO_InitTypeDef GPIO_InitStructure; |
| 157 | + |
| 158 | + index = get_pin(pin); |
| 159 | + if(index == RT_NULL) |
| 160 | + { |
| 161 | + return; |
| 162 | + } |
| 163 | + |
| 164 | + /* GPIO Periph clock enable */ |
| 165 | + RCC_AHB1PeriphClockCmd(index->rcc, ENABLE); |
| 166 | + |
| 167 | + /* Configure GPIO_InitStructure */ |
| 168 | + GPIO_InitStructure.GPIO_Pin = index->pin; |
| 169 | + GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; |
| 170 | + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz; |
| 171 | + |
| 172 | + if(mode == PIN_MODE_OUTPUT) |
| 173 | + { |
| 174 | + /* output setting */ |
| 175 | + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; |
| 176 | + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; |
| 177 | + } |
| 178 | + else if(mode == PIN_MODE_INPUT) |
| 179 | + { |
| 180 | + /* input setting: not pull. */ |
| 181 | + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; |
| 182 | + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; |
| 183 | + } |
| 184 | + else if(mode == PIN_MODE_INPUT_PULLUP) |
| 185 | + { |
| 186 | + /* input setting: pull up. */ |
| 187 | + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; |
| 188 | + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; |
| 189 | + } |
| 190 | + else |
| 191 | + { |
| 192 | + /* input setting:default. */ |
| 193 | + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN; |
| 194 | + GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_DOWN; |
| 195 | + } |
| 196 | + GPIO_Init(index->gpio, &GPIO_InitStructure); |
| 197 | +} |
| 198 | + |
| 199 | +const static struct rt_pin_ops _stm32_pin_ops = |
| 200 | +{ |
| 201 | + stm32_pin_mode, |
| 202 | + stm32_pin_write, |
| 203 | + stm32_pin_read, |
| 204 | +}; |
| 205 | + |
| 206 | +int stm32_hw_pin_init(void) |
| 207 | +{ |
| 208 | + rt_device_pin_register("pin", &_stm32_pin_ops, RT_NULL); |
| 209 | + return 0; |
| 210 | +} |
| 211 | +INIT_BOARD_EXPORT(stm32_hw_pin_init); |
| 212 | + |
| 213 | +#endif |
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