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20 files changed

+1140
-1212
lines changed

20 files changed

+1140
-1212
lines changed

‎bsp/ls2kdev/drivers/board.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@
1515

1616
extern unsigned char __bss_end;
1717

18-
#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000
18+
#define CPU_HZ (1000 * 1000 * 1000) //QEMU 200*1000*1000
1919
#define RT_HW_HEAP_BEGIN (void*)&__bss_end
2020
#define RT_HW_HEAP_END (void*)(RT_HW_HEAP_BEGIN + 64 * 1024 * 1024)
2121

‎bsp/ls2kdev/drivers/clk.c‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@
1414
#include <rtthread.h>
1515
#include "ls2k1000.h"
1616

17-
1817
struct loongson_pll {
1918
rt_uint64_t PLL_SYS_0;
2019
rt_uint64_t PLL_SYS_1;

‎bsp/ls2kdev/drivers/drv_gpio.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
* Change Logs:
66
* Date Author Notes
77
* 2015-01-20 Bernard the first version
8-
* 2017-10-20 ZYH add mode open drain and input pull down
9-
* 2020-06-01 Du Huanpeng GPIO driver based on <components/drivers/include/drivers/pin.h>
8+
* 2017-10-20 ZYH add mode open drain and input pull down
9+
* 2020-06-01 Du Huanpeng GPIO driver based on <components/drivers/include/drivers/pin.h>
1010
*/
1111
#include <rtthread.h>
1212
#include <drivers/pin.h>

‎bsp/ls2kdev/drivers/drv_gpio.h‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@
66
*
77
* Change Logs:
88
* Date Author Notes
9-
* 2017-11-24 勤为本 first version
9+
* 2017-11-24 勤为本 first version
1010
* 2018-05-11 zhuangwei add gpio interrupt ops
1111
*/
1212

@@ -36,6 +36,5 @@ struct loongson_gpio {
3636

3737
int loongson_pin_init(void);
3838

39-
4039
#endif
4140

‎bsp/ls2kdev/drivers/drv_uart.h‎

Lines changed: 74 additions & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -15,100 +15,99 @@
1515
#include <rthw.h>
1616

1717
/* UART registers */
18-
#define UART_DAT(base) HWREG8(base + 0x00)
19-
#define UART_IER(base) HWREG8(base + 0x01)
20-
#define UART_IIR(base) HWREG8(base + 0x02)
21-
#define UART_FCR(base) HWREG8(base + 0x02)
22-
#define UART_LCR(base) HWREG8(base + 0x03)
23-
#define UART_MCR(base) HWREG8(base + 0x04)
24-
#define UART_LSR(base) HWREG8(base + 0x05)
25-
#define UART_MSR(base) HWREG8(base + 0x06)
18+
#define UART_DAT(base) HWREG8(base + 0x00)
19+
#define UART_IER(base) HWREG8(base + 0x01)
20+
#define UART_IIR(base) HWREG8(base + 0x02)
21+
#define UART_FCR(base) HWREG8(base + 0x02)
22+
#define UART_LCR(base) HWREG8(base + 0x03)
23+
#define UART_MCR(base) HWREG8(base + 0x04)
24+
#define UART_LSR(base) HWREG8(base + 0x05)
25+
#define UART_MSR(base) HWREG8(base + 0x06)
2626

27-
#define UART_LSB(base) HWREG8(base + 0x00)
28-
#define UART_MSB(base) HWREG8(base + 0x01)
27+
#define UART_LSB(base) HWREG8(base + 0x00)
28+
#define UART_MSB(base) HWREG8(base + 0x01)
2929

3030
/* interrupt enable register */
31-
#define IER_IRxE 0x1
32-
#define IER_ITxE 0x2
33-
#define IER_ILE 0x4
34-
#define IER_IME 0x8
31+
#define IER_IRxE 0x1
32+
#define IER_ITxE 0x2
33+
#define IER_ILE 0x4
34+
#define IER_IME 0x8
3535

3636
/* interrupt identification register */
37-
#define IIR_IMASK 0xf /* mask */
38-
#define IIR_RXTOUT 0xc /* receive timeout */
39-
#define IIR_RLS 0x6 /* receive line status */
40-
#define IIR_RXRDY 0x4 /* receive ready */
41-
#define IIR_TXRDY 0x2 /* transmit ready */
42-
#define IIR_NOPEND 0x1 /* nothing */
43-
#define IIR_MLSC 0x0 /* modem status */
44-
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
37+
#define IIR_IMASK 0xf /* mask */
38+
#define IIR_RXTOUT 0xc /* receive timeout */
39+
#define IIR_RLS 0x6 /* receive line status */
40+
#define IIR_RXRDY 0x4 /* receive ready */
41+
#define IIR_TXRDY 0x2 /* transmit ready */
42+
#define IIR_NOPEND 0x1 /* nothing */
43+
#define IIR_MLSC 0x0 /* modem status */
44+
#define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */
4545

4646
/* fifo control register */
47-
#define FIFO_ENABLE 0x01 /* enable fifo */
48-
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
49-
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
50-
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
51-
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
52-
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
53-
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
54-
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
47+
#define FIFO_ENABLE 0x01 /* enable fifo */
48+
#define FIFO_RCV_RST 0x02 /* reset receive fifo */
49+
#define FIFO_XMT_RST 0x04 /* reset transmit fifo */
50+
#define FIFO_DMA_MODE 0x08 /* enable dma mode */
51+
#define FIFO_TRIGGER_1 0x00 /* trigger at 1 char */
52+
#define FIFO_TRIGGER_4 0x40 /* trigger at 4 chars */
53+
#define FIFO_TRIGGER_8 0x80 /* trigger at 8 chars */
54+
#define FIFO_TRIGGER_14 0xc0 /* trigger at 14 chars */
5555

56-
// 线路控制寄存器
5756
/* character format control register */
58-
#define CFCR_DLAB 0x80 /* divisor latch */
59-
#define CFCR_SBREAK 0x40 /* send break */
60-
#define CFCR_PZERO 0x30 /* zero parity */
61-
#define CFCR_PONE 0x20 /* one parity */
62-
#define CFCR_PEVEN 0x10 /* even parity */
63-
#define CFCR_PODD 0x00 /* odd parity */
64-
#define CFCR_PENAB 0x08 /* parity enable */
65-
#define CFCR_STOPB 0x04 /* 2 stop bits */
66-
#define CFCR_8BITS 0x03 /* 8 data bits */
67-
#define CFCR_7BITS 0x02 /* 7 data bits */
68-
#define CFCR_6BITS 0x01 /* 6 data bits */
69-
#define CFCR_5BITS 0x00 /* 5 data bits */
57+
#define CFCR_DLAB 0x80 /* divisor latch */
58+
#define CFCR_SBREAK 0x40 /* send break */
59+
#define CFCR_PZERO 0x30 /* zero parity */
60+
#define CFCR_PONE 0x20 /* one parity */
61+
#define CFCR_PEVEN 0x10 /* even parity */
62+
#define CFCR_PODD 0x00 /* odd parity */
63+
#define CFCR_PENAB 0x08 /* parity enable */
64+
#define CFCR_STOPB 0x04 /* 2 stop bits */
65+
#define CFCR_8BITS 0x03 /* 8 data bits */
66+
#define CFCR_7BITS 0x02 /* 7 data bits */
67+
#define CFCR_6BITS 0x01 /* 6 data bits */
68+
#define CFCR_5BITS 0x00 /* 5 data bits */
7069

7170
/* modem control register */
72-
#define MCR_LOOPBACK 0x10 /* loopback */
73-
#define MCR_IENABLE 0x08 /* output 2 = int enable */
74-
#define MCR_DRS 0x04 /* output 1 = xxx */
75-
#define MCR_RTS 0x02 /* enable RTS */
76-
#define MCR_DTR 0x01 /* enable DTR */
71+
#define MCR_LOOPBACK 0x10 /* loopback */
72+
#define MCR_IENABLE 0x08 /* output 2 = int enable */
73+
#define MCR_DRS 0x04 /* output 1 = xxx */
74+
#define MCR_RTS 0x02 /* enable RTS */
75+
#define MCR_DTR 0x01 /* enable DTR */
7776

7877
/* line status register */
79-
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
80-
#define LSR_TSRE 0x40 /* transmitter empty */
81-
#define LSR_TXRDY 0x20 /* transmitter ready */
82-
#define LSR_BI 0x10 /* break detected */
83-
#define LSR_FE 0x08 /* framing error */
84-
#define LSR_PE 0x04 /* parity error */
85-
#define LSR_OE 0x02 /* overrun error */
86-
#define LSR_RXRDY 0x01 /* receiver ready */
87-
#define LSR_RCV_MASK 0x1f
78+
#define LSR_RCV_FIFO 0x80 /* error in receive fifo */
79+
#define LSR_TSRE 0x40 /* transmitter empty */
80+
#define LSR_TXRDY 0x20 /* transmitter ready */
81+
#define LSR_BI 0x10 /* break detected */
82+
#define LSR_FE 0x08 /* framing error */
83+
#define LSR_PE 0x04 /* parity error */
84+
#define LSR_OE 0x02 /* overrun error */
85+
#define LSR_RXRDY 0x01 /* receiver ready */
86+
#define LSR_RCV_MASK 0x1f
8887

8988

9089
/* UART interrupt enable register value */
91-
#define UARTIER_IME (1 << 3)
92-
#define UARTIER_ILE (1 << 2)
93-
#define UARTIER_ITXE (1 << 1)
94-
#define UARTIER_IRXE (1 << 0)
90+
#define UARTIER_IME (1 << 3)
91+
#define UARTIER_ILE (1 << 2)
92+
#define UARTIER_ITXE (1 << 1)
93+
#define UARTIER_IRXE (1 << 0)
9594

9695
/* UART line control register value */
97-
#define UARTLCR_DLAB (1 << 7)
98-
#define UARTLCR_BCB (1 << 6)
99-
#define UARTLCR_SPB (1 << 5)
100-
#define UARTLCR_EPS (1 << 4)
101-
#define UARTLCR_PE (1 << 3)
102-
#define UARTLCR_SB (1 << 2)
96+
#define UARTLCR_DLAB (1 << 7)
97+
#define UARTLCR_BCB (1 << 6)
98+
#define UARTLCR_SPB (1 << 5)
99+
#define UARTLCR_EPS (1 << 4)
100+
#define UARTLCR_PE (1 << 3)
101+
#define UARTLCR_SB (1 << 2)
103102

104103
/* UART line status register value */
105-
#define UARTLSR_ERROR (1 << 7)
106-
#define UARTLSR_TE (1 << 6)
107-
#define UARTLSR_TFE (1 << 5)
108-
#define UARTLSR_BI (1 << 4)
109-
#define UARTLSR_FE (1 << 3)
110-
#define UARTLSR_PE (1 << 2)
111-
#define UARTLSR_OE (1 << 1)
112-
#define UARTLSR_DR (1 << 0)
104+
#define UARTLSR_ERROR (1 << 7)
105+
#define UARTLSR_TE (1 << 6)
106+
#define UARTLSR_TFE (1 << 5)
107+
#define UARTLSR_BI (1 << 4)
108+
#define UARTLSR_FE (1 << 3)
109+
#define UARTLSR_PE (1 << 2)
110+
#define UARTLSR_OE (1 << 1)
111+
#define UARTLSR_DR (1 << 0)
113112

114113
#endif

‎bsp/ls2kdev/drivers/interrupt.h‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -64,22 +64,22 @@
6464
#define LS2K_GPIO2_INT_IRQ (62)
6565
#define LS2K_GPIO3_INT_IRQ (63)
6666

67-
#define MAX_INTR 64
68-
#define LIOINTC0_IRQBASE 0
69-
#define LIOINTC1_IRQBASE 32
67+
#define MAX_INTR (64)
68+
#define LIOINTC0_IRQBASE (0)
69+
#define LIOINTC1_IRQBASE (32)
7070

71-
#define LIOINTC_SHIFT_INTx 4
72-
#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
71+
#define LIOINTC_SHIFT_INTx (4)
72+
#define LIOINTC_COREx_INTy(x, y) ((1 << x) | (1 << (y + LIOINTC_SHIFT_INTx)))
7373

74-
#define LIOINTC_INTC_CHIP_START 0x20
74+
#define LIOINTC_INTC_CHIP_START 0x20
7575

76-
#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00)
77-
#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
78-
#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
79-
#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
80-
#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
81-
#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
76+
#define LIOINTC_REG_INTC_STATUS (LIOINTC_INTC_CHIP_START + 0x00)
77+
#define LIOINTC_REG_INTC_EN_STATUS (LIOINTC_INTC_CHIP_START + 0x04)
78+
#define LIOINTC_REG_INTC_ENABLE (LIOINTC_INTC_CHIP_START + 0x08)
79+
#define LIOINTC_REG_INTC_DISABLE (LIOINTC_INTC_CHIP_START + 0x0c)
80+
#define LIOINTC_REG_INTC_POL (LIOINTC_INTC_CHIP_START + 0x10)
81+
#define LIOINTC_REG_INTC_EDGE (LIOINTC_INTC_CHIP_START + 0x14)
8282

8383
void liointc_set_irq_mode(int irq, int mode);
8484

85-
#endif
85+
#endif

‎bsp/ls2kdev/drivers/ls2k1000.h‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -6,23 +6,23 @@
66

77
#define APB_BASE CKSEG1ADDR(0xbfe00000)
88

9-
#define UART0_BASE_ADDR 0xbfe00000
10-
#define UART0_OFF 0x0
11-
#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
9+
#define UART0_BASE_ADDR (0xbfe00000)
10+
#define UART0_OFF (0x0)
11+
#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
1212

13-
#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8)))
13+
#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8)))
1414

1515
#define LIOINTC0_BASE CKSEG1ADDR(0x1fe11400)
1616
#define CORE0_INTISR0 CKSEG1ADDR(0x1fe11040)
1717

1818
#define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440)
1919
#define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048)
2020

21-
#define GPIO_BASE 0xFFFFFFFFBFE10500
22-
#define PLL_SYS_BASE 0xFFFFFFFFBFE10480
23-
#define RTC_BASE 0xFFFFFFFFBFE07820
21+
#define GPIO_BASE (0xFFFFFFFFBFE10500)
22+
#define PLL_SYS_BASE (0xFFFFFFFFBFE10480)
23+
#define RTC_BASE (0xFFFFFFFFBFE07820)
2424

25-
#define GEN_CONFIG0_REG 0xFFFFFFFFBfe10420
25+
#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420)
2626

2727
void rt_hw_timer_handler(void);
2828
void rt_hw_uart_init(void);

‎bsp/ls2kdev/drivers/net/mii.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2006-2018, RT-Thread Development Team
2+
* Copyright (c) 2006-2020, RT-Thread Development Team
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*

‎bsp/ls2kdev/drivers/net/mii.h‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737

3838
/* Basic mode control register. */
3939
#define BMCR_RESV 0x003f /* Unused... */
40-
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
40+
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
4141
#define BMCR_CTST 0x0080 /* Collision test */
4242
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
4343
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
@@ -135,8 +135,8 @@
135135
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
136136
#define EXPANSION_RESV 0xffe0 /* Unused... */
137137

138-
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
139-
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
138+
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
139+
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
140140

141141
/* N-way test register. */
142142
#define NWAYTEST_RESV1 0x00ff /* Unused... */
@@ -170,11 +170,11 @@
170170

171171

172172
/* Which connector port. */
173-
#define PORT_TP 0x00
174-
#define PORT_AUI 0x01
175-
#define PORT_MII 0x02
176-
#define PORT_FIBRE 0x03
177-
#define PORT_BNC 0x04
173+
#define PORT_TP 0x00
174+
#define PORT_AUI 0x01
175+
#define PORT_MII 0x02
176+
#define PORT_FIBRE 0x03
177+
#define PORT_BNC 0x04
178178

179179
/* Which transceiver to use. */
180180
#define XCVR_INTERNAL 0x00
@@ -183,18 +183,18 @@
183183
#define XCVR_DUMMY2 0x03
184184
#define XCVR_DUMMY3 0x04
185185

186-
#define AUTONEG_DISABLE 0x00
187-
#define AUTONEG_ENABLE 0x01
186+
#define AUTONEG_DISABLE 0x00
187+
#define AUTONEG_ENABLE 0x01
188188

189189

190-
#define SPEED_10 10
191-
#define SPEED_100 100
192-
#define SPEED_1000 1000
193-
#define SPEED_2500 2500
194-
#define SPEED_10000 10000
190+
#define SPEED_10 10
191+
#define SPEED_100 100
192+
#define SPEED_1000 1000
193+
#define SPEED_2500 2500
194+
#define SPEED_10000 10000
195195

196-
#define DUPLEX_HALF 0x00
197-
#define DUPLEX_FULL 0x01
196+
#define DUPLEX_HALF 0x00
197+
#define DUPLEX_FULL 0x01
198198

199199
struct ethtool_cmd {
200200
u32 cmd;

‎bsp/ls2kdev/drivers/net/synopGMAC.c‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -260,7 +260,6 @@ s32 synopGMAC_check_phy_init(synopGMACPciNetworkAdapter *adapter)
260260
return gmacdev->Speed | (gmacdev->DuplexMode << 4);
261261
}
262262

263-
264263
static int Mac_change_check(u8 *macaddr0, u8 *macaddr1)
265264
{
266265
int i;
@@ -894,7 +893,6 @@ int rt_hw_eth_init(void)
894893
struct synopGMACNetworkAdapter *synopGMACadapter;
895894
static u8 mac_addr0[6] = DEFAULT_MAC_ADDRESS;
896895
int index;
897-
//rt_kprintf("rt_hw_eth_init 1\n");
898896
rt_sem_init(&sem_ack, "tx_ack", 1, RT_IPC_FLAG_FIFO);
899897
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
900898

@@ -958,8 +956,6 @@ int rt_hw_eth_init(void)
958956

959957
eth_device_init(&(eth_dev.parent), "e0");
960958
eth_device_linkchange(&eth_dev.parent, RT_TRUE); //linkup the e0 for lwip to check
961-
//rt_kprintf("rt_hw_eth_init 2\n");
962959
return 0;
963960
}
964-
965961
INIT_COMPONENT_EXPORT(rt_hw_eth_init);

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