Merge pull request #1714 from xeonxu/fix_pwm

lymzzyh · web-flow · commit b571cd8899ff · 2018-08-12T20:56:30.000+08:00
[STM32 BSP]Fix PWM channel calculate argorithm.
diff --git a/bsp/stm32f4xx-HAL/drivers/drv_pwm.c b/bsp/stm32f4xx-HAL/drivers/drv_pwm.c
@@ -38,18 +38,21 @@ static struct rt_pwm_ops drv_ops =
 
 static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)
 {
-    rt_uint32_t channel = 0x04 * configuration->channel;
+    rt_uint32_t channel = 0x04 * (configuration->channel - 1);
     if(!enable)
     {
         HAL_TIM_PWM_Stop(htim, channel);
     }
-    HAL_TIM_PWM_Start(htim, channel);
+    else
+    {
+        HAL_TIM_PWM_Start(htim, channel);
+    }
     return RT_EOK;
 }
 
 static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration)
 {
-    rt_uint32_t channel = 0x04 * configuration->channel;
+    rt_uint32_t channel = 0x04 * (configuration->channel - 1);
     rt_uint32_t tim_clock;
 #if (RT_HSE_HCLK > 100000000UL)//100M
     if(htim->Instance == TIM1 && htim->Instance == TIM8)
@@ -81,7 +84,7 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio
 {
     rt_uint32_t period, pulse;
     rt_uint32_t tim_clock, psc;
-    rt_uint32_t channel = 0x04 * configuration->channel;
+    rt_uint32_t channel = 0x04 * (configuration->channel - 1);
 #if (RT_HSE_HCLK > 100000000UL)//100M
     if(htim->Instance == TIM1 && htim->Instance == TIM8)
     {

Original file line number	Diff line number	Diff line change
`@@ -38,18 +38,21 @@ static struct rt_pwm_ops drv_ops =`
`38`	`38`
`39`	`39`	`static rt_err_t drv_pwm_enable(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration, rt_bool_t enable)`
`40`	`40`	`{`
`41`		`- rt_uint32_t channel = 0x04 * configuration->channel;`
	`41`	`+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);`
`42`	`42`	`if(!enable)`
`43`	`43`	`{`
`44`	`44`	`HAL_TIM_PWM_Stop(htim, channel);`
`45`	`45`	`}`
`46`		`- HAL_TIM_PWM_Start(htim, channel);`
	`46`	`+ else`
	`47`	`+ {`
	`48`	`+ HAL_TIM_PWM_Start(htim, channel);`
	`49`	`+ }`
`47`	`50`	`return RT_EOK;`
`48`	`51`	`}`
`49`	`52`
`50`	`53`	`static rt_err_t drv_pwm_get(TIM_HandleTypeDef * htim, struct rt_pwm_configuration *configuration)`
`51`	`54`	`{`
`52`		`- rt_uint32_t channel = 0x04 * configuration->channel;`
	`55`	`+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);`
`53`	`56`	`rt_uint32_t tim_clock;`
`54`	`57`	`#if (RT_HSE_HCLK > 100000000UL)//100M`
`55`	`58`	`if(htim->Instance == TIM1 && htim->Instance == TIM8)`
`@@ -81,7 +84,7 @@ static rt_err_t drv_pwm_set(TIM_HandleTypeDef * htim, struct rt_pwm_configuratio`
`81`	`84`	`{`
`82`	`85`	`rt_uint32_t period, pulse;`
`83`	`86`	`rt_uint32_t tim_clock, psc;`
`84`		`- rt_uint32_t channel = 0x04 * configuration->channel;`
	`87`	`+ rt_uint32_t channel = 0x04 * (configuration->channel - 1);`
`85`	`88`	`#if (RT_HSE_HCLK > 100000000UL)//100M`
`86`	`89`	`if(htim->Instance == TIM1 && htim->Instance == TIM8)`
`87`	`90`	`{`