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HuangboNo2HuangboNo2
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1 parent 466f9ad commit b8db37f

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2 files changed

+75
-73
lines changed

2 files changed

+75
-73
lines changed

‎bsp/ti-tms320c6678/applications/board.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
void rt_hw_board_init(void)
2222
{
2323
// initial CPU core
24-
keystone_cpu_init();
24+
keystone_cpu_init();
2525

2626
// initial interrupt controller
2727
rt_hw_interrupt_init();

‎bsp/ti-tms320c6678/common/common.c‎

Lines changed: 74 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -58,7 +58,7 @@ void reset_timer(int timer_num)
5858
{
5959
if(gpTimerRegs[timer_num]->TGCR)
6060
{
61-
gpTimerRegs[timer_num]->TGCR= 0;
61+
gpTimerRegs[timer_num]->TGCR = 0;
6262
gpTimerRegs[timer_num]->TCR= 0;
6363
}
6464
}
@@ -67,135 +67,137 @@ void timer64_init(Timer64_Config * tmrCfg)
6767
{
6868
reset_timer(tmrCfg->timer_num);
6969

70-
gpTimerRegs[tmrCfg->timer_num]->CNTLO= 0;
71-
gpTimerRegs[tmrCfg->timer_num]->CNTHI= 0;
70+
gpTimerRegs[tmrCfg->timer_num]->CNTLO = 0;
71+
gpTimerRegs[tmrCfg->timer_num]->CNTHI = 0;
7272

7373
/*please note, in clock mode, two timer periods generate a clock,
7474
one timer period output high voltage level, the other timer period
7575
output low voltage level, so, the timer period should be half to the
7676
desired output clock period*/
77-
if(TIMER_PERIODIC_CLOCK==tmrCfg->timerMode)
78-
tmrCfg->period= tmrCfg->period/2;
77+
if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
78+
{
79+
tmrCfg->period = tmrCfg->period/2;
80+
}
7981

8082
/*the value written into period register is the expected value minus one*/
81-
gpTimerRegs[tmrCfg->timer_num]->PRDLO= _loll(tmrCfg->period-1);
82-
gpTimerRegs[tmrCfg->timer_num]->PRDHI= _hill(tmrCfg->period-1);
83+
gpTimerRegs[tmrCfg->timer_num]->PRDLO = _loll(tmrCfg->period-1);
84+
gpTimerRegs[tmrCfg->timer_num]->PRDHI = _hill(tmrCfg->period-1);
8385
if(tmrCfg->reload_period>1)
8486
{
85-
gpTimerRegs[tmrCfg->timer_num]->RELLO= _loll(tmrCfg->reload_period-1);
86-
gpTimerRegs[tmrCfg->timer_num]->RELHI= _hill(tmrCfg->reload_period-1);
87+
gpTimerRegs[tmrCfg->timer_num]->RELLO = _loll(tmrCfg->reload_period-1);
88+
gpTimerRegs[tmrCfg->timer_num]->RELHI = _hill(tmrCfg->reload_period-1);
8789
}
8890

89-
if(TIMER_WATCH_DOG==tmrCfg->timerMode)
91+
if(TIMER_WATCH_DOG == tmrCfg->timerMode)
9092
{
91-
gpTimerRegs[tmrCfg->timer_num]->TGCR=
93+
gpTimerRegs[tmrCfg->timer_num]->TGCR =
9294
/*Select watch-dog mode*/
93-
(CSL_TMR_TIMMODE_WDT<<CSL_TMR_TGCR_TIMMODE_SHIFT)
95+
(CSL_TMR_TIMMODE_WDT << CSL_TMR_TGCR_TIMMODE_SHIFT)
9496
/*Remove the timer from reset*/
95-
|(CSL_TMR_TGCR_TIMLORS_MASK)
96-
|(CSL_TMR_TGCR_TIMHIRS_MASK);
97+
| (CSL_TMR_TGCR_TIMLORS_MASK)
98+
| (CSL_TMR_TGCR_TIMHIRS_MASK);
9799
}
98-
else if(TIMER_PERIODIC_WAVE==tmrCfg->timerMode)
100+
else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
99101
{
100-
gpTimerRegs[tmrCfg->timer_num]->TGCR= TMR_TGCR_PLUSEN_MASK
102+
gpTimerRegs[tmrCfg->timer_num]->TGCR = TMR_TGCR_PLUSEN_MASK
101103
/*for plus featuers, dual 32-bit unchained timer mode should be used*/
102-
|(CSL_TMR_TIMMODE_DUAL_UNCHAINED<<CSL_TMR_TGCR_TIMMODE_SHIFT)
104+
| (CSL_TMR_TIMMODE_DUAL_UNCHAINED << CSL_TMR_TGCR_TIMMODE_SHIFT)
103105
/*Remove the timer from reset*/
104-
|(CSL_TMR_TGCR_TIMLORS_MASK);
106+
| (CSL_TMR_TGCR_TIMLORS_MASK);
105107

106108
//in plus mode, interrupt/event must be enabled manually
107109
gpTimerRegs[tmrCfg->timer_num]->INTCTL_STAT= TMR_INTCTLSTAT_EN_ALL_CLR_ALL;
108110
}
109111
else
110112
{
111-
gpTimerRegs[tmrCfg->timer_num]->TGCR=
113+
gpTimerRegs[tmrCfg->timer_num]->TGCR =
112114
/*Select 64-bit general timer mode*/
113-
(CSL_TMR_TIMMODE_GPT<<CSL_TMR_TGCR_TIMMODE_SHIFT)
115+
(CSL_TMR_TIMMODE_GPT << CSL_TMR_TGCR_TIMMODE_SHIFT)
114116
/*Remove the timer from reset*/
115-
|(CSL_TMR_TGCR_TIMLORS_MASK)
116-
|(CSL_TMR_TGCR_TIMHIRS_MASK);
117+
| (CSL_TMR_TGCR_TIMLORS_MASK)
118+
| (CSL_TMR_TGCR_TIMHIRS_MASK);
117119
}
118120

119121
/*make timer stop with emulation*/
120122
gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD = (gpTimerRegs[tmrCfg->timer_num]->EMUMGT_CLKSPD&
121123
~(CSL_TMR_EMUMGT_CLKSPD_FREE_MASK|CSL_TMR_EMUMGT_CLKSPD_SOFT_MASK));
122124

123-
if(TIMER_WATCH_DOG==tmrCfg->timerMode)
125+
if(TIMER_WATCH_DOG == tmrCfg->timerMode)
124126
{
125127
/*enable watchdog timer*/
126128
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
127-
|(CSL_TMR_WDTCR_WDKEY_CMD1<<CSL_TMR_WDTCR_WDKEY_SHIFT);
129+
| (CSL_TMR_WDTCR_WDKEY_CMD1 << CSL_TMR_WDTCR_WDKEY_SHIFT);
128130

129131
gpTimerRegs[tmrCfg->timer_num]->TCR=
130-
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
131-
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
132+
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
133+
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
132134
/*The timer is enabled continuously*/
133-
|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
134-
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
135+
| (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
136+
| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
135137
/*select pulse mode*/
136-
|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT )
137-
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
138-
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
139-
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
138+
| (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
139+
| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
140+
| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
141+
| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
140142

141143
/*active watchdog timer*/
142144
gpTimerRegs[tmrCfg->timer_num]->WDTCR = CSL_TMR_WDTCR_WDEN_MASK
143-
|(CSL_TMR_WDTCR_WDKEY_CMD2<<CSL_TMR_WDTCR_WDKEY_SHIFT);
145+
| (CSL_TMR_WDTCR_WDKEY_CMD2 << CSL_TMR_WDTCR_WDKEY_SHIFT);
144146
}
145-
else if(TIMER_ONE_SHOT_PULSE==tmrCfg->timerMode)
147+
else if(TIMER_ONE_SHOT_PULSE == tmrCfg->timerMode)
146148
{
147-
gpTimerRegs[tmrCfg->timer_num]->TCR=
148-
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
149-
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
149+
gpTimerRegs[tmrCfg->timer_num]->TCR =
150+
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
151+
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
150152
/*The timer is enabled one-shot*/
151-
|(CSL_TMR_ENAMODE_ENABLE<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
152-
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
153+
| (CSL_TMR_ENAMODE_ENABLE << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
154+
| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
153155
/*select pulse mode*/
154-
|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT )
155-
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
156-
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
157-
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
156+
| (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
157+
| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
158+
| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
159+
| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
158160
}
159-
else if(TIMER_PERIODIC_CLOCK==tmrCfg->timerMode)
161+
else if(TIMER_PERIODIC_CLOCK == tmrCfg->timerMode)
160162
{
161-
gpTimerRegs[tmrCfg->timer_num]->TCR=
162-
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
163-
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
163+
gpTimerRegs[tmrCfg->timer_num]->TCR =
164+
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
165+
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
164166
/*The timer is enabled continuously*/
165-
|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
166-
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
167+
| (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
168+
| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
167169
/*select clock mode*/
168-
|(CSL_TMR_CP_CLOCK<<CSL_TMR_TCR_CP_LO_SHIFT )
169-
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
170-
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
171-
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
170+
| (CSL_TMR_CP_CLOCK << CSL_TMR_TCR_CP_LO_SHIFT)
171+
| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
172+
| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
173+
| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
172174
}
173-
else if(TIMER_PERIODIC_WAVE==tmrCfg->timerMode)
175+
else if(TIMER_PERIODIC_WAVE == tmrCfg->timerMode)
174176
{
175-
gpTimerRegs[tmrCfg->timer_num]->TCR=
176-
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
177-
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
177+
gpTimerRegs[tmrCfg->timer_num]->TCR =
178+
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
179+
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
178180
/*The timer is enabled continuously with period reload*/
179-
|(CSL_TMR_ENAMODE_CONT_RELOAD<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
180-
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
181+
| (CSL_TMR_ENAMODE_CONT_RELOAD << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
182+
| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
181183
/*select clock mode*/
182-
|(CSL_TMR_CP_CLOCK<<CSL_TMR_TCR_CP_LO_SHIFT )
183-
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
184-
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
185-
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
184+
| (CSL_TMR_CP_CLOCK << CSL_TMR_TCR_CP_LO_SHIFT)
185+
| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
186+
| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
187+
| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
186188
}
187189
else /*TIMER_PERIODIC_PULSE*/
188190
{
189-
gpTimerRegs[tmrCfg->timer_num]->TCR=
190-
(CSL_TMR_CLOCK_INP_NOGATE<<CSL_TMR_TCR_TIEN_LO_SHIFT )
191-
|(CSL_TMR_CLKSRC_INTERNAL<<CSL_TMR_TCR_CLKSRC_LO_SHIFT )
191+
gpTimerRegs[tmrCfg->timer_num]->TCR =
192+
(CSL_TMR_CLOCK_INP_NOGATE << CSL_TMR_TCR_TIEN_LO_SHIFT)
193+
| (CSL_TMR_CLKSRC_INTERNAL << CSL_TMR_TCR_CLKSRC_LO_SHIFT)
192194
/*The timer is enabled continuously*/
193-
|(CSL_TMR_ENAMODE_CONT<<CSL_TMR_TCR_ENAMODE_LO_SHIFT)
194-
|((tmrCfg->pulseWidth<<CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
195+
| (CSL_TMR_ENAMODE_CONT << CSL_TMR_TCR_ENAMODE_LO_SHIFT)
196+
| ((tmrCfg->pulseWidth << CSL_TMR_TCR_PWID_LO_SHIFT)&CSL_TMR_TCR_PWID_LO_MASK)
195197
/*select clock mode*/
196-
|(CSL_TMR_CP_PULSE<<CSL_TMR_TCR_CP_LO_SHIFT )
197-
|(CSL_TMR_INVINP_UNINVERTED<<CSL_TMR_TCR_INVINP_LO_SHIFT )
198-
|(CSL_TMR_INVOUTP_UNINVERTED<<CSL_TMR_TCR_INVOUTP_LO_SHIFT)
199-
|(0<<CSL_TMR_TCR_TSTAT_LO_SHIFT );
198+
| (CSL_TMR_CP_PULSE << CSL_TMR_TCR_CP_LO_SHIFT)
199+
| (CSL_TMR_INVINP_UNINVERTED << CSL_TMR_TCR_INVINP_LO_SHIFT)
200+
| (CSL_TMR_INVOUTP_UNINVERTED << CSL_TMR_TCR_INVOUTP_LO_SHIFT)
201+
| (0 << CSL_TMR_TCR_TSTAT_LO_SHIFT);
200202
}
201203
}

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