[bsp\raspi4]move io to iomap.h

Author: bigmagic123

bsp/raspberry-pi/raspi4/driver/board.c

@@ -18,18 +18,14 @@
 #include "mmu.h"
 
 static rt_uint64_t timerStep;
-// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
-#define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
-#define TIMER_IRQ               30
-#define NON_SECURE_TIMER_IRQ    (1 << 1)
 
 int rt_hw_get_gtimer_frq(void);
 void rt_hw_set_gtimer_val(rt_uint64_t value);
 int rt_hw_get_gtimer_val(void);
 int rt_hw_get_cntpct_val(void);
 void rt_hw_gtimer_enable(void);
 
-void core0_timer_enable_interrupt_controller()
+void core0_timer_enable_interrupt_controller(void)
 {
     CORE0_TIMER_IRQ_CTRL |= NON_SECURE_TIMER_IRQ;
 }
@@ -94,4 +90,4 @@ void rt_hw_board_init(void)
 #ifdef RT_USING_COMPONENTS_INIT
     rt_components_board_init();
 #endif
-}
+}

bsp/raspberry-pi/raspi4/driver/board.h

@@ -12,6 +12,7 @@
 #define BOARD_H__
 
 #include <stdint.h>
+#include "iomap.h"
 
 extern unsigned char __bss_start;
 extern unsigned char __bss_end;
@@ -22,4 +23,3 @@ extern unsigned char __bss_end;
 void rt_hw_board_init(void);
 
 #endif
-

bsp/raspberry-pi/raspi4/driver/drv_gpio.h

@@ -17,8 +17,6 @@
 #include "board.h"
 #include "interrupt.h"
 
-#define GPIO_BASE (0xFE000000 + 0x00200000)
-
 #define GPIO_REG_GPFSEL0(BASE)             HWREG32(BASE + 0x00)
 #define GPIO_REG_GPFSEL1(BASE)             HWREG32(BASE + 0x04)
 #define GPIO_REG_GPFSEL2(BASE)             HWREG32(BASE + 0x08)

bsp/raspberry-pi/raspi4/driver/drv_uart.c

@@ -16,12 +16,6 @@
 #include "drv_uart.h"
 #include "drv_gpio.h"
 
-#define UART0_BASE            (0xFE000000 + 0x00201000)
-#define PL011_BASE            UART0_BASE
-#define IRQ_PL011             (121 + 32)
-
-#define UART_REFERENCE_CLOCK 48000000
-
 struct hw_uart_device
 {
     rt_ubase_t hw_base;

bsp/raspberry-pi/raspi4/driver/drv_uart.h

@@ -81,4 +81,3 @@
 int rt_hw_uart_init(void);
 
 #endif /* DRV_UART_H__ */
-

bsp/raspberry-pi/raspi4/driver/iomap.h

@@ -1,8 +1,23 @@
 #ifndef __RASPI4_H__
 #define __RASPI4_H__
 
-#define ARM_GIC_NR_IRQS     512
-#define INTC_BASE   0xff800000
+//gpio
+#define GPIO_BASE (0xFE000000 + 0x00200000)
+
+//uart
+#define UART0_BASE                  (0xFE000000 + 0x00201000)
+#define PL011_BASE                  UART0_BASE
+#define IRQ_PL011                   (121 + 32)
+#define UART_REFERENCE_CLOCK        (48000000)
+
+// 0x40, 0x44, 0x48, 0x4c: Core 0~3 Timers interrupt control
+#define CORE0_TIMER_IRQ_CTRL    HWREG32(0xFF800040)
+#define TIMER_IRQ               30
+#define NON_SECURE_TIMER_IRQ    (1 << 1)
+
+//gic max
+#define ARM_GIC_NR_IRQS             (512)
+#define INTC_BASE                   (0xff800000)
 #define GIC_V2_DISTRIBUTOR_BASE     (INTC_BASE + 0x00041000)
 #define GIC_V2_CPU_INTERFACE_BASE   (INTC_BASE + 0x00042000)
 #define GIC_V2_HYPERVISOR_BASE      (INTC_BASE + 0x00044000)
@@ -11,4 +26,4 @@
 #define GIC_PL400_DISTRIBUTOR_PPTR  GIC_V2_DISTRIBUTOR_BASE
 #define GIC_PL400_CONTROLLER_PPTR   GIC_V2_CPU_INTERFACE_BASE
 
-#endif
+#endif