[xuantie] 添加玄铁R,C全系列RTOS支持

Author: Yaochenger

bsp/xuantie/libraries/device_drivers/drv_usart.c

@@ -27,7 +27,7 @@
     #include <rtdbg.h>
 
     #if !defined(BSP_USING_UART0) && !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) \
-        && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7) 
+        && !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && !defined(BSP_USING_UART7)
         #error "Please define at least one BSP_USING_UARTx"
         /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */
     #endif
@@ -148,7 +148,7 @@ static int xuantie_putc(struct rt_serial_device *serial, char c)
     ret = csi_uart_send(&uart->uart, &c, 1, 50);
     if (ret == 1)
         return RT_EOK;
-        
+
     return RT_ERROR;
 }
 
@@ -160,7 +160,7 @@ static int xuantie_getc(struct rt_serial_device *serial)
 
     csi_uart_receive(&uart->uart, &c, 1, 0x5);
     dw_uart_enable_recv_irq(uart_base);
-    return c;  
+    return c;
 }
 
 static const struct rt_uart_ops xuantie_uart_ops =

bsp/xuantie/libraries/device_drivers/drv_usart.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2022, RT-Thread Development Team
+ * Copyright (c) 2006-2025, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_asm_macro.h

@@ -19,7 +19,7 @@
 /*
  * attention: don't modify this file as a suggest
  * you should copy from chip_riscv_dummy/include/asm/riscv_asm_macro.h and keep it newer
- * please contact xuantie-rtos os team if have question 
+ * please contact xuantie-rtos os team if have question
  */
 
 #ifndef __RISCV_ASM_MACRO_H__

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/asm/riscv_csr.h

@@ -19,30 +19,30 @@
 /*
  * attention: don't modify this file as a suggest
  * you should copy from chip_riscv_dummy/include/asm/riscv_csr.h and keep it newer
- * please contact xuantie-rtos os team if have question 
+ * please contact xuantie-rtos os team if have question
  */
 
 #ifndef __RISCV_CSR_H__
 #define __RISCV_CSR_H__
 
 #if __riscv_xlen == 64
-	#define portWORD_SIZE 8
-	#define store_x       sd
-	#define load_x        ld
+    #define portWORD_SIZE 8
+    #define store_x       sd
+    #define load_x        ld
 #elif __riscv_xlen == 32
-	#define store_x       sw
-	#define load_x        lw
-	#define portWORD_SIZE 4
+    #define store_x       sw
+    #define load_x        lw
+    #define portWORD_SIZE 4
 #else
-	#error Assembler did not define __riscv_xlen
+    #error Assembler did not define __riscv_xlen
 #endif
 
 #if __riscv_flen == 64
-	#define fstore_x      fsd
-	#define fload_x       fld
+    #define fstore_x      fsd
+    #define fload_x       fld
 #elif __riscv_flen == 32
-	#define fstore_x      fsw
-	#define fload_x       flw
+    #define fstore_x      fsw
+    #define fload_x       flw
 #endif
 
 #if defined(CONFIG_RISCV_SMODE) && CONFIG_RISCV_SMODE
@@ -136,7 +136,7 @@
 #define MSTATUS_FS_SHIFT                13
 #define MSTATUS_MS_SHIFT                25
 
-#define INSERT_FIELD(val, which, fieldval)	(((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
+#define INSERT_FIELD(val, which, fieldval)  (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
 
 #if CONFIG_CPU_XUANTIE_C906 || CONFIG_CPU_XUANTIE_C906FD || CONFIG_CPU_XUANTIE_C906FDV || CONFIG_CPU_XUANTIE_C908 || CONFIG_CPU_XUANTIE_C908V ||CONFIG_CPU_XUANTIE_C908I || CONFIG_CPU_XUANTIE_R910 || CONFIG_CPU_XUANTIE_R920
 #define ATTR_SO                 (1ull << 4)

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/drv/dev_tag.h

@@ -90,7 +90,7 @@ typedef enum {
     DEV_RAMBUS_120SI_TAG,
     DEV_RAMBUS_120SII_TAG,
     DEV_RAMBUS_120SIII_TAG,
-	DEV_WJ_AVFS_TAG,
+    DEV_WJ_AVFS_TAG,
     DEV_WJ_BMU_TAG,
 } csi_dev_tag_t;
 

bsp/xuantie/libraries/xuantie_libraries/chip_riscv_dummy/include/dw_timer_ll.h

@@ -1,12 +1,12 @@
 /*
- *	Copyright (C) 2017-2024 Alibaba Group Holding Limited
+ *  Copyright (C) 2017-2024 Alibaba Group Holding Limited
  */
 
 /*******************************************************
- * @file 	dw_timer_ll.h
- * @brief	header file for timer ll driver
+ * @file    dw_timer_ll.h
+ * @brief   header file for timer ll driver
  * @version V1.0
- * @date	9. April 2020
+ * @date    9. April 2020
  * ******************************************************/
 
 #ifndef _DW_TIMER_LL_H_
@@ -21,7 +21,7 @@ extern "C"
 {
 #endif
 
-/*! Timer1 Control Reg, 	offset: 0x08 */
+/*! Timer1 Control Reg,     offset: 0x08 */
 #define DW_TIMER_CTL_ENABLE_SEL_Pos                                    (0U)
 #define DW_TIMER_CTL_ENABLE_SEL_Msk                                    (0x1U << DW_TIMER_CTL_ENABLE_SEL_Pos)
 #define DW_TIMER_CTL_ENABLE_SEL_EN                                     DW_TIMER_CTL_ENABLE_SEL_Msk