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[libcpu/risc-v][K210] add FPU support
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5 files changed

+173
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‎libcpu/Kconfig‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,14 @@ config ARCH_RISCV
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config ARCH_RISCV_FPU
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bool
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109+
config ARCH_RISCV_FPU_S
110+
select ARCH_RISCV_FPU
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bool
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113+
config ARCH_RISCV_FPU_D
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select ARCH_RISCV_FPU
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bool
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config ARCH_RISCV32
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select ARCH_RISCV
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bool

‎libcpu/risc-v/common/context_gcc.S‎

Lines changed: 77 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@
77
* Date Author Notes
88
* 2018/10/28 Bernard The unify RISC-V porting implementation
99
* 2018/12/27 Jesven Add SMP support
10+
* 2020/11/20 BalanceTWK Add FPU support
1011
*/
1112

1213
#include "cpuport.h"
@@ -72,6 +73,43 @@ rt_hw_context_switch:
7273
* mstatus.mie -> sp(2)
7374
* x(i) -> sp(i-4)
7475
*/
76+
#ifdef ARCH_RISCV_FPU
77+
addi sp, sp, -32 * FREGBYTES
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79+
FSTORE f0, 0 * FREGBYTES(sp)
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FSTORE f1, 1 * FREGBYTES(sp)
81+
FSTORE f2, 2 * FREGBYTES(sp)
82+
FSTORE f3, 3 * FREGBYTES(sp)
83+
FSTORE f4, 4 * FREGBYTES(sp)
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FSTORE f5, 5 * FREGBYTES(sp)
85+
FSTORE f6, 6 * FREGBYTES(sp)
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FSTORE f7, 7 * FREGBYTES(sp)
87+
FSTORE f8, 8 * FREGBYTES(sp)
88+
FSTORE f9, 9 * FREGBYTES(sp)
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FSTORE f10, 10 * FREGBYTES(sp)
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FSTORE f11, 11 * FREGBYTES(sp)
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FSTORE f12, 12 * FREGBYTES(sp)
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FSTORE f13, 13 * FREGBYTES(sp)
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FSTORE f14, 14 * FREGBYTES(sp)
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FSTORE f15, 15 * FREGBYTES(sp)
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FSTORE f16, 16 * FREGBYTES(sp)
96+
FSTORE f17, 17 * FREGBYTES(sp)
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FSTORE f18, 18 * FREGBYTES(sp)
98+
FSTORE f19, 19 * FREGBYTES(sp)
99+
FSTORE f20, 20 * FREGBYTES(sp)
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FSTORE f21, 21 * FREGBYTES(sp)
101+
FSTORE f22, 22 * FREGBYTES(sp)
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FSTORE f23, 23 * FREGBYTES(sp)
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FSTORE f24, 24 * FREGBYTES(sp)
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FSTORE f25, 25 * FREGBYTES(sp)
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FSTORE f26, 26 * FREGBYTES(sp)
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FSTORE f27, 27 * FREGBYTES(sp)
107+
FSTORE f28, 28 * FREGBYTES(sp)
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FSTORE f29, 29 * FREGBYTES(sp)
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FSTORE f30, 30 * FREGBYTES(sp)
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FSTORE f31, 31 * FREGBYTES(sp)
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112+
#endif
75113
addi sp, sp, -32 * REGBYTES
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STORE sp, (a0)
77115

@@ -174,7 +212,7 @@ rt_hw_context_switch_exit:
174212

175213
LOAD x1, 1 * REGBYTES(sp)
176214

177-
li t0, 0x00001800
215+
li t0, 0x00007800
178216
csrw mstatus, t0
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LOAD a0, 2 * REGBYTES(sp)
180218
csrs mstatus, a0
@@ -209,4 +247,42 @@ rt_hw_context_switch_exit:
209247
LOAD x31, 31 * REGBYTES(sp)
210248

211249
addi sp, sp, 32 * REGBYTES
250+
251+
#ifdef ARCH_RISCV_FPU
252+
FLOAD f0, 0 * FREGBYTES(sp)
253+
FLOAD f1, 1 * FREGBYTES(sp)
254+
FLOAD f2, 2 * FREGBYTES(sp)
255+
FLOAD f3, 3 * FREGBYTES(sp)
256+
FLOAD f4, 4 * FREGBYTES(sp)
257+
FLOAD f5, 5 * FREGBYTES(sp)
258+
FLOAD f6, 6 * FREGBYTES(sp)
259+
FLOAD f7, 7 * FREGBYTES(sp)
260+
FLOAD f8, 8 * FREGBYTES(sp)
261+
FLOAD f9, 9 * FREGBYTES(sp)
262+
FLOAD f10, 10 * FREGBYTES(sp)
263+
FLOAD f11, 11 * FREGBYTES(sp)
264+
FLOAD f12, 12 * FREGBYTES(sp)
265+
FLOAD f13, 13 * FREGBYTES(sp)
266+
FLOAD f14, 14 * FREGBYTES(sp)
267+
FLOAD f15, 15 * FREGBYTES(sp)
268+
FLOAD f16, 16 * FREGBYTES(sp)
269+
FLOAD f17, 17 * FREGBYTES(sp)
270+
FLOAD f18, 18 * FREGBYTES(sp)
271+
FLOAD f19, 19 * FREGBYTES(sp)
272+
FLOAD f20, 20 * FREGBYTES(sp)
273+
FLOAD f21, 21 * FREGBYTES(sp)
274+
FLOAD f22, 22 * FREGBYTES(sp)
275+
FLOAD f23, 23 * FREGBYTES(sp)
276+
FLOAD f24, 24 * FREGBYTES(sp)
277+
FLOAD f25, 25 * FREGBYTES(sp)
278+
FLOAD f26, 26 * FREGBYTES(sp)
279+
FLOAD f27, 27 * FREGBYTES(sp)
280+
FLOAD f28, 28 * FREGBYTES(sp)
281+
FLOAD f29, 29 * FREGBYTES(sp)
282+
FLOAD f30, 30 * FREGBYTES(sp)
283+
FLOAD f31, 31 * FREGBYTES(sp)
284+
285+
addi sp, sp, 32 * FREGBYTES
286+
#endif
287+
212288
mret

‎libcpu/risc-v/common/cpuport.c‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
* Change Logs:
77
* Date Author Notes
88
* 2018/10/28 Bernard The unify RISC-V porting code.
9+
* 2020/11/20 BalanceTWK Add FPU support
910
*/
1011

1112
#include <rthw.h>
@@ -53,6 +54,40 @@ struct rt_hw_stack_frame
5354
rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
5455
rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
5556
rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
57+
#ifdef ARCH_RISCV_FPU
58+
rv_floatreg_t f0; /* f0 */
59+
rv_floatreg_t f1; /* f1 */
60+
rv_floatreg_t f2; /* f2 */
61+
rv_floatreg_t f3; /* f3 */
62+
rv_floatreg_t f4; /* f4 */
63+
rv_floatreg_t f5; /* f5 */
64+
rv_floatreg_t f6; /* f6 */
65+
rv_floatreg_t f7; /* f7 */
66+
rv_floatreg_t f8; /* f8 */
67+
rv_floatreg_t f9; /* f9 */
68+
rv_floatreg_t f10; /* f10 */
69+
rv_floatreg_t f11; /* f11 */
70+
rv_floatreg_t f12; /* f12 */
71+
rv_floatreg_t f13; /* f13 */
72+
rv_floatreg_t f14; /* f14 */
73+
rv_floatreg_t f15; /* f15 */
74+
rv_floatreg_t f16; /* f16 */
75+
rv_floatreg_t f17; /* f17 */
76+
rv_floatreg_t f18; /* f18 */
77+
rv_floatreg_t f19; /* f19 */
78+
rv_floatreg_t f20; /* f20 */
79+
rv_floatreg_t f21; /* f21 */
80+
rv_floatreg_t f22; /* f22 */
81+
rv_floatreg_t f23; /* f23 */
82+
rv_floatreg_t f24; /* f24 */
83+
rv_floatreg_t f25; /* f25 */
84+
rv_floatreg_t f26; /* f26 */
85+
rv_floatreg_t f27; /* f27 */
86+
rv_floatreg_t f28; /* f28 */
87+
rv_floatreg_t f29; /* f29 */
88+
rv_floatreg_t f30; /* f30 */
89+
rv_floatreg_t f31; /* f31 */
90+
#endif
5691
};
5792

5893
/**

‎libcpu/risc-v/common/cpuport.h‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
* Change Logs:
77
* Date Author Notes
88
* 2018-10-03 Bernard The first version
9+
* 2020/11/20 BalanceTWK Add FPU support
910
*/
1011

1112
#ifndef CPUPORT_H__
@@ -24,4 +25,19 @@
2425
#define REGBYTES 4
2526
#endif
2627

28+
#ifdef ARCH_RISCV_FPU
29+
#ifdef ARCH_RISCV_FPU_D
30+
#define FSTORE fsd
31+
#define FLOAD fld
32+
#define FREGBYTES 8
33+
#define rv_floatreg_t rt_int64_t
34+
#endif
35+
#ifdef ARCH_RISCV_FPU_S
36+
#define FSTORE fsw
37+
#define FLOAD flw
38+
#define FREGBYTES 4
39+
#define rv_floatreg_t rt_int32_t
40+
#endif
41+
#endif
42+
2743
#endif

‎libcpu/risc-v/k210/interrupt_gcc.S‎

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,43 @@
1515
.align 2
1616
.global trap_entry
1717
trap_entry:
18+
#ifdef ARCH_RISCV_FPU
19+
addi sp, sp, -32 * FREGBYTES
20+
21+
FSTORE f0, 0 * FREGBYTES(sp)
22+
FSTORE f1, 1 * FREGBYTES(sp)
23+
FSTORE f2, 2 * FREGBYTES(sp)
24+
FSTORE f3, 3 * FREGBYTES(sp)
25+
FSTORE f4, 4 * FREGBYTES(sp)
26+
FSTORE f5, 5 * FREGBYTES(sp)
27+
FSTORE f6, 6 * FREGBYTES(sp)
28+
FSTORE f7, 7 * FREGBYTES(sp)
29+
FSTORE f8, 8 * FREGBYTES(sp)
30+
FSTORE f9, 9 * FREGBYTES(sp)
31+
FSTORE f10, 10 * FREGBYTES(sp)
32+
FSTORE f11, 11 * FREGBYTES(sp)
33+
FSTORE f12, 12 * FREGBYTES(sp)
34+
FSTORE f13, 13 * FREGBYTES(sp)
35+
FSTORE f14, 14 * FREGBYTES(sp)
36+
FSTORE f15, 15 * FREGBYTES(sp)
37+
FSTORE f16, 16 * FREGBYTES(sp)
38+
FSTORE f17, 17 * FREGBYTES(sp)
39+
FSTORE f18, 18 * FREGBYTES(sp)
40+
FSTORE f19, 19 * FREGBYTES(sp)
41+
FSTORE f20, 20 * FREGBYTES(sp)
42+
FSTORE f21, 21 * FREGBYTES(sp)
43+
FSTORE f22, 22 * FREGBYTES(sp)
44+
FSTORE f23, 23 * FREGBYTES(sp)
45+
FSTORE f24, 24 * FREGBYTES(sp)
46+
FSTORE f25, 25 * FREGBYTES(sp)
47+
FSTORE f26, 26 * FREGBYTES(sp)
48+
FSTORE f27, 27 * FREGBYTES(sp)
49+
FSTORE f28, 28 * FREGBYTES(sp)
50+
FSTORE f29, 29 * FREGBYTES(sp)
51+
FSTORE f30, 30 * FREGBYTES(sp)
52+
FSTORE f31, 31 * FREGBYTES(sp)
53+
54+
#endif
1855

1956
/* save thread context to thread stack */
2057
addi sp, sp, -32 * REGBYTES

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