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| 1 | +#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c |
| 2 | +/* |
| 3 | +** ################################################################### |
| 4 | +** Processors: LPC55S69JBD100_cm33_core0 |
| 5 | +** LPC55S69JET98_cm33_core0 |
| 6 | +** |
| 7 | +** Compiler: Keil ARM C/C++ Compiler |
| 8 | +** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.2 15 Aug 2018 |
| 9 | +** Version: rev. 1.0, 2018-08-22 |
| 10 | +** Build: b181008 |
| 11 | +** |
| 12 | +** Abstract: |
| 13 | +** Linker file for the Keil ARM C/C++ Compiler |
| 14 | +** |
| 15 | +** Copyright 2016 Freescale Semiconductor, Inc. |
| 16 | +** Copyright 2016-2018 NXP |
| 17 | +** Copyright 2019-2020 Arm Limited. All rights reserved. |
| 18 | +** All rights reserved. |
| 19 | +** |
| 20 | +** SPDX-License-Identifier: BSD-3-Clause |
| 21 | +** |
| 22 | +** http: www.nxp.com |
| 23 | + |
| 24 | +** |
| 25 | +** ################################################################### |
| 26 | +*/ |
| 27 | + |
| 28 | +/* |
| 29 | + * Original code taken from RTT project at: |
| 30 | + * https://github.com/RT-Thread/rt-thread |
| 31 | + * File: bsp/lpc55sxx/lpc55s69_nxp_evk/board/linker_scripts/LPC55S69_cm33_core0_flash_mdk.scf |
| 32 | + * Git SHA of the original version: 64945ba882d651a14933eb4e7b3d93d10d6daae1 |
| 33 | + */ |
| 34 | + |
| 35 | +/* USB BDT size */ |
| 36 | +#define usb_bdt_size 0x0 |
| 37 | +/* Sizes */ |
| 38 | +#if (defined(__stack_size__)) |
| 39 | + #define Stack_Size __stack_size__ |
| 40 | +#else |
| 41 | + #define Stack_Size 0x1000 |
| 42 | +#endif |
| 43 | + |
| 44 | +#if (defined(__heap_size__)) |
| 45 | + #define Heap_Size __heap_size__ |
| 46 | +#else |
| 47 | + #define Heap_Size 0x1000 |
| 48 | +#endif |
| 49 | + |
| 50 | +#define m_interrupts_start 0x00020000 |
| 51 | +#define m_interrupts_size 0x00000200 |
| 52 | + |
| 53 | +#define m_text_start 0x00020200 |
| 54 | +#define m_text_size 0x00031000 |
| 55 | + |
| 56 | +#define m_core1_image_start 0x00072000 |
| 57 | +#define m_core1_image_size 0x00026000 |
| 58 | + |
| 59 | +#if (defined(__use_shmem__)) |
| 60 | + #define m_data_start 0x20033000 |
| 61 | + #define m_data_size 0x00010800 |
| 62 | + #define m_rpmsg_sh_mem_start 0x20043800 |
| 63 | + #define m_rpmsg_sh_mem_size 0x00000800 |
| 64 | +#else |
| 65 | + #define m_data_start 0x20033000 |
| 66 | + #define m_data_size 0x0000cc00 |
| 67 | +#endif |
| 68 | + |
| 69 | +#define m_usb_sram_start 0x40100000 |
| 70 | +#define m_usb_sram_size 0x00004000 |
| 71 | + |
| 72 | + |
| 73 | +LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region |
| 74 | + |
| 75 | + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address |
| 76 | + * (RESET,+FIRST) |
| 77 | + } |
| 78 | + |
| 79 | + ER_m_text m_text_start FIXED m_text_size { ; load address = execution address |
| 80 | + * (InRoot$$Sections) |
| 81 | + * (+RO) |
| 82 | + } |
| 83 | + |
| 84 | +#if (defined(__use_shmem__)) |
| 85 | + RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG |
| 86 | + * (rpmsg_sh_mem_section) |
| 87 | + } |
| 88 | +#endif |
| 89 | + |
| 90 | + RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data |
| 91 | + * (+RW +ZI) |
| 92 | + } |
| 93 | + ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up |
| 94 | + } |
| 95 | + ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down |
| 96 | + } |
| 97 | + |
| 98 | + RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size { |
| 99 | + * (m_usb_bdt) |
| 100 | + } |
| 101 | + |
| 102 | + RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) { |
| 103 | + * (m_usb_global) |
| 104 | + } |
| 105 | +} |
| 106 | + |
| 107 | +LR_CORE1_IMAGE m_core1_image_start { |
| 108 | + CORE1_REGION m_core1_image_start m_core1_image_size { |
| 109 | + *(M0CODE) |
| 110 | + } |
| 111 | +} |
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