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| 1 | +/* |
| 2 | + * Copyright (c) 2006-2021, RT-Thread Development Team |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + * |
| 6 | + * Change Logs: |
| 7 | + * Date Author Notes |
| 8 | + * 2021-03-03 iysheng first version |
| 9 | + */ |
| 10 | + |
| 11 | +#include <board.h> |
| 12 | + |
| 13 | +#define DBG_TAG "drv.wdt" |
| 14 | +#define DBG_LVL DBG_INFO |
| 15 | +#include <rtdbg.h> |
| 16 | + |
| 17 | +#ifdef RT_USING_WDT |
| 18 | + |
| 19 | +typedef struct { |
| 20 | + struct rt_watchdog_device wdt; |
| 21 | + rt_uint32_t min_threshold_s; |
| 22 | + rt_uint32_t max_threshold_s; |
| 23 | + rt_uint32_t current_threshold_s; |
| 24 | +} gd32_wdt_device_t; |
| 25 | + |
| 26 | +static gd32_wdt_device_t g_wdt_dev; |
| 27 | + |
| 28 | +static rt_err_t gd32_iwdt_init(rt_watchdog_t *wdt) |
| 29 | +{ |
| 30 | + rcu_osci_on(RCU_IRC40K); |
| 31 | + if (ERROR == rcu_osci_stab_wait(RCU_IRC40K)) |
| 32 | + { |
| 33 | + LOG_E("failed init IRC40K clock for free watchdog."); |
| 34 | + return -EINVAL; |
| 35 | + } |
| 36 | + |
| 37 | + g_wdt_dev.min_threshold_s = 1; |
| 38 | + g_wdt_dev.max_threshold_s = (0xfff << 8) / 40000; |
| 39 | + LOG_I("threshold section [%u, %d]", \ |
| 40 | + g_wdt_dev.min_threshold_s, g_wdt_dev.max_threshold_s); |
| 41 | + |
| 42 | + IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE); |
| 43 | + IWDG_SetPrescaler(IWDG_PRESCALER_256); |
| 44 | + IWDG_SetReloadValue(0xfff); |
| 45 | + IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE); |
| 46 | + |
| 47 | + return 0; |
| 48 | +} |
| 49 | + |
| 50 | +static rt_err_t gd32_iwdt_control(rt_watchdog_t *wdt, int cmd, void *arg) |
| 51 | +{ |
| 52 | + rt_uint32_t param; |
| 53 | + |
| 54 | + switch (cmd) |
| 55 | + { |
| 56 | + case RT_DEVICE_CTRL_WDT_KEEPALIVE: |
| 57 | + IWDG_ReloadCounter(); |
| 58 | + break; |
| 59 | + case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: |
| 60 | + param = *(rt_uint32_t *) arg; |
| 61 | + if ((param > g_wdt_dev.max_threshold_s) || \ |
| 62 | + (param < g_wdt_dev.min_threshold_s)) |
| 63 | + { |
| 64 | + LOG_E("invalid param@%u.", param); |
| 65 | + return -E2BIG; |
| 66 | + } |
| 67 | + else |
| 68 | + { |
| 69 | + g_wdt_dev.current_threshold_s = param; |
| 70 | + } |
| 71 | + IWDG_Write_Enable(IWDG_WRITEACCESS_ENABLE); |
| 72 | + IWDG_SetReloadValue(param * 40000 >> 8); |
| 73 | + IWDG_Write_Enable(IWDG_WRITEACCESS_DISABLE); |
| 74 | + break; |
| 75 | + case RT_DEVICE_CTRL_WDT_GET_TIMEOUT: |
| 76 | + *(rt_uint32_t *)arg = g_wdt_dev.current_threshold_s; |
| 77 | + break; |
| 78 | + case RT_DEVICE_CTRL_WDT_START: |
| 79 | + IWDG_Enable(); |
| 80 | + break; |
| 81 | + default: |
| 82 | + LOG_W("This command is not supported."); |
| 83 | + return -RT_ERROR; |
| 84 | + } |
| 85 | + |
| 86 | + return RT_EOK; |
| 87 | +} |
| 88 | + |
| 89 | +static struct rt_watchdog_ops g_wdt_ops = { |
| 90 | + gd32_iwdt_init, |
| 91 | + gd32_iwdt_control, |
| 92 | +}; |
| 93 | + |
| 94 | +static int rt_hw_iwdt_init(void) |
| 95 | +{ |
| 96 | + rt_err_t ret; |
| 97 | + |
| 98 | + g_wdt_dev.wdt.ops = &g_wdt_ops; |
| 99 | + /* register watchdog device */ |
| 100 | + if (rt_hw_watchdog_register(&g_wdt_dev.wdt, "iwdt", \ |
| 101 | + RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK) |
| 102 | + { |
| 103 | + LOG_E("wdt device register failed."); |
| 104 | + return -RT_ERROR; |
| 105 | + } |
| 106 | + LOG_D("wdt device register success."); |
| 107 | + |
| 108 | + return ret; |
| 109 | +} |
| 110 | +INIT_BOARD_EXPORT(rt_hw_iwdt_init); |
| 111 | +#endif |
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