11/*
2- * Copyright (c) 2006-2024, RT-Thread Development Team
2+ * Copyright (c) 2006-2025 RT-Thread Development Team
33 *
44 * SPDX-License-Identifier: Apache-2.0
55 *
@@ -87,11 +87,23 @@ rt_inline rt_ssize_t spi_xfer_4line_data8(struct rt_spi_bit_ops *ops,
8787
8888 TOG_SCLK (ops );
8989
90- if (config -> mode & RT_SPI_MSB ) { rx_data <<= 1 ; bit = 0x01 ; }
91- else { rx_data >>= 1 ; bit = 0x80 ; }
90+ if (config -> mode & RT_SPI_MSB )
91+ {
92+ rx_data <<= 1 ; bit = 0x01 ;
93+ }
94+ else
95+ {
96+ rx_data >>= 1 ; bit = 0x80 ;
97+ }
9298
93- if (GET_MISO (ops )) { rx_data |= bit ; }
94- else { rx_data &= ~bit ; }
99+ if (GET_MISO (ops ))
100+ {
101+ rx_data |= bit ;
102+ }
103+ else
104+ {
105+ rx_data &= ~bit ;
106+ }
95107
96108 spi_delay2 (ops );
97109
@@ -150,11 +162,23 @@ rt_inline rt_ssize_t spi_xfer_4line_data16(struct rt_spi_bit_ops *ops,
150162
151163 TOG_SCLK (ops );
152164
153- if (config -> mode & RT_SPI_MSB ) { rx_data <<= 1 ; bit = 0x0001 ; }
154- else { rx_data >>= 1 ; bit = 0x8000 ; }
165+ if (config -> mode & RT_SPI_MSB )
166+ {
167+ rx_data <<= 1 ; bit = 0x0001 ;
168+ }
169+ else
170+ {
171+ rx_data >>= 1 ; bit = 0x8000 ;
172+ }
155173
156- if (GET_MISO (ops )) { rx_data |= bit ; }
157- else { rx_data &= ~bit ; }
174+ if (GET_MISO (ops ))
175+ {
176+ rx_data |= bit ;
177+ }
178+ else
179+ {
180+ rx_data &= ~bit ;
181+ }
158182
159183 spi_delay2 (ops );
160184
@@ -244,11 +268,23 @@ rt_inline rt_ssize_t spi_xfer_3line_data8(struct rt_spi_bit_ops *ops,
244268
245269 TOG_SCLK (ops );
246270
247- if (config -> mode & RT_SPI_MSB ) { rx_data <<= 1 ; bit = 0x01 ; }
248- else { rx_data >>= 1 ; bit = 0x80 ; }
271+ if (config -> mode & RT_SPI_MSB )
272+ {
273+ rx_data <<= 1 ; bit = 0x01 ;
274+ }
275+ else
276+ {
277+ rx_data >>= 1 ; bit = 0x80 ;
278+ }
249279
250- if (GET_MOSI (ops )) { rx_data |= bit ; }
251- else { rx_data &= ~bit ; }
280+ if (GET_MOSI (ops ))
281+ {
282+ rx_data |= bit ;
283+ }
284+ else
285+ {
286+ rx_data &= ~bit ;
287+ }
252288
253289 spi_delay2 (ops );
254290
@@ -345,11 +381,23 @@ rt_inline rt_ssize_t spi_xfer_3line_data16(struct rt_spi_bit_ops *ops,
345381
346382 TOG_SCLK (ops );
347383
348- if (config -> mode & RT_SPI_MSB ) { rx_data <<= 1 ; bit = 0x0001 ; }
349- else { rx_data >>= 1 ; bit = 0x8000 ; }
384+ if (config -> mode & RT_SPI_MSB )
385+ {
386+ rx_data <<= 1 ; bit = 0x0001 ;
387+ }
388+ else
389+ {
390+ rx_data >>= 1 ; bit = 0x8000 ;
391+ }
350392
351- if (GET_MOSI (ops )) { rx_data |= bit ; }
352- else { rx_data &= ~bit ; }
393+ if (GET_MOSI (ops ))
394+ {
395+ rx_data |= bit ;
396+ }
397+ else
398+ {
399+ rx_data &= ~bit ;
400+ }
353401
354402 spi_delay2 (ops );
355403
@@ -456,15 +504,14 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes
456504 rt_pin_write (cs_pin , PIN_LOW );
457505 }
458506 spi_delay (ops );
507+ }
459508
460509 /* spi phase */
461- if (config -> mode & RT_SPI_CPHA )
510+ if (( config -> mode & RT_SPI_CPHA ) )
462511 {
463512 spi_delay (ops );
464513 TOG_SCLK (ops );
465514 }
466- }
467-
468515 if (config -> mode & RT_SPI_3WIRE )
469516 {
470517 if (config -> data_width <= 8 )
@@ -487,10 +534,15 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes
487534 length = spi_xfer_4line_data16 (ops , config , message -> send_buf , message -> recv_buf , message -> length );
488535 }
489536 }
490-
491537 /* release CS */
492- if (message -> cs_take && !(device -> config .mode & RT_SPI_NO_CS ) && (cs_pin != PIN_NONE ))
538+ if (message -> cs_release && !(device -> config .mode & RT_SPI_NO_CS ) && (cs_pin != PIN_NONE ))
493539 {
540+
541+ if ((config -> mode & RT_SPI_CPOL ) && !GET_SCLK (ops ))
542+ {
543+ spi_delay (ops );
544+ TOG_SCLK (ops );
545+ }
494546 spi_delay (ops );
495547 if (device -> config .mode & RT_SPI_CS_HIGH )
496548 {
@@ -501,6 +553,7 @@ rt_ssize_t spi_bit_xfer(struct rt_spi_device *device, struct rt_spi_message *mes
501553 rt_pin_write (cs_pin , PIN_HIGH );
502554 }
503555 LOG_I ("spi release cs\n" );
556+
504557 }
505558
506559 return length ;
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