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- Remove duplicated line feeds and unnecessary annotations.
- Maintainers information is now corrected. - Withdraw the modification on EXEC_PATH of the gcc toolchain.
1 parent e6b5fea commit edc4028

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5 files changed

+14
-131
lines changed

5 files changed

+14
-131
lines changed

bsp/ls2kdev/README.md

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -123,10 +123,9 @@ title TFTPBOOT
123123

124124
## 6. 联系人信息
125125

126-
维护人:[bernard][4],[0xcccccccccccc][5]
126+
维护人:[bernard][4]
127127

128128
[1]: http://ftp.loongnix.org/loongsonpi/pi_2/doc
129129
[2]: https://pan.baidu.com/s/17dbdOE4NAJ-qEW7drVRq2w
130130
[3]: http://ftp.loongnix.org/embedd/ls2k/
131-
[4]: https://github.com/BernardXiong
132-
[5]: https://github.com/0xcccccccccccc
131+
[4]: https://github.com/BernardXiong

bsp/ls2kdev/drivers/drv_spi.c

Lines changed: 3 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -1,20 +1,13 @@
11
#include <stdio.h>
22
#include <stdlib.h>
33
#include <ctype.h>
4-
54
#include <rtthread.h>
65
#include <drivers/spi.h>
7-
86
#include "drv_spi.h"
97

108
#ifdef RT_USING_SPI
11-
12-
13-
149
static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha)
1510
{
16-
//rt_kprintf("SPI initiating with spre_spr:%2X ,copl:%2X ,cpha:%2X\n",spre_spr,copl,cpha);
17-
int d;
1811
SET_SPI(SPSR, 0xc0 | (spre_spr & 0b00000011));
1912
SET_SPI(PARAM, 0x40);
2013
SET_SPI(PARAM2, 0x01);
@@ -23,23 +16,19 @@ static void spi_init(uint8_t spre_spr, uint8_t copl, uint8_t cpha)
2316
SET_SPI(SOFTCS, 0xff);
2417
}
2518

26-
27-
static void spi_set_csn(uint8_t val) //old method
19+
static void spi_set_csn(uint8_t val)
2820
{
2921
SET_SPI(SOFTCS, val);
3022
}
31-
// #define RT_USING_SPI_GPIOCS
3223

3324
#ifdef RT_USING_SPI_GPIOCS
3425
#include <drivers/pin.h>
3526
#endif
36-
static void spi_set_cs(unsigned char cs, int new_status)
27+
static void spi_set_cs(unsigned char cs, int new_status)
3728
{
38-
3929
if (cs < 4)
4030
{
4131
unsigned char val = 0;
42-
4332
val = GET_SPI(SOFTCS);
4433
val |= 0x01 << cs ; // csen=1
4534
if (new_status) // cs = 1
@@ -51,20 +40,16 @@ static void spi_set_cs(unsigned char cs, int new_status)
5140
val &= ~(0x10 << cs); // csn=0
5241
}
5342
SET_SPI(SOFTCS, val);
54-
5543
return ;
5644
}
5745
#ifdef RT_USING_SPI_GPIOCS
5846
else
5947
{
60-
//rt_kprintf("[Warnning] GPIOCS is an experimental feature: \n ");
61-
//rt_kprintf("[Warnning] GPIO%d will be set to OUTPUT with value %d \n ",cs,new_status);
62-
rt_pin_mode(cs, PIN_MODE_OUTPUT);
48+
rt_pin_mode(cs, PIN_MODE_OUTPUT); // with RT_USING_SPI_GPIOCS feature enabled, gpio will be used as csn pin.
6349
rt_pin_write(cs, new_status);
6450
}
6551
#endif
6652
}
67-
6853
static uint8_t spi_write_for_response(uint8_t data)
6954
{
7055
uint8_t val;
@@ -74,33 +59,27 @@ static uint8_t spi_write_for_response(uint8_t data)
7459
return val;
7560
}
7661

77-
78-
7962
static int cmd_spi_init(int argc, char *argv[])
8063
{
8164
uint8_t spre_spr, cpol, cpha;
8265
switch (argc)
8366
{
8467
case 2:
85-
8668
spre_spr = strtoul(argv[1], NULL, 0);
8769
spi_init(spre_spr, 0, 0);
8870
break;
8971
case 4:
90-
9172
spre_spr = strtoul(argv[1], NULL, 0);
9273
cpol = strtoul(argv[2], NULL, 0);
9374
cpha = strtoul(argv[3], NULL, 0);
9475
spi_init(spre_spr, 0, 0);
9576
break;
96-
9777
default:
9878
printf("\nusage : cmd_spi_init spre_spr <cpol> <cpha>\n(cmd_spi_init 0x4 0x0 0x0)\n0x4:div8 0xb:div4096\n");
9979
break;
10080
}
10181
}
10282
MSH_CMD_EXPORT(cmd_spi_init, cmd_spi_init);
103-
10483
static int cmd_spi_set_csn(int argc, char *argv[])
10584
{
10685
uint8_t val, csn;
@@ -111,52 +90,43 @@ static int cmd_spi_set_csn(int argc, char *argv[])
11190
val = strtoul(argv[2], NULL, 0);
11291
spi_set_cs(csn, val);
11392
break;
114-
11593
default:
11694
printf("usage:cmd_spi_set_csn csn val\n(0xbf for csn1 enable,0xff for csn1 disable)\n");
11795
break;
11896
}
11997
}
12098
MSH_CMD_EXPORT(cmd_spi_set_csn, cmd_spi_set_csn);
121-
12299
static int cmd_spi_write(int argc, char *argv[])
123100
{
124101
uint8_t data, resp;
125102
switch (argc)
126103
{
127104
case 2:
128-
129105
data = strtoul(argv[1], NULL, 0);
130106
resp = spi_write_for_response(data);
131107
printf("resp:%2X\n", resp);
132108
break;
133-
134109
default:
135110
printf("usage:cmd_spi_write data\n");
136111
break;
137112
}
138113
}
139114
MSH_CMD_EXPORT(cmd_spi_write, cmd_spi_write);
140115

141-
142116
static rt_err_t configure(struct rt_spi_device *device, struct rt_spi_configuration *configuration);
143117
static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message);
144-
145118
const static unsigned char SPI_DIV_TABLE[] = {0b0000, 0b0001, 0b0100, 0b0010, 0b0011, 0b0101, 0b0110, 0b0111, 0b1000, 0b1001, 0b1010, 0b1011};
146119
// 2 4 8 16 32 64 128 256 512 1024 2048 4096
147120
static rt_err_t configure(struct rt_spi_device *device,
148121
struct rt_spi_configuration *configuration)
149122
{
150123

151-
152124
unsigned char cpol = 0;
153125
unsigned char cpha = 0;
154126

155-
156127
RT_ASSERT(NULL != device);
157128
RT_ASSERT(NULL != configuration);
158129

159-
160130
// baudrate
161131
if (configuration->mode & RT_SPI_CPOL) // cpol
162132
{
@@ -174,54 +144,36 @@ static rt_err_t configure(struct rt_spi_device *device,
174144
{
175145
cpha = 0;
176146
}
177-
//rt_kprintf("configure: cpol:%d cpha:%d\n",cpol,cpha);
178-
179147

180148
float spi_max_speed = ((float)APB_MAX_SPEED) / (8.0 / (float)APB_FREQSCALE);
181-
//rt_kprintf("spi max speed: %ld\n",(unsigned long)spi_max_speed);
182-
183-
184149
uint64_t div = (uint64_t)(spi_max_speed / (float)configuration->max_hz);
185-
//rt_kprintf("require speed: %ld\n",configuration->max_hz);
186150
int ctr = 0;
187151
while (div != 1 && ctr < 12)
188152
{
189153
ctr++;
190154
div = div >> 1;
191155
}
192-
//rt_kprintf("spi speed set to: %ld\n",(unsigned long)((spi_max_speed)/(float)(1<<ctr)));
193156
spi_init(SPI_DIV_TABLE[ctr], cpol, cpha);
194157

195-
196158
return RT_EOK;
197159
}
198-
199160
static rt_uint32_t xfer(struct rt_spi_device *device,
200161
struct rt_spi_message *message)
201162
{
202163

203-
204-
//rt_kprintf("xfer:\n");
205164
unsigned char cs = 0;
206165
rt_uint32_t size = 0;
207166
const rt_uint8_t *send_ptr = NULL;
208167
rt_uint8_t *recv_ptr = NULL;
209168
rt_uint8_t data = 0;
210-
211169
RT_ASSERT(NULL != device);
212170
RT_ASSERT(NULL != message);
213-
214171
cs = (unsigned char)(device->parent.user_data);
215172
size = message->length;
216-
217-
//rt_kprintf("[%s] cs=%d\n", __FUNCTION__, cs);
218-
219-
// take cs
220173
if (message->cs_take)
221174
{
222175
spi_set_cs(cs, 0);
223176
}
224-
225177
// send data
226178
send_ptr = message->send_buf;
227179
recv_ptr = message->recv_buf;
@@ -232,7 +184,6 @@ static rt_uint32_t xfer(struct rt_spi_device *device,
232184
{
233185
data = *send_ptr++;
234186
}
235-
236187
if (NULL != recv_ptr)
237188
{
238189
*recv_ptr++ = spi_write_for_response(data);
@@ -242,31 +193,24 @@ static rt_uint32_t xfer(struct rt_spi_device *device,
242193
spi_write_for_response(data);
243194
}
244195
}
245-
246196
// release cs
247197
if (message->cs_release)
248198
{
249199
spi_set_cs(cs, 1);
250200
}
251-
252201
return message->length;
253202
}
254-
255203
static struct rt_spi_ops loongson_spi_ops =
256204
{
257205
.configure = configure,
258206
.xfer = xfer
259207
};
260-
261208
static struct rt_spi_bus loongson_spi;
262-
263209
static int loongson_spi_init()
264210
{
265211
//rt_kprintf("spi_init\n");
266212
return rt_spi_bus_register(&loongson_spi, "spi", &loongson_spi_ops);
267213
}
268-
269214
INIT_BOARD_EXPORT(loongson_spi_init);
270215

271-
272216
#endif

bsp/ls2kdev/drivers/drv_spi.h

Lines changed: 8 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,22 +1,20 @@
1-
#ifndef DRV_SPI_H
2-
#define DRV_SPI_H
1+
#ifndef LS2K_DRV_SPI_H
2+
#define LS2K_DRV_SPI_H
33

44
#include <rtthread.h>
55
#include <rthw.h>
66

7-
8-
9-
#define RFEMPTY 1
7+
// kseg1 byte operation
108
#define KSEG1_STORE8(addr,val) *(volatile char *)(0xffffffffa0000000 | addr) = val
119
#define KSEG1_LOAD8(addr) *(volatile char *)(0xffffffffa0000000 | addr)
12-
10+
// clock configurations
1311
#define APB_MAX_SPEED 125000000U
1412
#define APB_FREQSCALE (((KSEG1_LOAD8(0xffffffffbfe104d2)>>4)&0x7)+1)
15-
13+
// base addrs
1614
#define SPI_BASE 0x1fff0220
1715
#define PMON_ADDR 0xa1000000
1816
#define FLASH_ADDR 0x000000
19-
17+
// bit bias
2018
#define SPCR 0x0
2119
#define SPSR 0x1
2220
#define FIFO 0x2
@@ -26,18 +24,9 @@
2624
#define PARAM 0x4
2725
#define SOFTCS 0x5
2826
#define PARAM2 0x6
29-
30-
31-
32-
27+
#define RFEMPTY 1
28+
// SPI controller operaion macros
3329
#define SET_SPI(addr,val) KSEG1_STORE8(SPI_BASE+addr,val)
3430
#define GET_SPI(addr) KSEG1_LOAD8(SPI_BASE+addr)
3531

36-
37-
38-
//void spi_init(uint8_t ,uint8_t,uint8_t);
39-
//void spi_set_csn(uint8_t);
40-
//uint8_t spi_write_for_response(uint8_t);
41-
42-
4332
#endif

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