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[bsp][renesas] add i2c compatibility support, disabled by default
[bsp][renesas] add spi device option to Kconfig, disabled by default [bsp][renesas] add timer pwm function support, disabled by default [bsp][renesas] fixed the compile error in drv_gpio.c [bsp][renesas] add adc device option to Kconfig, disabled by default [bsp][renesas] support code flash operations
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17 files changed

+335
-119
lines changed

17 files changed

+335
-119
lines changed

bsp/renesas/libraries/HAL_Drivers/drivers/config/drv_config.h

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@@ -87,6 +87,15 @@ extern "C"
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#ifdef SOC_SERIES_R7FA2E2
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#include "ra2e2/uart_config.h"
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#ifdef BSP_USING_PWM
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#include "ra2e2/pwm_config.h"
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#endif
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#ifdef BSP_USING_ADC
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#include "ra2e2/adc_config.h"
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#endif
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#endif /* SOC_SERIES_R7FA2E2 */
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#ifdef SOC_SERIES_R7FA2L1
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/*
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* Copyright (c) 2006-2025, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-08-17 CYFS first version
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*/
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#ifndef __ADC_CONFIG_H__
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#define __ADC_CONFIG_H__
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#include <rtthread.h>
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#include <rtdevice.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(BSP_USING_ADC0)
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struct rt_adc_dev
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{
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struct rt_adc_ops ops;
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struct rt_adc_device adc_device;
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};
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struct ra_adc_map
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{
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const char *device_name;
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const adc_cfg_t *g_cfg;
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const adc_ctrl_t *g_ctrl;
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const adc_channel_cfg_t *g_channel_cfg;
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};
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#endif
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#endif
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2006-2025, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2025-08-17 CYFS first version
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*/
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#ifndef __PWM_CONFIG_H__
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#define __PWM_CONFIG_H__
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#include <rtthread.h>
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#include <drv_config.h>
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#include "hal_data.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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enum
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{
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#ifdef BSP_USING_PWM4
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BSP_PWM4_INDEX,
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#endif
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#ifdef BSP_USING_PWM5
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BSP_PWM5_INDEX,
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#endif
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#ifdef BSP_USING_PWM6
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BSP_PWM6_INDEX,
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#endif
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#ifdef BSP_USING_PWM7
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BSP_PWM7_INDEX,
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#endif
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#ifdef BSP_USING_PWM8
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BSP_PWM8_INDEX,
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#endif
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#ifdef BSP_USING_PWM9
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BSP_PWM9_INDEX,
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#endif
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BSP_PWMS_NUM
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};
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#define PWM_DRV_INITIALIZER(num) \
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{ \
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.name = "pwm"#num , \
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.g_cfg = &g_timer##num##_cfg, \
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.g_ctrl = &g_timer##num##_ctrl, \
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.g_timer = &g_timer##num, \
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PWM_CONFIG_H__ */

bsp/renesas/libraries/HAL_Drivers/drivers/drv_flash.c

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@@ -228,7 +228,11 @@ bool calculate_block_num(int no, size_t addr, size_t size, void *erase_addr, voi
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level = rt_hw_interrupt_disable();
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R_FLASH_Reset(&g_flash_ctrl);
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231+
#if BSP_FEATURE_FLASH_HP_VERSION
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fal_block_iter(&_onchip_flash_hp0, &calculate_block_num, (void *)addr, (void *)size, &block_num);
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#else
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fal_block_iter(&_onchip_flash_lp, &calculate_block_num, (void *)addr, (void *)size, &block_num);
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#endif
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/* Erase Block */
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#if BSP_FEATURE_FLASH_HP_VERSION
@@ -337,6 +341,11 @@ static int fal_flash_lp_erase(long offset, size_t size)
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return _flash_lp_erase(_onchip_flash_lp.addr + offset, size);
338342
}
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344+
void flash_callback(flash_callback_args_t * p_args)
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{
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}
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#endif
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#endif

bsp/renesas/libraries/HAL_Drivers/drivers/drv_gpio.c

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@@ -26,7 +26,7 @@
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static rt_base_t ra_pin_get_irqx(rt_uint32_t pin)
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{
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PIN2IRQX_TABLE(pin)
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PIN2IRQX_TABLE(pin);
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}
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static struct rt_pin_irq_hdr pin_irq_hdr_tab[RA_IRQ_MAX] = {0};

bsp/renesas/libraries/HAL_Drivers/drivers/drv_i2c.c

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@@ -36,6 +36,14 @@
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#define RA_SCI_EVENT_ERROR BIT(3)
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#define RA_SCI_EVENT_ALL BITS(0,3)
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#ifdef SOC_SERIES_R7FA2E2
40+
#define R_IIC_MASTER_Open R_IIC_B_MASTER_Open
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#define R_IIC_MASTER_Write R_IIC_B_MASTER_Write
42+
#define R_IIC_MASTER_Read R_IIC_B_MASTER_Read
43+
#define R_IIC_MASTER_SlaveAddressSet R_IIC_B_MASTER_SlaveAddressSet
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#define R_IIC_MASTER_CallbackSet R_IIC_B_MASTER_CallbackSet
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#endif
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struct ra_i2c_handle
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{
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struct rt_i2c_bus_device bus;

bsp/renesas/ra2e2-ek/.config

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@@ -107,7 +107,7 @@ CONFIG_SOC_R7FA2E2A7=y
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# end of rt_strnlen options
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# end of klibc options
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110-
CONFIG_RT_NAME_MAX=8
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CONFIG_RT_NAME_MAX=16
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# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
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# CONFIG_RT_USING_NANO is not set
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# CONFIG_RT_USING_SMART is not set
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#
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CONFIG_RT_USING_SEMAPHORE=y
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CONFIG_RT_USING_MUTEX=y
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# CONFIG_RT_USING_EVENT is not set
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CONFIG_RT_USING_EVENT=y
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# CONFIG_RT_USING_MAILBOX is not set
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# CONFIG_RT_USING_MESSAGEQUEUE is not set
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# CONFIG_RT_USING_SIGNALS is not set
@@ -1286,6 +1286,10 @@ CONFIG_BSP_USING_UART9=y
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# CONFIG_BSP_UART9_TX_USING_DMA is not set
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CONFIG_BSP_UART9_RX_BUFSIZE=256
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CONFIG_BSP_UART9_TX_BUFSIZE=0
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# CONFIG_BSP_USING_HW_I2C is not set
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# CONFIG_BSP_USING_SPI is not set
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# CONFIG_BSP_USING_PWM is not set
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# CONFIG_BSP_USING_ADC is not set
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# end of On-chip Peripheral Drivers
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#

bsp/renesas/ra2e2-ek/.secure_azone

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@@ -18,10 +18,6 @@
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<peripheral name="PORT3.CM23" group="PORT">
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<slot name="P300.CM23" secure="false"/>
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</peripheral>
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<peripheral name="PORT4.CM23" group="PORT">
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<slot name="P400.CM23" secure="false"/>
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<slot name="P401.CM23" secure="false"/>
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</peripheral>
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<peripheral name="PORT9.CM23" group="PORT">
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<slot name="P914.CM23" secure="false"/>
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</peripheral>

bsp/renesas/ra2e2-ek/.secure_xml

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</raClockConfiguration>
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<raPinConfiguration>
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<pincfg active="true" name="" symbol="">
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<configSetting altId="i3c0.scl0.p400" configurationId="i3c0.scl0" peripheral="I3C0"/>
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<configSetting altId="i3c0.sda0.p401" configurationId="i3c0.sda0" peripheral="I3C0"/>
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<configSetting altId="jtag_fslash_swd.swclk.p300" configurationId="jtag_fslash_swd.swclk" peripheral="JTAG/SWD"/>
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<configSetting altId="jtag_fslash_swd.swdio.p108" configurationId="jtag_fslash_swd.swdio" peripheral="JTAG/SWD"/>
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<configSetting altId="p015.output.low" configurationId="p015"/>

bsp/renesas/ra2e2-ek/.settings/standalone.prefs

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@@ -1,4 +1,4 @@
1-
#Thu Aug 21 14:44:11 CST 2025
1+
#Wed Sep 10 17:06:33 CST 2025
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com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat
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com.renesas.cdt.ddsc.contentgen.options/options/suppresswarningspaths=ra/arm
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com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#Main\#\#CoreM\#\#\#\#6.1.0+fsp.6.0.0/all=1441545198,ra/arm/CMSIS_6/LICENSE|409404162,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_armclang.h|3070162158,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_clang.h|2642675438,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_compiler.h|432601292,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_gcc.h|1219721305,ra/arm/CMSIS_6/CMSIS/Core/Include/cmsis_version.h|1716662092,ra/arm/CMSIS_6/CMSIS/Core/Include/core_ca.h|3033126542,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0.h|3716711724,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm0plus.h|1573341164,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm1.h|1528066797,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm23.h|956077447,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm3.h|3181146757,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm33.h|3422691989,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm35p.h|3011809468,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm4.h|862174236,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm52.h|3557548549,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm55.h|2145813412,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm7.h|215226313,ra/arm/CMSIS_6/CMSIS/Core/Include/core_cm85.h|3759822293,ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc000.h|3285488134,ra/arm/CMSIS_6/CMSIS/Core/Include/core_sc300.h|3342995321,ra/arm/CMSIS_6/CMSIS/Core/Include/core_starmc1.h|440777068,ra/arm/CMSIS_6/CMSIS/Core/Include/tz_context.h|987654843,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_armclang_a.h|1790528804,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_clang_a.h|117658130,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_cp15.h|3644000269,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_gcc_a.h|947683335,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/cmsis_iccarm_a.h|3200474466,ra/arm/CMSIS_6/CMSIS/Core/Include/a-profile/irq_ctrl.h|2703360002,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_cachel1.h|271089146,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv7m_mpu.h|3180041419,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv81m_pac.h|1572899130,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_mpu.h|1964429271,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/armv8m_pmu.h|2095512231,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_armclang_m.h|2951442685,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_clang_m.h|1179088122,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_gcc_m.h|1753083115,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_iccarm_m.h|163659099,ra/arm/CMSIS_6/CMSIS/Core/Include/m-profile/cmsis_tiarmclang_m.h|718227869,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_armclang_r.h|681720804,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_clang_r.h|154254372,ra/arm/CMSIS_6/CMSIS/Core/Include/r-profile/cmsis_gcc_r.h
@@ -22,5 +22,8 @@ com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_io
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#6.0.0/all=429738396,ra/fsp/inc/api/r_transfer_api.h|2894177435,ra/fsp/inc/api/r_uart_api.h|3371921742,ra/fsp/inc/instances/r_sci_uart.h|4212520575,ra/fsp/src/r_sci_uart/r_sci_uart.c
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com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#6.0.0/libraries=
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com.renesas.cdt.ddsc.project.standalone.projectgenerationoptions/isCpp=false
25-
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator
25+
com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=PinConfiguration
26+
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.i2c_on_iic_b_master.1621234958=true
27+
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.i2c_on_iic_b_master.1927481972=false
28+
com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.spi_on_spi.880747616=false
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com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.1832981131=false

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