【ci】添加 timer、irq 测试

Guozhanxin · Guozhanxin · commit fe4bec08a561 · 2021-08-24T17:20:12.000+08:00
diff --git a/.github/workflows/action_utest.yml b/.github/workflows/action_utest.yml
@@ -13,6 +13,8 @@ jobs:
        legs:
          - {UTEST: "kernel/mem",       RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/mem.conf",     SD_FILE: "sd.bin"}
          - {UTEST: "kernel/ipc",       RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/ipc.conf",     SD_FILE: "sd.bin"}
+         - {UTEST: "kernel/irq",       RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/irq.conf",     SD_FILE: "sd.bin"}
+         - {UTEST: "kernel/timer",     RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "kernel/timer.conf",   SD_FILE: "sd.bin"}
          - {UTEST: "components/utest", RTT_BSP: "bsp/qemu-vexpress-a9",    QEMU_ARCH: "arm",      QEMU_MACHINE: "vexpress-a9", CONFIG_FILE: "utest_self/self.conf", SD_FILE: "sd.bin"}
          - {UTEST: "kernel/mem/riscv64", RTT_BSP: "bsp/qemu-riscv-virt64", QEMU_ARCH: "riscv64",  QEMU_MACHINE: "virt",  CONFIG_FILE: "kernel/mem.conf",   SD_FILE: "None"}
     env:
diff --git a/examples/utest/configs/kernel/irq.conf b/examples/utest/configs/kernel/irq.conf
@@ -0,0 +1,2 @@
+CONFIG_UTEST_IRQ_TC=y
+# dependencies
diff --git a/examples/utest/configs/kernel/timer.conf b/examples/utest/configs/kernel/timer.conf
@@ -0,0 +1,4 @@
+CONFIG_UTEST_TIMER_TC=y
+
+# dependencies
+CONFIG_RT_USING_TIMER_SOFT=y

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,2 @@`
	`1`	`+CONFIG_UTEST_IRQ_TC=y`
	`2`	`+# dependencies`