diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 3dae5e30fca..6d503086dd2 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -73,6 +73,7 @@ "asm9260t", "allwinner_tina", "ft32/ft32f072xb-starter", + "ft32/ft32f407xe-starter", "mini2440", "at91/at91sam9g45", "at91/at91sam9260", diff --git a/bsp/ft32/ft32f072xb-starter/project.uvprojx b/bsp/ft32/ft32f072xb-starter/project.uvprojx index a529cc31b2c..61fc4e1f607 100644 --- a/bsp/ft32/ft32f072xb-starter/project.uvprojx +++ b/bsp/ft32/ft32f072xb-starter/project.uvprojx @@ -1,43 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ rt-thread 0x4 ARM-ADS - 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060528::V5.06 update 5 (build 528)::.\ARMCC 0 FT32F072RBATx FMD - FMD.FT32F0xx_DFP.1.0.5 + FMD.FT32F0xx_DFP.1.1.2 https://www.fremontmicro.com/upload/tools/pack/ IRAM(0x20000000,0x00006000) IROM(0x08000000,0x00020000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE - - + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F0xx_128 -FS08000000 -FL020000 -FP0($$Device:FT32F072RBATx$CMSIS\Flash\FT32F0xx_128.FLM)) 0 $$Device:FT32F072RBATx$Drivers\CMSIS\FT32F0xx\Include\ft32f0xx.h - - - - - - - - - + + + + + + + + + $$Device:FT32F072RBATx$CMSIS\SVD\FT32F0xx.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 1 0 fromelf --bin !L --output rtthread.bin - + 0 0 0 0 0 - + 0 @@ -101,8 +104,8 @@ 0 0 3 - - + + 1 @@ -135,11 +138,11 @@ 1 BIN\UL2CM3.DLL - - - - - + + + + + 0 @@ -172,7 +175,7 @@ 0 0 "Cortex-M0" - + 0 0 0 @@ -183,6 +186,7 @@ 0 0 0 + 0 0 0 8 @@ -306,7 +310,7 @@ 0x0 - + 1 @@ -333,9 +337,9 @@ 0 0 - + FT32F072xB, RT_USING_LIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC - + ..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m0;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;board;..\libraries\Drivers;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\phy;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\libraries\FT32F0xx\FT32F0xx_Driver\Inc;..\..\..\components\drivers\include;applications;..\libraries\FT32F0xx\FT32F0xx_Driver\templates\Inc;.;..\..\..\include;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\libraries\FT32F0xx\CMSIS\FT32F0xx\Include @@ -351,10 +355,10 @@ 0 4 - - - - + + + + @@ -366,13 +370,13 @@ 0 0x08000000 0x20000000 - + .\board\linker_scripts\link.sct - - - - - + + + + + @@ -395,50 +399,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cunistd.c 1 ..\..\..\components\libc\compilers\common\cunistd.c - - cwchar.c 1 @@ -454,222 +444,668 @@ 1 ..\..\..\components\drivers\core\device.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - completion_comm.c 1 ..\..\..\components\drivers\ipc\completion_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - completion_up.c 1 ..\..\..\components\drivers\ipc\completion_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - condvar.c 1 ..\..\..\components\drivers\ipc\condvar.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - dev_pin.c 1 ..\..\..\components\drivers\pin\dev_pin.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + - - dev_serial.c 1 ..\..\..\components\drivers\serial\dev_serial.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_IPC_SOURCE__ - + @@ -685,22 +1121,16 @@ 1 board\board.c - - startup_ft32f072xb.s 2 ..\libraries\FT32F0xx\CMSIS\FT32F0xx\source\arm\startup_ft32f072xb.s - - drv_gpio.c 1 ..\libraries\Drivers\drv_gpio.c - - drv_usart.c 1 @@ -716,22 +1146,16 @@ 1 ..\..\..\components\finsh\cmd.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - shell.c 1 ..\..\..\components\finsh\shell.c - - msh.c 1 @@ -747,279 +1171,836 @@ 1 ..\..\..\src\clock.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - components.c 1 ..\..\..\src\components.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - cpu_up.c 1 ..\..\..\src\cpu_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - defunct.c 1 ..\..\..\src\defunct.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - idle.c 1 ..\..\..\src\idle.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - ipc.c 1 ..\..\..\src\ipc.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - irq.c 1 ..\..\..\src\irq.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - kservice.c 1 ..\..\..\src\kservice.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mem.c 1 ..\..\..\src\mem.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - mempool.c 1 ..\..\..\src\mempool.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - object.c 1 ..\..\..\src\object.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_comm.c 1 ..\..\..\src\scheduler_comm.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - thread.c 1 ..\..\..\src\thread.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + - - timer.c 1 ..\..\..\src\timer.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 __RT_KERNEL_SOURCE__ - + @@ -1035,29 +2016,21 @@ 1 ..\..\..\src\klibc\kstring.c - - kerrno.c 1 ..\..\..\src\klibc\kerrno.c - - rt_vsnprintf_tiny.c 1 ..\..\..\src\klibc\rt_vsnprintf_tiny.c - - rt_vsscanf.c 1 ..\..\..\src\klibc\rt_vsscanf.c - - kstdio.c 1 @@ -1073,22 +2046,16 @@ 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m0\context_rvds.S - - cpuport.c 1 @@ -1104,113 +2071,81 @@ 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_syscfg.c - - ft32f0xx_comp.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_comp.c - - system_ft32f0xx.c 1 ..\libraries\FT32F0xx\CMSIS\FT32F0xx\source\system_ft32f0xx.c - - ft32f0xx_dma.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_dma.c - - ft32f0xx_gpio.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_gpio.c - - ft32f0xx_misc.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_misc.c - - ft32f0xx_crs.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_crs.c - - ft32f0xx_opa.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_opa.c - - ft32f0xx_pwr.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_pwr.c - - ft32f0xx_rcc.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_rcc.c - - ft32f0xx_tim.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_tim.c - - ft32f0xx_usart.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_usart.c - - ft32f0xx_exti.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_exti.c - - ft32f0xx_debug.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_debug.c - - ft32f0xx_div.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_div.c - - ft32f0xx_crc.c 1 ..\libraries\FT32F0xx\FT32F0xx_Driver\Src\ft32f0xx_crc.c - - ft32f0xx_iwdg.c 1 @@ -1221,9 +2156,11 @@ + - - - + + + + diff --git a/bsp/ft32/ft32f407xe-starter/.config b/bsp/ft32/ft32f407xe-starter/.config new file mode 100644 index 00000000000..95af1822427 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/.config @@ -0,0 +1,1417 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=12 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +# CONFIG_RT_USING_TIMER_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart2" +CONFIG_RT_VER_NUM=0x50201 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M0=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +# CONFIG_RT_SERIAL_USING_DMA is not set +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_MCOREDUMP is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_RP2350_SDK is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F4_SERIES_DRIVER is not set +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_FT32=y +CONFIG_SOC_SERIES_FT32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_FT32F407VE=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +CONFIG_BSP_USING_UART2=y +# CONFIG_BSP_USING_CRC is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/ft32/ft32f407xe-starter/.gitignore b/bsp/ft32/ft32f407xe-starter/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/ft32/ft32f407xe-starter/Kconfig b/bsp/ft32/ft32f407xe-starter/Kconfig new file mode 100644 index 00000000000..029e5afd21a --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/Kconfig @@ -0,0 +1,13 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" + diff --git a/bsp/ft32/ft32f407xe-starter/README.md b/bsp/ft32/ft32f407xe-starter/README.md new file mode 100644 index 00000000000..181d7cf9317 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/README.md @@ -0,0 +1,53 @@ +# FT32F407xx-StarterKit-32 # + +## 1. 简介 + +[StarterKit-32](https://www.fremontmicro.com/down/demoboard/index.aspx)是辉芒微提供的开发板，使用 Cortex-M4 内核的 FT32F407xE 作为主控制器。提供包括扩展引脚等外设资源。 + +板载主要资源如下： + +| 硬件 | 描述 | +| -- | -- | +|CPU| Cortex-M4 | +|主频| 210MHz | +|SRAM| 128KB+64KB | +|Flash| 512KB | + +- 常用外设 + - LED：3个，（PD13、PD14、PD15） + - 按键：1个，（PA0或PC13) +- 常用接口：串口（PA2、PA3） + +## 2. 编译说明 + +StarterKit-32板级包支持 MDK5，以下是具体版本信息： + +| IDE/编译器 | 已测试版本 | +| -- | -- | +| MDK5(ARM Compiler 5 and 6) | MDK5.38 | + +## 3. 烧写及执行 + +下载程序：使用 CMSIS-DAP或者J-link等工具。 + +### 3.1 配置和仿真 + +工程已经默认使能了RT-Thread UART驱动、GPIO驱动。若想进一步配置工程请 +使用ENV工具。 + +## 4. 驱动支持情况及计划 + +| 驱动 | 支持情况 | 备注 | +| ------ | ---- | :------: | +| UART | 支持 | USART0/1 | +| GPIO | 支持 | | + +## 5. 联系人信息 + +维护人： + +- [FMD-AE](https://github.com/FmdAE) + +## 6. 参考 + +* [StarterKit-32](https://www.fremontmicro.com/down/demoboard/index.aspx) diff --git a/bsp/ft32/ft32f407xe-starter/SConscript b/bsp/ft32/ft32f407xe-starter/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/ft32/ft32f407xe-starter/SConstruct b/bsp/ft32/ft32f407xe-starter/SConstruct new file mode 100644 index 00000000000..77382caa378 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rt-thread_ft32f407.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rt-thread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +ft32_library = 'FT32F4xx' +rtconfig.BSP_LIBRARY_TYPE = ft32_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, ft32_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/ft32/ft32f407xe-starter/applications/SConscript b/bsp/ft32/ft32f407xe-starter/applications/SConscript new file mode 100644 index 00000000000..5efd37ed23c --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/applications/SConscript @@ -0,0 +1,9 @@ +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') + Glob('*.cpp') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/ft32/ft32f407xe-starter/applications/main.c b/bsp/ft32/ft32f407xe-starter/applications/main.c new file mode 100644 index 00000000000..f9919d8538d --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/applications/main.c @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-02 FMD-AE first version + */ + +#include +#include +#include + +/* defined the LED2 pin: PD13 */ +#define LED2_PIN GET_PIN(D, 13) + +int main(void) +{ + /* set LED0 pin mode to output */ + rt_pin_mode(LED2_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED2_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED2_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} diff --git a/bsp/ft32/ft32f407xe-starter/board/Kconfig b/bsp/ft32/ft32f407xe-starter/board/Kconfig new file mode 100644 index 00000000000..64d0cff977b --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/Kconfig @@ -0,0 +1,52 @@ +menu "Hardware Drivers Config" + +config SOC_FT32F407VE + bool + select SOC_SERIES_FT32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default n + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default y + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + endif + rsource "../../libraries/Drivers/Kconfig" + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/ft32/ft32f407xe-starter/board/SConscript b/bsp/ft32/ft32f407xe-starter/board/SConscript new file mode 100644 index 00000000000..16f55269efa --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/SConscript @@ -0,0 +1,29 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] + +startup_path_prefix = SDK_LIB + +if rtconfig.PLATFORM in ['gcc']: + src += [startup_path_prefix + '/FT32F4xx/CMSIS/FT32F4xx/source/gcc/startup_ft32f407xe.s'] +elif rtconfig.PLATFORM in ['armcc', 'armclang']: + src += [startup_path_prefix + '/FT32F4xx/CMSIS/FT32F4xx/source/arm/startup_ft32f407xe.s'] +elif rtconfig.PLATFORM in ['iccarm']: + src += [startup_path_prefix + '/FT32F4xx/CMSIS/FT32F4xx/source/iar/startup_ft32f407xe.s'] + +# FT32F407xE +# You can select chips from the list above +CPPDEFINES = ['FT32F407xE'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/ft32/ft32f407xe-starter/board/board.c b/bsp/ft32/ft32f407xe-starter/board/board.c new file mode 100644 index 00000000000..41b06ac6de7 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/board.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-02 FMD-AE first version + */ + +#include "board.h" + +#ifdef RT_USING_SERIAL + #include "drv_usart.h" +#endif /* RT_USING_SERIAL */ + +#define DBG_TAG "drv_common" +#define DBG_LVL DBG_INFO +#include + +#ifdef RT_USING_FINSH +#include + +static void reboot(uint8_t argc, char **argv) +{ + rt_hw_cpu_reset(); +} +MSH_CMD_EXPORT(reboot, Reboot System); +#endif /* RT_USING_FINSH */ + +__IO uint32_t uwTick; +static uint32_t _systick_ms = 1; + +void IncTick(void) +{ + uwTick += _systick_ms; +} +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + IncTick(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +uint32_t GetTick(void) +{ + if (SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) + IncTick(); + + return uwTick; +} + +void SuspendTick(void) +{ +} + +void ResumeTick(void) +{ +} + +void Delay(__IO uint32_t Delay) +{ + if (rt_thread_self()) + { + rt_thread_mdelay(Delay); + } + else + { + for (rt_uint32_t count = 0; count < Delay; count++) + { + rt_hw_us_delay(1000); + } + } +} +/** + * This function will delay for some us. + * + * @param us the delay time of us + */ +void rt_hw_us_delay(rt_uint32_t us) +{ + rt_uint32_t ticks; + rt_uint32_t told, tnow, tcnt = 0; + rt_uint32_t reload = SysTick->LOAD; + + ticks = us * reload / (1000000 / RT_TICK_PER_SECOND); + told = SysTick->VAL; + while (1) + { + tnow = SysTick->VAL; + if (tnow != told) + { + if (tnow < told) + { + tcnt += told - tnow; + } + else + { + tcnt += reload - tnow + told; + } + told = tnow; + if (tcnt >= ticks) + { + break; + } + } + } +} + +/** + * This function will initial FT32 board. + */ +rt_weak void rt_hw_board_init() +{ + SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND); + /* Heap initialization */ +#if defined(RT_USING_HEAP) + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + + /* Pin driver initialization is open by default */ +#ifdef RT_USING_PIN + rt_hw_pin_init(); +#endif + + /* USART driver initialization is open by default */ +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + + /* Set the shell console output device */ +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + + /* Board underlying hardware initialization */ +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + + diff --git a/bsp/ft32/ft32f407xe-starter/board/board.h b/bsp/ft32/ft32f407xe-starter/board/board.h new file mode 100644 index 00000000000..b8611133be1 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/board.h @@ -0,0 +1,57 @@ +/* + * Copyright (c) 2006-2022, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-03-02 FMD-AE first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include +#include "drv_gpio.h" +#include +#include +#include +#include +#include +#include +#include +#ifdef RT_USING_DEVICE + #include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#define FT32_FLASH_START_ADRESS ((uint32_t)0x08000000) +#define FT32_FLASH_SIZE (128 * 1024) +#define FT32_FLASH_END_ADDRESS ((uint32_t)(FT32_FLASH_START_ADRESS + FT32_FLASH_SIZE)) + +/* Internal SRAM memory size[Kbytes] <8-64>, Default: 64*/ +#define FT32_SRAM_SIZE 24 +#define FT32_SRAM_END (0x20000000 + FT32_SRAM_SIZE * 1024) + +#if defined(__ARMCC_VERSION) +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN ((void *)&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="CSTACK" +#define HEAP_BEGIN (__segment_end("CSTACK")) +#else +extern int __bss_end; +#define HEAP_BEGIN ((void *)&__bss_end) +#endif + +#define HEAP_END FT32_SRAM_END + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.icf b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.icf new file mode 100644 index 00000000000..ae5a7f57f86 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.lds b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.lds new file mode 100644 index 00000000000..cbe152d39f5 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.lds @@ -0,0 +1,157 @@ +/* + * linker script for STM32F10x with GNU ld + */ + +/* Program Entry, set to mark it as "used" and avoid gc */ +MEMORY +{ + ROM (rx) : ORIGIN = 0x08000000, LENGTH = 512k /* 512KB flash */ + RAM (rw) : ORIGIN = 0x20000000, LENGTH = 128k /* 128K sram */ +} +ENTRY(Reset_Handler) +_system_stack_size = 0x400; + +SECTIONS +{ + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + + . = ALIGN(4); + + PROVIDE(__ctors_start__ = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + PROVIDE(__ctors_end__ = .); + + . = ALIGN(4); + + _etext = .; + } > ROM = 0 + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + + /* This is used by the startup in order to initialize the .data secion */ + _sidata = .; + } > ROM + __exidx_end = .; + + /* .data section which is used for initialized data */ + + .data : AT (_sidata) + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _sdata = . ; + + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + + + PROVIDE(__dtors_start__ = .); + KEEP(*(SORT(.dtors.*))) + KEEP(*(.dtors)) + PROVIDE(__dtors_end__ = .); + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .data secion */ + _edata = . ; + } >RAM + + .stack : + { + . = ALIGN(4); + _sstack = .; + . = . + _system_stack_size; + . = ALIGN(4); + _estack = .; + } >RAM + + __bss_start = .; + .bss : + { + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _sbss = .; + + *(.bss) + *(.bss.*) + *(COMMON) + + . = ALIGN(4); + /* This is used by the startup in order to initialize the .bss secion */ + _ebss = . ; + + *(.bss.init) + } > RAM + __bss_end = .; + + _end = .; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.sct b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.sct new file mode 100644 index 00000000000..5d1e3e6c008 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00080000 { ; load region size_region + ER_IROM1 0x08000000 0x00080000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x20000000 0x00020000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/ft32/ft32f407xe-starter/figures/ft32f407xe-starter.jpg b/bsp/ft32/ft32f407xe-starter/figures/ft32f407xe-starter.jpg new file mode 100644 index 00000000000..444e0ac9f2f Binary files /dev/null and b/bsp/ft32/ft32f407xe-starter/figures/ft32f407xe-starter.jpg differ diff --git a/bsp/ft32/ft32f407xe-starter/project.uvprojx b/bsp/ft32/ft32f407xe-starter/project.uvprojx new file mode 100644 index 00000000000..9ff21b6819a --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/project.uvprojx @@ -0,0 +1,2275 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::.\ARMCC + 0 + + + FT32F407VEA2 + FMD + FMD.FT32F4xx_DFP.1.0.0 + https://www.fremontmicro.com/upload/tools/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:FT32F407VEA2$Flash\FT32F4xx_512.FLM)) + 0 + + + + + + + + + + + $$Device:FT32F407VEA2$SVD\FT32F407x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + FT32F407xE, RT_USING_LIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC + + ..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\eventfd;..\..\..\components\drivers\include;..\..\..\components\finsh;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\drivers\smp_call;board;..\libraries\Drivers;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\phy;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\libraries\FT32F4xx\FT32F4xx_Driver\inc;..\..\..\components\drivers\include;applications;..\libraries\FT32F4xx\FT32F4xx_Driver\templates\inc;.;..\..\..\include;..\..\..\components\libc\posix\io\epoll;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\libraries\FT32F4xx\CMSIS\FT32F4xx\include + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + .\applications\main.c + + + + + Compiler + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + completion_up.c + 1 + ..\..\..\components\drivers\ipc\completion_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dev_pin.c + 1 + ..\..\..\components\drivers\pin\dev_pin.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + dev_serial.c + 1 + ..\..\..\components\drivers\serial\dev_serial.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + board.c + 1 + .\board\board.c + + + startup_ft32f407xe.s + 2 + ..\libraries\FT32F4xx\CMSIS\FT32F4xx\source\arm\startup_ft32f407xe.s + + + drv_gpio.c + 1 + ..\libraries\Drivers\drv_gpio.c + + + drv_usart.c + 1 + ..\libraries\Drivers\drv_usart.c + + + + + Finsh + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + klibc + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + libcpu + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + Libraries + + + ft32f4xx_adc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_adc.c + + + ft32f4xx_comp.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_comp.c + + + ft32f4xx_crc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_crc.c + + + ft32f4xx_crs.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_crs.c + + + ft32f4xx_dac.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_dac.c + + + ft32f4xx_debug.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_debug.c + + + ft32f4xx_dma.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_dma.c + + + ft32f4xx_ecap.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_ecap.c + + + ft32f4xx_epwm.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_epwm.c + + + ft32f4xx_eqep.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_eqep.c + + + ft32f4xx_eth.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_eth.c + + + ft32f4xx_exti.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_exti.c + + + ft32f4xx_fdcan.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_fdcan.c + + + ft32f4xx_flash.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_flash.c + + + ft32f4xx_fmc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_fmc.c + + + ft32f4xx_gpio.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_gpio.c + + + ft32f4xx_i2c.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_i2c.c + + + ft32f4xx_i2s.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_i2s.c + + + ft32f4xx_iwdg.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_iwdg.c + + + ft32f4xx_lptim.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_lptim.c + + + ft32f4xx_misc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_misc.c + + + ft32f4xx_opamp.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_opamp.c + + + ft32f4xx_pwr.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_pwr.c + + + ft32f4xx_qspi.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_qspi.c + + + ft32f4xx_rcc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_rcc.c + + + ft32f4xx_rng.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_rng.c + + + ft32f4xx_rtc.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_rtc.c + + + ft32f4xx_sdio.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_sdio.c + + + ft32f4xx_spdif.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_spdif.c + + + ft32f4xx_spi.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_spi.c + + + ft32f4xx_ssi.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_ssi.c + + + ft32f4xx_syscfg.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_syscfg.c + + + ft32f4xx_tim.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_tim.c + + + ft32f4xx_uart.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_uart.c + + + ft32f4xx_usart.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_usart.c + + + ft32f4xx_wwdg.c + 1 + ..\libraries\FT32F4xx\FT32F4xx_Driver\src\ft32f4xx_wwdg.c + + + system_ft32f4xx.c + 1 + ..\libraries\FT32F4xx\CMSIS\FT32F4xx\source\system_ft32f4xx.c + + + + + + + + + + + + + + + + + project + 1 + + + + + diff --git a/bsp/ft32/ft32f407xe-starter/rtconfig.h b/bsp/ft32/ft32f407xe-starter/rtconfig.h new file mode 100644 index 00000000000..5942ded4c8d --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/rtconfig.h @@ -0,0 +1,413 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 12 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart2" +#define RT_VER_NUM 0x50201 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M0 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_FT32 +#define SOC_SERIES_FT32F4 + +/* Hardware Drivers Config */ + +#define SOC_FT32F407VE + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART2 + +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/ft32/ft32f407xe-starter/rtconfig.py b/bsp/ft32/ft32f407xe-starter/rtconfig.py new file mode 100644 index 00000000000..5ad587f65a2 --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/rtconfig.py @@ -0,0 +1,185 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.3' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4 ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m4 ' + CFLAGS += ' -mcpu=cortex-m4 ' + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) + diff --git a/bsp/ft32/ft32f407xe-starter/template.uvprojx b/bsp/ft32/ft32f407xe-starter/template.uvprojx new file mode 100644 index 00000000000..695d59daa2b --- /dev/null +++ b/bsp/ft32/ft32f407xe-starter/template.uvprojx @@ -0,0 +1,397 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060528::V5.06 update 5 (build 528)::.\ARMCC + 0 + + + FT32F407VEA2 + FMD + FMD.FT32F4xx_DFP.1.0.0 + https://www.fremontmicro.com/upload/tools/pack/ + IRAM(0x20000000,0x00020000) IRAM2(0x10000000,0x00010000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0FT32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:FT32F407VEA2$Flash\FT32F4xx_512.FLM)) + 0 + + + + + + + + + + + $$Device:FT32F407VEA2$SVD\FT32F407x.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x10000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 4 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git a/bsp/ft32/libraries/Drivers/drv_config.h b/bsp/ft32/libraries/Drivers/drv_config.h index 8b0c854f8ab..eca48e4f5c4 100644 --- a/bsp/ft32/libraries/Drivers/drv_config.h +++ b/bsp/ft32/libraries/Drivers/drv_config.h @@ -23,6 +23,11 @@ extern "C" { #include "uart_config.h" #endif +#if defined(SOC_SERIES_FT32F4) +#include "dma_config.h" +#include "uart_config.h" +#endif + #ifdef __cplusplus } #endif diff --git a/bsp/ft32/libraries/Drivers/drv_dma.h b/bsp/ft32/libraries/Drivers/drv_dma.h index fe455f958f7..cc1e39c6c91 100644 --- a/bsp/ft32/libraries/Drivers/drv_dma.h +++ b/bsp/ft32/libraries/Drivers/drv_dma.h @@ -22,6 +22,10 @@ extern "C" { #define DMA_INSTANCE_TYPE DMA_Channel_TypeDef #endif +#if defined(SOC_SERIES_FT32F4) +#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef +#endif + struct dma_config { DMA_INSTANCE_TYPE *Instance; rt_uint32_t dma_rcc; diff --git a/bsp/ft32/libraries/Drivers/drv_gpio.c b/bsp/ft32/libraries/Drivers/drv_gpio.c index 479294a3d03..94b03b5c651 100644 --- a/bsp/ft32/libraries/Drivers/drv_gpio.c +++ b/bsp/ft32/libraries/Drivers/drv_gpio.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-03-02 FMD-AE first version + * 2025-12-31 FMD-AE add ft32f4 support */ #include @@ -59,6 +60,24 @@ static const struct pin_irq_map pin_irq_map[] = {GPIO_Pin_14, EXTI4_15_IRQn}, {GPIO_Pin_15, EXTI4_15_IRQn}, #endif +#if defined(SOC_SERIES_FT32F4) + {GPIO_Pin_0, EXTI0_IRQn}, + {GPIO_Pin_1, EXTI1_IRQn}, + {GPIO_Pin_2, EXTI2_IRQn}, + {GPIO_Pin_3, EXTI3_IRQn}, + {GPIO_Pin_4, EXTI4_IRQn}, + {GPIO_Pin_5, EXTI9_5_IRQn}, + {GPIO_Pin_6, EXTI9_5_IRQn}, + {GPIO_Pin_7, EXTI9_5_IRQn}, + {GPIO_Pin_8, EXTI9_5_IRQn}, + {GPIO_Pin_9, EXTI9_5_IRQn}, + {GPIO_Pin_10, EXTI15_10_IRQn}, + {GPIO_Pin_11, EXTI15_10_IRQn}, + {GPIO_Pin_12, EXTI15_10_IRQn}, + {GPIO_Pin_13, EXTI15_10_IRQn}, + {GPIO_Pin_14, EXTI15_10_IRQn}, + {GPIO_Pin_15, EXTI15_10_IRQn}, +#endif }; static struct rt_pin_irq_hdr pin_irq_hdr_tab[] = @@ -339,12 +358,18 @@ static void rt_gpio_deinit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /* Deactivate the Pull-up and Pull-down resistor for the current IO */ GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << (position * 2u)); +#if defined (SOC_SERIES_FT32F0) /* Configure the default value IO Output Type */ GPIOx->OTYPER &= ~(GPIO_OTYPER_OT_0 << position) ; - /* Configure the default value for IO Speed */ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (position * 2u)); - +#endif +#if defined (SOC_SERIES_FT32F4) + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR0 << (position * 2u)); +#endif } position++; @@ -416,6 +441,7 @@ static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin, break; } GPIO_Init(PIN_FTPORT(pin), &GPIO_InitStruct); + EXTI_Init(&EXTI_InitStructure); NVIC_SetPriority(irqmap->irqno, 5); @@ -438,7 +464,6 @@ static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin, pin_irq_enable_mask &= ~irqmap->pinbit; - #if defined(SOC_SERIES_FT32F0) if ((irqmap->pinbit >= GPIO_Pin_0) && (irqmap->pinbit <= GPIO_Pin_1)) { @@ -467,6 +492,26 @@ static rt_err_t ft32_pin_irq_enable(struct rt_device *device, rt_base_t pin, NVIC_DisableIRQ(irqmap->irqno); } +#endif +#if defined(SOC_SERIES_FT32F4) + if ((irqmap->pinbit >= GPIO_Pin_5) && (irqmap->pinbit <= GPIO_Pin_9)) + { + if (!(pin_irq_enable_mask & (GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else if ((irqmap->pinbit >= GPIO_Pin_10) && (irqmap->pinbit <= GPIO_Pin_15)) + { + if (!(pin_irq_enable_mask & (GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 | GPIO_Pin_15))) + { + NVIC_DisableIRQ(irqmap->irqno); + } + } + else + { + NVIC_DisableIRQ(irqmap->irqno); + } #endif rt_hw_interrupt_enable(level); } @@ -546,15 +591,84 @@ void EXTI4_15_IRQHandler(void) rt_interrupt_leave(); } #endif +#if defined(SOC_SERIES_FT32F4) +void EXTI0_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_0); + rt_interrupt_leave(); +} + +void EXTI1_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_1); + rt_interrupt_leave(); +} + +void EXTI2_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_2); + rt_interrupt_leave(); +} + +void EXTI3_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_3); + rt_interrupt_leave(); +} + +void EXTI4_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_4); + rt_interrupt_leave(); +} + +void EXTI5_9_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_5); + GPIO_EXTI_IRQHandler(GPIO_Pin_6); + GPIO_EXTI_IRQHandler(GPIO_Pin_7); + GPIO_EXTI_IRQHandler(GPIO_Pin_8); + GPIO_EXTI_IRQHandler(GPIO_Pin_9); + rt_interrupt_leave(); +} + +void EXTI10_15_Handler(void) +{ + rt_interrupt_enter(); + GPIO_EXTI_IRQHandler(GPIO_Pin_10); + GPIO_EXTI_IRQHandler(GPIO_Pin_11); + GPIO_EXTI_IRQHandler(GPIO_Pin_12); + GPIO_EXTI_IRQHandler(GPIO_Pin_13); + GPIO_EXTI_IRQHandler(GPIO_Pin_14); + GPIO_EXTI_IRQHandler(GPIO_Pin_15); + rt_interrupt_leave(); +} +#endif int rt_hw_pin_init(void) { +#if defined(SOC_SERIES_FT32F0) RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE); RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE); return rt_device_pin_register("pin", &_ft32_pin_ops, RT_NULL); +#endif +#if defined(SOC_SERIES_FT32F4) + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOE, ENABLE); + return rt_device_pin_register("pin", &_ft32_pin_ops, RT_NULL); +#endif } #endif /* RT_USING_PIN */ diff --git a/bsp/ft32/libraries/Drivers/drv_gpio.h b/bsp/ft32/libraries/Drivers/drv_gpio.h index c571f35bea3..4e124e45f51 100644 --- a/bsp/ft32/libraries/Drivers/drv_gpio.h +++ b/bsp/ft32/libraries/Drivers/drv_gpio.h @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2022-03-02 FMD-AE first version + * 2025-12-31 FMD-AE add ft32f4 support */ #ifndef __DRV_GPIO_H__ @@ -17,11 +18,21 @@ extern "C" { #endif +#if defined(SOC_SERIES_FT32F0) #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ ((__GPIOx__) == (GPIOB))? 1U :\ ((__GPIOx__) == (GPIOC))? 2U :\ ((__GPIOx__) == (GPIOD))? 3U :\ ((__GPIOx__) == (GPIOF))? 5U : 4U) +#elif defined(SOC_SERIES_FT32F4) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U : 5U) +#else +#error "Unsupported SOC series" +#endif #define __GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) diff --git a/bsp/ft32/libraries/Drivers/drv_usart.c b/bsp/ft32/libraries/Drivers/drv_usart.c index 5cbd353ea02..a31d27fae78 100644 --- a/bsp/ft32/libraries/Drivers/drv_usart.c +++ b/bsp/ft32/libraries/Drivers/drv_usart.c @@ -23,10 +23,6 @@ /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif -#ifdef RT_SERIAL_USING_DMA - static void ft32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); -#endif - enum { #ifdef BSP_USING_UART1 @@ -54,7 +50,12 @@ void UART_MspInit(USART_TypeDef *USARTx) GPIO_InitTypeDef GPIO_InitStruct; if (USARTx == USART1) { +#if defined(SOC_SERIES_FT32F0) RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); +#endif +#if defined(SOC_SERIES_FT32F4) + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); +#endif RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); /*GPIO INIT*/ @@ -64,17 +65,28 @@ void UART_MspInit(USART_TypeDef *USARTx) GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOA, &GPIO_InitStruct); +#if defined(SOC_SERIES_FT32F0) GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_1); - +#endif +#if defined(SOC_SERIES_FT32F4) + GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_7); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_7); +#endif /* USART1 interrupt Init */ NVIC_SetPriority(USART1_IRQn, 5); NVIC_EnableIRQ(USART1_IRQn); } else if (USARTx == USART2) { +#if defined(SOC_SERIES_FT32F0) RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE); RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); +#endif +#if defined(SOC_SERIES_FT32F4) + RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); +#endif /*GPIO INIT*/ GPIO_InitStruct.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3; @@ -83,8 +95,14 @@ void UART_MspInit(USART_TypeDef *USARTx) GPIO_InitStruct.GPIO_OType = GPIO_OType_PP; GPIO_InitStruct.GPIO_PuPd = GPIO_PuPd_NOPULL; GPIO_Init(GPIOA, &GPIO_InitStruct); +#if defined(SOC_SERIES_FT32F0) GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_1); GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_1); +#endif +#if defined(SOC_SERIES_FT32F4) + GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_7); + GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_7); +#endif /* USART2 interrupt Init */ NVIC_SetPriority(USART2_IRQn, 5); @@ -100,15 +118,24 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co uart = rt_container_of(serial, struct ft32_uart, serial); uart->Init.USART_BaudRate = cfg->baud_rate; +#if defined(SOC_SERIES_FT32F0) uart->Init.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; - +#endif +#if defined(SOC_SERIES_FT32F4) + uart->Init.USART_Mode = USART_MODE_TX_RX; +#endif switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None; break; case RT_SERIAL_FLOWCONTROL_CTSRTS: +#if defined(SOC_SERIES_FT32F0) uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_CTS; +#endif +#if defined(SOC_SERIES_FT32F4) + uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_RTS_DTR; +#endif break; default: uart->Init.USART_HardwareFlowControl = USART_HardwareFlowControl_None; @@ -117,6 +144,7 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co switch (cfg->data_bits) { +#if defined(SOC_SERIES_FT32F0) case DATA_BITS_8: if (cfg->parity == PARITY_ODD || cfg->parity == PARITY_EVEN) uart->Init.USART_WordLength = USART_WordLength_9b; @@ -129,10 +157,32 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co default: uart->Init.USART_WordLength = USART_WordLength_8b; break; +#endif +#if defined(SOC_SERIES_FT32F4) + case DATA_BITS_9: + uart->Init.USART_WordLength = USART_CHAR_LENGTH9_ENABLE; + break; + case DATA_BITS_8: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_8BIT; + break; + case DATA_BITS_7: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_7BIT; + break; + case DATA_BITS_6: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_6BIT; + break; + case DATA_BITS_5: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_5BIT; + break; + default: + uart->Init.USART_WordLength = USART_CHAR_LENGTH_8BIT; + break; +#endif } switch (cfg->stop_bits) { +#if defined(SOC_SERIES_FT32F0) case STOP_BITS_1: uart->Init.USART_StopBits = USART_StopBits_1; break; @@ -142,10 +192,23 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co default: uart->Init.USART_StopBits = USART_StopBits_1; break; +#endif +#if defined(SOC_SERIES_FT32F4) + case STOP_BITS_1: + uart->Init.USART_StopBits = USART_STOPBITS_1; + break; + case STOP_BITS_2: + uart->Init.USART_StopBits = USART_STOPBITS_2; + break; + default: + uart->Init.USART_StopBits = USART_STOPBITS_1; + break; +#endif } switch (cfg->parity) { +#if defined(SOC_SERIES_FT32F0) case PARITY_NONE: uart->Init.USART_Parity = USART_Parity_No; break; @@ -158,11 +221,23 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co default: uart->Init.USART_Parity = USART_Parity_No; break; +#endif +#if defined(SOC_SERIES_FT32F4) + case PARITY_NONE: + uart->Init.USART_Parity = USART_PARITY_NONE; + break; + case PARITY_ODD: + uart->Init.USART_Parity = USART_PARITY_ODD; + break; + case PARITY_EVEN: + uart->Init.USART_Parity = USART_PARITY_EVEN; + break; + default: + uart->Init.USART_Parity = USART_PARITY_NONE; + break; +#endif } -#ifdef RT_SERIAL_USING_DMA - uart->dma_rx.last_index = 0; -#endif UART_MspInit(uart->config->Instance); USART_Init(uart->config->Instance, &(uart->Init)); USART_Cmd(uart->config->Instance, ENABLE); @@ -172,9 +247,6 @@ static rt_err_t ft32_configure(struct rt_serial_device *serial, struct serial_co static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg) { struct ft32_uart *uart; -#ifdef RT_SERIAL_USING_DMA - rt_ubase_t ctrl_arg = (rt_ubase_t)arg; -#endif RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ft32_uart, serial); @@ -186,21 +258,17 @@ static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg /* disable rx irq */ NVIC_DisableIRQ(uart->config->irq_type); /* disable interrupt */ +#if defined(SOC_SERIES_FT32F0) + /* enable interrupt */ USART_ITConfig(uart->config->Instance, USART_IT_RXNE, DISABLE); - -#ifdef RT_SERIAL_USING_DMA - /* disable DMA */ - if (ctrl_arg == RT_DEVICE_FLAG_DMA_RX) - { - NVIC_DisableIRQ(uart->config->dma_rx->dma_irq); - DMA_DeInit(uart->dma_rx.Instance); - } - else if (ctrl_arg == RT_DEVICE_FLAG_DMA_TX) - { - NVIC_DisableIRQ(uart->config->dma_tx->dma_irq); - DMA_DeInit(uart->dma_rx.Instance); - } + break; +#endif +#if defined(SOC_SERIES_FT32F4) + /* enable interrupt */ + USART_ITConfig(uart->config->Instance, USART_IT_RXRDY, DISABLE); + break; #endif + break; /* enable interrupt */ @@ -208,15 +276,17 @@ static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg /* enable rx irq */ NVIC_SetPriority(uart->config->irq_type, 1); NVIC_EnableIRQ(uart->config->irq_type); +#if defined(SOC_SERIES_FT32F0) /* enable interrupt */ USART_ITConfig(uart->config->Instance, USART_IT_RXNE, ENABLE); break; - -#ifdef RT_SERIAL_USING_DMA - case RT_DEVICE_CTRL_CONFIG: - ft32_dma_config(serial, ctrl_arg); +#endif +#if defined(SOC_SERIES_FT32F4) + /* enable interrupt */ + USART_ITConfig(uart->config->Instance, USART_IT_RXRDY, ENABLE); break; #endif + break; case RT_DEVICE_CTRL_CLOSE: USART_DeInit(uart->config->Instance); @@ -226,6 +296,7 @@ static rt_err_t ft32_control(struct rt_serial_device *serial, int cmd, void *arg return RT_EOK; } +#if defined(SOC_SERIES_FT32F0) rt_uint32_t ft32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) { rt_uint32_t mask; @@ -269,6 +340,7 @@ rt_uint32_t ft32_uart_get_mask(rt_uint32_t word_length, rt_uint32_t parity) } return mask; } +#endif static int ft32_putc(struct rt_serial_device *serial, char c) { @@ -276,13 +348,20 @@ static int ft32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ft32_uart, serial); - UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC); #if defined(SOC_SERIES_FT32F0) + UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC); uart->config->Instance->TDR = c; +#elif defined(SOC_SERIES_FT32F4) + USART_Transmit(uart->config->Instance, c); #else uart->config->Instance->DR = c; #endif +#if defined(SOC_SERIES_FT32F0) while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) == RESET); +#endif +#if defined(SOC_SERIES_FT32F4) + while (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TXRDY) == RESET); +#endif return 1; } @@ -294,14 +373,21 @@ static int ft32_getc(struct rt_serial_device *serial) uart = rt_container_of(serial, struct ft32_uart, serial); ch = -1; +#if defined(SOC_SERIES_FT32F0) if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET) - { +#endif +#if defined(SOC_SERIES_FT32F4) + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXRDY) != RESET) +#endif + { #if defined(SOC_SERIES_FT32F0) - ch = uart->config->Instance->RDR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); + ch = uart->config->Instance->RDR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); +#elif defined(SOC_SERIES_FT32F4) + ch = USART_Receive(uart->config->Instance); #else - ch = uart->config->Instance->DR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); + ch = uart->config->Instance->DR & ft32_uart_get_mask(uart->Init.USART_WordLength, uart->Init.USART_Parity); #endif - } + } return ch; } @@ -329,43 +415,24 @@ static rt_ssize_t ft32_dma_transmit(struct rt_serial_device *serial, rt_uint8_t static void uart_isr(struct rt_serial_device *serial) { struct ft32_uart *uart; -#ifdef RT_SERIAL_USING_DMA - rt_size_t recv_total_index, recv_len; - rt_base_t level; -#endif RT_ASSERT(serial != RT_NULL); uart = rt_container_of(serial, struct ft32_uart, serial); - +#if defined(SOC_SERIES_FT32F0) /* UART in mode Receiver -------------------------------------------------*/ if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET) { rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } -#ifdef RT_SERIAL_USING_DMA - else if ((uart->uart_dma_flag) && (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXNE) != RESET)) - { - level = rt_hw_interrupt_disable(); - recv_total_index = serial->config.bufsz - DMA_GetCurrDataCounter(&(uart->dma_rx.Instance)); - recv_len = recv_total_index - uart->dma_rx.last_index; - uart->dma_rx.last_index = recv_total_index; - rt_hw_interrupt_enable(level); - - if (recv_len) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); - } - USART_ClearFlag(uart->config->Instance, USART_IT_IDLE); - } - else if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_TC) != RESET) +#endif +#if defined(SOC_SERIES_FT32F4) + /* UART in mode Receiver -------------------------------------------------*/ + if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_RXRDY) != RESET) { - if ((serial->parent.open_flag & RT_DEVICE_FLAG_DMA_TX) != 0) - { - - } - UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_TC); + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); } #endif +#if defined (SOC_SERIES_FT32F0) else { if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_ORE) != RESET) @@ -384,12 +451,6 @@ static void uart_isr(struct rt_serial_device *serial) { USART_ClearFlag(uart->config->Instance, USART_FLAG_PE); } -#if !defined(SOC_SERIES_FT32F0) - if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_LBD) != RESET) - { - UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_LBD); - } -#endif if (USART_GetFlagStatus(uart->config->Instance, USART_FLAG_CTS) != RESET) { UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_CTS); @@ -407,42 +468,16 @@ static void uart_isr(struct rt_serial_device *serial) UART_INSTANCE_CLEAR_FUNCTION(uart->config->Instance, USART_FLAG_RXNE); } } -} - -#ifdef RT_SERIAL_USING_DMA -static void dma_isr(struct rt_serial_device *serial) -{ - struct ft32_uart *uart; - rt_size_t recv_total_index, recv_len; - rt_base_t level; - - RT_ASSERT(serial != RT_NULL); - uart = rt_container_of(serial, struct ft32_uart, serial); - - if ((DMA_GetITStatus(uart->dma_rx.Instance, DMA_IT_TC) != RESET) || - (DMA_GetITStatus(uart->dma_rx.Instance, DMA_IT_HT) != RESET)) +#endif +#if defined (SOC_SERIES_FT32F4) + else { - level = rt_hw_interrupt_disable(); - recv_total_index = serial->config.bufsz - DMA_GetCurrDataCounter(uart->dma_rx.Instance); - if (recv_total_index == 0) - { - recv_len = serial->config.bufsz - uart->dma_rx.last_index; - } - else - { - recv_len = recv_total_index - uart->dma_rx.last_index; - } - uart->dma_rx.last_index = recv_total_index; - rt_hw_interrupt_enable(level); - if (recv_len) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); - } } -} #endif +} +#if defined(SOC_SERIES_FT32F0) #if defined(BSP_USING_UART1) void USART1_IRQHandler(void) { @@ -454,30 +489,7 @@ void USART1_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) -void UART1_DMA_RX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - __DMA_IRQHandler(uart_obj[UART1_INDEX].dma_rx.Instance); - - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_RX_USING_DMA) */ -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) -void UART1_DMA_TX_IRQHandler(void) -{ - /* enter interrupt */ - rt_interrupt_enter(); - - __DMA_IRQHandler(uart_obj[UART1_INDEX].dma_tx.Instance); - /* leave interrupt */ - rt_interrupt_leave(); -} -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART1_TX_USING_DMA) */ #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) @@ -491,170 +503,51 @@ void USART2_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) -void UART2_DMA_RX_IRQHandler(void) + +#endif /* BSP_USING_UART2 */ +#endif + +#if defined(SOC_SERIES_FT32F4) +#if defined(BSP_USING_UART1) +void USART1_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - __DMA_IRQHandler(uart_obj[UART2_INDEX].dma_rx.Instance); + uart_isr(&(uart_obj[UART1_INDEX].serial)); /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_RX_USING_DMA) */ -#if defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) -void UART2_DMA_TX_IRQHandler(void) + +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +void USART2_Handler(void) { /* enter interrupt */ rt_interrupt_enter(); - __DMA_IRQHandler(uart_obj[UART2_INDEX].dma_tx.Instance); + uart_isr(&(uart_obj[UART2_INDEX].serial)); /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(RT_SERIAL_USING_DMA) && defined(BSP_UART2_TX_USING_DMA) */ -#endif /* BSP_USING_UART2 */ +#endif /* BSP_USING_UART2 */ +#endif static void ft32_uart_get_dma_config(void) { #ifdef BSP_USING_UART1 uart_obj[UART1_INDEX].uart_dma_flag = 0; -#ifdef BSP_UART1_RX_USING_DMA - uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; - uart_config[UART1_INDEX].dma_rx = &uart1_dma_rx; -#endif -#ifdef BSP_UART1_TX_USING_DMA - uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart1_dma_tx = UART1_DMA_TX_CONFIG; - uart_config[UART1_INDEX].dma_tx = &uart1_dma_tx; -#endif #endif #ifdef BSP_USING_UART2 uart_obj[UART2_INDEX].uart_dma_flag = 0; -#ifdef BSP_UART2_RX_USING_DMA - uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; - static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; - uart_config[UART2_INDEX].dma_rx = &uart2_dma_rx; -#endif -#ifdef BSP_UART2_TX_USING_DMA - uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; - static struct dma_config uart2_dma_tx = UART2_DMA_TX_CONFIG; - uart_config[UART2_INDEX].dma_tx = &uart2_dma_tx; #endif -#endif -} - -#ifdef RT_SERIAL_USING_DMA -static void ft32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) -{ - struct rt_serial_rx_fifo *rx_fifo; - - DMA_InitTypeDef Init; - struct dma_config *dma_config; - struct ft32_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(flag == RT_DEVICE_FLAG_DMA_TX || flag == RT_DEVICE_FLAG_DMA_RX); - uart = rt_container_of(serial, struct ft32_uart, serial); - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - Init = &uart->dma_rx.Init; - dma_config = uart->config->dma_rx; - } - else /* RT_DEVICE_FLAG_DMA_TX == flag */ - { - Init = &uart->dma_tx.Init; - dma_config = uart->config->dma_tx; - } - LOG_D("%s dma config start", uart->config->name); - - { - rt_uint32_t tmpreg = 0x00U; -#if defined(SOC_SERIES_FT32F0) - /* enable DMA clock && Delay after an RCC peripheral clock enabling*/ - SET_BIT(RCC->AHBENR, dma_config->dma_rcc); - tmpreg = READ_BIT(RCC->AHBENR, dma_config->dma_rcc); -#endif - - (void)(tmpreg); /* To avoid compiler warnings */ - } - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - } - else if (RT_DEVICE_FLAG_DMA_TX == flag) - { - } - - Init.DMA_PeripheralInc = DMA_PeripheralInc_Disable; - Init.MemInc = DMA_MemoryInc_Enable; - Init.PeriphDataAlignment = DMA_PeripheralDataSize_Byte; - Init.MemDataAlignment = DMA_MemoryDataSize_Byte; - - if (RT_DEVICE_FLAG_DMA_RX == flag) - { - Init.Direction = DMA_DIR_PeripheralSRC; - Init.Mode = DMA_Mode_Circular; - } - else if (RT_DEVICE_FLAG_DMA_TX == flag) - { - Init.Direction = DMA_DIR_PeripheralDST; - Init.Mode = DMA_Mode_Normal; - } - - Init.Priority = DMA_Priority_Medium; - DMA_DeInit(dma_config->Instance); - DMA_Init(dma_config->Instance); - - /* enable interrupt */ - if (flag == RT_DEVICE_FLAG_DMA_RX) - { - rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; - /* Start DMA transfer */ - UART_Receive_DMA(uart->config->Instance, rx_fifo->buffer, serial->config.bufsz); - CLEAR_BIT(uart->handle.Instance->CR3, USART_CR3_EIE); - USART_ITConfig(uart->config->Instance, USART_IT_IDLE, ENABLE); - } - - /* DMA irq should set in DMA TX mode, or HAL_UART_TxCpltCallback function will not be called */ - NVIC_SetPriority(dma_config->dma_irq, 0, 0); - NVIC_EnableIRQ(dma_config->dma_irq); - - NVIC_SetPriority(uart->config->irq_type, 1, 0); - NVIC_EnableIRQ(uart->config->irq_type); - - LOG_D("%s dma %s instance: %x", uart->config->name, flag == RT_DEVICE_FLAG_DMA_RX ? "RX" : "TX", DMA_Handle->Instance); - LOG_D("%s dma config done", uart->config->name); } -static void _dma_tx_complete(struct rt_serial_device *serial) -{ - struct ft32_uart *uart; - rt_size_t trans_total_index; - rt_base_t level; - - RT_ASSERT(serial != RT_NULL); - uart = rt_container_of(serial, struct ft32_uart, serial); - - level = rt_hw_interrupt_disable(); - trans_total_index = DMA_GetCurrDataCounter(uart->dma_tx.Instance); - rt_hw_interrupt_enable(level); - - if (trans_total_index == 0) - { - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_TX_DMADONE); - } -} - - -#endif /* RT_SERIAL_USING_DMA */ - static const struct rt_uart_ops ft32_uart_ops = { .configure = ft32_configure, diff --git a/bsp/ft32/libraries/Drivers/drv_usart.h b/bsp/ft32/libraries/Drivers/drv_usart.h index ae0462f407c..0530ddcfe0e 100644 --- a/bsp/ft32/libraries/Drivers/drv_usart.h +++ b/bsp/ft32/libraries/Drivers/drv_usart.h @@ -25,6 +25,9 @@ int rt_hw_usart_init(void); #if defined(SOC_SERIES_FT32F0) #define UART_INSTANCE_CLEAR_FUNCTION USART_ClearITPendingBit #endif +#if defined(SOC_SERIES_FT32F4) + #define UART_INSTANCE_CLEAR_FUNCTION USART_ClearFlag +#endif #define USART_TX_Pin GPIO_PIN_2 #define USART_TX_GPIO_Port GPIOA @@ -46,20 +49,6 @@ struct ft32_uart { USART_InitTypeDef Init; struct ft32_uart_config *config; - -#ifdef RT_SERIAL_USING_DMA - struct - { - DMA_InitTypeDef Init; - DMA_Channel_TypeDef *Instance; - rt_size_t last_index; - } dma_rx; - struct - { - DMA_InitTypeDef Init; - DMA_Channel_TypeDef *Instance; - } dma_tx; -#endif rt_uint16_t uart_dma_flag; struct rt_serial_device serial; }; diff --git a/bsp/ft32/libraries/Drivers/uart_config.h b/bsp/ft32/libraries/Drivers/uart_config.h index 19a9ab79739..febb31f71da 100644 --- a/bsp/ft32/libraries/Drivers/uart_config.h +++ b/bsp/ft32/libraries/Drivers/uart_config.h @@ -28,17 +28,6 @@ extern "C" { #endif /* UART1_CONFIG */ #endif /* BSP_USING_UART1 */ -#if defined(BSP_UART1_RX_USING_DMA) -#ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .dma_rcc = UART1_RX_DMA_RCC, \ - .dma_irq = UART1_RX_DMA_IRQ, \ - } -#endif /* UART1_DMA_RX_CONFIG */ -#endif /* BSP_UART1_RX_USING_DMA */ - #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG #define UART2_CONFIG \ @@ -50,17 +39,6 @@ extern "C" { #endif /* UART2_CONFIG */ #endif /* BSP_USING_UART2 */ -#if defined(BSP_UART2_RX_USING_DMA) -#ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .dma_rcc = UART2_RX_DMA_RCC, \ - .dma_irq = UART2_RX_DMA_IRQ, \ - } -#endif /* UART2_DMA_RX_CONFIG */ -#endif /* BSP_UART2_RX_USING_DMA */ - #ifdef __cplusplus } #endif diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cachel1_armv7.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cachel1_armv7.h new file mode 100644 index 00000000000..abebc95f946 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cachel1_armv7.h @@ -0,0 +1,411 @@ +/****************************************************************************** + * @file cachel1_armv7.h + * @brief CMSIS Level 1 Cache API for Armv7-M and later + * @version V1.0.1 + * @date 19. April 2021 + ******************************************************************************/ +/* + * Copyright (c) 2020-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_CACHEL1_ARMV7_H +#define ARM_CACHEL1_ARMV7_H + +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#ifndef __SCB_DCACHE_LINE_SIZE +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +#ifndef __SCB_ICACHE_LINE_SIZE +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#endif + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + +#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armcc.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armcc.h new file mode 100644 index 00000000000..55f87a0995f --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armcc.h @@ -0,0 +1,888 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.3.2 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) +#define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + +/* __ARM_ARCH_8M_BASE__ not applicable */ +/* __ARM_ARCH_8M_MAIN__ not applicable */ +/* __ARM_ARCH_8_1M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + #define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP + #define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT + #define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE + #define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE + #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) +#define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return (__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; + __ISB(); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); +#else + return (0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armclang.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armclang.h new file mode 100644 index 00000000000..69114177477 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armclang.h @@ -0,0 +1,1503 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.4.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ + (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armclang_ltm.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armclang_ltm.h new file mode 100644 index 00000000000..1e255d5907f --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_armclang_ltm.h @@ -0,0 +1,1928 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.5.3 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} +#endif + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +#ifndef __ARM_COMPAT_H +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} +#endif + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_compiler.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_compiler.h new file mode 100644 index 00000000000..cf1b6e4c6ec --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_compiler.h @@ -0,0 +1,292 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) +#include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) +#include "cmsis_armclang_ltm.h" + +/* +* Arm Compiler above 6.10.1 (armclang) +*/ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) +#include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) +#include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) +#include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) +#include + +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +struct __attribute__((packed)) T_UINT32 +{ + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 +#endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __packed__ +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +struct __packed__ T_UINT32 +{ + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __align(x) +#endif +#ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT +#endif +#ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 +#endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) +#include + +#ifndef __ASM + #define __ASM _asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE +#endif +#ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN +#endif +#ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED +#endif +#ifndef __WEAK + #define __WEAK __weak +#endif +#ifndef __PACKED + #define __PACKED @packed +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION @packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ +@packed struct T_UINT32 +{ + uint32_t v; +}; +#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE +__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; +#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ +__PACKED_STRUCT T_UINT16_READ { uint16_t v; }; +#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE +__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; +#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ +__PACKED_STRUCT T_UINT32_READ { uint32_t v; }; +#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) +#endif +#ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT +#endif +#ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 +#endif + + +#else +#error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_gcc.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_gcc.h new file mode 100644 index 00000000000..67bda4ef3c3 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_gcc.h @@ -0,0 +1,2211 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.4.1 + * @date 27. May 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL __StackSeal +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting special-purpose register PRIMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); + __ISB(); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); + __ISB(); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); + } else { + result = __SXTB16(__ROR(op1, rotate)) ; + } + return result; +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) +{ + uint32_t result; + if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { + __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); + } else { + result = __SXTAB16(op1, __ROR(op2, rotate)); + } + return result; +} + + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +#define __PKHBT(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +__extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_iccarm.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_iccarm.h new file mode 100644 index 00000000000..65b824b009c --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_iccarm.h @@ -0,0 +1,1002 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.3.0 + * @date 14. April 2021 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2021 IAR Systems +// Copyright (c) 2017-2021 Arm Limited. All rights reserved. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#undef __WEAK /* undo the definition from DLib_Defaults.h */ +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#ifndef __STACK_SEAL +#define __STACK_SEAL STACKSEAL$$Base +#endif + +#ifndef __TZ_STACK_SEAL_SIZE +#define __TZ_STACK_SEAL_SIZE 8U +#endif + +#ifndef __TZ_STACK_SEAL_VALUE +#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL +#endif + +__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { + *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; +} +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __arm_wsr("CONTROL", control); + __iar_builtin_ISB(); +} + + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __arm_wsr("CONTROL_NS", control); + __iar_builtin_ISB(); +} + + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + __iar_builtin_ISB(); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) + +#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_version.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_version.h new file mode 100644 index 00000000000..8a74531e8de --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.5 + * @date 02. February 2022 + ******************************************************************************/ +/* + * Copyright (c) 2009-2022 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv81mml.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv81mml.h new file mode 100644 index 00000000000..94128a1a709 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv81mml.h @@ -0,0 +1,4228 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.4.2 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2018-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +#if defined ( __CC_ARM ) + #error Legacy Arm Compiler does not support Armv8.1-M target architecture. +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #if __FPU_PRESENT != 0U + #ifndef __FPU_DP + #define __FPU_DP 0U + #warning "__FPU_DP not defined in device header file; using default!" + #endif + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __PMU_PRESENT + #define __PMU_PRESENT 0U + #warning "__PMU_PRESENT not defined in device header file; using default!" + #endif + + #if __PMU_PRESENT != 0U + #ifndef __PMU_NUM_EVENTCNT + #define __PMU_NUM_EVENTCNT 2U + #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" + #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) + #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ + #endif + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ + uint32_t RESERVED4[14U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ +#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ + +#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ +#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ +#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ + +#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ +#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ + +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ +#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ + +#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ +#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ + +#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ +#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ + +#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ +#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ + +#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ +#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ + +#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ +#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ + +#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ +#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ + +#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ +#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ + +/* SCB Debug Feature Register 0 Definitions */ +#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ +#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ + +#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ +#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB RAS Fault Status Register Definitions */ +#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ +#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ + +#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ +#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ + +#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ +#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[3U]; + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ +#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) + \brief Type definitions for the Performance Monitoring Unit (PMU) + @{ + */ + +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ +#if __PMU_NUM_EVENTCNT<31 + uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; +#endif + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ + __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ + uint32_t RESERVED13[3]; + __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ + __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ + __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ + __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ + __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ + __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ + __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ + __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ +} PMU_Type; + +/** \brief PMU Event Counter Registers (0-30) Definitions */ + +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ + +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ + +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ + +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ + +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ + +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ + +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ + +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ + +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ + +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/*@} end of group CMSIS_PMU */ +#endif + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ +#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ + +#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ +#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ +#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ + +#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ +#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ + +#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ +#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ +#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ + +#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ +#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ + +#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ +#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ +#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ + +#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ +#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ + +#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ +#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ + +#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ +#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ + +#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ +#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ + +#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ +#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ +#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ + +#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ +#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ + +#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ +#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ + +#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ +#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ +#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Set Clear Exception and Monitor Control Register Definitions */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ +#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ + +#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ +#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ +#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ + +#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ +#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ +#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ + +#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ +#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ + +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ + #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## PMU functions and events #################################### */ + +#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) + +#include "pmu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + +/* ########################## MVE functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_MveFunctions MVE Functions + \brief Function that provides MVE type. + @{ + */ + +/** + \brief get MVE type + \details returns the MVE type + \returns + - \b 0: No Vector Extension (MVE) + - \b 1: Integer Vector Extension (MVE-I) + - \b 2: Floating-point Vector Extension (MVE-F) + */ +__STATIC_INLINE uint32_t SCB_GetMVEType(void) +{ + const uint32_t mvfr1 = FPU->MVFR1; + if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) + { + return 2U; + } + else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) + { + return 1U; + } + else + { + return 0U; + } +} + + +/*@} end of CMSIS_Core_MveFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv8mbl.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv8mbl.h new file mode 100644 index 00000000000..932d3d188bf --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv8mbl.h @@ -0,0 +1,2222 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 27. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv8mml.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv8mml.h new file mode 100644 index 00000000000..c119fbf2424 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_armv8mml.h @@ -0,0 +1,3209 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.2.3 + * @date 13. October 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (80U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 1U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED7[21U]; + __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ + uint32_t RESERVED3[69U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and VFP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and VFP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and VFP Feature Register 2 Definitions */ +#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ +#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ + +/*@} end of group CMSIS_FPU */ + +/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DCB Debug Control Block + \brief Type definitions for the Debug Control Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/* DHCSR, Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/* DCRSR, Debug Core Register Select Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/* DCRDR, Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/* DEMCR, Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/* DAUTHCTRL, Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/* DSCSR, Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/*@} end of group CMSIS_DCB */ + + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DIB Debug Identification Block + \brief Type definitions for the Debug Identification Block Registers + @{ + */ + +/** + \brief Structure type to access the Debug Identification Block Registers (DIB). + */ +typedef struct +{ + __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ + __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ + __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ + __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ + __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ +} DIB_Type; + +/* DLAR, SCS Software Lock Access Register Definitions */ +#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ +#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ + +/* DLSR, SCS Software Lock Status Register Definitions */ +#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ +#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ + +#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ +#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ + +#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ +#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ + +/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ +#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ +#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ + +/* DDEVARCH, SCS Device Architecture Register Definitions */ +#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ +#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ + +#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ +#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ + +#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ +#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ + +#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ +#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ + +#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ +#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ + +/* DDEVTYPE, SCS Device Type Register Definitions */ +#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ +#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ + +#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ +#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ + + +/*@} end of group CMSIS_DIB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ + #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ + #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ + #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ + #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ + #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ + #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ + #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ + #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_register_aliases Backwards Compatibility Aliases + \brief Register alias definitions for backwards compatibility. + @{ + */ +#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ +/*@} */ + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + +/* ########################## Cache functions #################################### */ + +#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ + (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) +#include "cachel1_armv7.h" +#endif + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## Debug Control function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DCBFunctions Debug Control Functions + \brief Functions that access the Debug Control Block. + @{ + */ + + +/** + \brief Set Debug Authentication Control Register + \details writes to Debug Authentication Control register. + \param [in] value value to be writen. + */ +__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) +{ + __DSB(); + __ISB(); + DCB->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register + \details Reads Debug Authentication Control register. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) +{ + return (DCB->DAUTHCTRL); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Debug Authentication Control Register (non-secure) + \details writes to non-secure Debug Authentication Control register when in secure state. + \param [in] value value to be writen + */ +__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) +{ + __DSB(); + __ISB(); + DCB_NS->DAUTHCTRL = value; + __DSB(); + __ISB(); +} + + +/** + \brief Get Debug Authentication Control Register (non-secure) + \details Reads non-secure Debug Authentication Control register when in secure state. + \return Debug Authentication Control Register. + */ +__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) +{ + return (DCB_NS->DAUTHCTRL); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## Debug Identification function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions + \brief Functions that access the Debug Identification Block. + @{ + */ + + +/** + \brief Get Debug Authentication Status Register + \details Reads Debug Authentication Status register. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) +{ + return (DIB->DAUTHSTATUS); +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Debug Authentication Status Register (non-secure) + \details Reads non-secure Debug Authentication Status register when in secure state. + \return Debug Authentication Status Register. + */ +__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) +{ + return (DIB_NS->DAUTHSTATUS); +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_DCBFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_cm4.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_cm4.h new file mode 100644 index 00000000000..2b1f4633d2b --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/core_cm4.h @@ -0,0 +1,2129 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.2 + * @date 04. June 2021 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) +#if defined __TARGET_FPU_VFP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#if defined __ARM_FP +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __GNUC__ ) +#if defined (__VFP_FP__) && !defined(__SOFTFP__) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __ICCARM__ ) +#if defined __ARMVFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TI_ARM__ ) +#if defined __TI_VFP_SUPPORT__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __TASKING__ ) +#if defined __FPU_VFP__ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#elif defined ( __CSMC__ ) +#if ( __CSMC__ & 0x400U) +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) +#define __FPU_USED 1U +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0U +#endif +#else +#define __FPU_USED 0U +#endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus +extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000U +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0U +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0U +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __VTOR_PRESENT +#define __VTOR_PRESENT 1U +#warning "__VTOR_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 3U +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0U +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0: 16; /*!< bit: 0..15 Reserved */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 7; /*!< bit: 20..26 Reserved */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR: 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0: 1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1: 6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE: 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1: 4; /*!< bit: 20..23 Reserved */ + uint32_t T: 1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2: 2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q: 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V: 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C: 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z: 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N: 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV: 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL: 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA: 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0: 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL +#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE +#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" +#endif +#include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping +#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping +#define NVIC_EnableIRQ __NVIC_EnableIRQ +#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ +#define NVIC_DisableIRQ __NVIC_DisableIRQ +#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ +#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ +#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +#define NVIC_GetActive __NVIC_GetActive +#define NVIC_SetPriority __NVIC_SetPriority +#define NVIC_GetPriority __NVIC_GetPriority +#define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL +#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" +#endif +#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else +#define NVIC_SetVector __NVIC_SetVector +#define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos)); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return ((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return (0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return ((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return (0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return ((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return (0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL) -4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return (((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return (((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL) -4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits)) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority) & (uint32_t)((1UL << (SubPriorityBits)) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for (;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL) != 0UL)) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/ft32f407xe.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/ft32f407xe.h new file mode 100644 index 00000000000..b46f626fa68 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/ft32f407xe.h @@ -0,0 +1,20900 @@ +/**************************************************************************//** + * @file ft32f407xe.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File for + * Device CMSDK_CM4 + * @version V3.01 + * @date 06. March 2012 + * + * @note + * Copyright (C) 2010-2012 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + + +#ifndef __FT32F407XE_H +#define __FT32F407XE_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Library_configuration_section + * @{ + */ + +/* Uncomment the line below according to the target FT32F0 device used in your + application + */ + +#if !defined (FT32F407XE) +#define FT32F407XE +#endif + + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ + + +#if !defined USE_STDPERIPH_DRIVER +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ +/*#define USE_STDPERIPH_DRIVER*/ +#endif /* USE_STDPERIPH_DRIVER */ + +/** + * @brief In the following line adjust the value of External High Speed oscillator (HSE) + used in your application + + Tip: To avoid modifying this file each time you need to use different HSE, you + can define the HSE value in your toolchain compiler preprocessor. + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/ +#endif /* HSE_VALUE */ + +/** + * @brief In the following line adjust the External High Speed oscillator (HSE) Startup + Timeout value + */ +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT ((uint32_t)0x00005000) /*!< Time out for HSE start up */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup + Timeout value + */ +#if !defined (HSI_STARTUP_TIMEOUT) +#define HSI_STARTUP_TIMEOUT ((uint32_t)0x00005000) /*!< Time out for HSI start up */ +#endif /* HSI_STARTUP_TIMEOUT */ + +#if !defined (HSI48_STARTUP_TIMEOUT) +#define HSI48_STARTUP_TIMEOUT ((uint32_t)0x00005000) /*!< Time out for HSI48 start up */ +#endif /* HSI48_STARTUP_TIMEOUT */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT ((uint32_t)0x00005000) /*!< Time out for LSE start up */ +#endif /* LSE_STARTUP_TIMEOUT */ + +#if !defined (LSI_STARTUP_TIMEOUT) +#define LSI_STARTUP_TIMEOUT ((uint32_t)0x00005000) /*!< Time out for LSI start up */ +#endif /* LSI_STARTUP_TIMEOUT */ + +#if !defined (PLL_STARTUP_TIMEOUT) +#define PLL_STARTUP_TIMEOUT ((uint32_t)0x00005000) /*!< Time out for PLL start up */ +#endif /* PLL_STARTUP_TIMEOUT */ + +#if !defined (PLL2_STARTUP_TIMEOUT) +#define PLL2_STARTUP_TIMEOUT ((uint32_t)0x00005000) /*!< Time out for PLL2 start up */ +#endif /* PLL2_STARTUP_TIMEOUT */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI_VALUE */ + +#if !defined (HSE_VALUE) +#define HSE_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSE_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* HSI48_VALUE */ + +#if !defined (LSI_VALUE) +#define LSI_VALUE ((uint32_t)32000) /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +#endif /* LSI_VALUE */ + +#if !defined (LSE_VALUE) +#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ + +/** + * @brief FT32F0XX Standard Peripheral Library version number V1.4.0 + */ +#define __FT32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __FT32F4XX_STDPERIPH_VERSION_SUB1 (0x05) /*!< [23:16] sub1 version */ +#define __FT32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ +#define __FT32F4XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __FT32F4XX_STDPERIPH_VERSION ((__FT32F4XX_STDPERIPH_VERSION_MAIN << 24)\ + |(__FT32F4XX_STDPERIPH_VERSION_SUB1 << 16)\ + |(__FT32F4XX_STDPERIPH_VERSION_SUB2 << 8)\ + |(__FT32F4XX_STDPERIPH_VERSION_RC)) + + +/** @addtogroup CMSDK_CM4_Definitions CMSDK_CM4 Definitions + This file defines all structures and symbols for CMSDK_CM4: + - registers and bitfields + - peripheral base address + - peripheral ID + - Peripheral definitions + @{ +*/ + + +/******************************************************************************/ +/* Processor and Core Peripherals */ +/******************************************************************************/ +/** @addtogroup CMSDK_CM4_CMSIS Device CMSIS Definitions + Configuration of the Cortex-M4 Processor and Core Peripherals + @{ +*/ + +/* + * ========================================================================== + * ---------- Interrupt Number Definition ----------------------------------- + * ========================================================================== + */ + +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */ + + /****** CMSDK Specific Interrupt Numbers *******************************************************/ + WWDG_IRQn = 0, + PVD_IRQn = 1, + TAMP_STAMP_IRQn = 2, + RTC_IRQn = 3, + FLASH_IRQn = 4, + RCC_IRQn = 5, + EXTI0_IRQn = 6, + EXTI1_IRQn = 7, + EXTI2_IRQn = 8, + EXTI3_IRQn = 9, + EXTI4_IRQn = 10, + DMA1_CH0_IRQn = 11, + DMA1_CH1_IRQn = 12, + DMA1_CH2_IRQn = 13, + DMA1_CH3_IRQn = 14, + DMA1_CH4_IRQn = 15, + DMA1_CH5_IRQn = 16, + DMA1_CH6_IRQn = 17, + ADC_IRQn = 18, + CAN1_IRQn = 19, + CAN2_IRQn = 20, + CAN3_IRQn = 21, + CAN4_IRQn = 22, + EXTI9_5_IRQn = 23, + TIM1_BRK_TIM9_IRQn = 24, + TIM1_UP_TIM1O_IRQn = 25, + TIM1_TRG_COM_TIM11_IRQn = 26, + TIM1_CC_IRQn = 27, + TIM2_IRQn = 28, + TIM3_IRQn = 29, + TIM4_IRQn = 30, + I2C1_IRQn = 31, + I2C2_IRQn = 32, + QSPI_IRQn = 33, + SPI1_IRQn = 34, + SPI2_IRQn = 35, + USART1_IRQn = 36, + USART2_IRQn = 37, + USART3_IRQn = 38, + EXTI15_10_IRQn = 39, + RTCAlarm_IRQn = 40, + OTG_FS_WKUP_IRQn = 41, + TIM8_BRK_TIM12_IRQn = 42, + TIM8_UP_TIM13_IRQn = 43, + TIM8_TRG_COM_TIM14_IRQn = 44, + TIM8_CC_IRQn = 45, + DMA1_CH7_IRQn = 46, + FMC_IRQn = 47, + SDIO_IRQn = 48, + TIM5_IRQn = 49, + SPI3_IRQn = 50, + UART4_IRQn = 51, + UART5_IRQn = 52, + TIM6_DAC_IRQn = 53, + TIM7_IRQn = 54, + DMA2_CH0_IRQn = 55, + DMA2_CH1_IRQn = 56, + DMA2_CH2_IRQn = 57, + DMA2_CH3_IRQn = 58, + DMA2_CH4_IRQn = 59, + OTG_FS_IRQn = 60, + DMA2_CH5_IRQn = 61, + DMA2_CH6_IRQn = 62, + DMA2_CH7_IRQn = 63, + USART6_IRQn = 64, + I2C3_IRQn = 65, + OTG_HS_EP1_OUT_IRQn = 66, + OTG_HS_EP1_IN_IRQn = 67, + OTG_HS_WKUP_IRQn = 68, + OTG_HS_IRQn = 69, + RNG_IRQn = 70, + FPU_IRQn = 71, + CRS_IRQn = 72, + SPDIF_IRQn = 73, + SSI_AC97_IRQn = 74, + ETH_WKUP_IRQn = 75, + LPUART_IRQn = 76, + LPTIM_IRQn = 77, + ETH_SBD_IRQn = 78, + ETH_PERCHTX_IRQn = 79, + ETH_PERCHRX_IRQn = 80, + EPWM1_IRQn = 81, + EPWM1_TZ_IRQn = 82, + EPWM2_IRQn = 83, + EPWM2_TZ_IRQn = 84, + EPWM3_IRQn = 85, + EPWM3_TZ_IRQn = 86, + EPWM4_IRQn = 87, + EPWM4_TZ_IRQn = 88, + ECAP_IRQn = 89, + EQEP_IRQn = 90, + DLL_CAL_IRQn = 91, + COMP1_IRQn = 92, + COMP2_IRQn = 93, + COMP3_IRQn = 94, + COMP4_IRQn = 95, + COMP5_IRQn = 96, + COMP6_IRQn = 97, + ICACHE_IRQn = 98, + DCACHE_IRQn = 99, + UART7_IRQn = 100 +} IRQn_Type; + + +/* + * ========================================================================== + * ----------- Processor and Core Peripheral Section ------------------------ + * ========================================================================== + */ + +/* Configuration of the Cortex-M4 Processor and Core Peripherals */ +#define __CM4_REV 0x0001 /*!< Core Revision r0p1 */ +#define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ + +/*@}*/ /* end of group CMSDK_CM4_CMSIS */ + +#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ +#include "ft32f4xx.h" +#include "system_ft32f4xx.h" /* CMSDK_CM4 System include file */ +#include +#include +#include +#include + + +/** @addtogroup Exported_types + * @{ + */ +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + ERROR = 0, + SUCCESS = !ERROR +} ErrorStatus; + + +/******************************************************************************/ +/* Device Specific Peripheral registers structures */ +/******************************************************************************/ +/** @addtogroup CMSDK_CM4_Peripherals CMSDK_CM4 Peripherals + CMSDK_CM4 Device Specific Peripheral registers structures + @{ +*/ + +//#if defined ( __CC_ARM ) +//#pragma anon_unions +//#endif + +typedef struct +{ + __IO uint32_t TIM1_CR1 ; + __IO uint32_t TIM1_CR2 ; + __IO uint32_t TIM1_SMCR ; + __IO uint32_t TIM1_DIER ; + __IO uint32_t TIM1_SR ; + __IO uint32_t TIM1_EGR ; + __IO uint32_t TIM1_CCMR1 ; + __IO uint32_t TIM1_CCMR2 ; + __IO uint32_t TIM1_CCER ; + __IO uint32_t TIM1_CNT ; + __IO uint32_t TIM1_PSC ; + __IO uint32_t TIM1_ARR ; + __IO uint32_t TIM1_RCR ; + __IO uint32_t TIM1_CCR1 ; + __IO uint32_t TIM1_CCR2 ; + __IO uint32_t TIM1_CCR3 ; + __IO uint32_t TIM1_CCR4 ; + __IO uint32_t TIM1_BDTR ; + __IO uint32_t TIM1_DCR ; + __IO uint32_t TIM1_DMAR ; + __IO uint32_t TIM1_OR1 ; //0x50, added by yqiu + __IO uint32_t TIM1_CCMR3 ; //0x54, added by yqiu + __IO uint32_t TIM1_CCR5 ; //0x58, added by yqiu + __IO uint32_t TIM1_CCR6 ; //0x5c, added by yqiu + __IO uint32_t TIM1_AF ; //0x60, added by yqiu + __IO uint32_t TIM1_AF2 ; //0x64, added by yqiu + __IO uint32_t TIM1_TISEL ; //0x68, added by yqiu +} TIM1_TypeDef; + + +typedef struct +{ + __IO uint32_t TBCTL ; + __IO uint32_t TBSTS ; + __IO uint32_t TBPHSHR ; + __IO uint32_t TBPHS ; + __IO uint32_t TBCTR ; + __IO uint32_t TBPRD ; + __IO uint32_t TBPRDHR ; + __IO uint32_t CMPCTL ; + __IO uint32_t CMPAHR ; + __IO uint32_t CMPA ; + __IO uint32_t CMPB ; + __IO uint32_t AQCTLA ; + __IO uint32_t AQCTLB ; + __IO uint32_t AQSFRC ; + __IO uint32_t AQCSFRC ; + __IO uint32_t DBCTL ; + __IO uint32_t DBRED ; + __IO uint32_t DBFED ; + __IO uint32_t PCCTL ; + __IO uint32_t TZSEL ; + __IO uint32_t TZDCSEL ; + __IO uint32_t TZCTL ; + __IO uint32_t TZEINT ; + __IO uint32_t TZFLG ; + __IO uint32_t TZCLR ; + __IO uint32_t TZFRC ; + __IO uint32_t ETSEL ; + __IO uint32_t ETPS ; + __IO uint32_t ETFLG ; + __IO uint32_t ETCLR ; + __IO uint32_t ETFRC ; + __IO uint32_t DCTRIPSEL ; + __IO uint32_t DCACTL ; + __IO uint32_t DCBCTL ; + __IO uint32_t DCFCTL ; + __IO uint32_t DCCAPCTL ; + __IO uint32_t DCFOFFSET ; + __IO uint32_t DCFOFFSETCNT ; + __IO uint32_t DCFWINDOW ; + __IO uint32_t DCFWINDOWCNT ; + __IO uint32_t DCCAP ; + __IO uint32_t HRCNFG ; + __IO uint32_t HRPWR ; + __IO uint32_t HRMSTEP ; + __IO uint32_t HRPCTL ; + __IO uint32_t MEPINT ; + __IO uint32_t MEPFLG ; + __IO uint32_t MEPCLR ; +} EPWM_TypeDef; + + +typedef struct +{ + __IO uint32_t TSCTR ; + __IO uint32_t CTRPHS ; + __IO uint32_t CAP1 ; + __IO uint32_t CAP2 ; + __IO uint32_t CAP3 ; + __IO uint32_t CAP4 ; + __IO uint32_t ECCTL1 ; + __IO uint32_t ECCTL2 ; + __IO uint32_t ECEINT ; + __IO uint32_t ECFLG ; + __IO uint32_t ECCLR ; + __IO uint32_t ECFRC ; +} ECAP_TypeDef; + + +typedef struct +{ + __IO uint32_t QPOSCNT ; + __IO uint32_t QPOSINIT ; + __IO uint32_t QPOSMAX ; + __IO uint32_t QPOSCMP ; + __IO uint32_t QPOSILAT ; + __IO uint32_t QPOSSLAT ; + __IO uint32_t QPOSLAT ; + __IO uint32_t QUTMR ; + __IO uint32_t QUPRD ; + __IO uint32_t QWDTMR ; + __IO uint32_t QWDPRD ; + __IO uint32_t QDECCTL ; + __IO uint32_t QEPCTL ; + __IO uint32_t QCAPCTL ; + __IO uint32_t QPOSCTL ; + __IO uint32_t QEINT ; + __IO uint32_t QFLG ; + __IO uint32_t QCLR ; + __IO uint32_t QFRC ; + __IO uint32_t QEPSTS ; + __IO uint32_t QCTMR ; + __IO uint32_t QCPRD ; + __IO uint32_t QCTMRLAT ; + __IO uint32_t QCPRDLAT ; +} EQEP_TypeDef; + + +typedef struct +{ + __IO uint32_t ISR ; + __IO uint32_t IER ; + __IO uint32_t CR ; + __IO uint32_t CFGR1 ; + __IO uint32_t CFGR2 ; + __IO uint32_t SMPR1 ; + __IO uint32_t SMPR2 ; + __IO uint32_t SMPR3 ; + __IO uint32_t TR1 ; + __IO uint32_t TR2 ; + __IO uint32_t TR3 ; + uint32_t RESERVED1 ; + __IO uint32_t SQR1 ; + __IO uint32_t SQR2 ; + __IO uint32_t SQR3 ; + __IO uint32_t SQR4 ; + __IO uint32_t DR ; + uint32_t RESERVED2[2] ; + __IO uint32_t JSQR ; + uint32_t RESERVED3[4] ; + __IO uint32_t OFR1 ; + __IO uint32_t OFR2 ; + __IO uint32_t OFR3 ; + __IO uint32_t OFR4 ; + uint32_t RESERVED4[4] ; + __IO uint32_t JDR1 ; + __IO uint32_t JDR2 ; + __IO uint32_t JDR3 ; + __IO uint32_t JDR4 ; + uint32_t RESERVED5[4] ; + __IO uint32_t AWD2CR ; + __IO uint32_t AWD3CR ; + uint32_t RESERVED6[2] ; + __IO uint32_t DIFSEL ; + __IO uint32_t CALFACT ; + uint32_t RESERVED7[2] ; + __IO uint32_t GCOMP ; +} ADC_TypeDef; + + +typedef struct +{ + __IO uint32_t CSR1 ; + __IO uint32_t CSR2 ; + __IO uint32_t CCR ; + __IO uint32_t CDR ; +} ADC_Common_TypeDef; + + +//------------------- added by yqiu ------------------ +/*------------- DMA --------------------------------------*/ +/** @addtogroup DMA controller + @{ +*/ +typedef struct +{ + __IO uint64_t SAR; /*!< Offset: 0x000 Channel Source Address Register (R/W) */ + __IO uint64_t DAR; /*!< Offset: 0x008 Channel Destination Address Register (R/W) */ + uint64_t RESERVED0[1]; + //__IO uint64_t LLP; /*!< Offset: 0x010 Channel Linked List Pointer Register (R/W) */ + __IO uint64_t CTL; /*!< Offset: 0x018 Channel Control Register (R/W) */ + uint64_t RESERVED1[4]; + //__IO uint64_t SSTAT; /*!< Offset: 0x020 Channel Source Status Register (R/W) */ + //__IO uint64_t DSTAT; /*!< Offset: 0x028 Channel Destination Status Register (R/W) */ + //__IO uint64_t SSTATAR; /*!< Offset: 0x030 Channel Source Status Address Register (R/W) */ + //__IO uint64_t DSTATAR; /*!< Offset: 0x038 Channel Destination Status Address Register (R/W) */ + __IO uint64_t CFG; /*!< Offset: 0x040 Channel Configuration Register (R/W) */ + //__IO uint64_t SGR; /*!< Offset: 0x048 Channel Source Gather Register (R/W) */ + //__IO uint64_t DSR; /*!< Offset: 0x050 Channel Destination Scatter Register (R/W) */ +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint64_t RAWTFR; /*!< Offset: 0x2c0 Raw Status for IntTfr Interrupt Register (R/W) */ + __IO uint64_t RAWBLOCK; /*!< Offset: 0x2c8 Raw Status for IntBlock Interrupt Register (R/W) */ + __IO uint64_t RAWSRCTRAN; /*!< Offset: 0x2d0 Raw Status for IntSrcTran Interrupt Register (R/W) */ + __IO uint64_t RAWDSTTRAN; /*!< Offset: 0x2d8 Raw Status for IntDstTran Interrupt Register (R/W) */ + __IO uint64_t RAWERR; /*!< Offset: 0x2e0 Raw Status for IntErr Interrupt Register (R/W) */ + __I uint64_t STATUSTFR; /*!< Offset: 0x2e8 Status for IntTfr Interrupt Register (R/ ) */ + __I uint64_t STATUSBLOCK; /*!< Offset: 0x2f0 Status for IntBlock Interrupt Register (R/ ) */ + __I uint64_t STATUSSRCTRAN; /*!< Offset: 0x2f8 Status for IntSrcTran Interrupt Register (R/ ) */ + __I uint64_t STATUSDSTTRAN; /*!< Offset: 0x300 Status for IntDstTran Interrupt Register (R/ ) */ + __I uint64_t STATUSERR; /*!< Offset: 0x308 Status for IntErr Interrupt Register (R/ ) */ + __IO uint64_t MASKTFR; /*!< Offset: 0x310 Mask for IntTfr Interrupt Register (R/W) */ + __IO uint64_t MASKBLOCK; /*!< Offset: 0x318 Mask for IntBlock Interrupt Register (R/W) */ + __IO uint64_t MASKSRCTRAN; /*!< Offset: 0x320 Mask for IntSrcTran Interrupt Register (R/W) */ + __IO uint64_t MASKDSTTRAN; /*!< Offset: 0x328 Mask for IntDstTran Interrupt Register (R/W) */ + __IO uint64_t MASKERR; /*!< Offset: 0x330 Mask for IntErr Interrupt Register (R/W) */ + __O uint64_t CLEARTFR; /*!< Offset: 0x338 Clear for IntTfr Interrupt Register ( /W) */ + __O uint64_t CLEARBLOCK; /*!< Offset: 0x340 Clear for IntBlock Interrupt Register ( /W) */ + __O uint64_t CLEARSRCTRAN; /*!< Offset: 0x348 Clear for IntSrcTran Interrupt Register ( /W) */ + __O uint64_t CLEARDSTTRAN; /*!< Offset: 0x350 Clear for IntDstTran Interrupt Register ( /W) */ + __O uint64_t CLEARERR; /*!< Offset: 0x358 Clear for IntErr Interrupt Register ( /W) */ + __I uint64_t STATUSINT; /*!< Offset: 0x360 Status for Each Interrupt Type Register (R/ ) */ + + __IO uint64_t REQSRC; /*!< Offset: 0x368 Source Software Transaction Request Register (R/W) */ + __IO uint64_t REQDST; /*!< Offset: 0x370 Destination Software Transaction Request Register (R/W) */ + __IO uint64_t SGLRQSRC; /*!< Offset: 0x378 Source Single Transaction Request Register (R/W) */ + __IO uint64_t SGLRQDST; /*!< Offset: 0x380 Destination Single Transaction Request Register (R/W) */ + __IO uint64_t LSTSRC; /*!< Offset: 0x388 Source Last Transaction Request Register (R/W) */ + __IO uint64_t LSTDST; /*!< Offset: 0x390 Destination Last Transaction Request Register (R/W) */ + + __IO uint64_t DMACFG; /*!< Offset: 0x398 DMA Configuration Register (R/W) */ + __IO uint64_t CHEN; /*!< Offset: 0x3a0 DMA Channel Enable Register (R/W) */ + __I uint64_t ID; /*!< Offset: 0x3a8 DMA ID Register (R/ ) */ + __IO uint64_t TEST; /*!< Offset: 0x3b0 DMA Test Register (R/W) */ + __IO uint64_t LPTIMEOUT; /*!< Offset: 0x3b8 DMA Low Power Timeout Register (R/W) */ + __IO uint64_t CHSEL; /*!< Offset: 0x3c0 DMA Channel Request Select Register (R/W) */ + __I uint64_t COMPPARAMS6; /*!< Offset: 0x3c8 DMA Component Parameters Register 6 (R/ ) */ + __I uint64_t COMPPARAMS5; /*!< Offset: 0x3d0 DMA Component Parameters Register 5 (R/ ) */ + __I uint64_t COMPPARAMS4; /*!< Offset: 0x3d8 DMA Component Parameters Register 4 (R/ ) */ + __I uint64_t COMPPARAMS3; /*!< Offset: 0x3e0 DMA Component Parameters Register 3 (R/ ) */ + __I uint64_t COMPPARAMS2; /*!< Offset: 0x3e8 DMA Component Parameters Register 2 (R/ ) */ + __I uint64_t COMPPARAMS1; /*!< Offset: 0x3f0 DMA Component Parameters Register 1 (R/ ) */ + __I uint64_t COMPSID; /*!< Offset: 0x3f8 DMA Component ID Register (R/ ) */ + +} DMA_TypeDef; + +/*@}*/ /* end of group DMA */ +//---------------------------------------------------- + + +#if defined ( __CC_ARM ) +#pragma no_anon_unions +#endif + +//******************** flash register define******************************* +typedef struct +{ + __IO uint32_t RDC; //Address offset : 0000H + __IO uint32_t KEYR; //Address offset : 0004H + __IO uint32_t OPTKEYR; //Address offset : 0008H + __IO uint32_t FR; //Address offset : 000cH + __IO uint32_t WRC; //Address offset : 0010H + __IO uint32_t OPBC; //Address offset : 0014H + __IO uint32_t WRPR; //Address offset : 0018H + uint32_t RESERVED0[185]; //Address offset : 001cH -- 02FCH + __IO uint32_t FLAC_KEYR; //Address offset : 0300H + __IO uint32_t FLAC_CR; //Address offset : 0304H + __IO uint32_t FLAC_ITEST; //Address offset : 0308H + __IO uint32_t FLAC_DUMMY; //Address offset : 030cH + __IO uint32_t FLAC_FCFG0; //Address offset : 0310H + __IO uint32_t FLAC_FCFG1; //Address offset : 0314H + __IO uint32_t FLAC_FCFG2; //Address offset : 0318H + __IO uint32_t FLAC_FCFG3; //Address offset : 031cH + __IO uint32_t FLAC_FCFG4; //Address offset : 0320H + __IO uint32_t FLAC_FCFG5; //Address offset : 0324H + __IO uint32_t FLAC_FCFG6; //Address offset : 0328H + __IO uint32_t FLAC_FCFG7; //Address offset : 032cH + __IO uint32_t FLAC_FUNC0; //Address offset : 0330H + __IO uint32_t FLAC_FUNC1; //Address offset : 0334H + __IO uint32_t FLAC_FUNC2; //Address offset : 0338H + __IO uint32_t FLAC_FUNC3; //Address offset : 033cH + __IO uint32_t FLAC_PID0123; //Address offset : 0340H + __IO uint32_t FLAC_PID4; //Address offset : 0344H + __IO uint32_t FLAC_BDSCID; //Address offset : 0348H + __IO uint32_t FLAC_DBGMCU; //Address offset : 0348H 34C + __IO uint32_t FLAC_INFO10; //Address offset : 0348H 350 + __IO uint32_t FLAC_INFO11; //Address offset : 034cH 354 + __IO uint32_t FLAC_INFO12; //Address offset : 034cH 358 + __IO uint32_t FLAC_INFO13; //Address offset : 034cH 35C + __IO uint32_t FLAC_CHIPV; //Address offset : 0350H 360 +} FLASH_TypeDef; + + +//******************** rcc register define******************************* +typedef struct +{ + __IO uint32_t CR; // Clock control register Address offset : 0000H + __IO uint32_t PLLCFGR; // PLL configuration register Address offset : 0004H + __IO uint32_t PLL2CFGR; // PLL2 configuration register Address offset : 0008H + __IO uint32_t CFGR; // Clock configuration register Address offset : 000CH + __IO uint32_t CIR; // Clock interrupt register Address offset : 0010H + __IO uint32_t AHB1RSTR; // AHB1 peripheral reset register Address offset : 0014H + __IO uint32_t AHB2RSTR; // AHB2 peripheral reset register Address offset : 0018H + __IO uint32_t AHB3RSTR; // AHB3 peripheral reset register Address offset : 001CH + __IO uint32_t APB1RSTR; // APB1 peripheral reset register Address offset : 0020H + __IO uint32_t APB2RSTR; // APB2 peripheral reset register Address offset : 0024H + __IO uint32_t AHB1ENR; // AHB1 peripheral clock enable register Address offset : 0028H + __IO uint32_t AHB2ENR; // AHB2 peripheral clock enable register Address offset : 002CH + __IO uint32_t AHB3ENR; // AHB3 peripheral clock enable register Address offset : 0030H + __IO uint32_t APB1ENR; // APB1 peripheral clock enable register Address offset : 0034H + __IO uint32_t APB2ENR; // APB2 peripheral clock enable register Address offset : 0038H + __IO uint32_t AHB1LPENR; // AHB1 peripheral clock enable in low power register Address offset : 003CH + __IO uint32_t AHB2LPENR; // AHB2 peripheral clock enable in low power register Address offset : 0040H + __IO uint32_t AHB3LPENR; // AHB3 peripheral clock enable in low power register Address offset : 0044H + __IO uint32_t APB1LPENR; // APB1 peripheral clock enable in low power register Address offset : 0048H + __IO uint32_t APB2LPENR; // APB2 peripheral clock enable in low power register Address offset : 004CH + __IO uint32_t CCIPR; // Peripheral independent clock configuration register Address offset : 0050H + __IO uint32_t CR2; // Clock control register Address offset : 0054H + __IO uint32_t BDCR; // Backup domain control register Address offset : 0058H + __IO uint32_t CSR; // Clock control & status register Address offset : 005CH + uint32_t RESERVED0[40]; // Address offset : 0060H -- 00FCH + __IO uint32_t RAMCTL; // CACHE SDIO USB CAN ETH RAM control register Address offset : 0100H +} RCC_TypeDef; + + +//******************** crs register define******************************* +typedef struct +{ + __IO uint32_t CR; // control register Address offset : 0000H + __IO uint32_t CFGR; // configuration register Address offset : 0004H + __IO uint32_t ISR; // interrupt status register Address offset : 0008H + __IO uint32_t ICR; // interrupt clear register Address offset : 000CH +} CRS_TypeDef; + + +//******************** SYSCFG register define******************************* +typedef struct +{ + __IO uint32_t MEMRMP; // memory remap register Address offset : 0000H + __IO uint32_t PMC; // peripheral mode configuration register Address offset : 0004H + __IO uint32_t EXTICR[4]; // external interrupt configuration register Address offset : 0008H ~ 0014H + __IO uint32_t RESERVED0; // Address offset : 0018H + __IO uint32_t CFGR; // configuration register Address offset : 001CH +} SYSCFG_TypeDef; + + +//******************** usb_fs_otg register define******************************* +typedef struct +{ + __IO uint8_t FADDR; // function address register Address offset : 0000H + __IO uint8_t POWER; // power management register Address offset : 0001H + __IO uint8_t INTRTX1; // interrupt register for enapoint 0 and tx1~7 Address offset : 0002H + uint8_t RESERVED0; // Address offset : 0003H + __IO uint8_t INTRRX1; // interrupt register for rx enapoint 1~7 Address offset : 0004H + uint8_t RESERVED1; // Address offset : 0005H + __IO uint8_t INTRUSB; // interrupt register for common USB interrupt Address offset : 0006H + __IO uint8_t INTRTX1E; // interrupt enable register for INTRTX1 Address offset : 0007H + uint8_t RESERVED2; // Address offset : 0008H + __IO uint8_t INTRRX1E; // interrupt enable register for INTRRX1 Address offset : 0009H + uint8_t RESERVED3; // Address offset : 000AH + __IO uint8_t INTRUSBE; // interrupt enable register for INTRUSBE Address offset : 000BH + __IO uint8_t FRAME1; // frame number bits 0 to 7 Address offset : 000CH + __IO uint8_t FRAME2; // frame number bits 8 to 10 Address offset : 000DH + __IO uint8_t INDEX; // index register for selecting the endpoint Address offset : 000EH + __IO uint8_t DEVCTL; // usb device control register Address offset : 000FH + __IO uint8_t TXMAXP; // maximum packet size for IN/OUT endpoint(except ep0) Address offset : 0010H + union // Address offset : 0011H + { + __IO uint8_t CSR0; // main control status register for ep0 + __IO uint8_t TXCSR1; // control status register 1 for IN/HOST OUT endpoint1~15 + }; + union // Address offset : 0012H + { + __IO uint8_t CSR02; // subsidiary control status register for ep0 + __IO uint8_t TXCSR2; // control status register 2 for IN/OUT endpoint1~15 + }; + __IO uint8_t RXMAXP; // maximum packet size for OUT/IN endpoint(except ep0) Address offset : 0013H + __IO uint8_t RXCSR1; // control status register 1 for OUT/HOST IN endpoint Address offset : 0014H + __IO uint8_t RXCSR2; // control status rehister 2 for OUT/HOST IN endpoint Address offset : 0015H + union // Address offset : 0016H + { + __IO uint8_t COUNT0; // number received bytes in ep0 fifo + __IO uint8_t RXCOUNT1; // number of bytes in OUT/HOST IN endpoint fifo(lower byte) + }; + __IO uint8_t RXCOUNT2; // number of bytes in OUT/HOST IN endpoint fifo(upper byte) Address offset : 0017H + __IO uint8_t TXTYPE; // set the transaction type and ep number for host out Address offset : 0018H + union // Address offset : 0019H + { + __IO uint8_t NAKLMT0; // set nak response timeout on endpoint + __IO uint8_t TXINTERVAL; // set polling interval for an out interrupt/iso endpoint + }; + __IO uint8_t RXTYPE; // set the transaction type and ep number for host in Address offset : 001AH + __IO uint8_t RXINTERVAL; // set polling interval for in endpoint Address offset : 001BH + __IO uint8_t TXFIFO1; // txfifox configuration1 Address offset : 001CH + __IO uint8_t TXFIFO2; // txfifox configuration2 Address offset : 001DH + __IO uint8_t RXFIFO1; // rxfifox configuration1 Address offset : 001EH + __IO uint8_t RXFIFO2; // rxfifox configuration2 Address offset : 001FH + __IO uint32_t FIFO0; // fifos for endpoint0 Address offset : 0020H + __IO uint32_t FIFO1; // fifos for endpoint1 Address offset : 0024H + __IO uint32_t FIFO2; // fifos for endpoint2 Address offset : 0028H + __IO uint32_t FIFO3; // fifos for endpoint3 Address offset : 002CH + +} OTG_FS_TypeDef; + + +/** + *@brief USB_OTG_HS_Core_register + */ + +typedef struct +{ + __IO uint32_t GOTGCTL; // OTG control and status register Address offset : 0000H + __IO uint32_t GOTGINT; // OTG interrupt register Address offset : 0004H + __IO uint32_t GAHBCFG; // AHB configuration register Address offset : 0008H + __IO uint32_t GUSBCFG; // USB configuration register Address offset : 000CH + __IO uint32_t GRSTCTL; // Reset register Address offset : 0010H + __IO uint32_t GINTSTS; // Interrupt register Address offset : 0014H + __IO uint32_t GINTMSK; // Interrupt mask register Address offset : 0018H + __IO uint32_t GRXSTSR; // Recieve status read register Address offset : 001CH + __IO uint32_t GRXSTSP; // Recieve status read/pop register Address offset : 0020H + __IO uint32_t GRXFSIZ; // Receice FIFO size register Address offset : 0024H + __IO uint32_t DIEPTXF0_HNPTXFSIZ; // Non-periodic transmit FIFO size register Address offset : 0028H + __IO uint32_t HNPTXSTS; // Non-periodic transmit FIFO/queue status register Address offset : 002CH + uint32_t RESERVED0[3]; // Address offset : 0030H -- 003BH + __IO uint32_t GUID; // User ID register Address offset : 003CH + uint32_t RESERVED1[7]; // Address offset : 0040H -- 005BH + __IO uint32_t GDFIFOCFG; // Global DFIFO configuration register Address offset : 005CH + uint32_t RESERVED3[40]; // Address offset : 0060H -- 00FFH + __IO uint32_t HPTXFSIZ; // Host periodic transmit FIFO size register Address offset : 0100H + __IO uint32_t DIEPTXF[0x0F]; // Device IN endpoint transmit FIFO size register Address offset : 0104H +} USB_OTG_HS_GlobalTypeDef; + +/** + *@brief USB_OTG_HS_Device_register + */ +typedef struct +{ + __IO uint32_t DCFG; // Device configuration register Address offset : 0800H + __IO uint32_t DCTL; // Device control register Address offset : 0804H + __IO uint32_t DSTS; // Device status register Address offset : 0808H + uint32_t RESERVED19; // Address offset : 080CH + __IO uint32_t DIEPMSK; // Device IN endpoint common interrupt mask register Address offset : 0810H + __IO uint32_t DOEPMSK; // Device OUT endpoint common interrupt mask register Address offset : 0814H + __IO uint32_t DAINT; // Device all endpoints interrupt register Address offset : 0818H + __IO uint32_t DAINTMSK; // Device all endpoints interrupt mask register Address offset : 081CH + uint32_t RESERVED20[2]; // Address offset : 0820H -- 0824H + __IO uint32_t DVBUSDIS; // Device VBUS discharge time register Address offset : 0828H + __IO uint32_t DVBUSPULSE; // Device VBUS pulsing time register Address offset : 082CH + __IO uint32_t DTHRCTL; // Device threshold control register Address offset : 0830H + __IO uint32_t DIEPEMPMSK; // Device IN endpoint FIFO empty interrupt mask register Address offset : 0834H + __IO uint32_t DEACHINT; // Device each endpoints interrupt register Address offset : 0838H + __IO uint32_t DEACHMSK; // Device each endpoints interrupt mask register Address offset : 083CH + uint32_t RESERVED21; // Address offset : 0840H + __IO uint32_t DINEP1MSK; // Device each IN endpoint 1 interrupt register Address offset : 0844H + uint32_t RESERVED22[15]; // Address offset : 0848H -- 0880H + __IO uint32_t DOUTEP1MSK; // Device each OUT endpoint 1 interrupt register Address offset : 0884H +} USB_OTG_HS_DeviceTypeDef; +/** + *@brief USB_OTG_HS_IN_Endpoint_specific_register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; // Device control IN endpoint control register Address offset : 0900H + ep_num*20h + uint32_t RESERVED24; // Address offset : 0904H + ep_num*20h + __IO uint32_t DIEPINT; // Device IN endpoint interrupt register Address offset : 0908H + ep_num*20h + uint32_t RESERVED25; // Address offset : 090CH + ep_num*20h + __IO uint32_t DIEPTSIZ; // Device IN endpoint transfer size register Address offset : 0910H + ep_num*20h + __IO uint32_t DIEPDMA; // Device IN endpoint DMA address register Address offset : 0914H + ep_num*20h + __IO uint32_t DTXFSTS; // Device IN endpoint transmit FIFO status register Address offset : 0918H + ep_num*20h + uint32_t RESERVED26; // Address offset : 091CH + ep_num*20h +} USB_OTG_HS_INEndpointTypeDef; + +/** + *@brief USB_OTG_HS_OUT_Endpoint_specific_register + */ +typedef struct +{ + __IO uint32_t DOEPCTL; // Device control OUT endpoint control register Address offset : 0B00H + ep_num*20h + uint32_t RESERVED42; // Address offset : 0B04H + ep_num*20h + __IO uint32_t DOEPINT; // Device OUT endpoint interrupt register Address offset : 0B08H + ep_num*20h + uint32_t RESERVED43; // Address offset : 0B0CH + ep_num*20h + __IO uint32_t DOEPTSIZ; // Device OUT endpoint transfer size register Address offset : 0B10H + ep_num*20h + __IO uint32_t DOEPDMA; // Device OUT endpoint DMA address register Address offset : 0B14H + ep_num*20h + uint32_t RESERVED44[2]; // Address offset : 0B18H -- 0B1CH + ep_num*20h +} USB_OTG_HS_OUTEndpointTypeDef; + +/** + *@brief USB_OTG_HS_HOST_MODE_register + */ +typedef struct +{ + __IO uint32_t HCFG; // Host configuration register Address offset : 0400H + __IO uint32_t HFIR; // Host frame interval register Address offset : 0404H + __IO uint32_t HFNUM; // Host frame number/frame time remaining register Address offset : 0408H + uint32_t RESERVED4; // Address offset : 040CH + __IO uint32_t HPTXSTS; // Host periodic transmit FIFO/queue status register Address offset : 0410H + __IO uint32_t HAINT; // Host all channels interrupt register Address offset : 0414H + __IO uint32_t HAINTMSK; // Host all channels interrupt mask register Address offset : 0418H +} USB_OTG_HS_HostTypeDef; + +/** + *@brief USB_OTG_HS_HOST_Channel_specific_register + */ +typedef struct +{ + __IO uint32_t HCCHAR; // Host channel characteristics register Address offset : 0500H + ch_num*20h + __IO uint32_t HCSPLT; // Host channel split control register Address offset : 0504H + ch_num*20h + __IO uint32_t HCINT; // Host channel interrupt register Address offset : 0508H + ch_num*20h + __IO uint32_t HCINTMSK; // Host channel interrupt mask register Address offset : 050CH + ch_num*20h + __IO uint32_t HCTSIZ; // Host channel transfer size register Address offset : 0510H + ch_num*20h + __IO uint32_t HCDMA; // Host channel DMA address register Address offset : 0514H + ch_num*20h + uint32_t RESERVED7[2]; // Address offset : 0518H -- 051CH + ch_num*20h +} USB_OTG_HS_HostChannelTypeDef; + +// *************************************************************************** +//******************** i2c register define******************************* +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t TIMINGR; + __IO uint32_t TIMEOUTR; + __IO uint32_t ISR; + __IO uint32_t ICR; + __IO uint32_t PECR; + __IO uint32_t RXDR; + __IO uint32_t TXDR; +} I2C_TypeDef; + + +// *************************************************************************** +//******************** ucpd register define******************************* +typedef struct +{ + __IO uint32_t UCPD_CFG; + __IO uint32_t UCPD_CR; + __IO uint32_t UCPD_TX; + __IO uint32_t UCPD_TX_DR; + __IO uint32_t UCPD_IE; + __IO uint32_t UCPD_SR; + __IO uint32_t UCPD_ICR; + __IO uint32_t UCPD_TX_ORDSET; + __IO uint32_t UCPD_TX_PAYSZ; + __IO uint32_t UCPD_RX_ORDSET; + __IO uint32_t UCPD_RX_PAYSZ; + __IO uint32_t UCPD_RXRD; +} UCPD_TypeDef; + + +typedef struct +{ + __IO uint32_t CAN_RECEIVE_BUFFER0; + __IO uint32_t CAN_RECEIVE_BUFFER1; + __IO uint32_t CAN_RECEIVE_BUFFER[16]; + __IO uint32_t CAN_RECEIVE_BUFFER_RTS[2]; + __IO uint32_t CAN_TRANSMIT_BUFFER0; + __IO uint32_t CAN_TRANSMIT_BUFFER1; + __IO uint32_t CAN_TRANSMIT_BUFFER[16]; + __IO uint32_t CAN_TRANSMISION_TS[2]; + __IO uint32_t CAN_CMD_CTRL; //0xA0 + __IO uint32_t CAN_INT_FLAG1; //0xA4 + __IO uint32_t CAN_S_SEG_UNIT_SET; //0xA8 + __IO uint32_t CAN_F_SEG_UNIT_SET; //0xAC + __IO uint32_t CAN_ERR_CNT; //0xB0 + __IO uint32_t CAN_FILTER_CTRL; //0xB4 + __IO uint32_t CAN_ACF; //0xB8 + __IO uint32_t CAN_INT_FLAG2; //0xBC + __IO uint32_t CAN_REF_MSG; //0xC0 + __IO uint32_t CAN_TRIG_CFG; //0xC4 + __IO uint32_t CAN_TRANS_INT_STAT; //0xC8 + __IO uint32_t CAN_MEM_ES; //0xCC + __IO uint32_t CAN_SCFG; //0xD0 + __IO uint32_t CAN_INIT_CFG_OFFSET; //0xD4 +} FDCAN_TypeDef; + +/******************* Bit definition for FDCAN_ISR register ******************/ +#define FDCAN_ISR_RACTIVE ((uint32_t)0x00000004) /*!< Reception ACTIVE */ +#define FDCAN_ISR_TACTIVE ((uint32_t)0x00000002) /*!< Transmission ACTIVE */ +#define FDCAN_ISR_TSSTAT ((uint32_t)0x00030000) /*!< Tansmission Secondary Status */ +#define FDCAN_ISR_RSTAT ((uint32_t)0x03000010) /*!< Receive Buffer Overflow */ +#define FDCAN_ISR_ROV ((uint32_t)0x20000000) /*!< Receive Buffer OverRun Error */ +// *************************************************************************** +//******************** spi register define******************************* +typedef struct +{ + __IO uint32_t CR1 ; //0x00 + __IO uint32_t CR2 ; //0x04 + __IO uint32_t SR ; //0x08 + __IO uint32_t DR ; //0x0c + __IO uint32_t CRCPR ; //0x10 + __IO uint32_t RXCRCR ; //0x14 + __IO uint32_t TXCRCR ; //0x18 + __IO uint32_t SSPR ; //0x1c +} SPI_TypeDef; + + +// *************************************************************************** +//******************** qspi register define******************************* +typedef struct +{ + __IO uint32_t CTRLR0 ; // 0x0 Control Register 0 + __IO uint32_t CTRLR1 ; // 0x4 Control Register 1 + __IO uint32_t SSIENR ; // 0x8 SSI Enable Register + __IO uint32_t MWCR ; // 0xc Microwire Control Register + __IO uint32_t SER ; // 0x10 Target Enable Register + __IO uint32_t BAUDR ; // 0x14 Baud Rate Select + __IO uint32_t TXFTLR ; // 0x18 Transmit FIFO Threshold Level + __IO uint32_t RXFTLR ; // 0x1c Receive FIFO Threshold Level + __IO uint32_t TXFLR ; // 0x20 Transmit FIFO Level Register + __IO uint32_t RXFLR ; // 0x24 Receive FIFO Level Register + __IO uint32_t SR ; // 0x28 Status Register + __IO uint32_t IMR ; // 0x2c Interrupt Mask Register + __IO uint32_t ISR ; // 0x30 Interrupt Status Register + __IO uint32_t RISR ; // 0x34 Raw Interrupt Status Register + __IO uint32_t TXEICR ; // 0x38 Transmit FIFO Error Interrupt Clear Register Register + __IO uint32_t RXOICR ; // 0x3c Receive FIFO Overflow Interrupt Clear Register + __IO uint32_t RXUICR ; // 0x40 Receive FIFO Underflow Interrupt Clear Register + __IO uint32_t MSTICR ; // 0x44 Multi-Controller Interrupt Clear Register + __IO uint32_t ICR ; // 0x48 Interrupt Clear Register + __IO uint32_t DMACR ; // 0x4c DMA Control Register + __IO uint32_t DMATDLR ; // 0x50 DMA Transmit Data Level + __IO uint32_t DMARDLR ; // 0x54 DMA Receive Data Level + __IO uint32_t IDR ; // 0x58 Identification Register + __IO uint32_t SSIC_VERSION_ID ; // 0x5c DWC_ssi component version +// __IO uint32_t DR0 ; // 0x60 DWC_ssi Data Register +// __IO uint32_t DR1 ; // 0x64 DWC_ssi Data Register +// __IO uint32_t DR2 ; // 0x68 DWC_ssi Data Register +// __IO uint32_t DR3 ; // 0x6c DWC_ssi Data Register +// __IO uint32_t DR4 ; // 0x70 DWC_ssi Data Register +// __IO uint32_t DR5 ; // 0x74 DWC_ssi Data Register +// __IO uint32_t DR6 ; // 0x78 DWC_ssi Data Register +// __IO uint32_t DR7 ; // 0x7c DWC_ssi Data Register +// __IO uint32_t DR8 ; // 0x80 DWC_ssi Data Register +// __IO uint32_t DR9 ; // 0x84 DWC_ssi Data Register +// __IO uint32_t DR10 ; // 0x88 DWC_ssi Data Register +// __IO uint32_t DR11 ; // 0x8c DWC_ssi Data Register +// __IO uint32_t DR12 ; // 0x90 DWC_ssi Data Register +// __IO uint32_t DR13 ; // 0x94 DWC_ssi Data Register +// __IO uint32_t DR14 ; // 0x98 DWC_ssi Data Register +// __IO uint32_t DR15 ; // 0x9c DWC_ssi Data Register +// __IO uint32_t DR16 ; // 0xa0 DWC_ssi Data Register +// __IO uint32_t DR17 ; // 0xa4 DWC_ssi Data Register +// __IO uint32_t DR18 ; // 0xa8 DWC_ssi Data Register +// __IO uint32_t DR19 ; // 0xac DWC_ssi Data Register +// __IO uint32_t DR20 ; // 0xb0 DWC_ssi Data Register +// __IO uint32_t DR21 ; // 0xb4 DWC_ssi Data Register +// __IO uint32_t DR22 ; // 0xb8 DWC_ssi Data Register +// __IO uint32_t DR23 ; // 0xbc DWC_ssi Data Register +// __IO uint32_t DR24 ; // 0xc0 DWC_ssi Data Register +// __IO uint32_t DR25 ; // 0xc4 DWC_ssi Data Register +// __IO uint32_t DR26 ; // 0xc8 DWC_ssi Data Register +// __IO uint32_t DR27 ; // 0xcc DWC_ssi Data Register +// __IO uint32_t DR28 ; // 0xd0 DWC_ssi Data Register +// __IO uint32_t DR29 ; // 0xd4 DWC_ssi Data Register +// __IO uint32_t DR30 ; // 0xd8 DWC_ssi Data Register +// __IO uint32_t DR31 ; // 0xdc DWC_ssi Data Register +// __IO uint32_t DR32 ; // 0xe0 DWC_ssi Data Register +// __IO uint32_t DR33 ; // 0xe4 DWC_ssi Data Register +// __IO uint32_t DR34 ; // 0xe8 DWC_ssi Data Register +// __IO uint32_t DR35 ; // 0xec DWC_ssi Data Register + __IO uint32_t DR[16] ; // 0x60 DWC_ssi Data Register + __IO uint32_t RES0[20] ; // 0xa0 ~ 0xec,Reserved. + __IO uint32_t RX_SAMPLE_DELAY ; // 0xf0 RX Sample Delay Register + __IO uint32_t SPI_CTRLR0 ; // 0xf4 SPI_CTRLR0 - SPI Control Register + __IO uint32_t DDR_DRIVE_EDGE ; // 0xf8 DDR_DRIVE_EDGE - Transmit Drive Edge Register + __IO uint32_t XIP_MODE_BITS ; // 0xfc eXecute in Place - Mode bits + __IO uint32_t XIP_INCR_INST ; // 0x100 XIP_INCR_INST - XIP INCR transfer opcode + __IO uint32_t XIP_WRAP_INST ; // 0x104 XIP_WRAP_INST - XIP WRAP transfer opcode + __IO uint32_t RES[3] ; // 0x108 ~ 110 Reserved. //XIP_CTRL ; // 0x108 XIP_CTRL - XIP Control Register +// __IO uint32_t XIP_SER ; // 0x10c Target Enable Register +// __IO uint32_t XRXOICR ; // 0x110 XIP Receive FIFO Overflow Interrupt Clear Register + __IO uint32_t XIP_CNT_TIME_OUT ; // 0x114 XIP time out register for continuous transfers + __IO uint32_t SPI_CTRLR1 ; // 0x118 SPI_CTRLR1 Control 1 register +// __IO uint32_t XIP_WRITE_INCR_INST ; // 0x140 XIP_WRITE_INCR_INST - XIP Write INCR transfer opcode +// __IO uint32_t XIP_WRITE_WRAP_INST ; // 0x144 XIP_WRITE_WRAP_INST - XIP Write WRAP transfer opcode +// __IO uint32_t XIP_WRITE_CTRL ; // 0x148 XIP_WRITE_CTRL - XIP Write Control Register +} QSPI_TypeDef; + + +// *************************************************************************** +//******************** usart register define******************************* +typedef struct +{ + __IO uint32_t CR ; //0x0 + __IO uint32_t MR ; //0x4 + __IO uint32_t IER ; //0x8 + __IO uint32_t IDR ; //0xc + __IO uint32_t IMR ; //0x10 + __IO uint32_t CSR ; //0x14 + __IO uint32_t RHR ; //0x18 + __IO uint32_t THR ; //0x1c + __IO uint32_t BRGR ; //0x20 + __IO uint32_t RTOR ; //0x24 + __IO uint32_t TTGR ; //0x28 + __IO uint32_t RES1 ; //0x2c + __IO uint32_t RES2 ; //0x30 + __IO uint32_t RES3 ; //0x34 + __IO uint32_t RES4 ; //0x38 + __IO uint32_t RES5 ; //0x3c + __IO uint32_t FIDI ; //0x40 + __IO uint32_t NER ; //0x44 + __IO uint32_t XON_XOFF ; //RES6 //0x48 + __IO uint32_t IF ; //0x4c +// __IO uint32_t MAN ; //0x50 + __IO uint32_t RES7 ; //0x50 + __IO uint32_t LINMR ; //0x54 + __IO uint32_t LINIR ; //0x58 + __IO uint32_t LINBRR ; //0x5c +// __IO uint32_t LONMR ; //0x60, not has function, this regster is reserved +// __IO uint32_t LONPR ; //0x64, not has function, this regster is reserved +// __IO uint32_t LONDL ; //0x68, not has function, this regster is reserved +// __IO uint32_t LONL2HDR ; //0x6c, not has function, this regster is reserved +// __IO uint32_t LONBL ; //0x70, not has function, this regster is reserved +// __IO uint32_t LONB1TX ; //0x74, not has function, this regster is reserved +// __IO uint32_t LONB1RX ; //0x78, not has function, this regster is reserved +// __IO uint32_t LONPRIO ; //0x7c, not has function, this regster is reserved +// __IO uint32_t IDTTX ; //0x80, not has function, this regster is reserved +// __IO uint32_t IDTRX ; //0x84, not has function, this regster is reserved +// __IO uint32_t ICDIFF ; //0x88, not has function, this regster is reserved +} USART_TypeDef; + + +typedef struct +{ + __IO uint32_t WPMR ; + __IO uint32_t WPSR ; +} USART_WP_TypeDef; + + +// *************************************************************************** +//******************** FMC register define******************************* +typedef struct +{ + __IO uint32_t BTCR[8]; // 0x00-0x1C +} FMC_Bank1_TypeDef; + + +typedef struct +{ + __IO uint32_t BWTR[7]; // 0x104-0x11C +} FMC_Bank1E_TypeDef; + +typedef struct +{ + __IO uint32_t PCR2; // 0x60 + __IO uint32_t SR2; // 0x64 + __IO uint32_t PMEM2; // 0x68 + __IO uint32_t PATT2; // 0x6c + uint32_t RESERVED0; + __IO uint32_t ECCR2; // 0x74 + uint32_t RESERVED1[2]; + __IO uint32_t PCR3; // 0x80 + __IO uint32_t SR3; // 0x84 + __IO uint32_t PMEM3; // 0x88 + __IO uint32_t PATT3; // 0x8c + uint32_t RESERVED2; + __IO uint32_t ECCR3; // 0x94 +} FMC_Bank2_3_TypeDef; + +typedef struct +{ + __IO uint32_t SDCR[2]; // 0x140-0x144 + __IO uint32_t SDTR[2]; // 0x148-0x14c + __IO uint32_t SDCMR; // 0x150 + __IO uint32_t SDRTR; // 0x154 + __IO uint32_t SDSR; // 0x158 +} FMC_Bank5_6_TypeDef; + +// *************************************************************************** +// ******************** CRC register define*********************************** +typedef struct +{ + __IO uint32_t DR; // 0x00 + __IO uint32_t IDR; // 0x04 + __IO uint32_t CR; // 0x08 + __IO uint32_t RESERVED0; // 0x0c + __IO uint32_t INIT; // 0x10 +} CRC_TypeDef; + + +// *************************************************************************** +// *********************** gpio register define******************************* +typedef struct +{ + __IO uint32_t MODER; // 0x00 + __IO uint32_t OTYPER; // 0x04 + __IO uint32_t OSPEEDR; // 0x08 + __IO uint32_t PUPDR; // 0x0c + __IO uint32_t IDR; // 0x10 + __IO uint32_t ODR; // 0x14 + __IO uint32_t BSRR; // 0x18 + __IO uint32_t LCKR; // 0x1c + __IO uint32_t AFR[2]; // 0x20-0x24 +} GPIO_TypeDef; + + +// *************************************************************************** +//******************** SDIO register define******************************* +typedef struct +{ + __IO uint32_t CTRL ; // 0x0 Control register + __IO uint32_t PWREN ; // 0x4 Power Enable Register + __IO uint32_t CLKDIV ; // 0x8 Clock Divider Register + __IO uint32_t CLKSRC ; // 0xc Clock Source Register + __IO uint32_t CLKENA ; // 0x10 Clock Enable Register + __IO uint32_t TMOUT ; // 0x14 Timeout Register + __IO uint32_t CTYPE ; // 0x18 Card Type Register + __IO uint32_t BLKSIZ ; // 0x1c Block Size Register + __IO uint32_t BYTCNT ; // 0x20 Byte Count Register + __IO uint32_t INTMASK ; // 0x24 Interrupt Mask Register + __IO uint32_t CMDARG ; // 0x28 Command Argument Register + __IO uint32_t CMD ; // 0x2c Command Register + __IO uint32_t RESP0 ; // 0x30 Response Register 0 + __IO uint32_t RESP1 ; // 0x34 Response Register 1 + __IO uint32_t RESP2 ; // 0x38 Response Register 2 + __IO uint32_t RESP3 ; // 0x3c Response Register 3 + __IO uint32_t MINTSTS ; // 0x40 Masked Interrupt Status Register Size: 32 bits Address Offset: 0x40 Read/write access: read MISTATS... + __IO uint32_t RINTSTS ; // 0x44 Raw Interrupt Status Register Size: 32 bits Address Offset: 0x44 Read/write access:... + __IO uint32_t STATUS ; // 0x48 Status Register Size: 32 bits Address Offset: 0x48 Read/write access: read + __IO uint32_t FIFOTH ; // 0x4c FIFO Threshold Watermark Register Size: 32 bits Address Offset: 0x4C Read/write access:... + __IO uint32_t CDETECT ; // 0x50 Card Detect Register Size: 32 bits Address Offset: 0x50 Read/write access: read-only + __IO uint32_t WRTPRT ; // 0x54 Write Protect Register Size: 32 bits Address Offset: 0x54 Read/write access: read-only + __IO uint32_t GPIO ; // 0x58 General Purpose Input/Output Register Size: 32 bits Address Offset: 0x58 Read/write access:... + __IO uint32_t TCBCNT ; // 0x5c Transferred CIU Card Byte Count Register Size: 32 bits Address Offset: 0x5C Read/write access:... + __IO uint32_t TBBCNT ; // 0x60 Transferred Host to BIU-FIFO Byte Count Register Size: 32 bits Address Offset: 0x60 Read/write... + __IO uint32_t DEBNCE ; // 0x64 Debounce Count Register Size: 32 bits Address Offset: 0x64 Read/write access:... + __IO uint32_t USRID ; // 0x68 User ID Register Size: 32 bits Address Offset: 0x68 Read/write access: write/readUser ID... + __IO uint32_t VERID ; // 0x6c Version ID Register Size: 32 bits Address Offset: 0x6C Read/write access: read + __IO uint32_t HCON ; // 0x70 Hardware Configuration Register Size: 32 bits Address Offset: 0x70 Read/Write access: readHardware... + __IO uint32_t UHS_REG ; // 0x74 UHS-1 Register Size: 32 bits Address Offset: 0x74 Read/write access: write/read + __IO uint32_t RST_N ; // 0x78 H/W Reset Size: 32 bits Address Offset: 0x78 Read/write access: write/read + __IO uint32_t RES[33] ; // 0x7C ~ FF Reserved + __IO uint32_t CARDTHRCTL ; // 0x100 Card Threshold Control Register Size: 32 bits Address Offset: 0x100 Read/Write access:... + __IO uint32_t BACK_END_POWER_R ; // 0x104 Back End Power Register Size: 32 bits Address Offset: 0x104 Read/Write access:... + __IO uint32_t UHS_REG_EXT ; // 0x108 UHS Register Extention Size: 32 bits Address Offset: 0x108 Read/Write access:... + __IO uint32_t EMMC_DDR_REG ; // 0x10c EMMC DDR Register Size: 32 bits Address Offset: 0x10C Read/Write access: read/write + __IO uint32_t ENABLE_SHIFT ; // 0x110 Enable Phase Shift Register Address Offset: 0x110 Read/Write access: read/write +} SDIO_TypeDef; + + +typedef struct +{ + __IO uint32_t DATA ; // 0x200 SDIO FIFO, depth = 32 Words = 128 Bytes +} SDIO_DATA_TypeDef; + + +typedef struct +{ + __IO uint32_t SPDIF_CTRL ; + __IO uint32_t INT ; + __IO uint32_t FIFO_CTRL ; + __IO uint32_t STAT ; + __IO uint32_t DATA ; //FIFO address +} SPDIF_TypeDef; + + +// SSI/I2S/AC97 registers +typedef struct +{ + __IO uint32_t STX0 ; //0x00 + __IO uint32_t STX1 ; //0x04 + __IO uint32_t SRX0 ; //0x08 + __IO uint32_t SRX1 ; //0x0C + __IO uint32_t SCR ; //0x10 + __IO uint32_t SISR ; //0x14 + __IO uint32_t SIER ; //0x18 + __IO uint32_t STCR ; //0x1C + __IO uint32_t SRCR ; //0x20 + __IO uint32_t STCCR ; //0x24 + __IO uint32_t SRCCR ; //0x28 + __IO uint32_t SFCSR ; //0x2C + __IO uint32_t STR ; //0x30 + __IO uint32_t SOR ; //0x34 + __IO uint32_t SACNT ; //0x38 + __IO uint32_t SACADD ; //0x3C + __IO uint32_t SACDAT ; //0x40 + __IO uint32_t SATAG ; //0x44 + __IO uint32_t STMSK ; //0x48 + __IO uint32_t SRMSK ; //0x4C + __IO uint32_t SACCST ; //0x50 + __IO uint32_t SACCEN ; //0x54 + __IO uint32_t SACCDIS ; //0x58 +} SSI_TypeDef; + + +typedef struct +{ + __O uint32_t KR; // Independent watchdog key reg + __IO uint32_t PR; // Independent watchdog prescaler reg + __IO uint32_t RLR; // Independent watchdog reload reg + __I uint32_t SR; // Independent watchdog status reg + __IO uint32_t WINR; // Independent watchdog window reg +} IWDG_TypeDef; + +#define IWDG_KR_Pos 0 +#define IWDG_KR_Msk (0x0ul << IWDG_KR_Pos) + +#define IWDG_PR_Pos 0 +#define IWDG_PR_Msk (0x0ul << IWDG_PR_Pos) + +#define IWDG_RLR_Pos 0 +#define IWDG_RLR_Msk (0xFFFFFFFFul << IWDG_RLR_Pos) + +#define IWDG_SR_Pos 0 +#define IWDG_SR_Msk (0x0ul << IWDG_SR_Pos) + +#define IWDG_WINR_Pos 0 +#define IWDG_WINR_Msk (0xFFFFFFFFul << IWDG_WINR_Pos) + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PR register ********************/ +#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */ +#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */ +#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */ +#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */ + +/******************* Bit definition for IWDG_RLR register *******************/ +#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */ + +/******************* Bit definition for IWDG_SR register ********************/ +#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */ +#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */ +#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */ + +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */ + +/*------------------- Window Watchdog -----------------------------------------*/ +typedef struct +{ + __IO uint32_t CR; // Window watchdog control reg + __IO uint32_t CFR; // Window watchdog configure reg + __IO uint32_t SR; // Window watchdog status reg +} WWDG_TypeDef; + +#define WWDG_CR_WDGA_Pos 7 +#define WWDG_CR_WDGA_Msk (0x1ul << WWDG_CR_WDGA_Pos) +#define WWDG_CR_T_Pos 0 +#define WWDG_CR_T_Msk (0x7Ful << WWDG_CR_T_Pos) + +#define WWDG_CFR_EWI_Pos 9 +#define WWDG_CFR_EWI_Msk (0x1ul << WWDG_CFR_EWI_Pos) +#define WWDG_CFR_WDGTB_Pos 7 +#define WWDG_CFR_WDGTB_Msk (0x3ul << WWDG_CFR_WDGTB_Pos) +#define WWDG_CFR_W_Pos 0 +#define WWDG_CFR_W_Msk (0x7Ful << WWDG_CFR_W_Pos) + +#define WWDG_SR_EWIF_Pos 0 +#define WWDG_SR_EWIF_Msk (0x0ul << WWDG_SR_EWIF_Pos) + +/******************* Bit definition for WWDG_CR register ********************/ +#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */ +#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */ +#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */ +#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */ +#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */ +#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */ +#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */ + +#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */ + +/******************* Bit definition for WWDG_CFR register *******************/ +#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */ +#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */ +#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */ +#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */ +#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */ +#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */ +#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */ +#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */ + +#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */ +#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */ + +#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_SR register ********************/ +#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */ + + +typedef struct +{ + __IO uint32_t IMR; + __IO uint32_t EMR; + __IO uint32_t RTSR; + __IO uint32_t FTSR; + __IO uint32_t SWIER; + __IO uint32_t PR; +} EXTI_TypeDef; + + +typedef struct +{ + __IO uint32_t CR1 ; + __IO uint32_t CR2 ; + __IO uint32_t SMCR ; + __IO uint32_t DIER ; + __IO uint32_t SR ; + __IO uint32_t EGR ; + __IO uint32_t CCMR1 ; + __IO uint32_t CCMR2 ; + __IO uint32_t CCER ; + __IO uint32_t CNT ; + __IO uint32_t PSC ; + __IO uint32_t ARR ; + __IO uint32_t RCR ; + __IO uint32_t CCR1 ; + __IO uint32_t CCR2 ; + __IO uint32_t CCR3 ; + __IO uint32_t CCR4 ; + __IO uint32_t BDTR ; + __IO uint32_t DCR ; + __IO uint32_t DMAR ; + __IO uint32_t OR ; + __IO uint32_t CCMR3 ; + __IO uint32_t CCR5 ; + __IO uint32_t CCR6 ; + __IO uint32_t AF1 ; + __IO uint32_t AF2 ; + __IO uint32_t TISEL ; +} TIM_TypeDef; + + +typedef struct +{ + __IO uint32_t ISR ; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR ; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER ; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR ; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR ; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CMP ; /*!< LPTIM Compare register, Address offset: 0x14 */ + __IO uint32_t ARR ; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT ; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t OR ; /*!< LPTIM Option register, Address offset: 0x20 */ +} LPTIM_TypeDef; + + +/******************************************************************************/ +/* */ +/* Low Power Timer (LPTIM) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for LPTIM_ISR register *******************/ +#define LPTIM_ISR_CMPM_Pos (0U) +#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */ +#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */ +#define LPTIM_ISR_ARRM_Pos (1U) +#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */ +#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */ +#define LPTIM_ISR_EXTTRIG_Pos (2U) +#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */ +#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */ +#define LPTIM_ISR_CMPOK_Pos (3U) +#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */ +#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */ +#define LPTIM_ISR_ARROK_Pos (4U) +#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */ +#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */ +#define LPTIM_ISR_UP_Pos (5U) +#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */ +#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */ +#define LPTIM_ISR_DOWN_Pos (6U) +#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */ +#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */ + +/****************** Bit definition for LPTIM_ICR register *******************/ +#define LPTIM_ICR_CMPMCF_Pos (0U) +#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */ +#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */ +#define LPTIM_ICR_ARRMCF_Pos (1U) +#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */ +#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */ +#define LPTIM_ICR_EXTTRIGCF_Pos (2U) +#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */ +#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */ +#define LPTIM_ICR_CMPOKCF_Pos (3U) +#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */ +#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */ +#define LPTIM_ICR_ARROKCF_Pos (4U) +#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */ +#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */ +#define LPTIM_ICR_UPCF_Pos (5U) +#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */ +#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */ +#define LPTIM_ICR_DOWNCF_Pos (6U) +#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */ +#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */ + +/****************** Bit definition for LPTIM_IER register ********************/ +#define LPTIM_IER_CMPMIE_Pos (0U) +#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */ +#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */ +#define LPTIM_IER_ARRMIE_Pos (1U) +#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */ +#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */ +#define LPTIM_IER_EXTTRIGIE_Pos (2U) +#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */ +#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */ +#define LPTIM_IER_CMPOKIE_Pos (3U) +#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */ +#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */ +#define LPTIM_IER_ARROKIE_Pos (4U) +#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */ +#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */ +#define LPTIM_IER_UPIE_Pos (5U) +#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */ +#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */ +#define LPTIM_IER_DOWNIE_Pos (6U) +#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */ +#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */ + +/****************** Bit definition for LPTIM_CFGR register *******************/ +#define LPTIM_CFGR_CKSEL_Pos (0U) +#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */ +#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */ + +#define LPTIM_CFGR_CKPOL_Pos (1U) +#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */ +#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */ +#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */ +#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */ + +#define LPTIM_CFGR_CKFLT_Pos (3U) +#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */ +#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */ +#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */ +#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */ + +#define LPTIM_CFGR_TRGFLT_Pos (6U) +#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */ +#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */ +#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */ +#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */ + +#define LPTIM_CFGR_PRESC_Pos (9U) +#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */ +#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */ +#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */ +#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */ +#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */ + +#define LPTIM_CFGR_TRIGSEL_Pos (13U) +#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */ +#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */ +#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */ +#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */ +#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */ +#define LPTIM_CFGR_TRIGSEL_3 (0x1UL << 29) /*!< 0x20000000 */ + + +#define LPTIM_CFGR_TRIGEN_Pos (17U) +#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */ +#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */ +#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */ +#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */ + +#define LPTIM_CFGR_TIMOUT_Pos (19U) +#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */ +#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timeout enable */ +#define LPTIM_CFGR_WAVE_Pos (20U) +#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */ +#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */ +#define LPTIM_CFGR_WAVPOL_Pos (21U) +#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */ +#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */ +#define LPTIM_CFGR_PRELOAD_Pos (22U) +#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */ +#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */ +#define LPTIM_CFGR_COUNTMODE_Pos (23U) +#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */ +#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */ +#define LPTIM_CFGR_ENC_Pos (24U) +#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */ +#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */ + +/****************** Bit definition for LPTIM_CR register ********************/ +#define LPTIM_CR_ENABLE_Pos (0U) +#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */ +#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */ +#define LPTIM_CR_SNGSTRT_Pos (1U) +#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */ +#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */ +#define LPTIM_CR_CNTSTRT_Pos (2U) +#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */ +#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */ +#define LPTIM_CR_COUNTRST_Pos (3U) +#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */ +#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Counter reset */ +#define LPTIM_CR_RSTARE_Pos (4U) +#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */ +#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Reset after read enable */ + +/****************** Bit definition for LPTIM_CMP register *******************/ +#define LPTIM_CMP_CMP_Pos (0U) +#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */ + +/****************** Bit definition for LPTIM_ARR register *******************/ +#define LPTIM_ARR_ARR_Pos (0U) +#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */ +#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */ + +/****************** Bit definition for LPTIM_CNT register *******************/ +#define LPTIM_CNT_CNT_Pos (0U) +#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */ +#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */ + +/****************** Bit definition for LPTIM_OR register *******************/ +#define LPTIM_OR_IN1_Pos (0U) +#define LPTIM_OR_IN1_Msk (0xDUL << LPTIM_OR_IN1_Pos) /*!< 0x0000000D */ +#define LPTIM_OR_IN1 LPTIM_OR_IN1_Msk /*!< OR[3:2],OR[0] bits (INPUT1 selection) */ +#define LPTIM_OR_IN1_0 0x00000001UL +#define LPTIM_OR_IN1_1 0x00000004UL +#define LPTIM_OR_IN1_2 0x00000008UL + +#define LPTIM_OR_IN2_Pos (1U) +#define LPTIM_OR_IN2_Msk (0x32UL << LPTIM_OR_IN2_Pos) /*!< 0x00000032 */ +#define LPTIM_OR_IN2 LPTIM_OR_IN2_Msk /*!< OR[5:4],OR[1] bits (INPUT2 selection) */ +#define LPTIM_OR_IN2_0 0x00000002UL +#define LPTIM_OR_IN2_1 0x00000010UL +#define LPTIM_OR_IN2_2 0x00000020UL + +//******************** ETHERNET register define******************************* +typedef struct +{ +//Ethernet mac + __IO uint32_t ETH_MAC_CFG; // 0x0000 Ethernet mac configuration register + __IO uint32_t ETH_MAC_EXTDCFG; // 0x0004 Ethernet mac extended configuration register + __IO uint32_t ETH_MAC_PKTFILT; // 0x0008 Ethernet mac packet filter register + __IO uint32_t ETH_MAC_WTDTO; // 0x000c Ethernet mac watch dog timeout register + __IO uint32_t ETH_MAC_HASHTB0; // 0x0010 Ethernet mac Hash table register 0 + __IO uint32_t ETH_MAC_HASHTB1; // 0x0014 Ethernet mac Hash table register 1 + __IO uint32_t RESERVED0[14]; // 0x0018 - 0x004c + __IO uint32_t ETH_MAC_VLANT; // 0x0050 Ethernet mac VLAN tag register + __IO uint32_t RESERVED1[7]; // 0x0054 - 0x006c + __IO uint32_t ETH_MAC_TXFLCTL; // 0x0070 Ethernet mac Tx FLow control register + __IO uint32_t RESERVED2[7]; // 0x0074 - 0x008c + __IO uint32_t ETH_MAC_RXFLCTL; // 0x0090 Ethernet mac Rx Flow control register + __IO uint32_t RESERVED3[7]; // 0x0094 - 0x00ac + __IO uint32_t ETH_MAC_IRSTU; // 0x00b0 Ethernet mac interrupt status register + __IO uint32_t ETH_MAC_IREN; // 0x00b4 Ethernet mac interrupt enable register + __IO uint32_t ETH_MAC_RXTXSTU; // 0x00b8 Ethernet mac receive tranmit status register + __IO uint32_t RESERVED4[1]; // 0x00bc + __IO uint32_t ETH_MAC_PMTCTLSTU; // 0x00c0 Ethernet mac PMT control and status register + __IO uint32_t ETH_MAC_RWKPKTFILT; // 0x00c4 Ethernet mac remote wakeup filter register + __IO uint32_t RESERVED5[19]; // 0X00c8 - 0x0110 + __IO uint32_t ETH_MAC_DBG; // 0x0114 Ethernet mac debug register + __IO uint32_t RESERVED6[58]; // 0x0118 - 0x01fc + __IO uint32_t ETH_MAC_MDIOADDR; // 0x0200 Ethernet mac MDIO address register + __IO uint32_t ETH_MAC_MDIODATA; // 0x0204 Ethernet MDIO data register + __IO uint32_t RESERVED7[10]; // 0x0208 - 0x022c + __IO uint32_t ETH_MAC_SWCTL; // 0x0230 Ethernet mac software programmable control + __IO uint32_t RESERVED8[51]; // 0x0234 - 0x02fc + __IO uint32_t ETH_MAC_ADDRH0; // 0x0300 Ethernet mac address0 high register + __IO uint32_t ETH_MAC_ADDRL0; // 0x0304 Ethernet mac address0 low register + __IO uint32_t ETH_MAC_ADDRH1; // 0x0308 Ethernet mac address1 high register + __IO uint32_t ETH_MAC_ADDRL1; // 0x030c Ethernet mac address1 low register + __IO uint32_t ETH_MAC_ADDRH2; // 0x0310 Ethernet mac address2 high register + __IO uint32_t ETH_MAC_ADDRL2; // 0x0314 Ethernet mac address2 low register + __IO uint32_t ETH_MAC_ADDRH3; // 0x0318 Ethernet mac address3 high register + __IO uint32_t ETH_MAC_ADDRL3; // 0x031c Ethernet mac address3 low register + __IO uint32_t RESERVED9[248]; // 0x0320 - 0x06fc + + //Ethernet mmc + __IO uint32_t ETH_MMC_CTL; // 0x0700 Ethernet mmc control refister + __IO uint32_t ETH_MMC_RXIR; // 0x0704 Ethernet mmc receive statistics counters interrupt + __IO uint32_t ETH_MMC_TXIR; // 0x0708 Ethernet mmc transmit statistics counters interrupt + __IO uint32_t ETH_MMC_RXIRMSK; // 0x070c Ethernet mmc masks for receive statistics counters + __IO uint32_t ETH_MMC_TXIRMSK; // 0x0710 Ethernet mmc masks for transmit statistic counters + __IO uint32_t RESERVED10[14]; // 0x0714 - 0x0748 + __IO uint32_t ETH_MMC_TXSCGP; // 0x074c Ethernet mmc transmit number of single collision good packets + __IO uint32_t ETH_MMC_TXMCGP; // 0x0750 Ethernet mmc transmit number of multiple collision good packets + __IO uint32_t RESERVED11[5]; // 0x0754 - 0x0764 + __IO uint32_t ETH_MMC_TXGP; // 0x0768 Ethernet mmc transmit number of good packets + __IO uint32_t RESERVED12[10]; // 0x076C - 0x0790 + __IO uint32_t ETH_MMC_RXCRCERRP; // 0x0794 Ethernet mmc receive number of packets with CRC error + __IO uint32_t ETH_MMC_RXALGERRP; // 0x0798 Ethernet mmc receive number of packets with alignment error + __IO uint32_t RESERVED13[10]; // 0x079c - 0x07c0 + __IO uint32_t ETH_MMC_RXUCASTP; // 0x07c4 Ethernet mmc receive number of good unicast packets + __IO uint32_t RESERVED14[206]; // 0x07c8 - 0x0afc + + //Ethernet ptp + __IO uint32_t ETH_PTP_TSCTL; // 0x0b00 Ethernet mac PTP pkt timstamp control register + __IO uint32_t ETH_PTP_SUBSECINR; // 0x0b04 Ethernet mac sub second increment + __IO uint32_t ETH_PTP_SYSTMSEC; // 0x0b08 Ethernet mac system time seconds register + __IO uint32_t ETH_PTP_SYSTMNSEC; // 0x0b0c Ethernet mac system time nanoseconds register + __IO uint32_t ETH_PTP_SYSTMSECUPDT; // 0x0b10 Etherner mac system time seconds updata register + __IO uint32_t ETH_PTP_SYSTMNSECUPDT; // 0x0b14 Ethernet mac system time nanoseconds updata register + __IO uint32_t ETH_PTP_TSADD; // 0x0b18 Ethernet mac timestamp addend register + __IO uint32_t RESERVED15[1]; // 0x0b1c + __IO uint32_t ETH_PTP_TSSTU; // 0x0b20 Ethernet mac timestamp status register + __IO uint32_t RESERVED16[3]; // 0x0b24 - 0x0b2c + __IO uint32_t ETH_PTP_TXTSSTUNSEC; // 0x0b30 Ethernet mac nanosecond part of timestamp status + __IO uint32_t ETH_PTP_TXTSSTUSEC; // 0x0b34 Ethernet mac higher 32 bits of timestamp captured when PTP is transmit + __IO uint32_t RESERVED17[6]; // 0x0b38 - 0x0b4c + __IO uint32_t ETH_PTP_TSINGASMCOR; // 0x0b50 Ethernet Timestamp Ingress Asymmetry Correction register + __IO uint32_t ETH_PTP_TSEGASMCOR; // 0x0b54 Ethernet Timestamp Egress Asymmetry Correction register + __IO uint32_t ETH_PTP_TSINGCORNSEC; // 0x0b58 Ethernet nanoseconds correction value with captured timestamp value in the ingress path + __IO uint32_t ETH_PTP_TSEGCORNSEC; // 0x0b5C Ethernet nanoseconds correction value with captured timestamp value in the egress path + __IO uint32_t RESERVED18[2]; // 0x0b60 - 0x0b64 + __IO uint32_t ETH_PTP_TSINGLAT; // 0x0b68 Ethernet mac ingress latency + __IO uint32_t ETH_PTP_TSEGLAT; // 0x0b6c Ethernet mac egress latency + __IO uint32_t ETH_PTP_PPSCTL; // 0x0b70 Ethernet PPS control register + __IO uint32_t RESERVED19[3]; // 0x0b74 - 0x0b7c + __IO uint32_t ETH_PTP_TRGTTMSEC; // 0x0b80 Ethernet PPS target time seconds register + __IO uint32_t ETH_PTP_TRGTTMNSEC; // 0x0b84 Ethernet PPS target time nanoseconds register + __IO uint32_t RESERVED20[30]; // 0x0b88 - 0x0bfc + + //Ethernet MTL + __IO uint32_t ETH_MTL_OPMODE; // 0x0c00 Ethernet transmit and receive operation mode + __IO uint32_t RESERVED21[7]; // 0x0c04 - 0x0c1c + __IO uint32_t ETH_MTL_INTRSTU; // 0x0c20 Ethernet app reads during interrupt service routing or polling to determine interrupt status + __IO uint32_t RESERVED22[55]; // 0x0c24 - 0x0cfc; + __IO uint32_t ETH_MTL_TXQOPMODE; // 0x0d00 Ethernet queue 0 transmit operation mode register + __IO uint32_t ETH_MTL_TXQUDFLW; // 0x0d04 Ethernet queue 0 underflow counter register + __IO uint32_t ETH_MTL_TXQDBG; // 0x0d08 Ethernet queue 0 transmit debug register + __IO uint32_t RESERVED23[8]; // 0x0d0c - 0x0d28 + __IO uint32_t ETH_MTL_QINTRCTRLSTU; // 0x0d2c Ethernet queue 0 interrupt enable and status + __IO uint32_t ETH_MTL_RXQOPMODE; // 0x0d30 Ethernet queue 0 receive operation mode register + __IO uint32_t ETH_MTL_RXQMISPKTOVFLWCNT; // 0X0d34 Ethernet queue 0 missed packet and overflow counter register + __IO uint32_t ETH_MTL_RXQDBG; // 0x0d38 Ethernet queue 0 receive debug register + __IO uint32_t RESERVED24[177]; // 0x0d3c - 0x0ffc + + //Ethernet DMA + __IO uint32_t ETH_DMA_OPMODE; // 0x1000 Ethernet BUS mode register + __IO uint32_t ETH_DMA_SYSBUSMODE; // 0x1004 Ethernet system bus mode register + __IO uint32_t ETH_DMA_INTRSTU; // 0x1008 Ethernet DMA channel interrupt status + __IO uint32_t ETH_DMA_DBGSTU; // 0x100c Ethernet DMA channel receive and transmit process status + __IO uint32_t RESERVED25[60]; // 0x1010-0x10fc + __IO uint32_t ETH_DMA_CTL; // 0x1100 Ethernet DMA channel0 control register + __IO uint32_t ETH_DMA_TXCTL; // 0x1104 Ethernet DMA channel0 transmit control register + __IO uint32_t ETH_DMA_RXCTL; // 0x1108 Ethernet DMA channel0 receive control register + __IO uint32_t RESERVED26[2]; // 0x110C - 0x1110 + __IO uint32_t ETH_DMA_TXDESCLSTADDR; // 0x1114 Ethernet DMA channel0 TX descriptor list address register + __IO uint32_t RESERVED27[1]; // 0x1118 + __IO uint32_t ETH_DMA_RXDESCLSTADDR; // 0x111c Ethernet DMA channel0 RX descriptor list address register + __IO uint32_t ETH_DMA_TXDESCTAILPTR; // 0x1120 Ethernet DMA channel0 TX descriptor tail pointer register + __IO uint32_t RESERVED28[1]; // 0x1124 + __IO uint32_t ETH_DMA_RXDESCTAILPTR; // 0x1128 Ethernet DMA channel0 RX descriptor tail pointer register + __IO uint32_t ETH_DMA_TXDESCRINGLEN; // 0x112c Ethernet DMA descriptor ring length reister + __IO uint32_t ETH_DMA_RXCTL2; // 0x1130 Ethernet DMA channel0 receive control register + __IO uint32_t ETH_DMA_INTRENA; // 0x1134 Ethernet DMA channel0 interrupt enable register + __IO uint32_t ETH_DMA_RXINTRWDGTMR; // 0x1138 Ethernet DMA channel0 receive interrupt watchdog timer register + __IO uint32_t RESERVED29[2]; // 0x113c - 0x1140 + __IO uint32_t ETH_DMA_CURAPPTXDESC; // 0x1144 Ethernet DMA channel0 current application transmit descriptor register + __IO uint32_t RESERVED30[1]; // 0x1148 + __IO uint32_t ETH_DMA_CURAPPRXDESC; // 0x114c Ethernet DMA channel0 current application receive descriptor register + __IO uint32_t RESERVED31[1]; // 0X1150 + __IO uint32_t ETH_DMA_CURAPPTXBUF; // 0x1154 Ethernet DMA channel0 current application transmit buffer address register + __IO uint32_t RESERVED32[1]; // 0x1158 + __IO uint32_t ETH_DMA_CURAPPRXBUF; // 0x115c Ethernet DMA channel0 current application receive buffer address register + __IO uint32_t ETH_DMA_STU; // 0x1160 Ethernet DMA channel0 status + __IO uint32_t ETH_DMA_MISFRMCNT; // 0x1164 Ethernet DMA channel0 number of packet counter that got dropped by the DMA + __IO uint32_t RESERVED33[1]; // 0x1168 + __IO uint32_t ETH_DMA_RXERICNT; // 0x116c Ethernet DMA channel0 provides the count of the number of times ERI was asserted + +} ETH_TypeDef; + + + +//******************** DBGMCU register define******************************* +typedef struct +{ + __IO uint32_t IDCODE; // 0xE0042000 + __IO uint32_t CR; // 0xE0042004 + __IO uint32_t APB1FZ; // 0xE0042008 + __IO uint32_t APB2FZ; // 0xE004200C + +} DBG_TypeDef; + + +//******************** COMP_OPAM_DAC register define******************************* +typedef struct +{ + //---DAC + __IO uint32_t DAC_CR ; // 0x40007400 + __IO uint32_t DAC_SWTRIGR ; // 0x40007404 + __IO uint32_t DAC_DHR12R1 ; // 0x40007408 + __IO uint32_t DAC_DHR12L1 ; // 0x4000740C + __IO uint32_t DAC_DHR8R1 ; // 0x40007410 + __IO uint32_t DAC_DHR12R2 ; // 0x40007414 + __IO uint32_t DAC_DHR12L2 ; // 0x40007418 + __IO uint32_t DAC_DHR8R2 ; // 0x4000741c + __IO uint32_t DAC_DHR12RD ; // 0x40007420 + __IO uint32_t DAC_DHR12LD ; // 0x40007424 + __IO uint32_t DAC_DHR8RD ; // 0x40007428 + __IO uint32_t DAC_DOR1 ; // 0x4000742c + __IO uint32_t DAC_DOR2 ; // 0x40007430 + __IO uint32_t DAC_SR ; // 0x40007434 + + //---OPAMP + __IO uint32_t OPAMP1_CSR ; // 0x40007438 + __IO uint32_t OPAMP2_CSR ; // 0X4000743C + __IO uint32_t OPAMP3_CSR ; // 0x40007440 + __IO uint32_t OPAMP1_TCMR ; // 0x40007444 + __IO uint32_t OPAMP2_TCMR ; // 0x40007448 + __IO uint32_t OPAMP3_TCMR ; // 0x4000744c + + //---COMP + __IO uint32_t COMP1_CSR ; // 0x40007450 + __IO uint32_t COMP2_CSR ; // 0x40007454 + __IO uint32_t COMP1_RAMPMAXREF_SHADOW; // 0x40007458 + __IO uint32_t COMP1_RAMPMAXREF_ACTIV ; // 0x4000745c + __IO uint32_t COMP1_RAMPDECVAL_SHADOW; // 0x40007460 + __IO uint32_t COMP1_RAMPDECVAL_ACTIV ; // 0x40007464 + __IO uint32_t COMP2_RAMPMAXREF_SHADOW; // 0x40007468 + __IO uint32_t COMP2_RAMPMAXREF_ACTIV ; // 0x4000746c + __IO uint32_t COMP2_RAMPDECVAL_SHADOW; // 0x40007470 + __IO uint32_t COMP2_RAMPDECVAL_ACTIV ; // 0x40007474 + __IO uint32_t COMP1_RAMPSTS ; // 0x40007478 + __IO uint32_t COMP2_RAMPSTS ; // 0x4000747c + __IO uint32_t COMP3_CSR ; // 0x40007480 + __IO uint32_t COMP4_CSR ; // 0x40007480 + __IO uint32_t COMP5_CSR ; // 0x40007480 + __IO uint32_t COMP6_CSR ; // 0x40007480 + + +} COMP_OPAM_DAC_TypeDef; + +//******************** CACHE register define******************************* +typedef struct +{ + //---ICACHE + __IO uint32_t ICACHE_CTRL ; // 0x4002E000 + __IO uint32_t ICACHE_SR ; // 0x4002E004 + __IO uint32_t ICACHE_IRQMASK ; // 0X4002E008 + __IO uint32_t ICACHE_IRQSTAT ; // 0X4002E00c + __IO uint32_t ICACHE_TYPE ; // 0x4002E010 + __IO uint32_t ICACHE_CSHR ; // 0x4002E014 + __IO uint32_t ICACHE_CSMR ; // 0x4002E018 +} ICACHE_TypeDef; + +typedef struct +{ + //---DCACHE + __IO uint32_t DCACHE_CTRL ; // 0x4003E020 + __IO uint32_t DCACHE_SR ; // 0x4003E024 + __IO uint32_t DCACHE_IRQMASK ; // 0X4003E028 + __IO uint32_t DCACHE_IRQSTAT ; // 0X4003E02c + __IO uint32_t DCACHE_TYPE ; // 0x4003E030 + __IO uint32_t DCACHE_CSHR ; // 0x4003E034 + __IO uint32_t DCACHE_CSMR ; // 0x4003E038 +} DCACHE_TypeDef; + +//******************** RNG register define******************************* +typedef struct +{ + //---RNG + __IO uint32_t RNG_CR ; // 0x50060800 + __IO uint32_t RNG_SR ; // 0X50060804 + __IO uint32_t RNG_DR ; // 0x50060808 +} RNG_TypeDef; + +//******************** VREFBUF register define******************************* +typedef struct +{ + __IO uint32_t VREFBUF_CSR ; // 0x40016400 + __IO uint32_t VREFBUF_CCR ; // 0X40016404 + +} VREFBUF_TypeDef; + + +/******************************************************************************/ +/* pwr_register_typedef */ +/******************************************************************************/ +typedef struct +{ + __IO uint32_t CR; // 0x0000 pwr configuration register + __IO uint32_t CSR; // 0x0004 pwr configuration register +} PWR_TypeDef; +/******************************************************************************/ +/* rtc_register_typedef */ +/******************************************************************************/ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wkup timing register, Address offset: 0x14 */ + __IO uint32_t CALIBR; /*!< RTC rough calibration, Address offset: 0x18 */ + __IO uint32_t ALRMAR; /*!< RTC alram A register, Address offset: 0x1C */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time stamp sub second register, Address offset: 0x38 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */ + __IO uint32_t TAFCR; /*!< RTC tamper and alternate funtion configuration register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alram A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBSSR; /*!< RTC alram B sub second register, Address offset: 0x48 */ + uint32_t RESERVES; /*!< RTC reserves register, Address offset: 0x4C */ + __IO uint32_t BKP0R; /*!< RTC backup register, Address offset: 0x50 */ + __IO uint32_t BKP1R; /*!< RTC backup register, Address offset: 0x54 */ + __IO uint32_t BKP2R; /*!< RTC backup register, Address offset: 0x58 */ + __IO uint32_t BKP3R; /*!< RTC backup register, Address offset: 0x5c */ + __IO uint32_t BKP4R; /*!< RTC backup register, Address offset: 0x60 */ + __IO uint32_t BKP5R; /*!< RTC backup register, Address offset: 0x64 */ + __IO uint32_t BKP6R; /*!< RTC backup register, Address offset: 0x68 */ + __IO uint32_t BKP7R; /*!< RTC backup register, Address offset: 0x6c */ + __IO uint32_t BKP8R; /*!< RTC backup register, Address offset: 0x70 */ + __IO uint32_t BKP9R; /*!< RTC backup register, Address offset: 0x74 */ + __IO uint32_t BKP10R; /*!< RTC backup register, Address offset: 0x78 */ + __IO uint32_t BKP11R; /*!< RTC backup register, Address offset: 0x7c */ + __IO uint32_t BKP12R; /*!< RTC backup register, Address offset: 0x80 */ + __IO uint32_t BKP13R; /*!< RTC backup register, Address offset: 0x84 */ + __IO uint32_t BKP14R; /*!< RTC backup register, Address offset: 0x88 */ + __IO uint32_t BKP15R; /*!< RTC backup register, Address offset: 0x8c */ + __IO uint32_t BKP16R; /*!< RTC backup register, Address offset: 0x90 */ + __IO uint32_t BKP17R; /*!< RTC backup register, Address offset: 0x94 */ + __IO uint32_t BKP18R; /*!< RTC backup register, Address offset: 0x98 */ + __IO uint32_t BKP19R; /*!< RTC backup register, Address offset: 0x9c */ +} RTC_TypeDef; + +//*************************************************************************** +//******************** i2s register define*********************************** +typedef struct +{ + __IO uint32_t CTRL ; //0x00 + __IO uint32_t INTR_STAT ; //0x04 + __IO uint32_t SRR ; //0x08 + __IO uint32_t CID_CTRL ; //0x0C + __I uint32_t TFIFO_STAT ; //0x10 + __I uint32_t RFIFO_STAT ; //0x14 + __IO uint32_t TFIFO_CTRL ; //0x18 + __IO uint32_t RFIFO_CTRL ; //0x1C + __IO uint32_t DEV_CONF ; //0x20 + __I uint32_t POLL_STAT ; //0x24 + __IO uint32_t RESERVED0[5] ; //0x28 + __IO uint32_t FIFO ; //0x3C +} I2S_TypeDef; + + +/******************************************************************************/ +/* Peripheral memory map */ +/******************************************************************************/ +/** @addtogroup CM4_MemoryMap CM4 Memory Mapping + @{ +*/ + +/* Peripheral and SRAM base address */ +//#define FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */ +#define SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */ +#define PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */ +#define FMC_R_BASE (0xA0000000UL) /*!< FMC register Base Address */ + +/* Base addresses */ +#define RAM_BASE (0x20000000UL) +#define APB1_BASE (0x40000000UL) +#define APB2_BASE (0x40010000UL) +#define AHB1_BASE (0x40020000UL) +#define AHB2_BASE (0x50000000UL) +#define AHB3_BASE (0x60000000UL) +#define FLASH_BASE (0x08000000UL) +#define FLASH_CTL_BASE (AHB1_BASE + 0x3C00UL) +#define RCC_BASE (AHB1_BASE + 0x3800UL) +#define CRS_BASE (APB1_BASE + 0x8000UL) +#define SYSCFG_BASE (APB2_BASE + 0x3800UL) +#define PWR_BASE (APB1_BASE + 0x7000UL) +#define RTC_BASE (APB1_BASE + 0x2800UL) +#define VREFBUF_BASE (APB2_BASE + 0x6400UL) + + +/* APB peripherals */ +#define I2C1_BASE (APB1_BASE + 0x5400UL) +#define I2C2_BASE (APB1_BASE + 0x5800UL) +#define I2C3_BASE (APB1_BASE + 0x5C00UL) + +#define USART1_BASE (APB2_BASE + 0x1000UL) +#define USART6_BASE (APB2_BASE + 0x1400UL) +#define USART1_WP_BASE (USART1_BASE + 0xE4UL) +#define USART6_WP_BASE (USART6_BASE + 0xE4UL) +#define SDIO_BASE (APB2_BASE + 0x2C00UL) +#define SDIO_DATA_BASE (SDIO_BASE + 0x200UL) +#define SPI1_BASE (APB2_BASE + 0x3000UL) + +#define USART2_BASE (APB1_BASE + 0x4000UL) +#define USART3_BASE (APB1_BASE + 0x4400UL) +#define UART4_BASE (APB1_BASE + 0x4800UL) +#define UART5_BASE (APB1_BASE + 0x4C00UL) +#define UART7_BASE (APB1_BASE + 0x7800UL) +#define LPUART_BASE (APB1_BASE + 0x5000UL) +#define USART2_WP_BASE (USART2_BASE + 0xE4UL) +#define USART3_WP_BASE (USART3_BASE + 0xE4UL) +#define UART4_WP_BASE (UART4_BASE + 0xE4UL) +#define UART5_WP_BASE (UART5_BASE + 0xE4UL) +#define UART7_WP_BASE (UART7_BASE + 0xE4UL) +#define LPUART_WP_BASE (LPUART_BASE + 0xE4UL) +#define SPI2_BASE (APB1_BASE + 0x3800UL) +#define SPI3_BASE (APB1_BASE + 0x3C00UL) +#define SPDIF_BASE (APB2_BASE + 0x2400UL) +#define SSI_BASE (APB1_BASE + 0x3400UL) +#define IWDG_BASE (APB1_BASE + 0x3000UL) +#define WWDG_BASE (APB1_BASE + 0x2C00UL) +#define EXTI_BASE (APB2_BASE + 0x3C00UL) +#define TIM2_BASE (APB1_BASE + 0x0000UL) +#define TIM3_BASE (APB1_BASE + 0x0400UL) +#define TIM4_BASE (APB1_BASE + 0x0800UL) +#define TIM5_BASE (APB1_BASE + 0x0c00UL) +#define TIM6_BASE (APB1_BASE + 0x1000UL) +#define TIM7_BASE (APB1_BASE + 0x1400UL) +#define TIM9_BASE (APB2_BASE + 0x4000UL) +#define TIM10_BASE (APB2_BASE + 0x4400UL) +#define TIM11_BASE (APB2_BASE + 0x4800UL) +#define TIM12_BASE (APB1_BASE + 0x1800UL) +#define TIM13_BASE (APB1_BASE + 0x1c00UL) +#define TIM14_BASE (APB1_BASE + 0x2000UL) +#define LPTIM_BASE (APB2_BASE + 0x5400UL) +#define CAN1_BASE (APB1_BASE + 0x6000UL) +#define CAN2_BASE (APB1_BASE + 0x6400UL) +#define CAN3_BASE (APB1_BASE + 0x6800UL) +#define CAN4_BASE (APB1_BASE + 0x6C00UL) +#define TIM1_BASE (APB2_BASE + 0x0000UL) +#define TIM8_BASE (APB2_BASE + 0x0400UL) +#define EPWM1_BASE (APB2_BASE + 0x4C00UL) +#define EPWM2_BASE (APB2_BASE + 0x5800UL) +#define EPWM3_BASE (APB2_BASE + 0x5C00UL) +#define EPWM4_BASE (APB2_BASE + 0x6000UL) +#define ECAP_BASE (APB2_BASE + 0x0800UL) +#define EQEP_BASE (APB2_BASE + 0x0C00UL) +#define UCPD_BASE (APB1_BASE + 0x7C00UL) +#define DBGMCU_BASE (0xE0042000UL) +#define COMP_OPAM_DAC_BASE (APB1_BASE + 0x7400UL) +#define RNG_BASE (AHB2_BASE + 0x060800L) +#define I2S2_BASE (SPI2_BASE + 0x200UL) +#define I2S3_BASE (SPI3_BASE + 0x200UL) + +/* AHB peripherals */ +#define OTG_FS_BASE (AHB2_BASE + 0UL) +#define OTG_HS_BASE (AHB1_BASE + 0x20000UL) +#define ETH_BASE (AHB1_BASE + 0x8000UL) +#define ICACHE_BASE (AHB1_BASE + 0xE000UL) +#define DCACHE_BASE (AHB1_BASE + 0xE020UL) + +#define DMA1_BASE (AHB1_BASE + 0x6000UL) +#define DMA2_BASE (AHB1_BASE + 0x6400UL) +#define QSPI_BASE (0xA0000000UL + 0x1000UL) +#define QSPI_BANK (AHB3_BASE + 0x30000000UL) + +/*!< FMC Bankx registers base address */ +#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL) +#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL) +#define FMC_Bank2_3_R_BASE (FMC_R_BASE + 0x0060UL) +#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL) + + +#define FMC_BASE (AHB3_BASE + 0x40000000UL) +#define FMC_BANK1 (AHB3_BASE) +#define FMC_BANK1_1 (FMC_BANK1) +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) + +#define FMC_BANK2 (AHB3_BASE + 0x10000000UL) +#define FMC_BANK3 (AHB3_BASE + 0x20000000UL) + +#ifdef SWP_FMC +#define NAND2_MEM_DATA_BASE (AHB3_BASE + 0x60000000UL) +#define NAND2_MEM_CMD_BASE (AHB3_BASE + 0x60010000UL) +#define NAND2_MEM_ADDR_BASE (AHB3_BASE + 0x60020000UL) + +#define NAND2_ATT_DATA_BASE (AHB3_BASE + 0x68000000UL) +#define NAND2_ATT_CMD_BASE (AHB3_BASE + 0x68010000UL) +#define NAND2_ATT_ADDR_BASE (AHB3_BASE + 0x68020000UL) + +#define NAND3_MEM_DATA_BASE (AHB3_BASE + 0x70000000UL) +#define NAND3_MEM_CMD_BASE (AHB3_BASE + 0x70010000UL) +#define NAND3_MEM_ADDR_BASE (AHB3_BASE + 0x70020000UL) + +#define NAND3_ATT_DATA_BASE (AHB3_BASE + 0x78000000UL) +#define NAND3_ATT_CMD_BASE (AHB3_BASE + 0x78010000UL) +#define NAND3_ATT_ADDR_BASE (AHB3_BASE + 0x78020000UL) + +#define FMC_BANK5 (FMC_BANK1 + 0x10000000UL) +#define FMC_BANK6 (FMC_BANK1 + 0x20000000UL) +#else +#define NAND2_MEM_DATA_BASE (AHB3_BASE + 0x10000000UL) +#define NAND2_MEM_CMD_BASE (AHB3_BASE + 0x10010000UL) +#define NAND2_MEM_ADDR_BASE (AHB3_BASE + 0x10020000UL) + +#define NAND2_ATT_DATA_BASE (AHB3_BASE + 0x18000000UL) +#define NAND2_ATT_CMD_BASE (AHB3_BASE + 0x18010000UL) +#define NAND2_ATT_ADDR_BASE (AHB3_BASE + 0x18020000UL) + +#define NAND3_MEM_DATA_BASE (AHB3_BASE + 0x20000000UL) +#define NAND3_MEM_CMD_BASE (AHB3_BASE + 0x20010000UL) +#define NAND3_MEM_ADDR_BASE (AHB3_BASE + 0x20020000UL) + +#define NAND3_ATT_DATA_BASE (AHB3_BASE + 0x28000000UL) +#define NAND3_ATT_CMD_BASE (AHB3_BASE + 0x28010000UL) +#define NAND3_ATT_ADDR_BASE (AHB3_BASE + 0x28020000UL) + +#define PCCARD4_MEM_BASE (AHB3_BASE + 0x30000000UL) +#define PCCARD4_ATT_BASE (AHB3_BASE + 0x38000000UL) +#define PCCARD4_IO_BASE (AHB3_BASE + 0x3C000000UL) + +#define FMC_BANK5 (FMC_BANK1 + 0x60000000UL) +#define FMC_BANK6 (FMC_BANK1 + 0x70000000UL) +#endif + +#define GPIO_BASE (AHB1_BASE) +#define GPIOA_BASE (GPIO_BASE + 0x0000UL) +#define GPIOB_BASE (GPIO_BASE + 0x0400UL) +#define GPIOC_BASE (GPIO_BASE + 0x0800UL) +#define GPIOD_BASE (GPIO_BASE + 0x0C00UL) +#define GPIOE_BASE (GPIO_BASE + 0x1000UL) +#define GPIOH_BASE (GPIO_BASE + 0x1C00UL) +#define CRC_BASE (AHB1_BASE + 0x3000UL) +#define CRC ((CRC_TypeDef *) CRC_BASE) + + +#define USB_OTG_HS_GLOBAL_BASE 0x0000UL +#define USB_OTG_HS_DEVICE_BASE 0x0800UL +#define USB_OTG_HS_IN_ENDPOINT_BASE 0x0900UL +#define USB_OTG_HS_OUT_ENDPOINT_BASE 0x0B00UL +#define USB_OTG_HS_EP_REG_SIZE 0x0020UL +#define USB_OTG_HS_HOST_BASE 0x0400UL +#define USB_OTG_HS_HOST_PORT_BASE 0x0440UL +#define USB_OTG_HS_HOST_CHANNEL_BASE 0x0500UL +#define USB_OTG_HS_HOST_CHANNEL_SIZE 0x0020UL +#define USB_OTG_HS_PCGCCTL_BASE 0x0E00UL +#define USB_OTG_HS_FIFO_BASE 0x1000UL +#define USB_OTG_HS_FIFO_SIZE 0x1000UL +#define USB_OTG_HS_PKEY_BASE 0x0E20UL +#define USB_OTG_HS_PREG_BASE 0x0E18UL + +/*@}*/ /* end of group CM4_MemoryMap */ + + +/******************************************************************************/ +/* Peripheral declaration */ +/******************************************************************************/ +/** @addtogroup CM4_PeripheralDecl CM4 Peripheral Declaration + @{ +*/ + +#define TIM1 ((TIM_TypeDef *) TIM1_BASE ) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE ) + +#define EPWM1 ((EPWM_TypeDef *) EPWM1_BASE) +#define EPWM2 ((EPWM_TypeDef *) EPWM2_BASE) +#define EPWM3 ((EPWM_TypeDef *) EPWM3_BASE) +#define EPWM4 ((EPWM_TypeDef *) EPWM4_BASE) +#define ECAP ((ECAP_TypeDef *) ECAP_BASE ) +#define EQEP ((EQEP_TypeDef *) EQEP_BASE ) + + +//DMA1 Registers Address +#define DMA1_channel0_BASE (DMA1_BASE + 0x00000000) +#define DMA1_channel1_BASE (DMA1_BASE + 0x00000058) +#define DMA1_channel2_BASE (DMA1_BASE + 0x000000B0) +#define DMA1_channel3_BASE (DMA1_BASE + 0x00000108) +#define DMA1_channel4_BASE (DMA1_BASE + 0x00000160) +#define DMA1_channel5_BASE (DMA1_BASE + 0x000001B8) +#define DMA1_channel6_BASE (DMA1_BASE + 0x00000210) +#define DMA1_channel7_BASE (DMA1_BASE + 0x00000268) +#define DMA1_CFG_BASE (DMA1_BASE + 0x000002C0) + +//DMA2 Registers Address +#define DMA2_channel0_BASE (DMA2_BASE + 0x00000000) +#define DMA2_channel1_BASE (DMA2_BASE + 0x00000058) +#define DMA2_channel2_BASE (DMA2_BASE + 0x000000B0) +#define DMA2_channel3_BASE (DMA2_BASE + 0x00000108) +#define DMA2_channel4_BASE (DMA2_BASE + 0x00000160) +#define DMA2_channel5_BASE (DMA2_BASE + 0x000001B8) +#define DMA2_channel6_BASE (DMA2_BASE + 0x00000210) +#define DMA2_channel7_BASE (DMA2_BASE + 0x00000268) +#define DMA2_CFG_BASE (DMA2_BASE + 0x000002C0) + +//DMA1 Registers Define +#define DMA1_Channel0 ((DMA_Channel_TypeDef *) DMA1_channel0_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_channel7_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_CFG_BASE ) + +//DMA2 Registers Define +#define DMA2_Channel0 ((DMA_Channel_TypeDef *) DMA2_channel0_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_channel7_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_CFG_BASE ) + + +#define DMA1_CH0 ((DMA_Channel_TypeDef *) DMA1_channel0_BASE) +#define DMA1_CH1 ((DMA_Channel_TypeDef *) DMA1_channel1_BASE) +#define DMA1_CH2 ((DMA_Channel_TypeDef *) DMA1_channel2_BASE) +#define DMA1_CH3 ((DMA_Channel_TypeDef *) DMA1_channel3_BASE) +#define DMA1_CH4 ((DMA_Channel_TypeDef *) DMA1_channel4_BASE) +#define DMA1_CH5 ((DMA_Channel_TypeDef *) DMA1_channel5_BASE) +#define DMA1_CH6 ((DMA_Channel_TypeDef *) DMA1_channel6_BASE) +#define DMA1_CH7 ((DMA_Channel_TypeDef *) DMA1_channel7_BASE) + +#define DMA2_CH0 ((DMA_Channel_TypeDef *) DMA2_channel0_BASE) +#define DMA2_CH1 ((DMA_Channel_TypeDef *) DMA2_channel1_BASE) +#define DMA2_CH2 ((DMA_Channel_TypeDef *) DMA2_channel2_BASE) +#define DMA2_CH3 ((DMA_Channel_TypeDef *) DMA2_channel3_BASE) +#define DMA2_CH4 ((DMA_Channel_TypeDef *) DMA2_channel4_BASE) +#define DMA2_CH5 ((DMA_Channel_TypeDef *) DMA2_channel5_BASE) +#define DMA2_CH6 ((DMA_Channel_TypeDef *) DMA2_channel6_BASE) +#define DMA2_CH7 ((DMA_Channel_TypeDef *) DMA2_channel7_BASE) + +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define I2C3 ((I2C_TypeDef *) I2C3_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_CTL_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define CRS ((CRS_TypeDef *) CRS_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define OTG_FS ((OTG_FS_TypeDef *) OTG_FS_BASE) +#define USB_FS ((OTG_FS_TypeDef *) OTG_FS_BASE) +#define OTG_HS ((USB_OTG_HS_GlobalTypeDef *) OTG_HS_BASE) +#define USB_HS ((USB_OTG_HS_GlobalTypeDef *) OTG_HS_BASE) +#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE) +#define UCPD ((UCPD_TypeDef *) UCPD_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART6 ((USART_TypeDef *) USART6_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define LPUART ((USART_TypeDef *) LPUART_BASE) +#define USART1_WP ((USART_WP_TypeDef *) USART1_WP_BASE) +#define USART2_WP ((USART_WP_TypeDef *) USART2_WP_BASE) +#define USART3_WP ((USART_WP_TypeDef *) USART3_WP_BASE) +#define USART6_WP ((USART_WP_TypeDef *) USART6_WP_BASE) +#define UART4_WP ((USART_WP_TypeDef *) UART4_WP_BASE) +#define UART5_WP ((USART_WP_TypeDef *) UART5_WP_BASE) +#define UART7_WP ((USART_WP_TypeDef *) UART7_WP_BASE) +#define LPUART_WP ((USART_WP_TypeDef *) LPUART_WP_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define QSPI ((QSPI_TypeDef *) QSPI_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) +#define SDIO_DATA ((SDIO_DATA_TypeDef *) SDIO_DATA_BASE) +#define SPDIF ((SPDIF_TypeDef *) SPDIF_BASE) +#define SSI ((SSI_TypeDef *) SSI_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE ) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define TIM11 ((TIM_TypeDef *) TIM11_BASE) +#define TIM12 ((TIM_TypeDef *) TIM12_BASE) +#define TIM13 ((TIM_TypeDef *) TIM13_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LPTIM ((LPTIM_TypeDef *) LPTIM_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM_BASE) +#define FDCAN1 ((FDCAN_TypeDef *) CAN1_BASE) +#define FDCAN2 ((FDCAN_TypeDef *) CAN2_BASE) +#define FDCAN3 ((FDCAN_TypeDef *) CAN3_BASE) +#define FDCAN4 ((FDCAN_TypeDef *) CAN4_BASE) +#define DBGMCU ((DBG_TypeDef *) DBGMCU_BASE) +#define COMP_OPAM_DAC ((COMP_OPAM_DAC_TypeDef *) COMP_OPAM_DAC_BASE) +#define ICACHE ((ICACHE_TypeDef *) ICACHE_BASE) +#define DCACHE ((DCACHE_TypeDef *) DCACHE_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) +#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) +#define FMC_Bank2_3 ((FMC_Bank2_3_TypeDef *) FMC_Bank2_3_R_BASE) +#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define I2S2 ((I2S_TypeDef *) I2S2_BASE) +#define I2S3 ((I2S_TypeDef *) I2S3_BASE) + +//****************** ADC Registers Address ****************** +//added by cpf +#define ADC1_BASE (APB2_BASE + 0x2000) +#define ADC2_BASE (APB2_BASE + 0x2100) +#define ADC3_BASE (APB2_BASE + 0x2200) +#define ADC_Common_BASE (APB2_BASE + 0x2300) + +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define ADC_Common ((ADC_Common_TypeDef *) ADC_Common_BASE) + + + +/*@}*/ /* end of group CM4_PeripheralDecl */ + + + +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ +/******************************************************************************/ +/* */ +/* USB High-speed On-The-Go (OTG_HS) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for OTG_HS_GOTGCTL register *******************/ +#define OTG_HS_GOTGCTL_SRQSCS_Pos (0U) +#define OTG_HS_GOTGCTL_SRQSCS_Msk (0x1UL << OTG_HS_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define OTG_HS_GOTGCTL_SRQSCS OTG_HS_GOTGCTL_SRQSCS_Msk /*! */ + +#define CACHE_SR_POWST_Pos (4U) +#define CACHE_SR_POWST_Msk (0x1UL << CACHE_SR_POWST_Pos) /*! 0x00000010 */ +#define POWST CACHE_SR_POWST_Msk /*< SRAM power acknowledges */ + +/**************** Bit definition for I/D CACHE_IRQMASK register ****************/ +#define CACHE_IRQMASK_POWERR_Pos (0U) +#define CACHE_IRQMASK_POWERR_Msk (0x1UL << CACHE_TRQMASK_POWERR_Pos) /*! 0x00000001 */ +#define MASK_POWERR CACHE_IRQMASK_POWERR_Msk /*< Mask interrupt request on power error indication >*/ + +#define CACHE_IRQMASK_MANINVERR_Pos (1U) +#define CACHE_IRQMASK_MANINVERR_Msk (0x2UL << CACHE_IRQMASK_MANINVERR_Pos) /*! 0x00000002 */ +#define MASK_MANINVERR CACHE_IRQMASK_MANINVERR_Msk /*< Mask interrupt request on manual invalidation error indication >*/ + + + +/**************** Bit definition for I/D CACHE_IRQSTAT register ****************/ +#define CACHE_IRQSTAT_POWERR_Pos (0U) +#define CACHE_IRQSTAT_POWERR_Msk (0x1UL << CACHE_IRQSTAT_POWERR_Pos) /*! 0x00000001 */ +#define POWERR CACHE_IRQSTAT_POWERR_Msk /*< SRAM power error status , write 1 to clear */ + +#define CACHE_IRQSTAT_MANINVERR_Pos (1U) +#define CACHE_IRQSTAT_MANINVERR_Msk (0x1UL << CACHE_IRQSTAT_MANINVERR_Pos) /*! 0x00000002 */ +#define MANINVERR CACHE_IRQSTAT_MANINVERR_Msk /*< Manual invalidation error status , write 1 to clear */ + + +/**************** Bit definition for I/D CACHE_TYPE register ****************/ +#define CACHE_TYPE_AW_Pos (0U) +#define CACHE_TYPE_AW_Msk (0x1fUL << CACHE_TYPE_AW_Pos) +#define AW_0 (0x1UL << CACHE_TYPE_AW_Pos) +#define AW_1 (0x2UL << CACHE_TYPE_AW_Pos) +#define AW_2 (0x4UL << CACHE_TYPE_AW_Pos) +#define AW_3 (0x8UL << CACHE_TYPE_AW_Pos) +#define AW_4 (0x10UL << CACHE_TYPE_AW_Pos) + +#define CACHE_TYPE_CW_Pos (5U) +#define CACHE_TYPE_CW_Msk (0x1fUL << CACHE_TYPE_CW_Pos) +#define CW_0 (0x1UL << CACHE_TYPE_CW_Pos) +#define CW_1 (0x2UL << CACHE_TYPE_CW_Pos) +#define CW_2 (0x4UL << CACHE_TYPE_CW_Pos) +#define CW_3 (0x8UL << CACHE_TYPE_CW_Pos) +#define CW_4 (0x10UL << CACHE_TYPE_CW_Pos) + +#define CACHE_TYPE_WAY_Pos (10U) +#define CACHE_TYPE_WAY_Msk (0x1fUL << CACHE_TYPE_WAY_Pos) +#define WAY_0 (0x1UL << CACHE_TYPE_WAY_Pos) +#define WAY_1 (0x2UL << CACHE_TYPE_WAY_Pos) + +#define CACHE_TYPE_RSTALLREG_Pos (12U) +#define CACHE_TYPE_RSTALLREG_Msk (0x1UL << CACHE_TYPE_RSTALLREG_Pos) +#define RSTALLREG CACHE_TYPE_RSTALLREG_Msk + +#define CACHE_TYPE_GENSTATLOGIC_Pos (13U) +#define CACHE_TYPE_GENSTATLOGIC_Msk (0x1UL << CACHE_TYPE_GENSTATLOGIC_Pos) +#define GENSTATLOGIC CACHE_TYPE_GENSTATLOGIC_Msk + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for RNG RNG_CR register ****************/ +#define RNG_EN_Pos (2U) +#define RNG_EN_Msk (0x1UL << RNG_EN_Pos) /*! 0x00000004 */ +#define RNG_EN RNG_EN_Msk /*< RNG enbable */ + +#define RNG_IE_Pos (3U) +#define RNG_IE_Msk (0x1UL << RNG_IE_Pos) /*! 0x00000008 */ +#define RNG_IE RNG_IE_Msk /*< RNG interrupt enable */ + + +/**************** Bit definition for RNG RNG_SR register ****************/ +#define RNG_DRDY_Pos (0U) +#define RNG_DRDY_Msk (0x1UL << RNG_DRDY_Pos) /*! 0x00000001 */ +#define RNG_DRDY RNG_DRDY_Msk /*< RNG DATA READY */ + +#define RNG_CECS_Pos (1U) +#define RNG_CECS_Msk (0x1UL << RNG_CECS_Pos) /*! 0x00000002 */ +#define RNG_CECS RNG_CECS_Msk /*< RNG CLK ERROR CURRENT STATUS*/ + +#define RNG_SECS_Pos (2U) +#define RNG_SECS_Msk (0x1UL << RNG_SECS_Pos) /*! 0x00000004 */ +#define RNG_SECS RNG_SECS_Msk /*< RNG SEED ERROR CURRENT STATUS */ + +#define RNG_CEIS_Pos (5U) +#define RNG_CEIS_Msk (0x1UL << RNG_CEIS_Pos) /*! 0x00000020 */ +#define RNG_CEIS RNG_CEIS_Msk /*< RNG CLK ERROR INTR STATUS */ + +#define RNG_SEIS_Pos (6U) +#define RNG_SEIS_Msk (0x1UL << RNG_SEIS_Pos) /*! 0x00000040 */ +#define RNG_SEIS RNG_SEIS_Msk /*< RNG SEED ERROR INTR STATUS */ + +/******************************************************************************/ +/* */ +/* VREFBUF */ +/* */ +/******************************************************************************/ + + +/**************** Bit definition for VREFBUF_CSR register ****************/ +#define VREFBUF_ENVR_Pos (0U) +#define VREFBUF_ENVR_Msk (0x1UL << VREFBUF_ENVR_Pos) /*! 0x00000001 */ +#define VREFBUF_ENVR VREFBUF_ENVR_Msk /*< Voltage reference buffer mode enable */ + +#define VREFBUF_HIZ_Pos (1U) +#define VREFBUF_HIZ_Msk (0x1UL << VREFBUF_HIZ_Pos) /*! 0x00000002 */ +#define VREFBUF_HIZ VREFBUF_HIZ_Msk /*< High impedance mode */ + +#define VREFBUF_VRS_Pos (2U) +#define VREFBUF_VRS_Msk (0x1UL << VREFBUF_VRS_Pos) /*! 0x00000004*/ +#define VREFBUF_VRS VREFBUF_VRS_Msk /*< Voltage reference scale */ + +#define VREFBUF_VRR_Pos (3U) +#define VREFBUF_VRR_Msk (0x1UL << VREFBUF_VRR_Pos) /*! 0x00000008*/ +#define VREFBUF_VRR VREFBUF_VRR_Msk /*!< Voltage reference buffer ready */ + +/**************** Bit definition for VREFBUF_CCR register ****************/ +#define VREFBUF_TRIM_Pos (0U) +#define VREFBUF_TRIM_Msk (0x3fUL << VREFBUF_TRIM_Pos) /*! 0x0000003f */ +#define VREFBUF_TRIM_0 (0x1UL << VREFBUF_TRIM_Pos) /*! 0x00000001 */ +#define VREFBUF_TRIM_1 (0x2UL << VREFBUF_TRIM_Pos) /*! 0x00000002 */ +#define VREFBUF_TRIM_2 (0x4UL << VREFBUF_TRIM_Pos) /*! 0x00000004 */ +#define VREFBUF_TRIM_3 (0x8UL << VREFBUF_TRIM_Pos) /*! 0x00000008 */ +#define VREFBUF_TRIM_4 (0x10UL << VREFBUF_TRIM_Pos) /*! 0x00000010 */ +#define VREFBUF_TRIM_5 (0x20UL << VREFBUF_TRIM_Pos) /*! 0x00000020 */ + + + + + +/******************************************************************************/ +/* */ +/* ADC */ +/* */ +/******************************************************************************/ + +/**************** Bit definition for ADC_ISR register ****************/ +#define ADC_ISR_Pos (0U) +#define ADC_ISR_Msk (0x7FFUL << ADC_ISR_Pos) +#define ADC_ISR_ADRDY (0x1UL << ADC_ISR_Pos) /*! 0x00000001 */ +#define ADC_ISR_EOSMP (0x2UL << ADC_ISR_Pos) /*! 0x00000002 */ +#define ADC_ISR_EOC (0x4UL << ADC_ISR_Pos) /*! 0x00000004 */ +#define ADC_ISR_EOS (0x8UL << ADC_ISR_Pos) /*! 0x00000008 */ +#define ADC_ISR_OVR (0x10UL << ADC_ISR_Pos) /*! 0x00000010 */ +#define ADC_ISR_JEOC (0x20UL << ADC_ISR_Pos) /*! 0x00000020 */ +#define ADC_ISR_JEOS (0x40UL << ADC_ISR_Pos) /*! 0x00000040 */ +#define ADC_ISR_AWD1 (0x80UL << ADC_ISR_Pos) /*! 0x00000080 */ +#define ADC_ISR_AWD2 (0x100UL << ADC_ISR_Pos) /*! 0x00000100 */ +#define ADC_ISR_AWD3 (0x200UL << ADC_ISR_Pos) /*! 0x00000200 */ +#define ADC_ISR_JQOVF (0x400UL << ADC_ISR_Pos) /*! 0x00000400 */ + +/**************** Bit definition for ADC_IER register ****************/ +#define ADC_IER_Pos (0U) +#define ADC_IER_Msk (0x7FFUL << ADC_IER_Pos) +#define ADC_IER_ADRDYIE (0x1UL << ADC_IER_Pos) /*! 0x00000001 */ +#define ADC_IER_EOSMPIE (0x2UL << ADC_IER_Pos) /*! 0x00000002 */ +#define ADC_IER_EOCIE (0x4UL << ADC_IER_Pos) /*! 0x00000004 */ +#define ADC_IER_EOSIE (0x8UL << ADC_IER_Pos) /*! 0x00000008 */ +#define ADC_IER_OVRIE (0x10UL << ADC_IER_Pos) /*! 0x00000010 */ +#define ADC_IER_JEOCIE (0x20UL << ADC_IER_Pos) /*! 0x00000020 */ +#define ADC_IER_JEOSIE (0x40UL << ADC_IER_Pos) /*! 0x00000040 */ +#define ADC_IER_AWD1IE (0x80UL << ADC_IER_Pos) /*! 0x00000080 */ +#define ADC_IER_AWD2IE (0x100UL << ADC_IER_Pos) /*! 0x00000100 */ +#define ADC_IER_AWD3IE (0x200UL << ADC_IER_Pos) /*! 0x00000200 */ +#define ADC_IER_JQOVIE (0x400UL << ADC_IER_Pos) /*! 0x00000400 */ + +/**************** Bit definition for ADC_CR register ****************/ +#define ADC_CR_Pos (0U) +#define ADC_CR_Msk (0xFFFFFFFFUL << ADC_CR_Pos) +#define ADC_CR_ADEN (0x1UL << ADC_CR_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADDIS (0x2UL << ADC_CR_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADSTART (0x4UL << ADC_CR_Pos) /*!< 0x00000004 */ +#define ADC_CR_JADSTART (0x8UL << ADC_CR_Pos) /*!< 0x00000008 */ +#define ADC_CR_ADSTP (0x10UL << ADC_CR_Pos) /*!< 0x00000010 */ +#define ADC_CR_JADSTP (0x20UL << ADC_CR_Pos) /*!< 0x00000020 */ +#define ADC_CR_SELREFLDO (0x4000000UL << ADC_CR_Pos) /*!< 0x04000000 */ +#define ADC_CR_SELRANGELDO (0x8000000UL << ADC_CR_Pos) /*!< 0x08000000 */ +#define ADC_CR_ADVREGEN (0x10000000UL << ADC_CR_Pos) /*!< 0x10000000 */ +#define ADC_CR_DEEPPWD (0x20000000UL << ADC_CR_Pos) /*!< 0x20000000 */ +#define ADC_CR_ADCALDIF (0x40000000UL << ADC_CR_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCAL (0x80000000UL << ADC_CR_Pos) /*!< 0x80000000 */ + +/**************** Bit definition for ADC_CFGR1 register ****************/ +#define ADC_CFGR1_Pos (0U) +#define ADC_CFGR1_Msk (0xFFFFFFFDUL << ADC_CFGR1_Pos) +#define ADC_CFGR1_DMAEN (0x1UL << ADC_CFGR1_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMACFG (0x2UL << ADC_CFGR1_Pos) /*!< 0x00000002 */ +#define ADC_CFGR1_RES_0 (0x8UL << ADC_CFGR1_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RES_1 (0x10UL << ADC_CFGR1_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_RES (0x18UL << ADC_CFGR1_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_EXTSEL_0 (0x20UL << ADC_CFGR1_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x40UL << ADC_CFGR1_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x80UL << ADC_CFGR1_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x100UL << ADC_CFGR1_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x200UL << ADC_CFGR1_Pos) /*!< 0x00000200 */ +#define ADC_CFGR1_EXTSEL (0x3E0UL << ADC_CFGR1_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTEN_0 (0x400UL << ADC_CFGR1_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x800UL << ADC_CFGR1_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_EXTEN (0xC00UL << ADC_CFGR1_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_OVRMOD (0x1000UL << ADC_CFGR1_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_CONT (0x2000UL << ADC_CFGR1_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_AUTDLY (0x4000UL << ADC_CFGR1_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_ALIGN (0x8000UL << ADC_CFGR1_Pos) /*!< 0x00008000 */ +#define ADC_CFGR1_DISCEN (0x10000UL << ADC_CFGR1_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCNUM_0 (0x20000UL << ADC_CFGR1_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x40000UL << ADC_CFGR1_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x80000UL << ADC_CFGR1_Pos) /*!< 0x00080000 */ +#define ADC_CFGR1_DISCNUM (0xE0000UL << ADC_CFGR1_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_JDISCEN (0x100000UL << ADC_CFGR1_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JQM (0x200000UL << ADC_CFGR1_Pos) /*!< 0x00200000 */ +#define ADC_CFGR1_AWD1SGL (0x400000UL << ADC_CFGR1_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1EN (0x800000UL << ADC_CFGR1_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_JAWD1EN (0x1000000UL << ADC_CFGR1_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAUTO (0x2000000UL << ADC_CFGR1_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_AWD1CH_0 (0x4000000UL << ADC_CFGR1_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x8000000UL << ADC_CFGR1_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x10000000UL << ADC_CFGR1_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x20000000UL << ADC_CFGR1_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x40000000UL << ADC_CFGR1_Pos) /*!< 0x40000000 */ +#define ADC_CFGR1_AWD1CH (0x7C000000UL << ADC_CFGR1_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_JQDIS (0x80000000UL << ADC_CFGR1_Pos) /*!< 0x80000000 */ + + +/**************** Bit definition for ADC_CFGR2 register ****************/ +#define ADC_CFGR2_Pos (0U) +#define ADC_CFGR2_Msk (0xE003FFFUL << ADC_CFGR2_Pos) +#define ADC_CFGR2_ROVSE (0x1UL << ADC_CFGR2_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_JOVSE (0x2UL << ADC_CFGR2_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_OVSR_0 (0x4UL << ADC_CFGR2_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x8UL << ADC_CFGR2_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x10UL << ADC_CFGR2_Pos) /*!< 0x00000010 */ +#define ADC_CFGR2_OVSR (0x1CUL << ADC_CFGR2_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSS_0 (0x20UL << ADC_CFGR2_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x40UL << ADC_CFGR2_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x80UL << ADC_CFGR2_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x100UL << ADC_CFGR2_Pos) /*!< 0x00000100 */ +#define ADC_CFGR2_OVSS (0x1E0UL << ADC_CFGR2_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_TROVS (0x200UL << ADC_CFGR2_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_ROVSM (0x400UL << ADC_CFGR2_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_OP1SEL (0x800UL << ADC_CFGR2_Pos) /*!< 0x00000800 */ +#define ADC_CFGR2_OP2SEL (0x1000UL << ADC_CFGR2_Pos) /*!< 0x00001000 */ +#define ADC_CFGR2_OP3SEL (0x2000UL << ADC_CFGR2_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_GCOMP (0x10000UL << ADC_CFGR2_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_SWTRIG (0x2000000UL << ADC_CFGR2_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_BULB (0x4000000UL << ADC_CFGR2_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_SMPTRIG (0x8000000UL << ADC_CFGR2_Pos) /*!< 0x08000000 */ + + +/**************** Bit definition for ADC_SMPR1 register ****************/ +#define ADC_SMPR1_Pos (0U) +#define ADC_SMPR1_Msk (0xDFFFFFFFUL << ADC_SMPR1_Pos) +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP1_0 (0x8UL << ADC_SMPR1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x10UL << ADC_SMPR1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x20UL << ADC_SMPR1_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP2_0 (0x40UL << ADC_SMPR1_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x80UL << ADC_SMPR1_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x100UL << ADC_SMPR1_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP3_0 (0x200UL << ADC_SMPR1_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x400UL << ADC_SMPR1_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x800UL << ADC_SMPR1_Pos) /*!< 0x00000800 */ +#define ADC_SMPR1_SMP4_0 (0x1000UL << ADC_SMPR1_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2000UL << ADC_SMPR1_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4000UL << ADC_SMPR1_Pos) /*!< 0x00004000 */ +#define ADC_SMPR1_SMP5_0 (0x8000UL << ADC_SMPR1_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x10000UL << ADC_SMPR1_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x20000UL << ADC_SMPR1_Pos) /*!< 0x00020000 */ +#define ADC_SMPR1_SMP6_0 (0x40000UL << ADC_SMPR1_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x80000UL << ADC_SMPR1_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x100000UL << ADC_SMPR1_Pos) /*!< 0x00100000 */ +#define ADC_SMPR1_SMP7_0 (0x200000UL << ADC_SMPR1_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x400000UL << ADC_SMPR1_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x800000UL << ADC_SMPR1_Pos) /*!< 0x00800000 */ +#define ADC_SMPR1_SMP8_0 (0x1000000UL << ADC_SMPR1_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2000000UL << ADC_SMPR1_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4000000UL << ADC_SMPR1_Pos) /*!< 0x04000000 */ +#define ADC_SMPR1_SMP9_0 (0x8000000UL << ADC_SMPR1_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x10000000UL << ADC_SMPR1_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x20000000UL << ADC_SMPR1_Pos) /*!< 0x20000000 */ +#define ADC_SMPR1_SMPLUS_0 (0x40000000UL << ADC_SMPR1_Pos) /*!< 0x40000000 */ +#define ADC_SMPR1_SMPLUS_1 (0x80000000UL << ADC_SMPR1_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPLUS (0xC0000000UL << ADC_SMPR1_Pos) /*!< 0xC0000000 */ + + +/**************** Bit definition for ADC_SMPR2 register ****************/ +#define ADC_SMPR2_Pos (0U) +#define ADC_SMPR2_Msk (0x7FFFFFFUL << ADC_SMPR2_Pos) +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_Pos) /*!< 0x00000004 */ +#define ADC_SMPR2_SMP11_0 (0x8UL << ADC_SMPR2_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x10UL << ADC_SMPR2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x20UL << ADC_SMPR2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR2_SMP12_0 (0x40UL << ADC_SMPR2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x80UL << ADC_SMPR2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x100UL << ADC_SMPR2_Pos) /*!< 0x00000100 */ +#define ADC_SMPR2_SMP13_0 (0x200UL << ADC_SMPR2_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x400UL << ADC_SMPR2_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x800UL << ADC_SMPR2_Pos) /*!< 0x00000800 */ +#define ADC_SMPR2_SMP14_0 (0x1000UL << ADC_SMPR2_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2000UL << ADC_SMPR2_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4000UL << ADC_SMPR2_Pos) /*!< 0x00004000 */ +#define ADC_SMPR2_SMP15_0 (0x8000UL << ADC_SMPR2_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x10000UL << ADC_SMPR2_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x20000UL << ADC_SMPR2_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP16_0 (0x40000UL << ADC_SMPR2_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x80000UL << ADC_SMPR2_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x100000UL << ADC_SMPR2_Pos) /*!< 0x00100000 */ +#define ADC_SMPR2_SMP17_0 (0x200000UL << ADC_SMPR2_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x400000UL << ADC_SMPR2_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x800000UL << ADC_SMPR2_Pos) /*!< 0x00800000 */ +#define ADC_SMPR2_SMP18_0 (0x1000000UL << ADC_SMPR2_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2000000UL << ADC_SMPR2_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4000000UL << ADC_SMPR2_Pos) /*!< 0x04000000 */ + + +/**************** Bit definition for ADC_SMPR3 register ****************/ +#define ADC_SMPR3_Pos (0U) +#define ADC_SMPR3_Msk (0x7FFFFFFUL << ADC_SMPR2_Pos) +#define ADC_SMPR3_SMP19_0 (0x1UL << ADC_SMPR2_Pos) /*!< 0x00000001 */ +#define ADC_SMPR3_SMP19_1 (0x2UL << ADC_SMPR2_Pos) /*!< 0x00000002 */ +#define ADC_SMPR3_SMP19_2 (0x4UL << ADC_SMPR2_Pos) /*!< 0x00000004 */ +#define ADC_SMPR3_SMP20_0 (0x8UL << ADC_SMPR2_Pos) /*!< 0x00000008 */ +#define ADC_SMPR3_SMP20_1 (0x10UL << ADC_SMPR2_Pos) /*!< 0x00000010 */ +#define ADC_SMPR3_SMP20_2 (0x20UL << ADC_SMPR2_Pos) /*!< 0x00000020 */ +#define ADC_SMPR3_SMP21_0 (0x40UL << ADC_SMPR2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR3_SMP21_1 (0x80UL << ADC_SMPR2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR3_SMP21_2 (0x100UL << ADC_SMPR2_Pos) /*!< 0x00000100 */ + + + + + +/**************** Bit definition for ADC_TR1 register ****************/ +#define ADC_TR1_Pos (0U) +#define ADC_TR1_Msk (0xFFF7FFFUL << ADC_TR1_Pos) +#define ADC_TR1_LT1_0 (0x1UL << ADC_TR1_Pos) /*!< 0x00000001 */ +#define ADC_TR1_LT1_1 (0x2UL << ADC_TR1_Pos) /*!< 0x00000002 */ +#define ADC_TR1_LT1_2 (0x4UL << ADC_TR1_Pos) /*!< 0x00000004 */ +#define ADC_TR1_LT1_3 (0x8UL << ADC_TR1_Pos) /*!< 0x00000008 */ +#define ADC_TR1_LT1_4 (0x10UL << ADC_TR1_Pos) /*!< 0x00000010 */ +#define ADC_TR1_LT1_5 (0x20UL << ADC_TR1_Pos) /*!< 0x00000020 */ +#define ADC_TR1_LT1_6 (0x40UL << ADC_TR1_Pos) /*!< 0x00000040 */ +#define ADC_TR1_LT1_7 (0x80UL << ADC_TR1_Pos) /*!< 0x00000080 */ +#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_Pos) /*!< 0x00000100 */ +#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_Pos) /*!< 0x00000200 */ +#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_Pos) /*!< 0x00000400 */ +#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_Pos) /*!< 0x00000800 */ +#define ADC_TR1_LT1 (0xFFFUL << ADC_TR1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_AWDFILT_0 (0x1000UL << ADC_TR1_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2000UL << ADC_TR1_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4000UL << ADC_TR1_Pos) /*!< 0x00004000 */ +#define ADC_TR1_AWDFILT (0x7000UL << ADC_TR1_Pos) /*!< 0x00007000 */ +#define ADC_TR1_HT1_0 (0x10000UL << ADC_TR1_Pos) /*!< 0x00010000 */ +#define ADC_TR1_HT1_1 (0x20000UL << ADC_TR1_Pos) /*!< 0x00020000 */ +#define ADC_TR1_HT1_2 (0x40000UL << ADC_TR1_Pos) /*!< 0x00040000 */ +#define ADC_TR1_HT1_3 (0x80000UL << ADC_TR1_Pos) /*!< 0x00080000 */ +#define ADC_TR1_HT1_4 (0x100000UL << ADC_TR1_Pos) /*!< 0x00100000 */ +#define ADC_TR1_HT1_5 (0x200000UL << ADC_TR1_Pos) /*!< 0x00200000 */ +#define ADC_TR1_HT1_6 (0x400000UL << ADC_TR1_Pos) /*!< 0x00400000 */ +#define ADC_TR1_HT1_7 (0x800000UL << ADC_TR1_Pos) /*!< 0x00800000 */ +#define ADC_TR1_HT1_8 (0x1000000UL << ADC_TR1_Pos) /*!< 0x01000000 */ +#define ADC_TR1_HT1_9 (0x2000000UL << ADC_TR1_Pos) /*!< 0x02000000 */ +#define ADC_TR1_HT1_10 (0x4000000UL << ADC_TR1_Pos) /*!< 0x04000000 */ +#define ADC_TR1_HT1_11 (0x8000000UL << ADC_TR1_Pos) /*!< 0x08000000 */ +#define ADC_TR1_HT1 (0xFFF0000UL << ADC_TR1_Pos) /*!< 0x0FFF0000 */ + + +/**************** Bit definition for ADC_TR2 register ****************/ +#define ADC_TR2_Pos (0U) +#define ADC_TR2_Msk (0xFF00FFUL << ADC_TR2_Pos) +#define ADC_TR2_LT2_0 (0x1UL << ADC_TR2_Pos) /*!< 0x00000001 */ +#define ADC_TR2_LT2_1 (0x2UL << ADC_TR2_Pos) /*!< 0x00000002 */ +#define ADC_TR2_LT2_2 (0x4UL << ADC_TR2_Pos) /*!< 0x00000004 */ +#define ADC_TR2_LT2_3 (0x8UL << ADC_TR2_Pos) /*!< 0x00000008 */ +#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_Pos) /*!< 0x00000010 */ +#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_Pos) /*!< 0x00000020 */ +#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_Pos) /*!< 0x00000040 */ +#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_Pos) /*!< 0x00000080 */ +#define ADC_TR2_LT2 (0xFFUL << ADC_TR2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_HT2_0 (0x10000UL << ADC_TR2_Pos) /*!< 0x00010000 */ +#define ADC_TR2_HT2_1 (0x20000UL << ADC_TR2_Pos) /*!< 0x00020000 */ +#define ADC_TR2_HT2_2 (0x40000UL << ADC_TR2_Pos) /*!< 0x00040000 */ +#define ADC_TR2_HT2_3 (0x80000UL << ADC_TR2_Pos) /*!< 0x00080000 */ +#define ADC_TR2_HT2_4 (0x100000UL << ADC_TR2_Pos) /*!< 0x00100000 */ +#define ADC_TR2_HT2_5 (0x200000UL << ADC_TR2_Pos) /*!< 0x00200000 */ +#define ADC_TR2_HT2_6 (0x400000UL << ADC_TR2_Pos) /*!< 0x00400000 */ +#define ADC_TR2_HT2_7 (0x800000UL << ADC_TR2_Pos) /*!< 0x00800000 */ +#define ADC_TR2_HT2 (0xFF0000UL << ADC_TR2_Pos) /*!< 0x00FF0000 */ + + +/**************** Bit definition for ADC_TR3 register ****************/ +#define ADC_TR3_Pos (0U) +#define ADC_TR3_Msk (0xFF00FFUL << ADC_TR3_Pos) +#define ADC_TR3_LT3_0 (0x1UL << ADC_TR3_Pos) /*!< 0x00000001 */ +#define ADC_TR3_LT3_1 (0x2UL << ADC_TR3_Pos) /*!< 0x00000002 */ +#define ADC_TR3_LT3_2 (0x4UL << ADC_TR3_Pos) /*!< 0x00000004 */ +#define ADC_TR3_LT3_3 (0x8UL << ADC_TR3_Pos) /*!< 0x00000008 */ +#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_Pos) /*!< 0x00000010 */ +#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_Pos) /*!< 0x00000020 */ +#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_Pos) /*!< 0x00000040 */ +#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_Pos) /*!< 0x00000080 */ +#define ADC_TR3_LT3 (0xFFUL << ADC_TR3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_HT3_0 (0x10000UL << ADC_TR3_Pos) /*!< 0x00010000 */ +#define ADC_TR3_HT3_1 (0x20000UL << ADC_TR3_Pos) /*!< 0x00020000 */ +#define ADC_TR3_HT3_2 (0x40000UL << ADC_TR3_Pos) /*!< 0x00040000 */ +#define ADC_TR3_HT3_3 (0x80000UL << ADC_TR3_Pos) /*!< 0x00080000 */ +#define ADC_TR3_HT3_4 (0x100000UL << ADC_TR3_Pos) /*!< 0x00100000 */ +#define ADC_TR3_HT3_5 (0x200000UL << ADC_TR3_Pos) /*!< 0x00200000 */ +#define ADC_TR3_HT3_6 (0x400000UL << ADC_TR3_Pos) /*!< 0x00400000 */ +#define ADC_TR3_HT3_7 (0x800000UL << ADC_TR3_Pos) /*!< 0x00800000 */ +#define ADC_TR3_HT3 (0xFF0000UL << ADC_TR3_Pos) /*!< 0x00FF0000 */ + + +/**************** Bit definition for ADC_SQR1 register ****************/ +#define ADC_SQR1_Pos (0U) +#define ADC_SQR1_Msk (0x1F7DF7CFUL << ADC_SQR1_Pos) +#define ADC_SQR1_L (0xF << ADC_SQR1_Pos) +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ1_0 (0x40UL << ADC_SQR1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x80UL << ADC_SQR1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x100UL << ADC_SQR1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x200UL << ADC_SQR1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x400UL << ADC_SQR1_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ1 (0x7C0UL << ADC_SQR1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ2_0 (0x1000UL << ADC_SQR1_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x2000UL << ADC_SQR1_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x4000UL << ADC_SQR1_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x8000UL << ADC_SQR1_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10000UL << ADC_SQR1_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ2 (0x1F000UL << ADC_SQR1_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ3_0 (0x40000UL << ADC_SQR1_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x80000UL << ADC_SQR1_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x100000UL << ADC_SQR1_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x200000UL << ADC_SQR1_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x400000UL << ADC_SQR1_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_SQ3 (0x7C0000UL << ADC_SQR1_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ4_0 (0x1000000UL << ADC_SQR1_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x2000000UL << ADC_SQR1_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x4000000UL << ADC_SQR1_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x8000000UL << ADC_SQR1_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10000000UL << ADC_SQR1_Pos) /*!< 0x10000000 */ +#define ADC_SQR1_SQ4 (0x1F000000UL << ADC_SQR1_Pos) /*!< 0x1F000000 */ + + +/**************** Bit definition for ADC_SQR2 register ****************/ +#define ADC_SQR2_Pos (0U) +#define ADC_SQR2_Msk (0xFFFFFFFFUL << ADC_SQR2_Pos) +#define ADC_SQR2_SQ5_0 (0x1UL << ADC_SQR2_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x2UL << ADC_SQR2_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x4UL << ADC_SQR2_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x8UL << ADC_SQR2_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_0 (0x40UL << ADC_SQR2_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x80UL << ADC_SQR2_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x100UL << ADC_SQR2_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x200UL << ADC_SQR2_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x400UL << ADC_SQR2_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ7_0 (0x1000UL << ADC_SQR2_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x2000UL << ADC_SQR2_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x4000UL << ADC_SQR2_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x8000UL << ADC_SQR2_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10000UL << ADC_SQR2_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ8_0 (0x40000UL << ADC_SQR2_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x80000UL << ADC_SQR2_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x100000UL << ADC_SQR2_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x200000UL << ADC_SQR2_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x400000UL << ADC_SQR2_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ9_0 (0x1000000UL << ADC_SQR2_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x2000000UL << ADC_SQR2_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x4000000UL << ADC_SQR2_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x8000000UL << ADC_SQR2_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10000000UL << ADC_SQR2_Pos) /*!< 0x10000000 */ + + +/**************** Bit definition for ADC_SQR3 register ****************/ +#define ADC_SQR3_Pos (0U) +#define ADC_SQR3_Msk (0xFFFFFFFFUL << ADC_SQR3_Pos) +#define ADC_SQR3_SQ10_0 (0x1UL << ADC_SQR3_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x2UL << ADC_SQR3_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x4UL << ADC_SQR3_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x8UL << ADC_SQR3_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_0 (0x40UL << ADC_SQR3_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x80UL << ADC_SQR3_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x100UL << ADC_SQR3_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x200UL << ADC_SQR3_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x400UL << ADC_SQR3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ12_0 (0x1000UL << ADC_SQR3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x2000UL << ADC_SQR3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x4000UL << ADC_SQR3_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x8000UL << ADC_SQR3_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10000UL << ADC_SQR3_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ13_0 (0x40000UL << ADC_SQR3_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x80000UL << ADC_SQR3_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x100000UL << ADC_SQR3_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x200000UL << ADC_SQR3_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x400000UL << ADC_SQR3_Pos) /*!< 0x00400000 */ +#define ADC_SQR3_SQ14_0 (0x1000000UL << ADC_SQR3_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x2000000UL << ADC_SQR3_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x4000000UL << ADC_SQR3_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x8000000UL << ADC_SQR3_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10000000UL << ADC_SQR3_Pos) /*!< 0x10000000 */ + + +/**************** Bit definition for ADC_SQR4 register ****************/ +#define ADC_SQR4_Pos (0U) +#define ADC_SQR4_Msk (0xFFFFFFFFUL << ADC_SQR4_Pos) +#define ADC_SQR4_SQ15_0 (0x1UL << ADC_SQR4_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x2UL << ADC_SQR4_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x4UL << ADC_SQR4_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x8UL << ADC_SQR4_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_0 (0x40UL << ADC_SQR4_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x80UL << ADC_SQR4_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x100UL << ADC_SQR4_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x200UL << ADC_SQR4_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x400UL << ADC_SQR4_Pos) /*!< 0x00000400 */ + + +/**************** Bit definition for ADC_DR register ****************/ +#define ADC_DR_Pos (0U) +#define ADC_DR_Msk (0xFFFFFFFFUL << ADC_DR_Pos) +#define ADC_DR_RDATA_0 (0x1UL << ADC_DR_Pos) /*!< 0x00000001 */ +#define ADC_DR_RDATA_1 (0x2UL << ADC_DR_Pos) /*!< 0x00000002 */ +#define ADC_DR_RDATA_2 (0x4UL << ADC_DR_Pos) /*!< 0x00000004 */ +#define ADC_DR_RDATA_3 (0x8UL << ADC_DR_Pos) /*!< 0x00000008 */ +#define ADC_DR_RDATA_4 (0x10UL << ADC_DR_Pos) /*!< 0x00000010 */ +#define ADC_DR_RDATA_5 (0x20UL << ADC_DR_Pos) /*!< 0x00000020 */ +#define ADC_DR_RDATA_6 (0x40UL << ADC_DR_Pos) /*!< 0x00000040 */ +#define ADC_DR_RDATA_7 (0x80UL << ADC_DR_Pos) /*!< 0x00000080 */ +#define ADC_DR_RDATA_8 (0x100UL << ADC_DR_Pos) /*!< 0x00000100 */ +#define ADC_DR_RDATA_9 (0x200UL << ADC_DR_Pos) /*!< 0x00000200 */ +#define ADC_DR_RDATA_10 (0x400UL << ADC_DR_Pos) /*!< 0x00000400 */ +#define ADC_DR_RDATA_11 (0x800UL << ADC_DR_Pos) /*!< 0x00000800 */ +#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_Pos) /*!< 0x00001000 */ +#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_Pos) /*!< 0x00002000 */ +#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_Pos) /*!< 0x00004000 */ +#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_Pos) /*!< 0x00008000 */ + + +/**************** Bit definition for ADC_JSQR register ****************/ +#define ADC_JSQR_Pos (0U) +#define ADC_JSQR_Msk (0xFFFFFFFFUL << ADC_JSQR_Pos) +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JL (0x3UL << ADC_JSQR_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JEXTSEL_0 (0x4UL << ADC_JSQR_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x8UL << ADC_JSQR_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x10UL << ADC_JSQR_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x20UL << ADC_JSQR_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x40UL << ADC_JSQR_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JEXTSEL (0x7C0UL << ADC_JSQR_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTEN_0 (0x80UL << ADC_JSQR_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x100UL << ADC_JSQR_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JEXTEN (0x180UL << ADC_JSQR_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JSQ1_0 (0x200UL << ADC_JSQR_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x400UL << ADC_JSQR_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x800UL << ADC_JSQR_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x1000UL << ADC_JSQR_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x2000UL << ADC_JSQR_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ2_0 (0x8000UL << ADC_JSQR_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x10000UL << ADC_JSQR_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x20000UL << ADC_JSQR_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x40000UL << ADC_JSQR_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x80000UL << ADC_JSQR_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JSQ3_0 (0x200000UL << ADC_JSQR_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x400000UL << ADC_JSQR_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x800000UL << ADC_JSQR_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x1000000UL << ADC_JSQR_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x2000000UL << ADC_JSQR_Pos) /*!< 0x02000000 */ +#define ADC_JSQR_JSQ4_0 (0x8000000UL << ADC_JSQR_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x10000000UL << ADC_JSQR_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x20000000UL << ADC_JSQR_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x40000000UL << ADC_JSQR_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x80000000UL << ADC_JSQR_Pos) /*!< 0x80000000 */ + + +/**************** Bit definition for ADC_OFR1 register ****************/ +#define ADC_OFR1_Pos (0U) +#define ADC_OFR1_Msk (0xFFFFFFFFUL << ADC_OFR1_Pos) +#define ADC_OFR1_OFFSET_0 (0x1UL << ADC_OFR1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET_1 (0x2UL << ADC_OFR1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET_2 (0x4UL << ADC_OFR1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET_3 (0x8UL << ADC_OFR1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET_4 (0x10UL << ADC_OFR1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET_5 (0x20UL << ADC_OFR1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET_6 (0x40UL << ADC_OFR1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET_7 (0x80UL << ADC_OFR1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET_8 (0x100UL << ADC_OFR1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET_9 (0x200UL << ADC_OFR1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET_10 (0x400UL << ADC_OFR1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET_11 (0x800UL << ADC_OFR1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET (0xFFFUL << ADC_OFR1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSETPOS (0x1000000UL << ADC_OFR1_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_SATEN (0x2000000UL << ADC_OFR1_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_OFFSET_CH_0 (0x4000000UL << ADC_OFR1_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET_CH_1 (0x8000000UL << ADC_OFR1_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET_CH_2 (0x10000000UL << ADC_OFR1_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET_CH_3 (0x20000000UL << ADC_OFR1_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET_CH_4 (0x40000000UL << ADC_OFR1_Pos) /*!< 0x40000000 */ +#define ADC_OFR1_OFFSET_EN (0x80000000UL << ADC_OFR1_Pos) /*!< 0x80000000 */ + + +/**************** Bit definition for ADC_OFR2 register ****************/ +#define ADC_OFR2_Pos (0U) +#define ADC_OFR2_Msk (0xFFFFFFFFUL << ADC_OFR2_Pos) +#define ADC_OFR2_OFFSET_0 (0x1UL << ADC_OFR2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET_1 (0x2UL << ADC_OFR2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET_2 (0x4UL << ADC_OFR2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET_3 (0x8UL << ADC_OFR2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET_4 (0x10UL << ADC_OFR2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET_5 (0x20UL << ADC_OFR2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET_6 (0x40UL << ADC_OFR2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET_7 (0x80UL << ADC_OFR2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET_8 (0x100UL << ADC_OFR2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET_9 (0x200UL << ADC_OFR2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET_10 (0x400UL << ADC_OFR2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET_11 (0x800UL << ADC_OFR2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET (0xFFFUL << ADC_OFR2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSETPOS (0x1000000UL << ADC_OFR2_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_SATEN (0x2000000UL << ADC_OFR2_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_OFFSET_CH_0 (0x4000000UL << ADC_OFR2_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET_CH_1 (0x8000000UL << ADC_OFR2_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET_CH_2 (0x10000000UL << ADC_OFR2_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET_CH_3 (0x20000000UL << ADC_OFR2_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET_CH_4 (0x40000000UL << ADC_OFR2_Pos) /*!< 0x40000000 */ +#define ADC_OFR2_OFFSET_EN (0x80000000UL << ADC_OFR2_Pos) /*!< 0x80000000 */ + + + +/**************** Bit definition for ADC_OFR3 register ****************/ +#define ADC_OFR3_Pos (0U) +#define ADC_OFR3_Msk (0xFFFFFFFFUL << ADC_OFR3_Pos) +#define ADC_OFR3_OFFSET_0 (0x1UL << ADC_OFR3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET_1 (0x2UL << ADC_OFR3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET_2 (0x4UL << ADC_OFR3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET_3 (0x8UL << ADC_OFR3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET_4 (0x10UL << ADC_OFR3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET_5 (0x20UL << ADC_OFR3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET_6 (0x40UL << ADC_OFR3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET_7 (0x80UL << ADC_OFR3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET_8 (0x100UL << ADC_OFR3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET_9 (0x200UL << ADC_OFR3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET_10 (0x400UL << ADC_OFR3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET_11 (0x800UL << ADC_OFR3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET (0xFFFUL << ADC_OFR3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSETPOS (0x1000000UL << ADC_OFR3_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_SATEN (0x2000000UL << ADC_OFR3_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_OFFSET_CH_0 (0x4000000UL << ADC_OFR3_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET_CH_1 (0x8000000UL << ADC_OFR3_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET_CH_2 (0x10000000UL << ADC_OFR3_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET_CH_3 (0x20000000UL << ADC_OFR3_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET_CH_4 (0x40000000UL << ADC_OFR3_Pos) /*!< 0x40000000 */ +#define ADC_OFR3_OFFSET_EN (0x80000000UL << ADC_OFR3_Pos) /*!< 0x80000000 */ + + +/**************** Bit definition for ADC_OFR4 register ****************/ +#define ADC_OFR4_Pos (0U) +#define ADC_OFR4_Msk (0xFFFFFFFFUL << ADC_OFR4_Pos) +#define ADC_OFR4_OFFSET_0 (0x1UL << ADC_OFR4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET_1 (0x2UL << ADC_OFR4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET_2 (0x4UL << ADC_OFR4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET_3 (0x8UL << ADC_OFR4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET_4 (0x10UL << ADC_OFR4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET_5 (0x20UL << ADC_OFR4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET_6 (0x40UL << ADC_OFR4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET_7 (0x80UL << ADC_OFR4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET_8 (0x100UL << ADC_OFR4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET_9 (0x200UL << ADC_OFR4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET_10 (0x400UL << ADC_OFR4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET_11 (0x800UL << ADC_OFR4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET (0xFFFUL << ADC_OFR4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSETPOS (0x1000000UL << ADC_OFR4_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_SATEN (0x2000000UL << ADC_OFR4_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_OFFSET_CH_0 (0x4000000UL << ADC_OFR4_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET_CH_1 (0x8000000UL << ADC_OFR4_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET_CH_2 (0x10000000UL << ADC_OFR4_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET_CH_3 (0x20000000UL << ADC_OFR4_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET_CH_4 (0x40000000UL << ADC_OFR4_Pos) /*!< 0x40000000 */ +#define ADC_OFR4_OFFSET_EN (0x80000000UL << ADC_OFR4_Pos) /*!< 0x80000000 */ + + +/**************** Bit definition for ADC_JDR1 register ****************/ +#define ADC_JDR1_Pos (0U) +#define ADC_JDR1_Msk (0xDFFFFFFFUL << ADC_JDR1_Pos) +#define ADC_JDR1_JDATA_0 (0x1UL << ADC_JDR1_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x2UL << ADC_JDR1_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x4UL << ADC_JDR1_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x8UL << ADC_JDR1_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x10UL << ADC_JDR1_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x20UL << ADC_JDR1_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x40UL << ADC_JDR1_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x80UL << ADC_JDR1_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x100UL << ADC_JDR1_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x200UL << ADC_JDR1_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x400UL << ADC_JDR1_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x800UL << ADC_JDR1_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_Pos) /*!< 0x00008000 */ + + +/**************** Bit definition for ADC_JDR2 register ****************/ +#define ADC_JDR2_Pos (0U) +#define ADC_JDR2_Msk (0xDFFFFFFFUL << ADC_JDR2_Pos) +#define ADC_JDR2_JDATA_0 (0x1UL << ADC_JDR2_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x2UL << ADC_JDR2_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x4UL << ADC_JDR2_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x8UL << ADC_JDR2_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x10UL << ADC_JDR2_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x20UL << ADC_JDR2_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x40UL << ADC_JDR2_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x80UL << ADC_JDR2_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x100UL << ADC_JDR2_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x200UL << ADC_JDR2_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x400UL << ADC_JDR2_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x800UL << ADC_JDR2_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_Pos) /*!< 0x00008000 */ + + +/**************** Bit definition for ADC_JDR2 register ****************/ +#define ADC_JDR3_Pos (0U) +#define ADC_JDR3_Msk (0xDFFFFFFFUL << ADC_JDR3_Pos) +#define ADC_JDR3_JDATA_0 (0x1UL << ADC_JDR3_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x2UL << ADC_JDR3_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x4UL << ADC_JDR3_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x8UL << ADC_JDR3_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x10UL << ADC_JDR3_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x20UL << ADC_JDR3_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x40UL << ADC_JDR3_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x80UL << ADC_JDR3_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x100UL << ADC_JDR3_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x200UL << ADC_JDR3_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x400UL << ADC_JDR3_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x800UL << ADC_JDR3_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_Pos) /*!< 0x00008000 */ + + +/**************** Bit definition for ADC_JDR4 register ****************/ +#define ADC_JDR4_Pos (0U) +#define ADC_JDR4_Msk (0xDFFFFFFFUL << ADC_JDR4_Pos) +#define ADC_JDR4_JDATA_0 (0x1UL << ADC_JDR4_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x2UL << ADC_JDR4_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x4UL << ADC_JDR4_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x8UL << ADC_JDR4_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x10UL << ADC_JDR4_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x20UL << ADC_JDR4_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x40UL << ADC_JDR4_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x80UL << ADC_JDR4_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x100UL << ADC_JDR4_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x200UL << ADC_JDR4_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x400UL << ADC_JDR4_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x800UL << ADC_JDR4_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_Pos) /*!< 0x00008000 */ + + +/**************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_Pos (0U) +#define ADC_AWD2CR_Msk (0xFFFFFFFFUL << ADC_AWD2CR_Pos) +#define ADC_AWD2CR_AWD2CH_0 (0x1UL << ADC_AWD2CR_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x2UL << ADC_AWD2CR_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x4UL << ADC_AWD2CR_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x8UL << ADC_AWD2CR_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x10UL << ADC_AWD2CR_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x20UL << ADC_AWD2CR_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x40UL << ADC_AWD2CR_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x80UL << ADC_AWD2CR_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x100UL << ADC_AWD2CR_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x200UL << ADC_AWD2CR_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x400UL << ADC_AWD2CR_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x800UL << ADC_AWD2CR_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x1000UL << ADC_AWD2CR_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x2000UL << ADC_AWD2CR_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x4000UL << ADC_AWD2CR_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x8000UL << ADC_AWD2CR_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_Pos) /*!< 0x00040000 */ + + +/**************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_Pos (0U) +#define ADC_AWD3CR_Msk (0xFFFFFFFFUL << ADC_AWD3CR_Pos) +#define ADC_AWD3CR_AWD3CH_0 (0x1UL << ADC_AWD3CR_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x2UL << ADC_AWD3CR_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x4UL << ADC_AWD3CR_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x8UL << ADC_AWD3CR_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x10UL << ADC_AWD3CR_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x20UL << ADC_AWD3CR_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x40UL << ADC_AWD3CR_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x80UL << ADC_AWD3CR_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x100UL << ADC_AWD3CR_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x200UL << ADC_AWD3CR_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x400UL << ADC_AWD3CR_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x800UL << ADC_AWD3CR_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x1000UL << ADC_AWD3CR_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x2000UL << ADC_AWD3CR_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x4000UL << ADC_AWD3CR_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x8000UL << ADC_AWD3CR_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_Pos) /*!< 0x00040000 */ + + +/**************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_Pos (0U) +#define ADC_DIFSEL_Msk (0xFFFFFFFFUL << ADC_DIFSEL_Pos) +#define ADC_DIFSEL_0 (0x1UL << ADC_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_1 (0x2UL << ADC_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_2 (0x4UL << ADC_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_3 (0x8UL << ADC_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_4 (0x10UL << ADC_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_5 (0x20UL << ADC_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_6 (0x40UL << ADC_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_7 (0x80UL << ADC_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_8 (0x100UL << ADC_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_9 (0x200UL << ADC_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_10 (0x400UL << ADC_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_11 (0x800UL << ADC_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_12 (0x1000UL << ADC_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_13 (0x2000UL << ADC_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_14 (0x4000UL << ADC_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_15 (0x8000UL << ADC_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_16 (0x10000UL << ADC_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_17 (0x20000UL << ADC_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_18 (0x40000UL << ADC_DIFSEL_Pos) /*!< 0x00040000 */ + + +/**************** Bit definition for ADC_CALFACT register ****************/ +#define ADC_CALFACT_Pos (0U) +#define ADC_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT_Pos) +#define ADC_CALFACT_S_0 (0x1UL << ADC_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_S_1 (0x2UL << ADC_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_S_2 (0x4UL << ADC_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_S_3 (0x8UL << ADC_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_S_4 (0x10UL << ADC_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_S_5 (0x20UL << ADC_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_S_6 (0x40UL << ADC_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_S (0x7FUL << ADC_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_D_0 (0x10000UL << ADC_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_D_1 (0x20000UL << ADC_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_D_2 (0x40000UL << ADC_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_D_3 (0x80000UL << ADC_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_D_4 (0x100000UL << ADC_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_D_5 (0x200000UL << ADC_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_D_6 (0x400000UL << ADC_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT_D (0x7F0000UL << ADC_CALFACT_Pos) /*!< 0x007F0000 */ + + +/**************** Bit definition for ADC_GCOMP register ****************/ +#define ADC_GCOMP_Pos (0U) +#define ADC_GCOMP_Msk (0xFFFFFFFFUL << ADC_GCOMP_Pos) +#define ADC_GCOMP_GCOMPCOEFF_0 (0x1UL << ADC_GCOMP_Pos) /*!< 0x00000001 */ +#define ADC_GCOMP_GCOMPCOEFF_1 (0x2UL << ADC_GCOMP_Pos) /*!< 0x00000002 */ +#define ADC_GCOMP_GCOMPCOEFF_2 (0x4UL << ADC_GCOMP_Pos) /*!< 0x00000004 */ +#define ADC_GCOMP_GCOMPCOEFF_3 (0x8UL << ADC_GCOMP_Pos) /*!< 0x00000008 */ +#define ADC_GCOMP_GCOMPCOEFF_4 (0x10UL << ADC_GCOMP_Pos) /*!< 0x00000010 */ +#define ADC_GCOMP_GCOMPCOEFF_5 (0x20UL << ADC_GCOMP_Pos) /*!< 0x00000020 */ +#define ADC_GCOMP_GCOMPCOEFF_6 (0x40UL << ADC_GCOMP_Pos) /*!< 0x00000040 */ +#define ADC_GCOMP_GCOMPCOEFF_7 (0x80UL << ADC_GCOMP_Pos) /*!< 0x00000080 */ +#define ADC_GCOMP_GCOMPCOEFF_8 (0x100UL << ADC_GCOMP_Pos) /*!< 0x00000100 */ +#define ADC_GCOMP_GCOMPCOEFF_9 (0x200UL << ADC_GCOMP_Pos) /*!< 0x00000200 */ +#define ADC_GCOMP_GCOMPCOEFF_10 (0x400UL << ADC_GCOMP_Pos) /*!< 0x00000400 */ +#define ADC_GCOMP_GCOMPCOEFF_11 (0x800UL << ADC_GCOMP_Pos) /*!< 0x00000800 */ +#define ADC_GCOMP_GCOMPCOEFF_12 (0x1000UL << ADC_GCOMP_Pos) /*!< 0x00001000 */ +#define ADC_GCOMP_GCOMPCOEFF_13 (0x2000UL << ADC_GCOMP_Pos) /*!< 0x00002000 */ +#define ADC_GCOMP_GCOMPCOEFF (0x3FFFUL << ADC_GCOMP_Pos) /*!< 0x00003FFF */ + + +/**************** Bit definition for ADC_Common_CSR1 register ****************/ +#define ADC_CSR1_Pos (0U) +#define ADC_CSR1_Msk (0xDFFFFFFFUL << ADC_CSR1_Pos) +#define ADC_CSR1_ADRDY1 (0x1UL << ADC_CSR1_Pos) /*!< 0x00000001 */ +#define ADC_CSR1_EOSMP1 (0x2UL << ADC_CSR1_Pos) /*!< 0x00000002 */ +#define ADC_CSR1_EOC1 (0x4UL << ADC_CSR1_Pos) /*!< 0x00000004 */ +#define ADC_CSR1_EOS1 (0x8UL << ADC_CSR1_Pos) /*!< 0x00000008 */ +#define ADC_CSR1_OVR1 (0x10UL << ADC_CSR1_Pos) /*!< 0x00000010 */ +#define ADC_CSR1_JEOC1 (0x20UL << ADC_CSR1_Pos) /*!< 0x00000020 */ +#define ADC_CSR1_JEOS1 (0x40UL << ADC_CSR1_Pos) /*!< 0x00000040 */ +#define ADC_CSR1_AWD11 (0x80UL << ADC_CSR1_Pos) /*!< 0x00000080 */ +#define ADC_CSR1_AWD21 (0x100UL << ADC_CSR1_Pos) /*!< 0x00000100 */ +#define ADC_CSR1_AWD31 (0x200UL << ADC_CSR1_Pos) /*!< 0x00000200 */ +#define ADC_CSR1_JQOVF1 (0x400UL << ADC_CSR1_Pos) /*!< 0x00000400 */ +#define ADC_CSR1_ADRDY2 (0x10000UL << ADC_CSR1_Pos) /*!< 0x00010000 */ +#define ADC_CSR1_EOSMP2 (0x20000UL << ADC_CSR1_Pos) /*!< 0x00020000 */ +#define ADC_CSR1_EOC2 (0x40000UL << ADC_CSR1_Pos) /*!< 0x00040000 */ +#define ADC_CSR1_EOS2 (0x80000UL << ADC_CSR1_Pos) /*!< 0x00080000 */ +#define ADC_CSR1_OVR2 (0x100000UL << ADC_CSR1_Pos) /*!< 0x00100000 */ +#define ADC_CSR1_JEOC2 (0x200000UL << ADC_CSR1_Pos) /*!< 0x00200000 */ +#define ADC_CSR1_JEOS2 (0x400000UL << ADC_CSR1_Pos) /*!< 0x00400000 */ +#define ADC_CSR1_AWD12 (0x800000UL << ADC_CSR1_Pos) /*!< 0x00800000 */ +#define ADC_CSR1_AWD22 (0x1000000UL << ADC_CSR1_Pos) /*!< 0x01000000 */ +#define ADC_CSR1_AWD32 (0x2000000UL << ADC_CSR1_Pos) /*!< 0x02000000 */ +#define ADC_CSR1_JQOVF2 (0x4000000UL << ADC_CSR1_Pos) /*!< 0x04000000 */ + + +/**************** Bit definition for ADC_Common_CSR2 register ****************/ +#define ADC_CSR2_Pos (0U) +#define ADC_CSR2_Msk (0xDFFFFFFFUL << ADC_CSR2_Pos) +#define ADC_CSR2_ADRDY3 (0x1UL << ADC_CSR2_Pos) /*!< 0x00000001 */ +#define ADC_CSR2_EOSMP3 (0x2UL << ADC_CSR2_Pos) /*!< 0x00000002 */ +#define ADC_CSR2_EOC3 (0x4UL << ADC_CSR2_Pos) /*!< 0x00000004 */ +#define ADC_CSR2_EOS3 (0x8UL << ADC_CSR2_Pos) /*!< 0x00000008 */ +#define ADC_CSR2_OVR3 (0x10UL << ADC_CSR2_Pos) /*!< 0x00000010 */ +#define ADC_CSR2_JEOC3 (0x20UL << ADC_CSR2_Pos) /*!< 0x00000020 */ +#define ADC_CSR2_JEOS3 (0x40UL << ADC_CSR2_Pos) /*!< 0x00000040 */ +#define ADC_CSR2_AWD13 (0x80UL << ADC_CSR2_Pos) /*!< 0x00000080 */ +#define ADC_CSR2_AWD23 (0x100UL << ADC_CSR2_Pos) /*!< 0x00000100 */ +#define ADC_CSR2_AWD33 (0x200UL << ADC_CSR2_Pos) /*!< 0x00000200 */ +#define ADC_CSR2_JQOVF3 (0x400UL << ADC_CSR2_Pos) /*!< 0x00000400 */ + + +/**************** Bit definition for ADC_Common_CCR register ****************/ +#define ADC_CCR_Pos (0U) +#define ADC_CCR_Msk (0xDFFFFFFFUL << ADC_CCR_Pos) +#define ADC_CCR_MULTI_0 (0x1UL << ADC_CCR_Pos) /*!< 0x00000001 */ +#define ADC_CCR_MULTI_1 (0x2UL << ADC_CCR_Pos) /*!< 0x00000002 */ +#define ADC_CCR_MULTI_2 (0x4UL << ADC_CCR_Pos) /*!< 0x00000004 */ +#define ADC_CCR_MULTI_3 (0x8UL << ADC_CCR_Pos) /*!< 0x00000008 */ +#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_Pos) /*!< 0x00000010 */ +#define ADC_CCR_MULTI (0x1FUL << ADC_CCR_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DELAY_0 (0x100UL << ADC_CCR_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x200UL << ADC_CCR_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x400UL << ADC_CCR_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x800UL << ADC_CCR_Pos) /*!< 0x00000800 */ +#define ADC_CCR_DELAY (0xF00UL << ADC_CCR_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DMACFG (0x2000UL << ADC_CCR_Pos) /*!< 0x00002000 */ +#define ADC_CCR_MDMA_0 (0x4000UL << ADC_CCR_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x8000UL << ADC_CCR_Pos) /*!< 0x00008000 */ +#define ADC_CCR_MDMA (0xC000UL << ADC_CCR_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_CKMODE_0 (0x10000UL << ADC_CCR_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x20000UL << ADC_CCR_Pos) /*!< 0x00020000 */ +#define ADC_CCR_CKMODE (0x30000UL << ADC_CCR_Pos) /*!< 0x00030000 */ +#define ADC_CCR_PRESC_0 (0x40000UL << ADC_CCR_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x80000UL << ADC_CCR_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x100000UL << ADC_CCR_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x200000UL << ADC_CCR_Pos) /*!< 0x00200000 */ +#define ADC_CCR_PRESC (0x3C0000UL << ADC_CCR_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_VREFEN (0x400000UL << ADC_CCR_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VSENSESEL (0x800000UL << ADC_CCR_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VBATSEL (0x1000000UL << ADC_CCR_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBEAUTO (0x2000000UL << ADC_CCR_Pos) /*!< 0x02000000 */ +#define ADC_CCR_AWDSEL (0x4000000UL << ADC_CCR_Pos) /*!< 0x04000000 */ + + +/**************** Bit definition for ADC_Common_CDR register ****************/ +#define ADC_CDR_Pos (0U) +#define ADC_CDR_Msk (0xDFFFFFFFUL << ADC_CDR_Pos) +#define ADC_CDR_DATA1_0 (0x1UL << ADC_CDR_Pos) /*!< 0x00000001 */ +#define ADC_CDR_DATA1_1 (0x2UL << ADC_CDR_Pos) /*!< 0x00000002 */ +#define ADC_CDR_DATA1_2 (0x4UL << ADC_CDR_Pos) /*!< 0x00000004 */ +#define ADC_CDR_DATA1_3 (0x8UL << ADC_CDR_Pos) /*!< 0x00000008 */ +#define ADC_CDR_DATA1_4 (0x10UL << ADC_CDR_Pos) /*!< 0x00000010 */ +#define ADC_CDR_DATA1_5 (0x20UL << ADC_CDR_Pos) /*!< 0x00000020 */ +#define ADC_CDR_DATA1_6 (0x40UL << ADC_CDR_Pos) /*!< 0x00000040 */ +#define ADC_CDR_DATA1_7 (0x80UL << ADC_CDR_Pos) /*!< 0x00000080 */ +#define ADC_CDR_DATA1_8 (0x100UL << ADC_CDR_Pos) /*!< 0x00000100 */ +#define ADC_CDR_DATA1_9 (0x200UL << ADC_CDR_Pos) /*!< 0x00000200 */ +#define ADC_CDR_DATA1_10 (0x400UL << ADC_CDR_Pos) /*!< 0x00000400 */ +#define ADC_CDR_DATA1_11 (0x800UL << ADC_CDR_Pos) /*!< 0x00000800 */ +#define ADC_CDR_DATA1_12 (0x1000UL << ADC_CDR_Pos) /*!< 0x00001000 */ +#define ADC_CDR_DATA1_13 (0x2000UL << ADC_CDR_Pos) /*!< 0x00002000 */ +#define ADC_CDR_DATA1_14 (0x4000UL << ADC_CDR_Pos) /*!< 0x00004000 */ +#define ADC_CDR_DATA1_15 (0x8000UL << ADC_CDR_Pos) /*!< 0x00008000 */ +#define ADC_CDR_DATA2_0 (0x10000UL << ADC_CDR_Pos) /*!< 0x00010000 */ +#define ADC_CDR_DATA2_1 (0x20000UL << ADC_CDR_Pos) /*!< 0x00020000 */ +#define ADC_CDR_DATA2_2 (0x40000UL << ADC_CDR_Pos) /*!< 0x00040000 */ +#define ADC_CDR_DATA2_3 (0x80000UL << ADC_CDR_Pos) /*!< 0x00080000 */ +#define ADC_CDR_DATA2_4 (0x100000UL << ADC_CDR_Pos) /*!< 0x00100000 */ +#define ADC_CDR_DATA2_5 (0x200000UL << ADC_CDR_Pos) /*!< 0x00200000 */ +#define ADC_CDR_DATA2_6 (0x400000UL << ADC_CDR_Pos) /*!< 0x00400000 */ +#define ADC_CDR_DATA2_7 (0x800000UL << ADC_CDR_Pos) /*!< 0x00800000 */ +#define ADC_CDR_DATA2_8 (0x1000000UL << ADC_CDR_Pos) /*!< 0x01000000 */ +#define ADC_CDR_DATA2_9 (0x2000000UL << ADC_CDR_Pos) /*!< 0x02000000 */ +#define ADC_CDR_DATA2_10 (0x4000000UL << ADC_CDR_Pos) /*!< 0x04000000 */ +#define ADC_CDR_DATA2_11 (0x8000000UL << ADC_CDR_Pos) /*!< 0x08000000 */ +#define ADC_CDR_DATA2_12 (0x10000000UL << ADC_CDR_Pos) /*!< 0x10000000 */ +#define ADC_CDR_DATA2_13 (0x20000000UL << ADC_CDR_Pos) /*!< 0x20000000 */ +#define ADC_CDR_DATA2_14 (0x40000000UL << ADC_CDR_Pos) /*!< 0x40000000 */ +#define ADC_CDR_DATA2_15 (0x80000000UL << ADC_CDR_Pos) /*!< 0x80000000 */ + + + +/******************************************************************************/ +/* */ +/* I2S */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for I2S_CTRL register ***************************/ +#define I2S_CTRL_I2SEN0_Pos 0 +#define I2S_CTRL_I2SEN0_Msk (0x1UL << I2S_CTRL_I2SEN0_Pos) /*!< 0x00000001 */ +#define I2S_CTRL_I2SEN0 I2S_CTRL_I2SEN0_Msk /*!< Enable bit for I2S channel 0 */ + +#define I2S_CTRL_I2SEN1_Pos 1 +#define I2S_CTRL_I2SEN1_Msk (0x1UL << I2S_CTRL_I2SEN1_Pos) /*!< 0x00000002 */ +#define I2S_CTRL_I2SEN1 I2S_CTRL_I2SEN1_Msk /*!< Enable bit for I2S channel 1 */ + +#define I2S_CTRL_TRCFG0_Pos 8 +#define I2S_CTRL_TRCFG0_Msk (0x1UL << I2S_CTRL_TRCFG0_Pos) /*!< 0x00000100 */ +#define I2S_CTRL_TRCFG0 I2S_CTRL_TRCFG0_Msk /*!< Transmitter or recevier for I2S channel 0 */ + +#define I2S_CTRL_TRCFG1_Pos 9 +#define I2S_CTRL_TRCFG1_Msk (0x1UL << I2S_CTRL_TRCFG1_Pos) /*!< 0x00000100 */ +#define I2S_CTRL_TRCFG1 I2S_CTRL_TRCFG1_Msk /*!< Transmitter or recevier for I2S channel 1 */ + +#define I2S_CTRL_LOOPBACK01_Pos 16 +#define I2S_CTRL_LOOPBACK01_Msk (0x1UL << I2S_CTRL_LOOPBACK01_Pos) /*!< 0x00010000 */ +#define I2S_CTRL_LOOPBACK01 I2S_CTRL_LOOPBACK01_Msk /*!< Loop-back test configuration for I2S channel 0/1*/ + +#define I2S_CTRL_SFRRST_Pos 20 +#define I2S_CTRL_SFRRST_Msk (0x1UL << I2S_CTRL_SFRRST_Pos) /*!< 0x00100000 */ +#define I2S_CTRL_SFRRST I2S_CTRL_SFRRST_Msk /*!< SFR block synchronour reset */ + +#define I2S_CTRL_TMS_Pos 21 +#define I2S_CTRL_TMS_Msk (0x1UL << I2S_CTRL_TMS_Pos) /*!< 0x00200000 */ +#define I2S_CTRL_TMS I2S_CTRL_TMS_Msk /*!< Master or slave configuration for transmitter */ + +#define I2S_CTRL_RMS_Pos 22 +#define I2S_CTRL_RMS_Msk (0x1UL << I2S_CTRL_RMS_Pos) /*!< 0x00400000 */ +#define I2S_CTRL_RMS I2S_CTRL_RMS_Msk /*!< Master or slave configuration for receiver */ + +#define I2S_CTRL_TFIFORST_Pos 23 +#define I2S_CTRL_TFIFORST_Msk (0x1UL << I2S_CTRL_TFIFORST_Pos) /*!< 0x00800000 */ +#define I2S_CTRL_TFIFORST I2S_CTRL_TFIFORST_Msk /*!< Transmait fifo reset */ + +#define I2S_CTRL_RFIFORST_Pos 24 +#define I2S_CTRL_RFIFORST_Msk (0x1UL << I2S_CTRL_RFIFORST_Pos) /*!< 0x01000000 */ +#define I2S_CTRL_RFIFORST I2S_CTRL_RFIFORST_Msk /*!< Receive fifo reset */ + +#define I2S_CTRL_TSYNCRST_Pos 25 +#define I2S_CTRL_TSYNCRST_Msk (0x1UL << I2S_CTRL_TSYNCRST_Pos) /*!< 0x02000000 */ +#define I2S_CTRL_TSYNCRST I2S_CTRL_TSYNCRST_Msk /*!< Reset for transmitter synchronizing unit */ + +#define I2S_CTRL_RSYNCRST_Pos 26 +#define I2S_CTRL_RSYNCRST_Msk (0x1UL << I2S_CTRL_RSYNCRST_Pos) /*!< 0x04000000 */ +#define I2S_CTRL_RSYNCRST I2S_CTRL_RSYNCRST_Msk /*!< Reset for receiver synchronizing unit */ + +#define I2S_CTRL_TSYNCLOOPBACK_Pos 27 +#define I2S_CTRL_TSYNCLOOPBACK_Msk (0x1UL << I2S_CTRL_TSYNCLOOPBACK_Pos) /*!< 0x08000000 */ +#define I2S_CTRL_TSYNCLOOPBACK I2S_CTRL_TSYNCLOOPBACK_Msk /*!< Loop-back configuration for transmitter synchronization unit */ + +#define I2S_CTRL_RSYNCLOOPBACK_Pos 28 +#define I2S_CTRL_RSYNCLOOPBACK_Msk (0x1UL << I2S_CTRL_RSYNCLOOPBACK_Pos) /*!< 0x10000000 */ +#define I2S_CTRL_RSYNCLOOPBACK I2S_CTRL_RSYNCLOOPBACK_Msk /*!< Loop-back configuration for receiver synchronization unit */ + +/****************** Bit definition for INTR_STAT register **************************/ +#define I2S_INTR_STAT_TDATAUNDERR_Pos 0 +#define I2S_INTR_STAT_TDATAUNDERR_Msk (0x1UL << I2S_INTR_STAT_TDATAUNDERR_Pos) /*!< 0x00000001 */ +#define I2S_INTR_STAT_TDATAUNDERR I2S_INTR_STAT_TDATAUNDERR_Msk /*!< Transmitter data underrun event */ + +#define I2S_INTR_STAT_UNDERRCODE_Pos 1 +#define I2S_INTR_STAT_UNDERRCODE_Msk (0x1UL << I2S_INTR_STAT_UNDERRCODE_Pos) /*!< 0x00000002 */ +#define I2S_INTR_STAT_UNDERRCODE I2S_INTR_STAT_UNDERRCODE_Msk /*!< Code of the transmitter that caused underrun event */ + +#define I2S_INTR_STAT_RDATAOVRERR_Pos 4 +#define I2S_INTR_STAT_RDATAOVRERR_Msk (0x1UL << I2S_INTR_STAT_RDATAOVRERR_Pos) /*!< 0x00000010 */ +#define I2S_INTR_STAT_RDATAOVRERR I2S_INTR_STAT_RDATAOVRERR_Msk /*!< Receiver data overrun error */ + +#define I2S_INTR_STAT_OVRERRCODE_Pos 5 +#define I2S_INTR_STAT_OVRERRCODE_Msk (0x1UL << I2S_INTR_STAT_OVRERRCODE_Pos) /*!< 0x00000020 */ +#define I2S_INTR_STAT_OVRERRCODE I2S_INTR_STAT_OVRERRCODE_Msk /*!< Code of the receiver that caused overrun error */ + +#define I2S_INTR_STAT_TFIFOEMPTY_Pos 8 +#define I2S_INTR_STAT_TFIFOEMPTY_Msk (0x1UL << I2S_INTR_STAT_TFIFOEMPTY_Pos) /*!< 0x00000100 */ +#define I2S_INTR_STAT_TFIFOEMPTY I2S_INTR_STAT_TFIFOEMPTY_Msk /*!< Transmit fifo empty flag */ + +#define I2S_INTR_STAT_TFIFOAEMPTY_Pos 9 +#define I2S_INTR_STAT_TFIFOAEMPTY_Msk (0x1UL << I2S_INTR_STAT_TFIFOAEMPTY_Pos) /*!< 0x00000200 */ +#define I2S_INTR_STAT_TFIFOAEMPTY I2S_INTR_STAT_TFIFOAEMPTY_Msk /*!< Transmit fifo almost empty flag */ + +#define I2S_INTR_STAT_TFIFOFULL_Pos 10 +#define I2S_INTR_STAT_TFIFOFULL_Msk (0x1UL << I2S_INTR_STAT_TFIFOFULL_Pos) /*!< 0x00000400 */ +#define I2S_INTR_STAT_TFIFOFULL I2S_INTR_STAT_TFIFOFULL_Msk /*!< Transmit fifo full flag */ + +#define I2S_INTR_STAT_TFIFOAFULL_Pos 11 +#define I2S_INTR_STAT_TFIFOAFULL_Msk (0x1UL << I2S_INTR_STAT_TFIFOAFULL_Pos) /*!< 0x00000800 */ +#define I2S_INTR_STAT_TFIFOAFULL I2S_INTR_STAT_TFIFOAFULL_Msk /*!< Transmit fifo almost full flag */ + +#define I2S_INTR_STAT_RFIFOEMPTY_Pos 12 +#define I2S_INTR_STAT_RFIFOEMPTY_Msk (0x1UL << I2S_INTR_STAT_RFIFOEMPTY_Pos) /*!< 0x00001000 */ +#define I2S_INTR_STAT_RFIFOEMPTY I2S_INTR_STAT_RFIFOEMPTY_Msk /*!< Receive fifo empty flag */ + +#define I2S_INTR_STAT_RFIFOAEMPTY_Pos 13 +#define I2S_INTR_STAT_RFIFOAEMPTY_Msk (0x1UL << I2S_INTR_STAT_RFIFOAEMPTY_Pos) /*!< 0x00002000 */ +#define I2S_INTR_STAT_RFIFOAEMPTY I2S_INTR_STAT_RFIFOAEMPTY_Msk /*!< Receive fifo almost empty flag */ + +#define I2S_INTR_STAT_RFIFOFULL_Pos 14 +#define I2S_INTR_STAT_RFIFOFULL_Msk (0x1UL << I2S_INTR_STAT_RFIFOFULL_Pos) /*!< 0x00004000 */ +#define I2S_INTR_STAT_RFIFOFULL I2S_INTR_STAT_RFIFOFULL_Msk /*!< Receive fifo full flag */ + +#define I2S_INTR_STAT_RFIFOAFULL_Pos 15 +#define I2S_INTR_STAT_RFIFOAFULL_Msk (0x1UL << I2S_INTR_STAT_RFIFOAFULL_Pos) /*!< 0x00008000 */ +#define I2S_INTR_STAT_RFIFOAFULL I2S_INTR_STAT_RFIFOAFULL_Msk /*!< Receive fifo almost full flag */ + +/****************** Bit definition for SRR register ********************************/ +#define I2S_SRR_TSAMPLERATE_Pos 0 +#define I2S_SRR_TSAMPLERATE_Msk (0x7FFUL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x000007FF */ +#define I2S_SRR_TSAMPLERATE I2S_SRR_TSAMPLERATE_Msk /*!< Transmitter sample rate */ +#define I2S_SRR_TSAMPLERATE_0 (0x1UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000001 */ +#define I2S_SRR_TSAMPLERATE_1 (0x2UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000002 */ +#define I2S_SRR_TSAMPLERATE_2 (0x4UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000004 */ +#define I2S_SRR_TSAMPLERATE_3 (0x8UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000008 */ +#define I2S_SRR_TSAMPLERATE_4 (0x10UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000010 */ +#define I2S_SRR_TSAMPLERATE_5 (0x20UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000020 */ +#define I2S_SRR_TSAMPLERATE_6 (0x40UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000040 */ +#define I2S_SRR_TSAMPLERATE_7 (0x80UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000080 */ +#define I2S_SRR_TSAMPLERATE_8 (0x100UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000100 */ +#define I2S_SRR_TSAMPLERATE_9 (0x200UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000200 */ +#define I2S_SRR_TSAMPLERATE_10 (0x400UL << I2S_SRR_TSAMPLERATE_Pos) /*!< 0x00000400 */ + +#define I2S_SRR_TRESOLUTION_Pos 11 +#define I2S_SRR_TRESOLUTION_Msk (0x1FUL << I2S_SRR_TRESOLUTION_Pos) /*!< 0x0000001F */ +#define I2S_SRR_TRESOLUTION I2S_SRR_TRESOLUTION_Msk /*!< Transmitter sample resolution */ +#define I2S_SRR_TRESOLUTION_0 (0x1UL << I2S_SRR_TRESOLUTION_Pos) /*!< 0x00000800 */ +#define I2S_SRR_TRESOLUTION_1 (0x2UL << I2S_SRR_TRESOLUTION_Pos) /*!< 0x00001000 */ +#define I2S_SRR_TRESOLUTION_2 (0x4UL << I2S_SRR_TRESOLUTION_Pos) /*!< 0x00002000 */ +#define I2S_SRR_TRESOLUTION_3 (0x8UL << I2S_SRR_TRESOLUTION_Pos) /*!< 0x00004000 */ +#define I2S_SRR_TRESOLUTION_4 (0x10UL << I2S_SRR_TRESOLUTION_Pos) /*!< 0x00008000 */ + +#define I2S_SRR_RSAMPLERATE_Pos 16 +#define I2S_SRR_RSAMPLERATE_Msk (0x7FFUL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x07FF0000 */ +#define I2S_SRR_RSAMPLERATE I2S_SRR_RSAMPLERATE_Msk /*!< Transmitter sample rate */ +#define I2S_SRR_RSAMPLERATE_0 (0x1UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00010000 */ +#define I2S_SRR_RSAMPLERATE_1 (0x2UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00020000 */ +#define I2S_SRR_RSAMPLERATE_2 (0x4UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00040000 */ +#define I2S_SRR_RSAMPLERATE_3 (0x8UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00080000 */ +#define I2S_SRR_RSAMPLERATE_4 (0x10UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00100000 */ +#define I2S_SRR_RSAMPLERATE_5 (0x20UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00200000 */ +#define I2S_SRR_RSAMPLERATE_6 (0x40UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00400000 */ +#define I2S_SRR_RSAMPLERATE_7 (0x80UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x00800000 */ +#define I2S_SRR_RSAMPLERATE_8 (0x100UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x01000000 */ +#define I2S_SRR_RSAMPLERATE_9 (0x200UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x02000000 */ +#define I2S_SRR_RSAMPLERATE_10 (0x400UL << I2S_SRR_RSAMPLERATE_Pos) /*!< 0x04000000 */ + +#define I2S_SRR_RRESOLUTION_Pos 27 +#define I2S_SRR_RRESOLUTION_Msk (0x1FUL << I2S_SRR_RRESOLUTION_Pos) /*!< 0x0000001F */ +#define I2S_SRR_RRESOLUTION I2S_SRR_RRESOLUTION_Msk /*!< Transmitter sample resolution */ +#define I2S_SRR_RRESOLUTION_0 (0x1UL << I2S_SRR_RRESOLUTION_Pos) /*!< 0x08000000 */ +#define I2S_SRR_RRESOLUTION_1 (0x2UL << I2S_SRR_RRESOLUTION_Pos) /*!< 0x01000000 */ +#define I2S_SRR_RRESOLUTION_2 (0x4UL << I2S_SRR_RRESOLUTION_Pos) /*!< 0x02000000 */ +#define I2S_SRR_RRESOLUTION_3 (0x8UL << I2S_SRR_RRESOLUTION_Pos) /*!< 0x04000000 */ +#define I2S_SRR_RRESOLUTION_4 (0x10UL << I2S_SRR_RRESOLUTION_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for CID_CTRL register ***************************/ +#define I2S_CID_CTRL_I2SSTROBE0_Pos 0 +#define I2S_CID_CTRL_I2SSTROBE0_Msk (0x1UL << I2S_CID_CTRL_I2SSTROBE0_Pos) /*!< 0x00000001 */ +#define I2S_CID_CTRL_I2SSTROBE0 I2S_CID_CTRL_I2SSTROBE0_Msk /*!< Clock enable, channel 0 */ + +#define I2S_CID_CTRL_I2SSTROBE1_Pos 1 +#define I2S_CID_CTRL_I2SSTROBE1_Msk (0x1UL << I2S_CID_CTRL_I2SSTROBE1_Pos) /*!< 0x00000002 */ +#define I2S_CID_CTRL_I2SSTROBE1 I2S_CID_CTRL_I2SSTROBE1_Msk /*!< Clock enable, channel 1 */ + +#define I2S_CID_CTRL_STROBETS_Pos 8 +#define I2S_CID_CTRL_STROBETS_Msk (0x1UL << I2S_CID_CTRL_STROBETS_Pos) /*!< 0x00000100 */ +#define I2S_CID_CTRL_STROBETS I2S_CID_CTRL_STROBETS_Msk /*!< Clock enable for the unit synchronizing transmitters */ + +#define I2S_CID_CTRL_STROBERS_Pos 9 +#define I2S_CID_CTRL_STROBERS_Msk (0x1UL << I2S_CID_CTRL_STROBERS_Pos) /*!< 0x00000200 */ +#define I2S_CID_CTRL_STROBERS I2S_CID_CTRL_STROBERS_Msk /*!< Clock enable for the unit synchronizing receivers */ + +#define I2S_CID_CTRL_INTREQMASK_Pos 15 +#define I2S_CID_CTRL_INTREQMASK_Msk (0x1UL << I2S_CID_CTRL_INTREQMASK_Pos) /*!< 0x00008000 */ +#define I2S_CID_CTRL_INTREQMASK I2S_CID_CTRL_INTREQMASK_Msk /*!< Bit masking all interrupt requests */ + +#define I2S_CID_CTRL_I2SMASK0_Pos 16 +#define I2S_CID_CTRL_I2SMASK0_Msk (0x1UL << I2S_CID_CTRL_I2SMASK0_Pos) /*!< 0x00010000 */ +#define I2S_CID_CTRL_I2SMASK0 I2S_CID_CTRL_I2SMASK0_Msk /*!< Bit masking interrupt request genaration after underrun/overrun in I2S channle 0 */ + +#define I2S_CID_CTRL_I2SMASK1_Pos 17 +#define I2S_CID_CTRL_I2SMASK1_Msk (0x1UL << I2S_CID_CTRL_I2SMASK1_Pos) /*!< 0x00020000 */ +#define I2S_CID_CTRL_I2SMASK1 I2S_CID_CTRL_I2SMASK1_Msk /*!< Bit masking interrupt request genaration after underrun/overrun in I2S channle 1 */ + +#define I2S_CID_CTRL_TFIFOEMPTYMASK_Pos 24 +#define I2S_CID_CTRL_TFIFOEMPTYMASK_Msk (0x1UL << I2S_CID_CTRL_TFIFOEMPTYMASK_Pos) /*!< 0x01000000 */ +#define I2S_CID_CTRL_TFIFOEMPTYMASK I2S_CID_CTRL_TFIFOEMPTYMASK_Msk /*!< Bit masking interrupt request genaration after transmit fifo empty */ + +#define I2S_CID_CTRL_TFIFOAEMPTYMASK_Pos 25 +#define I2S_CID_CTRL_TFIFOAEMPTYMASK_Msk (0x1L << I2S_CID_CTRL_TFIFOAEMPTYMASK_Pos) /*!< 0x02000000 */ +#define I2S_CID_CTRL_TFIFOAEMPTYMASK I2S_CID_CTRL_TFIFOAEMPTYMASK_Msk /*!< Bit masking interrupt request genaration after transmit fifo almost empty */ + +#define I2S_CID_CTRL_TFIFOFULLMASK_Pos 26 +#define I2S_CID_CTRL_TFIFOFULLMASK_Msk (0x1UL << I2S_CID_CTRL_TFIFOFULLMASK_Pos) /*!< 0x04000000 */ +#define I2S_CID_CTRL_TFIFOFULLMASK I2S_CID_CTRL_TFIFOFULLMASK_Msk /*!< Bit masking interrupt request genaration after transmit fifo full */ + +#define I2S_CID_CTRL_TFIFOAFULLMASK_Pos 27 +#define I2S_CID_CTRL_TFIFOAFULLMASK_Msk (0x1UL << I2S_CID_CTRL_TFIFOAFULLMASK_Pos) /*!< 0x08000000 */ +#define I2S_CID_CTRL_TFIFOAFULLMASK I2S_CID_CTRL_TFIFOAFULLMASK_Msk /*!< Bit masking interrupt request genaration after transmit fifo almost full */ + +#define I2S_CID_CTRL_RFIFOEMPTYMASK_Pos 28 +#define I2S_CID_CTRL_RFIFOEMPTYMASK_Msk (0x1UL << I2S_CID_CTRL_RFIFOEMPTYMASK_Pos) /*!< 0x10000000 */ +#define I2S_CID_CTRL_RFIFOEMPTYMASK I2S_CID_CTRL_RFIFOEMPTYMASK_Msk /*!< Bit masking interrupt request genaration after receive fifo empty */ + +#define I2S_CID_CTRL_RFIFOAEMPTYMASK_Pos 29 +#define I2S_CID_CTRL_RFIFOAEMPTYMASK_Msk (0x1UL << I2S_CID_CTRL_RFIFOAEMPTYMASK_Pos) /*!< 0x20000000 */ +#define I2S_CID_CTRL_RFIFOAEMPTYMASK I2S_CID_CTRL_RFIFOAEMPTYMASK_Msk /*!< Bit masking interrupt request genaration after receive fifo almost empty */ + +#define I2S_CID_CTRL_RFIFOFULLMASK_Pos 30 +#define I2S_CID_CTRL_RFIFOFULLMASK_Msk (0x1UL << I2S_CID_CTRL_RFIFOFULLMASK_Pos) /*!< 0x40000000 */ +#define I2S_CID_CTRL_RFIFOFULLMASK I2S_CID_CTRL_RFIFOFULLMASK_Msk /*!< Bit masking interrupt request genaration after receive fifo full */ + +#define I2S_CID_CTRL_RFIFOAFULLMASK_Pos 31 +#define I2S_CID_CTRL_RFIFOAFULLMASK_Msk (0x1UL << I2S_CID_CTRL_RFIFOAFULLMASK_Pos) /*!< 0x80000000 */ +#define I2S_CID_CTRL_RFIFOAFULLMASK I2S_CID_CTRL_RFIFOAFULLMASK_Msk /*!< Bit masking interrupt request genaration after receive fifo almost full */ + +/****************** Bit definition for TFIFO_STAT register *************************/ +#define I2S_TFIFO_STAT_TLEVEL_Pos 0 +#define I2S_TFIFO_STAT_TLEVEL_Msk (0xFUL << I2S_TFIFO_STAT_TLEVEL_Pos) /*!< 0x0000000F */ +#define I2S_TFIFO_STAT_TLEVEL I2S_TFIFO_STAT_TLEVEL_Msk /*!< Transmit fifo level */ +#define I2S_TFIFO_STAT_TLEVEL_0 (0x1UL << I2S_TFIFO_STAT_TLEVEL_Pos) /*!< 0x00000001 */ +#define I2S_TFIFO_STAT_TLEVEL_1 (0x2UL << I2S_TFIFO_STAT_TLEVEL_Pos) /*!< 0x00000002 */ +#define I2S_TFIFO_STAT_TLEVEL_2 (0x4UL << I2S_TFIFO_STAT_TLEVEL_Pos) /*!< 0x00000004 */ +#define I2S_TFIFO_STAT_TLEVEL_3 (0x8UL << I2S_TFIFO_STAT_TLEVEL_Pos) /*!< 0x00000008 */ + +/****************** Bit definition for RFIFO_STAT register *************************/ +#define I2S_RFIFO_STAT_RLEVEL_Pos 0 +#define I2S_RFIFO_STAT_RLEVEL_Msk (0xFUL << I2S_RFIFO_STAT_RLEVEL_Pos) /*!< 0x0000000F */ +#define I2S_RFIFO_STAT_RLEVEL I2S_RFIFO_STAT_RLEVEL_Msk /*!< Receive fifo level */ +#define I2S_RFIFO_STAT_RLEVEL_0 (0x1UL << I2S_RFIFO_STAT_RLEVEL_Pos) /*!< 0x00000001 */ +#define I2S_RFIFO_STAT_RLEVEL_1 (0x2UL << I2S_RFIFO_STAT_RLEVEL_Pos) /*!< 0x00000002 */ +#define I2S_RFIFO_STAT_RLEVEL_2 (0x4UL << I2S_RFIFO_STAT_RLEVEL_Pos) /*!< 0x00000004 */ +#define I2S_RFIFO_STAT_RLEVEL_3 (0x8UL << I2S_RFIFO_STAT_RLEVEL_Pos) /*!< 0x00000008 */ + +/****************** Bit definition for TFIFO_CTRL register *************************/ +#define I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_Pos 0 +#define I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_Msk (0x7UL << I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_Pos) /*!< 0x00000007 */ +#define I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_Msk /*!< Transmit fifo almost empty threshold level */ +#define I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_0 (0x1UL << I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_Pos) /*!< 0x00000001 */ +#define I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_1 (0x2UL << I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_Pos) /*!< 0x00000002 */ +#define I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_2 (0x4UL << I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD_Pos) /*!< 0x00000004 */ + +#define I2S_TFIFO_CTRL_TAFULLTHRESHOLD_Pos 16 +#define I2S_TFIFO_CTRL_TAFULLTHRESHOLD_Msk (0x7UL << I2S_TFIFO_CTRL_TAFULLTHRESHOLD_Pos) /*!< 0x00070000 */ +#define I2S_TFIFO_CTRL_TAFULLTHRESHOLD I2S_TFIFO_CTRL_TAFULLTHRESHOLD_Msk /*!< Transmit fifo almost full threshold level */ +#define I2S_TFIFO_CTRL_TAFULLTHRESHOLD_0 (0x1UL << I2S_TFIFO_CTRL_TAFULLTHRESHOLD_Pos) /*!< 0x00010000 */ +#define I2S_TFIFO_CTRL_TAFULLTHRESHOLD_1 (0x2UL << I2S_TFIFO_CTRL_TAFULLTHRESHOLD_Pos) /*!< 0x00020000 */ +#define I2S_TFIFO_CTRL_TAFULLTHRESHOLD_2 (0x4UL << I2S_TFIFO_CTRL_TAFULLTHRESHOLD_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for RFIFO_CTRL register *************************/ +#define I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_Pos 0 +#define I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_Msk (0x7UL << I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_Pos) /*!< 0x00000007 */ +#define I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_Msk /*!< Transmit fifo almost empty threshold level */ +#define I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_0 (0x1UL << I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_Pos) /*!< 0x00000001 */ +#define I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_1 (0x2UL << I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_Pos) /*!< 0x00000002 */ +#define I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_2 (0x4UL << I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD_Pos) /*!< 0x00000004 */ + +#define I2S_RFIFO_CTRL_RAFULLTHRESHOLD_Pos 16 +#define I2S_RFIFO_CTRL_RAFULLTHRESHOLD_Msk (0x7UL << I2S_RFIFO_CTRL_RAFULLTHRESHOLD_Pos) /*!< 0x00070000 */ +#define I2S_RFIFO_CTRL_RAFULLTHRESHOLD I2S_RFIFO_CTRL_RAFULLTHRESHOLD_Msk /*!< Transmit fifo almost full threshold level */ +#define I2S_RFIFO_CTRL_RAFULLTHRESHOLD_0 (0x1UL << I2S_RFIFO_CTRL_RAFULLTHRESHOLD_Pos) /*!< 0x00010000 */ +#define I2S_RFIFO_CTRL_RAFULLTHRESHOLD_1 (0x2UL << I2S_RFIFO_CTRL_RAFULLTHRESHOLD_Pos) /*!< 0x00020000 */ +#define I2S_RFIFO_CTRL_RAFULLTHRESHOLD_2 (0x4UL << I2S_RFIFO_CTRL_RAFULLTHRESHOLD_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for DEV_CONF register ***************************/ +#define I2S_DEV_CONF_TRANSCKPOLAR_Pos 0 +#define I2S_DEV_CONF_TRANSCKPOLAR_Msk (0x1UL << I2S_DEV_CONF_TRANSCKPOLAR_Pos) /*!< 0x00000001 */ +#define I2S_DEV_CONF_TRANSCKPOLAR I2S_DEV_CONF_TRANSCKPOLAR_Msk /*!< Continuous serial clock active edge for transmission */ + +#define I2S_DEV_CONF_TRANWSPOLAR_Pos 1 +#define I2S_DEV_CONF_TRANWSPOLAR_Msk (0x1UL << I2S_DEV_CONF_TRANWSPOLAR_Pos) /*!< 0x00000002 */ +#define I2S_DEV_CONF_TRANWSPOLAR I2S_DEV_CONF_TRANWSPOLAR_Msk /*!< Word select signal polarity selection for transmission */ + +#define I2S_DEV_CONF_TRANAPBALIGNLR_Pos 2 +#define I2S_DEV_CONF_TRANAPBALIGNLR_Msk (0x1UL << I2S_DEV_CONF_TRANAPBALIGNLR_Pos) /*!< 0x00000004 */ +#define I2S_DEV_CONF_TRANAPBALIGNLR I2S_DEV_CONF_TRANAPBALIGNLR_Msk /*!< Alignment of the transmitted digital data sample at the APB bus */ + +#define I2S_DEV_CONF_TRANI2SALIGNLR_Pos 3 +#define I2S_DEV_CONF_TRANI2SALIGNLR_Msk (0x1UL << I2S_DEV_CONF_TRANI2SALIGNLR_Pos) /*!< 0x00000008 */ +#define I2S_DEV_CONF_TRANI2SALIGNLR I2S_DEV_CONF_TRANI2SALIGNLR_Msk /*!< Alignment of the transmitted digital data sample at the I2S serial data line */ + +#define I2S_DEV_CONF_TRANDATAWSDEL_Pos 4 +#define I2S_DEV_CONF_TRANDATAWSDEL_Msk (0x1UL << I2S_DEV_CONF_TRANDATAWSDEL_Pos) /*!< 0x00000010 */ +#define I2S_DEV_CONF_TRANDATAWSDEL I2S_DEV_CONF_TRANDATAWSDEL_Msk /*!< Transmitted valid data delay at the I2S SD output line afte the WS line edge */ + +#define I2S_DEV_CONF_TRANWSDSPMODE_Pos 5 +#define I2S_DEV_CONF_TRANWSDSPMODE_Msk (0x1UL << I2S_DEV_CONF_TRANWSDSPMODE_Pos) /*!< 0x00000020 */ +#define I2S_DEV_CONF_TRANWSDSPMODE I2S_DEV_CONF_TRANWSDSPMODE_Msk /*!< WS signal format according to DSP audio interface spec for transmitter */ + +#define I2S_DEV_CONF_RECSCKPOLAR_Pos 6 +#define I2S_DEV_CONF_RECSCKPOLAR_Msk (0x1UL << I2S_DEV_CONF_RECSCKPOLAR_Pos) /*!< 0x00000040 */ +#define I2S_DEV_CONF_RECSCKPOLAR I2S_DEV_CONF_RECSCKPOLAR_Msk /*!< Continuous serial clock active edge for reception */ + +#define I2S_DEV_CONF_RECWSPOLAR_Pos 7 +#define I2S_DEV_CONF_RECWSPOLAR_Msk (0x1UL << I2S_DEV_CONF_RECWSPOLAR_Pos) /*!< 0x00000080 */ +#define I2S_DEV_CONF_RECWSPOLAR I2S_DEV_CONF_RECWSPOLAR_Msk /*!< Word select signal polarity selection for reception */ + +#define I2S_DEV_CONF_RECAPBALIGNLR_Pos 8 +#define I2S_DEV_CONF_RECAPBALIGNLR_Msk (0x1UL << I2S_DEV_CONF_RECAPBALIGNLR_Pos) /*!< 0x00000100 */ +#define I2S_DEV_CONF_RECAPBALIGNLR I2S_DEV_CONF_RECAPBALIGNLR_Msk /*!< Alignment of the received digital data sample at the I2S serial data line */ + +#define I2S_DEV_CONF_RECI2SALIGNLR_Pos 9 +#define I2S_DEV_CONF_RECI2SALIGNLR_Msk (0x1UL << I2S_DEV_CONF_RECI2SALIGNLR_Pos) /*!< 0x00000200 */ +#define I2S_DEV_CONF_RECI2SALIGNLR I2S_DEV_CONF_RECI2SALIGNLR_Msk /*!< Alignment of the received digital data sample at the I2S serial data line */ + +#define I2S_DEV_CONF_RECDATAWSDEL_Pos 10 +#define I2S_DEV_CONF_RECDATAWSDEL_Msk (0x1UL << I2S_DEV_CONF_RECDATAWSDEL_Pos) /*!< 0x00000400 */ +#define I2S_DEV_CONF_RECDATAWSDEL I2S_DEV_CONF_RECDATAWSDEL_Msk /*!< Received valid data delay at the I2S SD input line afte the WS line edge */ + +#define I2S_DEV_CONF_RECWSDSPMODE_Pos 11 +#define I2S_DEV_CONF_RECWSDSPMODE_Msk (0x1UL << I2S_DEV_CONF_RECWSDSPMODE_Pos) /*!< 0x00000800 */ +#define I2S_DEV_CONF_RECWSDSPMODE I2S_DEV_CONF_RECWSDSPMODE_Msk /*!< WS signal format according to DSP audio interface spec for receiver */ + +/****************** Bit definition for POLL_STAT register **************************/ +#define I2S_POLL_STAT_TXEMPTY_Pos 0 +#define I2S_POLL_STAT_TXEMPTY_Msk (0x1UL << I2S_POLL_STAT_TXEMPTY_Pos) /*!< 0x00000001 */ +#define I2S_POLL_STAT_TXEMPTY I2S_POLL_STAT_TXEMPTY_Msk /*!< Transmit fifo empty flag*/ + +#define I2S_POLL_STAT_TXAEMPTY_Pos 1 +#define I2S_POLL_STAT_TXAEMPTY_Msk (0x1UL << I2S_POLL_STAT_TXAEMPTY_Pos) /*!< 0x00000002 */ +#define I2S_POLL_STAT_TXAEMPTY I2S_POLL_STAT_TXAEMPTY_Msk /*!< Transmit fifo almost flag*/ + +#define I2S_POLL_STAT_TXUNDERRUN_Pos 2 +#define I2S_POLL_STAT_TXUNDERRUN_Msk (0x1UL << I2S_POLL_STAT_TXUNDERRUN_Pos) /*!< 0x00000004 */ +#define I2S_POLL_STAT_TXUNDERRUN I2S_POLL_STAT_TXUNDERRUN_Msk /*!< Transmitter data underrun */ + +#define I2S_POLL_STAT_RXFULL_Pos 4 +#define I2S_POLL_STAT_RXFULL_Msk (0x1UL << I2S_POLL_STAT_RXFULL_Pos) /*!< 0x00000010 */ +#define I2S_POLL_STAT_RXFULL I2S_POLL_STAT_RXFULL_Msk /*!< Receive fifo full flag */ + +#define I2S_POLL_STAT_RXAFULL_Pos 5 +#define I2S_POLL_STAT_RXAFULL_Msk (0x1UL << I2S_POLL_STAT_RXAFULL_Pos) /*!< 0x00000020 */ +#define I2S_POLL_STAT_RXAFULL I2S_POLL_STAT_RXAFULL_Msk /*!< Receive fifo almost full flag */ + +#define I2S_POLL_STAT_RXOVERRUN_Pos 6 +#define I2S_POLL_STAT_RXOVERRUN_Msk (0x1UL << I2S_POLL_STAT_RXOVERRUN_Pos) /*!< 0x00000040 */ +#define I2S_POLL_STAT_RXOVERRUN I2S_POLL_STAT_RXOVERRUN_Msk /*!< Receiver data overrun */ + +/****************** Bit definition for FIFO register *******************************/ +#define I2S_FIFO_Pos 0 +#define I2S_FIFO_Msk (0xFFFFFFFFUL << I2S_FIFO_Pos) /*!< 0xFFFFFFFF */ +#define I2S_FIFO I2S_FIFO_Msk /*!< I2S data fifo */ +#define I2S_FIFO_0 (0x1UL << I2S_FIFO_Pos) /*!< 0x00000001 */ +#define I2S_FIFO_1 (0x2UL << I2S_FIFO_Pos) /*!< 0x00000002 */ +#define I2S_FIFO_2 (0x4UL << I2S_FIFO_Pos) /*!< 0x00000004 */ +#define I2S_FIFO_3 (0x8UL << I2S_FIFO_Pos) /*!< 0x00000008 */ +#define I2S_FIFO_4 (0x10UL << I2S_FIFO_Pos) /*!< 0x00000010 */ +#define I2S_FIFO_5 (0x20UL << I2S_FIFO_Pos) /*!< 0x00000020 */ +#define I2S_FIFO_6 (0x40UL << I2S_FIFO_Pos) /*!< 0x00000040 */ +#define I2S_FIFO_7 (0x80UL << I2S_FIFO_Pos) /*!< 0x00000080 */ +#define I2S_FIFO_8 (0x100UL << I2S_FIFO_Pos) /*!< 0x00000100 */ +#define I2S_FIFO_9 (0x200UL << I2S_FIFO_Pos) /*!< 0x00000200 */ +#define I2S_FIFO_10 (0x400UL << I2S_FIFO_Pos) /*!< 0x00000400 */ +#define I2S_FIFO_11 (0x800UL << I2S_FIFO_Pos) /*!< 0x00000800 */ +#define I2S_FIFO_12 (0x1000UL << I2S_FIFO_Pos) /*!< 0x00001000 */ +#define I2S_FIFO_13 (0x2000UL << I2S_FIFO_Pos) /*!< 0x00002000 */ +#define I2S_FIFO_14 (0x4000UL << I2S_FIFO_Pos) /*!< 0x00004000 */ +#define I2S_FIFO_15 (0x8000UL << I2S_FIFO_Pos) /*!< 0x00008000 */ +#define I2S_FIFO_16 (0x10000UL << I2S_FIFO_Pos) /*!< 0x00010000 */ +#define I2S_FIFO_17 (0x20000UL << I2S_FIFO_Pos) /*!< 0x00020000 */ +#define I2S_FIFO_18 (0x40000UL << I2S_FIFO_Pos) /*!< 0x00040000 */ +#define I2S_FIFO_19 (0x80000UL << I2S_FIFO_Pos) /*!< 0x00080000 */ +#define I2S_FIFO_20 (0x100000UL << I2S_FIFO_Pos) /*!< 0x00100000 */ +#define I2S_FIFO_21 (0x200000UL << I2S_FIFO_Pos) /*!< 0x00200000 */ +#define I2S_FIFO_22 (0x400000UL << I2S_FIFO_Pos) /*!< 0x00400000 */ +#define I2S_FIFO_23 (0x800000UL << I2S_FIFO_Pos) /*!< 0x00800000 */ +#define I2S_FIFO_24 (0x1000000UL << I2S_FIFO_Pos) /*!< 0x01000000 */ +#define I2S_FIFO_25 (0x2000000UL << I2S_FIFO_Pos) /*!< 0x02000000 */ +#define I2S_FIFO_26 (0x4000000UL << I2S_FIFO_Pos) /*!< 0x04000000 */ +#define I2S_FIFO_27 (0x8000000UL << I2S_FIFO_Pos) /*!< 0x08000000 */ +#define I2S_FIFO_28 (0x10000000UL << I2S_FIFO_Pos) /*!< 0x10000000 */ +#define I2S_FIFO_29 (0x20000000UL << I2S_FIFO_Pos) /*!< 0x10000000 */ +#define I2S_FIFO_30 (0x40000000UL << I2S_FIFO_Pos) /*!< 0x40000000 */ +#define I2S_FIFO_31 (0x80000000UL << I2S_FIFO_Pos) /*!< 0x80000000 */ + + + +/****************** USB_OTG_HS Exported Constants *******************************/ +#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR 12U +#define USB_OTG_HS_MAX_IN_ENDPOINTS 6U /* Including EP0 */ +#define USB_OTG_HS_MAX_OUT_ENDPOINTS 6U /* Including EP0 */ +#define USB_OTG_HS_TOTAL_FIFO_SIZE 4096U /* in Bytes */ + +/************************* HCD Instances *************************************/ +#define IS_HCD_HS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) +/************************* PCD Instances *************************************/ +#define IS_PCD_HS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) + +/*@}*/ /* end of group __FT32F407XE_H Definitions */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F407XE_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/ft32f4xx.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/ft32f4xx.h new file mode 100644 index 00000000000..1407bd2e78d --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/ft32f4xx.h @@ -0,0 +1,117 @@ +/** + ****************************************************************************** + * @file ft32f4xx.h + * @author FMD AE + * @brief CMSIS FT32F4xx Device Peripheral Access Layer Header File. + * @version V1.0.0 + * @data 2025-03-04 + ****************************************************************************** + */ + +#ifndef __FT32F4xx_H +#define __FT32F4xx_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +#if !defined (FT32F4) +#define FT32F4 +#endif /* FT32F4 */ + + + +/** + * @brief CMSIS Device version number V2.3.3 + */ +#define __FT32F4_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */ +#define __FT32F4_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __FT32F4_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */ +#define __FT32F4_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __FT32F4_DEVICE_VERSION ((__FT32F4_DEVICE_VERSION_MAIN << 24)\ + |(__FT32F4_DEVICE_VERSION_SUB1 << 16)\ + |(__FT32F4_DEVICE_VERSION_SUB2 << 8 )\ + |(__FT32F4_DEVICE_VERSION_RC)) + + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT + +#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +//void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line) +{ + printf("Wrong parameters value: file %s on line %d\r\n", file, line); +} +#else +#define assert_param(expr) ((void)0) +#endif /* USE_FULL_ASSERT */ + + +#if !defined(UNUSED) +#define UNUSED(x) ((void)(x)) +#endif + + +#if defined(FT32F407xE) +#include "ft32f407xe.h" +#else +#error "Please select first the target FT32F4xx device used in your application (in ft32f4xx.h file)" +#endif + +/** + * @} + */ + +#if defined(__CC_ARM) // AC5 ARMCC +#define WEAK __weak +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) // AC6 ARMclang +#define WEAK __attribute__((weak)) +#else +#define WEAK __attribute__((weak)) +#endif + + + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __FT32F4xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + +/*****************************END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/mpu_armv7.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/mpu_armv7.h new file mode 100644 index 00000000000..be0d7048be2 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/mpu_armv7.h @@ -0,0 +1,277 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.2 + * @date 25. May 2020 + ******************************************************************************/ +/* + * Copyright (c) 2017-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct +{ + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rasr Value for RASR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t) / 4U; + while (cnt > MPU_TYPE_RALIASES) + { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES * rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt * rowWordSize); +} + +#endif diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/mpu_armv8.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/mpu_armv8.h new file mode 100644 index 00000000000..3de16efc86a --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/mpu_armv8.h @@ -0,0 +1,352 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.3 + * @date 03. February 2021 + ******************************************************************************/ +/* + * Copyright (c) 2017-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + (((BASE) & MPU_RBAR_BASE_Msk) | \ + (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ + (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + __DMB(); + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + __DMB(); + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; + __DSB(); + __ISB(); +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/pac_armv81.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/pac_armv81.h new file mode 100644 index 00000000000..854b60a204c --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/pac_armv81.h @@ -0,0 +1,206 @@ +/****************************************************************************** + * @file pac_armv81.h + * @brief CMSIS PAC key functions for Armv8.1-M PAC extension + * @version V1.0.0 + * @date 23. March 2022 + ******************************************************************************/ +/* + * Copyright (c) 2022 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef PAC_ARMV81_H +#define PAC_ARMV81_H + + +/* ################### PAC Key functions ########################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions + \brief Functions that access the PAC keys. + @{ + */ + +#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) + +/** + \brief read the PAC key used for privileged mode + \details Reads the PAC key stored in the PAC_KEY_P registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode + \details writes the given PAC key to the PAC_KEY_P registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode + \details Reads the PAC key stored in the PAC_KEY_U registers. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode + \details writes the given PAC key to the PAC_KEY_U registers. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) + +/** + \brief read the PAC key used for privileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_p_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_p_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_p_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_p_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for privileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_p_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_p_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_p_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_p_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief read the PAC key used for unprivileged mode (non-secure) + \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. + \param [out] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "mrs r1, pac_key_u_0_ns\n" + "str r1,[%0,#0]\n" + "mrs r1, pac_key_u_1_ns\n" + "str r1,[%0,#4]\n" + "mrs r1, pac_key_u_2_ns\n" + "str r1,[%0,#8]\n" + "mrs r1, pac_key_u_3_ns\n" + "str r1,[%0,#12]\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +/** + \brief write the PAC key used for unprivileged mode (non-secure) + \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. + \param [in] pPacKey 128bit PAC key + */ +__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { + __ASM volatile ( + "ldr r1,[%0,#0]\n" + "msr pac_key_u_0_ns, r1\n" + "ldr r1,[%0,#4]\n" + "msr pac_key_u_1_ns, r1\n" + "ldr r1,[%0,#8]\n" + "msr pac_key_u_2_ns, r1\n" + "ldr r1,[%0,#12]\n" + "msr pac_key_u_3_ns, r1\n" + : : "r" (pPacKey) : "memory", "r1" + ); +} + +#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ + +#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ + +/*@} end of CMSIS_Core_PacKeyFunctions */ + + +#endif /* PAC_ARMV81_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/pmu_armv8.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/pmu_armv8.h new file mode 100644 index 00000000000..f8f3d8935b8 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/pmu_armv8.h @@ -0,0 +1,337 @@ +/****************************************************************************** + * @file pmu_armv8.h + * @brief CMSIS PMU API for Armv8.1-M PMU + * @version V1.0.1 + * @date 15. April 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_PMU_ARMV8_H +#define ARM_PMU_ARMV8_H + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +/** \brief PMU Functions */ + +__STATIC_INLINE void ARM_PMU_Enable(void); +__STATIC_INLINE void ARM_PMU_Disable(void); + +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); + +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); + +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); + +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); + +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); + +/** + \brief Enable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Enable(void) +{ + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Disable the PMU +*/ +__STATIC_INLINE void ARM_PMU_Disable(void) +{ + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; +} + +/** + \brief Set event to count for PMU eventer counter + \param [in] num Event counter (0-30) to configure + \param [in] type Event to count +*/ +__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) +{ + PMU->EVTYPER[num] = type; +} + +/** + \brief Reset cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +/** + \brief Reset all event counters +*/ +__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) +{ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; +} + +/** + \brief Enable counters + \param [in] mask Counters to enable + \note Enables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) +{ + PMU->CNTENSET = mask; +} + +/** + \brief Disable counters + \param [in] mask Counters to enable + \note Disables one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) +{ + PMU->CNTENCLR = mask; +} + +/** + \brief Read cycle counter + \return Cycle count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) +{ + return PMU->CCNTR; +} + +/** + \brief Read event counter + \param [in] num Event counter (0-30) to read + \return Event count +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) +{ + return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; +} + +/** + \brief Read counter overflow status + \return Counter overflow status bits for the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) +{ + return PMU->OVSSET; +} + +/** + \brief Clear counter overflow status + \param [in] mask Counter overflow status bits to clear + \note Clears overflow status bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) +{ + PMU->OVSCLR = mask; +} + +/** + \brief Enable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to set + \note Sets overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) +{ + PMU->INTENSET = mask; +} + +/** + \brief Disable counter overflow interrupt request + \param [in] mask Counter overflow interrupt request bits to clear + \note Clears overflow interrupt request bits for one or more of the following: + - event counters (0-30) + - cycle counter +*/ +__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) +{ + PMU->INTENCLR = mask; +} + +/** + \brief Software increment event counter + \param [in] mask Counters to increment + \note Software increment bits for one or more event counters (0-30) +*/ +__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) +{ + PMU->SWINC = mask; +} + +#endif diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/system_ft32f4xx.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/system_ft32f4xx.h new file mode 100644 index 00000000000..05158326e24 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/system_ft32f4xx.h @@ -0,0 +1,49 @@ +/** + ****************************************************************************** + * @file system_ft32f4xx.h + * @author FMD AE + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Header File. + * @details + * @version V1.0.0 + * @date 2025-03-04 + ******************************************************************************* + */ + +/** + * @brief Define to prevent recursive inclusion + */ +#ifndef __SYSTEM_FT32F4xx_H +#define __SYSTEM_FT32F4xx_H +#include "ft32f4xx.h" +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/tz_context.h b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/tz_context.h new file mode 100644 index 00000000000..0d09749f3a5 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/arm/FT32F407_OPT.s b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/arm/FT32F407_OPT.s new file mode 100644 index 00000000000..bfa52deac21 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/arm/FT32F407_OPT.s @@ -0,0 +1,128 @@ +;/*******************************************************************************/ +;/* Copyright (c) 2014 Arm Limited (or its affiliates). All */ +;/* rights reserved. */ +;/* */ +;/* SPDX-License-Identifier: BSD-3-Clause */ +;/* */ +;/* Redistribution and use in source and binary forms, with or without */ +;/* modification, are permitted provided that the following conditions are met: */ +;/* 1.Redistributions of source code must retain the above copyright */ +;/* notice, this list of conditions and the following disclaimer. */ +;/* 2.Redistributions in binary form must reproduce the above copyright */ +;/* notice, this list of conditions and the following disclaimer in the */ +;/* documentation and/or other materials provided with the distribution. */ +;/* 3.Neither the name of Arm nor the names of its contributors may be used */ +;/* to endorse or promote products derived from this software without */ +;/* specific prior written permission. */ +;/* */ +;/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */ +;/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE */ +;/* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE */ +;/* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE */ +;/* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR */ +;/* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF */ +;/* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS */ +;/* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN */ +;/* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) */ +;/* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */ +;/* POSSIBILITY OF SUCH DAMAGE. */ +;/*******************************************************************************/ +;/* FT32F407_OPT.s: FT32F407 Flash Option Bytes */ +;/*******************************************************************************/ +;/* <<< Use Configuration Wizard in Context Menu >>> */ +;/*******************************************************************************/ + + +;// Flash Option Bytes +FLASH_OPT EQU 1 + +;// Flash Read Protection +;// Read protection is used to protect the software code stored in Flash memory +;// Read Protection Level +;// Level 0: No Protection +;// Level 1: Read Protection of Memories (debug features limited) +;// Level 2: Chip Protection (debug and boot in RAM features disabled) +;// <0xAA=> Level 0 (No Protection) +;// <0x00=> Level 1 (Read Protection of Memories) +;// <0xCC=> Level 2 (Chip Protection) +;// + +;// User Configuration +;// BOR_EN +;// BORF_LEV +;// <0=> BOR falling edge voltage 1: threshold value is approximately 2.0 V +;// <1=> BOR falling edge voltage 2: threshold value is approximately 2.2 V +;// <2=> BOR falling edge voltage 3: threshold value is approximately 2.5 V +;// <3=> BOR falling edge voltage 4: threshold value is approximately 2.8 V +;// BORR_LEV +;// <0=> BOR rising edge voltage 1: threshold value is approximately 2.1 V +;// <1=> BOR rising edge voltage 2: threshold value is approximately 2.3 V +;// <2=> BOR rising edge voltage 3: threshold value is approximately 2.6 V +;// <3=> BOR rising edge voltage 4: threshold value is approximately 2.9 V +;// WDG_SW +;// <0=> HW Watchdog +;// <1=> SW Watchdog +;// nRST_STOP +;// Generate Reset when entering STOP Mode +;// <0=> Enabled +;// <1=> Disabled +;// nRST_STDBY +;// Generate Reset when entering Standby Mode +;// <0=> Enabled +;// <1=> Disabled +;// + +;// Flash Write Protection +;// Flash write-protection setting, with 16KB as the unit, low effective +;// nWRP Page 0 to 1023 +;// Not write protect Page 0 to 1023 +;// Page 0 to 31 +;// Page 32 to 63 +;// Page 64 to 95 +;// Page 96 to 127 +;// Page 128 to 159 +;// Page 160 to 191 +;// Page 192 to 223 +;// Page 224 to 255 +;// Page 256 to 287 +;// Page 288 to 319 +;// Page 320 to 351 +;// Page 352 to 383 +;// Page 384 to 415 +;// Page 416 to 447 +;// Page 448 to 479 +;// Page 480 to 511 +;// Page 512 to 543 +;// Page 544 to 575 +;// Page 576 to 607 +;// Page 608 to 639 +;// Page 640 to 671 +;// Page 672 to 703 +;// Page 704 to 735 +;// Page 736 to 767 +;// Page 768 to 799 +;// Page 800 to 831 +;// Page 832 to 863 +;// Page 864 to 895 +;// Page 896 to 927 +;// Page 928 to 959 +;// Page 960 to 991 +;// Page 992 to 1023 +;// +;// + + +FLASH_OPBC EQU 0x001EAAE0 +FLASH_TEMP EQU ~FLASH_OPBC +FLASH_WRPR EQU 0xFFFFFFFF +;// + + + IF FLASH_OPT <> 0 + AREA |.ARM.__AT_0x1FFF0800|, CODE, READONLY + DCD FLASH_OPBC + DCD FLASH_TEMP + DCD FLASH_WRPR + ENDIF + + END diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/arm/startup_ft32f407xe.s b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/arm/startup_ft32f407xe.s new file mode 100644 index 00000000000..9336a63de75 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/arm/startup_ft32f407xe.s @@ -0,0 +1,491 @@ +;/**************************************************************************//** +; * @file startup_CMSDK_CM4.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Device CMSDK_CM4 +; * @version V3.01 +; * @date 06. March 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +;/*****************************************************************************/ +;/* Startup.s: Startup file for ARM Cortex-M4 Device Family */ +;/*****************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_Handler ; 16+ 0: Window Watchdog + DCD PVD_Handler ; 16+ 1: PVD PROG VDDIO Handler + DCD TAMP_STAMP_Handler ; 16+ 2: TAMP and STAMP Handler + DCD RTC_Handler ; 16+ 3: RTC Handler + DCD FLASH_Handler ; 16+ 4: FLASH Handler + DCD RCC_Handler ; 16+ 5: RCC Handler + DCD EXTI0_Handler ; 16+ 6: EXTI 0 handler + DCD EXTI1_Handler ; 16+ 7: EXTI 1 Handler + DCD EXTI2_Handler ; 16+ 8: EXTI 2 Handler + DCD EXTI3_Handler ; 16+ 9: EXTI 3 Handler + DCD EXTI4_Handler ; 16+10: EXTI 4 Handler + DCD DMA1_CH0_Handler ; 16+11: DMA1 CH0 Handler + DCD DMA1_CH1_Handler ; 16+12: DMA1 CH1 Handler + DCD DMA1_CH2_Handler ; 16+13: DMA1 CH2 Handler + DCD DMA1_CH3_Handler ; 16+14: DMA1 CH3 Handler + DCD DMA1_CH4_Handler ; 16+15: DMA1 CH4 Handler + DCD DMA1_CH5_Handler ; 16+16: DMA1 CH5 Handler + DCD DMA1_CH6_Handler ; 16+17: DMA1 CH6 Handler + DCD ADC_Handler ; 16+18: ADC Handler + DCD CAN1_Handler ; 16+19: FDxCAN1 Handler + DCD CAN2_Handler ; 16+20: FDxCAN2 Handler + DCD CAN3_Handler ; 16+21: FDxCAN3 Handler + DCD CAN4_Handler ; 16+22: FDxCAN4 Handler + DCD EXTI9_5_Handler ; 16+23: EXTI[9:5] Handler + DCD TIM1_BRK_TIM9_Handler ; 16+24: TIM1 BRK and TIM9 Handler + DCD TIM1_UP_TIM1O_Handler ; 16+25: TIM1 UP and TIM10 Handler + DCD TIM1_TRG_COM_TIM11_Handler ; 16+26: TIM1 TRG/COM and TIM10 Hand + DCD TIM1_CC_Handler ; 16+27: TIM1 CC Handler + DCD TIM2_Handler ; 16+28: TIM2 Handler + DCD TIM3_Handler ; 16+29: TIM3 Handler + DCD TIM4_Handler ; 16+30: TIM4 Handler + DCD I2C1_Handler ; 16+31: I2C1 Handler + DCD I2C2_Handler ; 16+32: I2C2 Handler + DCD QSPI_Handler ; 16+33: QSPI Handler + DCD SPI1_Handler ; 16+34: SPI1 Handler + DCD SPI2_Handler ; 16+35: SPI2 Handler + DCD USART1_Handler ; 16+36: USART1 Handler + DCD USART2_Handler ; 16+37: USART2 Handler + DCD USART3_Handler ; 16+38: USART3 Handler + DCD EXTI15_10_Handler ; 16+39: EXTI[15:10] Handler + DCD RTCAlarm_Handler ; 16+40: RTC Alarm Handler + DCD OTG_FS_WKUP_Handler ; 16+41: Connect EXTI USB OTG WKUP H + DCD TIM8_BRK_TIM12_Handler ; 16+42: TIM8 BRK and TIM12 Handler + DCD TIM8_UP_TIM13_Handler ; 16+43: TIM8 UP and TIM13 Handler + DCD TIM8_TRG_COM_TIM14_Handler ; 16+44: TIM8 TRG/COM and TIM14 Hand + DCD TIM8_CC_Handler ; 16+45: TIM8 CC Handler + DCD DMA1_CH7_Handler ; 16+46: DMA1 CH7 Handler + DCD FMC_Handler ; 16+47: FMC Handler + DCD SDIO_Handler ; 16+48: SDIO Handler + DCD TIM5_Handler ; 16+49: TIM5 Handler + DCD SPI3_Handler ; 16+50: SPI3 Handler + DCD UART4_Handler ; 16+51: UART4 Handler + DCD UART5_Handler ; 16+52: UART5 Handler + DCD TIM6_DAC_Handler ; 16+53: TIM6 DAC Handler + DCD TIM7_Handler ; 16+54: TIM7 Handler + DCD DMA2_CH0_Handler ; 16+55: DMA2 CH0 Handler + DCD DMA2_CH1_Handler ; 16+56: DMA2 CH1 Handler + DCD DMA2_CH2_Handler ; 16+57: DMA2 CH2 Handler + DCD DMA2_CH3_Handler ; 16+58: DMA2 CH3 Handler + DCD DMA2_CH4_Handler ; 16+59: DMA2 CH4 Handler + DCD OTG_FS_Handler ; 16+60: OTG FS Handler + DCD DMA2_CH5_Handler ; 16+61: DMA2 CH5 Handler + DCD DMA2_CH6_Handler ; 16+62: DMA2 CH6 Handler + DCD DMA2_CH7_Handler ; 16+63: DMA2 CH7 Handler + DCD USART6_Handler ; 16+64: USART6 Handler + DCD I2C3_Handler ; 16+65: I2C3 Handler + DCD OTG_HS_EP1_OUT_Handler ; 16+66: OTG HS EP1OUT Handler + DCD OTG_HS_EP1_IN_Handler ; 16+67: OTG HS EP1IN Handler + DCD OTG_HS_WKUP_Handler ; 16+68: OTG HS WKUP Handler + DCD OTG_HS_Handler ; 16+69: OTG HS Handler + DCD RNG_Handler ; 16+70: RNG Handler + DCD FPU_Handler ; 16+71: FPU Handler + DCD CRS_Handler ; 16+72: CRS Handler + DCD SPDIF_Handler ; 16+73: SPDIF Handler + DCD SSI_AC97_Handler ; 16+74: SSI_AC97 Handler + DCD ETH_WKUP_Handler ; 16+75: ETH_WKUP Handler + DCD LPUART_Handler ; 16+76: LPUART Handler + DCD LPTIM_Handler ; 16+77: LPTIM Handler + DCD ETH_SBD_Handler ; 16+78: ETH_SBD Handler + DCD ETH_PERCHTX_Handler ; 16+79: ETH_PERCHTX Handler + DCD ETH_PERCHRX_Handler ; 16+80: ETH_PERCHRX Handler + DCD EPWM1_Handler ; 16+81: EPWM1 Handler + DCD EPWM1_TZ_Handler ; 16+82: EPWM1 TZ Handler + DCD EPWM2_Handler ; 16+83: EPWM2 Handler + DCD EPWM2_TZ_Handler ; 16+84: EPWM2 TZ Handler + DCD EPWM3_Handler ; 16+85: EPWM3 Handler + DCD EPWM3_TZ_Handler ; 16+86: EPWM3 TZ Handler + DCD EPWM4_Handler ; 16+87: EPWM4 Handler + DCD EPWM4_TZ_Handler ; 16+88: EPWM4 TZ Handler + DCD ECAP_Handler ; 16+89: ECAP Handler + DCD EQEP_Handler ; 16+90: EQEP Handler + DCD DLL_CAL_Handler ; 16+91: DLL CAL Handler + DCD COMP1_Handler ; 16+92: COMP1 Handler + DCD COMP2_Handler ; 16+93: COMP2 Handler + DCD COMP3_Handler ; 16+94: COMP3 Handler + DCD COMP4_Handler ; 16+95: COMP4 Handler + DCD COMP5_Handler ; 16+96: COMP5 Handler + DCD COMP6_Handler ; 16+97: COMP6 Handler + DCD ICACHE_Handler ; 16+98: ICACHE Handler + DCD DCACHE_Handler ; 16+99: DCACHE Handler + DCD UART7_Handler ; 16+100: UART7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT WWDG_Handler [WEAK] + EXPORT PVD_Handler [WEAK] + EXPORT TAMP_STAMP_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT FLASH_Handler [WEAK] + EXPORT RCC_Handler [WEAK] + EXPORT EXTI0_Handler [WEAK] + EXPORT EXTI1_Handler [WEAK] + EXPORT EXTI2_Handler [WEAK] + EXPORT EXTI3_Handler [WEAK] + EXPORT EXTI4_Handler [WEAK] + EXPORT DMA1_CH0_Handler [WEAK] + EXPORT DMA1_CH1_Handler [WEAK] + EXPORT DMA1_CH2_Handler [WEAK] + EXPORT DMA1_CH3_Handler [WEAK] + EXPORT DMA1_CH4_Handler [WEAK] + EXPORT DMA1_CH5_Handler [WEAK] + EXPORT DMA1_CH6_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT CAN1_Handler [WEAK] + EXPORT CAN2_Handler [WEAK] + EXPORT CAN3_Handler [WEAK] + EXPORT CAN4_Handler [WEAK] + EXPORT EXTI9_5_Handler [WEAK] + EXPORT TIM1_BRK_TIM9_Handler [WEAK] + EXPORT TIM1_UP_TIM1O_Handler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_Handler [WEAK] + EXPORT TIM1_CC_Handler [WEAK] + EXPORT TIM2_Handler [WEAK] + EXPORT TIM3_Handler [WEAK] + EXPORT TIM4_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT I2C2_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT SPI1_Handler [WEAK] + EXPORT SPI2_Handler [WEAK] + EXPORT USART1_Handler [WEAK] + EXPORT USART2_Handler [WEAK] + EXPORT USART3_Handler [WEAK] + EXPORT EXTI15_10_Handler [WEAK] + EXPORT RTCAlarm_Handler [WEAK] + EXPORT OTG_FS_WKUP_Handler [WEAK] + EXPORT TIM8_BRK_TIM12_Handler [WEAK] + EXPORT TIM8_UP_TIM13_Handler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_Handler [WEAK] + EXPORT TIM8_CC_Handler [WEAK] + EXPORT DMA1_CH7_Handler [WEAK] + EXPORT FMC_Handler [WEAK] + EXPORT SDIO_Handler [WEAK] + EXPORT TIM5_Handler [WEAK] + EXPORT SPI3_Handler [WEAK] + EXPORT UART4_Handler [WEAK] + EXPORT UART5_Handler [WEAK] + EXPORT TIM6_DAC_Handler [WEAK] + EXPORT TIM7_Handler [WEAK] + EXPORT DMA2_CH0_Handler [WEAK] + EXPORT DMA2_CH1_Handler [WEAK] + EXPORT DMA2_CH2_Handler [WEAK] + EXPORT DMA2_CH3_Handler [WEAK] + EXPORT DMA2_CH4_Handler [WEAK] + EXPORT OTG_FS_Handler [WEAK] + EXPORT DMA2_CH5_Handler [WEAK] + EXPORT DMA2_CH6_Handler [WEAK] + EXPORT DMA2_CH7_Handler [WEAK] + EXPORT USART6_Handler [WEAK] + EXPORT I2C3_Handler [WEAK] + EXPORT OTG_HS_EP1_OUT_Handler [WEAK] + EXPORT OTG_HS_EP1_IN_Handler [WEAK] + EXPORT OTG_HS_WKUP_Handler [WEAK] + EXPORT OTG_HS_Handler [WEAK] + EXPORT RNG_Handler [WEAK] + EXPORT FPU_Handler [WEAK] + EXPORT CRS_Handler [WEAK] + EXPORT SPDIF_Handler [WEAK] + EXPORT SSI_AC97_Handler [WEAK] + EXPORT ETH_WKUP_Handler [WEAK] + EXPORT LPUART_Handler [WEAK] + EXPORT LPTIM_Handler [WEAK] + EXPORT ETH_SBD_Handler [WEAK] + EXPORT ETH_PERCHTX_Handler [WEAK] + EXPORT ETH_PERCHRX_Handler [WEAK] + EXPORT EPWM1_Handler [WEAK] + EXPORT EPWM1_TZ_Handler [WEAK] + EXPORT EPWM2_Handler [WEAK] + EXPORT EPWM2_TZ_Handler [WEAK] + EXPORT EPWM3_Handler [WEAK] + EXPORT EPWM3_TZ_Handler [WEAK] + EXPORT EPWM4_Handler [WEAK] + EXPORT EPWM4_TZ_Handler [WEAK] + EXPORT ECAP_Handler [WEAK] + EXPORT EQEP_Handler [WEAK] + EXPORT DLL_CAL_Handler [WEAK] + EXPORT COMP1_Handler [WEAK] + EXPORT COMP2_Handler [WEAK] + EXPORT COMP3_Handler [WEAK] + EXPORT COMP4_Handler [WEAK] + EXPORT COMP5_Handler [WEAK] + EXPORT COMP6_Handler [WEAK] + EXPORT ICACHE_Handler [WEAK] + EXPORT DCACHE_Handler [WEAK] + EXPORT UART7_Handler [WEAK] + + +WWDG_Handler +PVD_Handler +TAMP_STAMP_Handler +RTC_Handler +FLASH_Handler +RCC_Handler +EXTI0_Handler +EXTI1_Handler +EXTI2_Handler +EXTI3_Handler +EXTI4_Handler +DMA1_CH0_Handler +DMA1_CH1_Handler +DMA1_CH2_Handler +DMA1_CH3_Handler +DMA1_CH4_Handler +DMA1_CH5_Handler +DMA1_CH6_Handler +ADC_Handler +CAN1_Handler +CAN2_Handler +CAN3_Handler +CAN4_Handler +EXTI9_5_Handler +TIM1_BRK_TIM9_Handler +TIM1_UP_TIM1O_Handler +TIM1_TRG_COM_TIM11_Handler +TIM1_CC_Handler +TIM2_Handler +TIM3_Handler +TIM4_Handler +I2C1_Handler +I2C2_Handler +QSPI_Handler +SPI1_Handler +SPI2_Handler +USART1_Handler +USART2_Handler +USART3_Handler +EXTI15_10_Handler +RTCAlarm_Handler +OTG_FS_WKUP_Handler +TIM8_BRK_TIM12_Handler +TIM8_UP_TIM13_Handler +TIM8_TRG_COM_TIM14_Handler +TIM8_CC_Handler +DMA1_CH7_Handler +FMC_Handler +SDIO_Handler +TIM5_Handler +SPI3_Handler +UART4_Handler +UART5_Handler +TIM6_DAC_Handler +TIM7_Handler +DMA2_CH0_Handler +DMA2_CH1_Handler +DMA2_CH2_Handler +DMA2_CH3_Handler +DMA2_CH4_Handler +OTG_FS_Handler +DMA2_CH5_Handler +DMA2_CH6_Handler +DMA2_CH7_Handler +USART6_Handler +I2C3_Handler +OTG_HS_EP1_OUT_Handler +OTG_HS_EP1_IN_Handler +OTG_HS_WKUP_Handler +OTG_HS_Handler +RNG_Handler +FPU_Handler +CRS_Handler +SPDIF_Handler +SSI_AC97_Handler +ETH_WKUP_Handler +LPUART_Handler +LPTIM_Handler +ETH_SBD_Handler +ETH_PERCHTX_Handler +ETH_PERCHRX_Handler +EPWM1_Handler +EPWM1_TZ_Handler +EPWM2_Handler +EPWM2_TZ_Handler +EPWM3_Handler +EPWM3_TZ_Handler +EPWM4_Handler +EPWM4_TZ_Handler +ECAP_Handler +EQEP_Handler +DLL_CAL_Handler +COMP1_Handler +COMP2_Handler +COMP3_Handler +COMP4_Handler +COMP5_Handler +COMP6_Handler +ICACHE_Handler +DCACHE_Handler +UART7_Handler + + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/gcc/startup_ft32f407xe.s b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/gcc/startup_ft32f407xe.s new file mode 100644 index 00000000000..83e14985f09 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/gcc/startup_ft32f407xe.s @@ -0,0 +1,583 @@ +/** + ****************************************************************************** + * @file startup_ft32f072xb.s + * @author MCD Application Team + * @brief FT32F407xE devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * Copyright (c) 2006-2025 Fremontmicro + * All rights reserved. + * + * This software component is licensed by FMD under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + bl __libc_init_array +/* Call the application's entry point.*/ + bl entry + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + .word WWDG_Handler + .word PVD_Handler + .word TAMP_STAMP_Handler + .word RTC_Handler + .word FLASH_Handler + .word RCC_Handler + .word EXTI0_Handler + .word EXTI1_Handler + .word EXTI2_Handler + .word EXTI3_Handler + .word EXTI4_Handler + .word DMA1_CH0_Handler + .word DMA1_CH1_Handler + .word DMA1_CH2_Handler + .word DMA1_CH3_Handler + .word DMA1_CH4_Handler + .word DMA1_CH5_Handler + .word DMA1_CH6_Handler + .word ADC_Handler + .word CAN1_Handler + .word CAN2_Handler + .word CAN3_Handler + .word CAN4_Handler + .word EXTI9_5_Handler + .word TIM1_BRK_TIM9_Handler + .word TIM1_UP_TIM1O_Handler + .word TIM1_TRG_COM_TIM11_Handler + .word TIM1_CC_Handler + .word TIM2_Handler + .word TIM3_Handler + .word TIM4_Handler + .word I2C1_Handler + .word I2C2_Handler + .word QSPI_Handler + .word SPI1_Handler + .word SPI2_Handler + .word USART1_Handler + .word USART2_Handler + .word USART3_Handler + .word EXTI15_10_Handler + .word RTCAlarm_Handler + .word OTG_FS_WKUP_Handler + .word TIM8_BRK_TIM12_Handler + .word TIM8_UP_TIM13_Handler + .word TIM8_TRG_COM_TIM14_Handler + .word TIM8_CC_Handler + .word DMA1_CH7_Handler + .word FMC_Handler + .word SDIO_Handler + .word TIM5_Handler + .word SPI3_Handler + .word UART4_Handler + .word UART5_Handler + .word TIM6_DAC_Handler + .word TIM7_Handler + .word DMA2_CH0_Handler + .word DMA2_CH1_Handler + .word DMA2_CH2_Handler + .word DMA2_CH3_Handler + .word DMA2_CH4_Handler + .word OTG_FS_Handler + .word DMA2_CH5_Handler + .word DMA2_CH6_Handler + .word DMA2_CH7_Handler + .word USART6_Handler + .word I2C3_Handler + .word OTG_HS_EP1_OUT_Handler + .word OTG_HS_EP1_IN_Handler + .word OTG_HS_WKUP_Handler + .word OTG_HS_Handler + .word RNG_Handler + .word FPU_Handler + .word CRS_Handler + .word SPDIF_Handler + .word SSI_AC97_Handler + .word ETH_WKUP_Handler + .word LPUART_Handler + .word LPTIM_Handler + .word ETH_SBD_Handler + .word ETH_PERCHTX_Handler + .word ETH_PERCHRX_Handler + .word EPWM1_Handler + .word EPWM1_TZ_Handler + .word EPWM2_Handler + .word EPWM2_TZ_Handler + .word EPWM3_Handler + .word EPWM3_TZ_Handler + .word EPWM4_Handler + .word EPWM4_TZ_Handler + .word ECAP_Handler + .word EQEP_Handler + .word DLL_CAL_Handler + .word COMP1_Handler + .word COMP2_Handler + .word COMP3_Handler + .word COMP4_Handler + .word COMP5_Handler + .word COMP6_Handler + .word ICACHE_Handler + .word DCACHE_Handler + .word UART7_Handler + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_Handler + .thumb_set WWDG_Handler,Default_Handler + + .weak PVD_Handler + .thumb_set PVD_Handler,Default_Handler + + .weak TAMP_STAMP_Handler + .thumb_set TAMP_STAMP_Handler,Default_Handler + + .weak RTC_Handler + .thumb_set RTC_Handler,Default_Handler + + .weak FLASH_Handler + .thumb_set FLASH_Handler,Default_Handler + + .weak RCC_Handler + .thumb_set RCC_Handler,Default_Handler + + .weak EXTI0_Handler + .thumb_set EXTI0_Handler,Default_Handler + + .weak EXTI1_Handler + .thumb_set EXTI1_Handler,Default_Handler + + .weak EXTI2_Handler + .thumb_set EXTI2_Handler,Default_Handler + + .weak EXTI3_Handler + .thumb_set EXTI3_Handler,Default_Handler + + .weak EXTI4_Handler + .thumb_set EXTI4_Handler,Default_Handler + + .weak DMA1_CH0_Handler + .thumb_set DMA1_CH0_Handler,Default_Handler + + .weak DMA1_CH1_Handler + .thumb_set DMA1_CH1_Handler,Default_Handler + + .weak DMA1_CH2_Handler + .thumb_set DMA1_CH2_Handler,Default_Handler + + .weak DMA1_CH3_Handler + .thumb_set DMA1_CH3_Handler,Default_Handler + + .weak DMA1_CH4_Handler + .thumb_set DMA1_CH4_Handler,Default_Handler + + .weak DMA1_CH5_Handler + .thumb_set DMA1_CH5_Handler,Default_Handler + + .weak DMA1_CH6_Handler + .thumb_set DMA1_CH6_Handler,Default_Handler + + .weak ADC_Handler + .thumb_set ADC_Handler,Default_Handler + + .weak CAN1_Handler + .thumb_set CAN1_Handler,Default_Handler + + .weak CAN2_Handler + .thumb_set CAN2_Handler,Default_Handler + + .weak CAN3_Handler + .thumb_set CAN3_Handler,Default_Handler + + .weak CAN4_Handler + .thumb_set CAN4_Handler,Default_Handler + + .weak EXTI9_5_Handler + .thumb_set EXTI9_5_Handler,Default_Handler + + .weak TIM1_BRK_TIM9_Handler + .thumb_set TIM1_BRK_TIM9_Handler,Default_Handler + + .weak TIM1_UP_TIM1O_Handler + .thumb_set TIM1_UP_TIM1O_Handler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_Handler + .thumb_set TIM1_TRG_COM_TIM11_Handler,Default_Handler + + .weak TIM1_CC_Handler + .thumb_set TIM1_CC_Handler,Default_Handler + + .weak TIM2_Handler + .thumb_set TIM2_Handler,Default_Handler + + .weak TIM3_Handler + .thumb_set TIM3_Handler,Default_Handler + + .weak TIM4_Handler + .thumb_set TIM4_Handler,Default_Handler + + .weak I2C1_Handler + .thumb_set I2C1_Handler,Default_Handler + + .weak I2C2_Handler + .thumb_set I2C2_Handler,Default_Handler + + .weak QSPI_Handler + .thumb_set QSPI_Handler,Default_Handler + + .weak SPI1_Handler + .thumb_set SPI1_Handler,Default_Handler + + .weak SPI2_Handler + .thumb_set SPI2_Handler,Default_Handler + + .weak USART1_Handler + .thumb_set USART1_Handler,Default_Handler + + .weak USART2_Handler + .thumb_set USART2_Handler,Default_Handler + + .weak USART3_Handler + .thumb_set USART3_Handler,Default_Handler + + .weak EXTI15_10_Handler + .thumb_set EXTI15_10_Handler,Default_Handler + + .weak RTCAlarm_Handler + .thumb_set RTCAlarm_Handler,Default_Handler + + .weak OTG_FS_WKUP_Handler + .thumb_set OTG_FS_WKUP_Handler,Default_Handler + + .weak TIM8_BRK_TIM12_Handler + .thumb_set TIM8_BRK_TIM12_Handler,Default_Handler + + .weak TIM8_UP_TIM13_Handler + .thumb_set TIM8_UP_TIM13_Handler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_Handler + .thumb_set TIM8_TRG_COM_TIM14_Handler,Default_Handler + + .weak TIM8_CC_Handler + .thumb_set TIM8_CC_Handler,Default_Handler + + .weak DMA1_CH7_Handler + .thumb_set DMA1_CH7_Handler,Default_Handler + + .weak FMC_Handler + .thumb_set FMC_Handler,Default_Handler + + .weak SDIO_Handler + .thumb_set SDIO_Handler,Default_Handler + + .weak TIM5_Handler + .thumb_set TIM5_Handler,Default_Handler + + .weak SPI3_Handler + .thumb_set SPI3_Handler,Default_Handler + + .weak UART4_Handler + .thumb_set UART4_Handler,Default_Handler + + .weak UART5_Handler + .thumb_set UART5_Handler,Default_Handler + + .weak TIM6_DAC_Handler + .thumb_set TIM6_DAC_Handler,Default_Handler + + .weak TIM7_Handler + .thumb_set TIM7_Handler,Default_Handler + + .weak DMA2_CH0_Handler + .thumb_set DMA2_CH0_Handler,Default_Handler + + .weak DMA2_CH1_Handler + .thumb_set DMA2_CH1_Handler,Default_Handler + + .weak DMA2_CH2_Handler + .thumb_set DMA2_CH2_Handler,Default_Handler + + .weak DMA2_CH3_Handler + .thumb_set DMA2_CH3_Handler,Default_Handler + + .weak DMA2_CH4_Handler + .thumb_set DMA2_CH4_Handler,Default_Handler + + .weak OTG_FS_Handler + .thumb_set OTG_FS_Handler,Default_Handler + + .weak DMA2_CH5_Handler + .thumb_set DMA2_CH5_Handler,Default_Handler + + .weak DMA2_CH6_Handler + .thumb_set DMA2_CH6_Handler,Default_Handler + + .weak DMA2_CH7_Handler + .thumb_set DMA2_CH7_Handler,Default_Handler + + .weak USART6_Handler + .thumb_set USART6_Handler,Default_Handler + + .weak I2C3_Handler + .thumb_set I2C3_Handler,Default_Handler + + .weak OTG_HS_EP1_OUT_Handler + .thumb_set OTG_HS_EP1_OUT_Handler,Default_Handler + + .weak OTG_HS_EP1_IN_Handler + .thumb_set OTG_HS_EP1_IN_Handler,Default_Handler + + .weak OTG_HS_WKUP_Handler + .thumb_set OTG_HS_WKUP_Handler,Default_Handler + + .weak OTG_HS_Handler + .thumb_set OTG_HS_Handler,Default_Handler + + .weak RNG_Handler + .thumb_set RNG_Handler,Default_Handler + + .weak FPU_Handler + .thumb_set FPU_Handler,Default_Handler + + .weak CRS_Handler + .thumb_set CRS_Handler,Default_Handler + + .weak SPDIF_Handler + .thumb_set SPDIF_Handler,Default_Handler + + .weak SSI_AC97_Handler + .thumb_set SSI_AC97_Handler,Default_Handler + + .weak ETH_WKUP_Handler + .thumb_set ETH_WKUP_Handler,Default_Handler + + .weak LPUART_Handler + .thumb_set LPUART_Handler,Default_Handler + + .weak LPTIM_Handler + .thumb_set LPTIM_Handler,Default_Handler + + .weak ETH_SBD_Handler + .thumb_set ETH_SBD_Handler,Default_Handler + + .weak ETH_PERCHTX_Handler + .thumb_set ETH_PERCHTX_Handler,Default_Handler + + .weak ETH_PERCHRX_Handler + .thumb_set ETH_PERCHRX_Handler,Default_Handler + + .weak EPWM1_Handler + .thumb_set EPWM1_Handler,Default_Handler + + .weak EPWM1_TZ_Handler + .thumb_set EPWM1_TZ_Handler,Default_Handler + + .weak EPWM2_Handler + .thumb_set EPWM2_Handler,Default_Handler + + .weak EPWM2_TZ_Handler + .thumb_set EPWM2_TZ_Handler,Default_Handler + + .weak EPWM3_Handler + .thumb_set EPWM3_Handler,Default_Handler + + .weak EPWM3_TZ_Handler + .thumb_set EPWM3_TZ_Handler,Default_Handler + + .weak EPWM4_Handler + .thumb_set EPWM4_Handler,Default_Handler + + .weak EPWM4_TZ_Handler + .thumb_set EPWM4_TZ_Handler,Default_Handler + + .weak ECAP_Handler + .thumb_set ECAP_Handler,Default_Handler + + .weak EQEP_Handler + .thumb_set EQEP_Handler,Default_Handler + + .weak DLL_CAL_Handler + .thumb_set DLL_CAL_Handler,Default_Handler + + .weak COMP1_Handler + .thumb_set COMP1_Handler,Default_Handler + + .weak COMP2_Handler + .thumb_set COMP2_Handler,Default_Handler + + .weak COMP3_Handler + .thumb_set COMP3_Handler,Default_Handler + + .weak COMP4_Handler + .thumb_set COMP4_Handler,Default_Handler + + .weak COMP5_Handler + .thumb_set COMP5_Handler,Default_Handler + + .weak COMP6_Handler + .thumb_set COMP6_Handler,Default_Handler + + .weak ICACHE_Handler + .thumb_set ICACHE_Handler,Default_Handler + + .weak DCACHE_Handler + .thumb_set DCACHE_Handler,Default_Handler + + .weak UART7_Handler + .thumb_set UART7_Handler,Default_Handler + +/************************ (C) COPYRIGHT Fremontmicro *****END OF FILE****/ + diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/iar/linker/ft32f407xe_flash.icf b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/iar/linker/ft32f407xe_flash.icf new file mode 100644 index 00000000000..ae5a7f57f86 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/iar/linker/ft32f407xe_flash.icf @@ -0,0 +1,34 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x08000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x08000000; +define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000; +define symbol __ICFEDIT_region_RAM_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_CCMRAM_start__ = 0x10000000; +define symbol __ICFEDIT_region_CCMRAM_end__ = 0x1000FFFF; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x400; +define symbol __ICFEDIT_size_heap__ = 0x200; +/**** End of ICF editor section. ###ICF###*/ + + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; +define region CCMRAM_region = mem:[from __ICFEDIT_region_CCMRAM_start__ to __ICFEDIT_region_CCMRAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/iar/startup_ft32f407xe.s b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/iar/startup_ft32f407xe.s new file mode 100644 index 00000000000..b768cca602e --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/iar/startup_ft32f407xe.s @@ -0,0 +1,742 @@ +;******************************************************************************* +;* File Name : startup_ft32f407xe.s +;* Author : MCD Application Team +;* Description : FT32F407xE devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* @attention +;* +;* Copyright (c) 2006-2025 Fremontmicro. +;* All rights reserved. +;* +;* This software component is licensed by FMD under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MemManage_Handler + DCD BusFault_Handler ; BusFault_Handler + DCD UsageFault_Handler ; UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; DebugMon_Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_Handler ; 16+ 0: Window Watchdog + DCD PVD_Handler ; 16+ 1: PVD PROG VDDIO Handler + DCD TAMP_STAMP_Handler ; 16+ 2: TAMP and STAMP Handler + DCD RTC_Handler ; 16+ 3: RTC Handler + DCD FLASH_Handler ; 16+ 4: FLASH Handler + DCD RCC_Handler ; 16+ 5: RCC Handler + DCD EXTI0_Handler ; 16+ 6: EXTI 0 handler + DCD EXTI1_Handler ; 16+ 7: EXTI 1 Handler + DCD EXTI2_Handler ; 16+ 8: EXTI 2 Handler + DCD EXTI3_Handler ; 16+ 9: EXTI 3 Handler + DCD EXTI4_Handler ; 16+10: EXTI 4 Handler + DCD DMA1_CH0_Handler ; 16+11: DMA1 CH0 Handler + DCD DMA1_CH1_Handler ; 16+12: DMA1 CH1 Handler + DCD DMA1_CH2_Handler ; 16+13: DMA1 CH2 Handler + DCD DMA1_CH3_Handler ; 16+14: DMA1 CH3 Handler + DCD DMA1_CH4_Handler ; 16+15: DMA1 CH4 Handler + DCD DMA1_CH5_Handler ; 16+16: DMA1 CH5 Handler + DCD DMA1_CH6_Handler ; 16+17: DMA1 CH6 Handler + DCD ADC_Handler ; 16+18: ADC Handler + DCD CAN1_Handler ; 16+19: FDxCAN1 Handler + DCD CAN2_Handler ; 16+20: FDxCAN2 Handler + DCD CAN3_Handler ; 16+21: FDxCAN3 Handler + DCD CAN4_Handler ; 16+22: FDxCAN4 Handler + DCD EXTI9_5_Handler ; 16+23: EXTI[9:5] Handler + DCD TIM1_BRK_TIM9_Handler ; 16+24: TIM1 BRK and TIM9 Handler + DCD TIM1_UP_TIM1O_Handler ; 16+25: TIM1 UP and TIM10 Handler + DCD TIM1_TRG_COM_TIM11_Handler ; 16+26: TIM1 TRG/COM and TIM10 Hand + DCD TIM1_CC_Handler ; 16+27: TIM1 CC Handler + DCD TIM2_Handler ; 16+28: TIM2 Handler + DCD TIM3_Handler ; 16+29: TIM3 Handler + DCD TIM4_Handler ; 16+30: TIM4 Handler + DCD I2C1_Handler ; 16+31: I2C1 Handler + DCD I2C2_Handler ; 16+32: I2C2 Handler + DCD QSPI_Handler ; 16+33: QSPI Handler + DCD SPI1_Handler ; 16+34: SPI1 Handler + DCD SPI2_Handler ; 16+35: SPI2 Handler + DCD USART1_Handler ; 16+36: USART1 Handler + DCD USART2_Handler ; 16+37: USART2 Handler + DCD USART3_Handler ; 16+38: USART3 Handler + DCD EXTI15_10_Handler ; 16+39: EXTI[15:10] Handler + DCD RTCAlarm_Handler ; 16+40: RTC Alarm Handler + DCD OTG_FS_WKUP_Handler ; 16+41: Connect EXTI USB OTG WKUP H + DCD TIM8_BRK_TIM12_Handler ; 16+42: TIM8 BRK and TIM12 Handler + DCD TIM8_UP_TIM13_Handler ; 16+43: TIM8 UP and TIM13 Handler + DCD TIM8_TRG_COM_TIM14_Handler ; 16+44: TIM8 TRG/COM and TIM14 Hand + DCD TIM8_CC_Handler ; 16+45: TIM8 CC Handler + DCD DMA1_CH7_Handler ; 16+46: DMA1 CH7 Handler + DCD FMC_Handler ; 16+47: FMC Handler + DCD SDIO_Handler ; 16+48: SDIO Handler + DCD TIM5_Handler ; 16+49: TIM5 Handler + DCD SPI3_Handler ; 16+50: SPI3 Handler + DCD UART4_Handler ; 16+51: UART4 Handler + DCD UART5_Handler ; 16+52: UART5 Handler + DCD TIM6_DAC_Handler ; 16+53: TIM6 DAC Handler + DCD TIM7_Handler ; 16+54: TIM7 Handler + DCD DMA2_CH0_Handler ; 16+55: DMA2 CH0 Handler + DCD DMA2_CH1_Handler ; 16+56: DMA2 CH1 Handler + DCD DMA2_CH2_Handler ; 16+57: DMA2 CH2 Handler + DCD DMA2_CH3_Handler ; 16+58: DMA2 CH3 Handler + DCD DMA2_CH4_Handler ; 16+59: DMA2 CH4 Handler + DCD OTG_FS_Handler ; 16+60: OTG FS Handler + DCD DMA2_CH5_Handler ; 16+61: DMA2 CH5 Handler + DCD DMA2_CH6_Handler ; 16+62: DMA2 CH6 Handler + DCD DMA2_CH7_Handler ; 16+63: DMA2 CH7 Handler + DCD USART6_Handler ; 16+64: USART6 Handler + DCD I2C3_Handler ; 16+65: I2C3 Handler + DCD OTG_HS_EP1_OUT_Handler ; 16+66: OTG HS EP1OUT Handler + DCD OTG_HS_EP1_IN_Handler ; 16+67: OTG HS EP1IN Handler + DCD OTG_HS_WKUP_Handler ; 16+68: OTG HS WKUP Handler + DCD OTG_HS_Handler ; 16+69: OTG HS Handler + DCD RNG_Handler ; 16+70: RNG Handler + DCD FPU_Handler ; 16+71: FPU Handler + DCD CRS_Handler ; 16+72: CRS Handler + DCD SPDIF_Handler ; 16+73: SPDIF Handler + DCD SSI_AC97_Handler ; 16+74: SSI_AC97 Handler + DCD ETH_WKUP_Handler ; 16+75: ETH_WKUP Handler + DCD LPUART_Handler ; 16+76: LPUART Handler + DCD LPTIM_Handler ; 16+77: LPTIM Handler + DCD ETH_SBD_Handler ; 16+78: ETH_SBD Handler + DCD ETH_PERCHTX_Handler ; 16+79: ETH_PERCHTX Handler + DCD ETH_PERCHRX_Handler ; 16+80: ETH_PERCHRX Handler + DCD EPWM1_Handler ; 16+81: EPWM1 Handler + DCD EPWM1_TZ_Handler ; 16+82: EPWM1 TZ Handler + DCD EPWM2_Handler ; 16+83: EPWM2 Handler + DCD EPWM2_TZ_Handler ; 16+84: EPWM2 TZ Handler + DCD EPWM3_Handler ; 16+85: EPWM3 Handler + DCD EPWM3_TZ_Handler ; 16+86: EPWM3 TZ Handler + DCD EPWM4_Handler ; 16+87: EPWM4 Handler + DCD EPWM4_TZ_Handler ; 16+88: EPWM4 TZ Handler + DCD ECAP_Handler ; 16+89: ECAP Handler + DCD EQEP_Handler ; 16+90: EQEP Handler + DCD DLL_CAL_Handler ; 16+91: DLL CAL Handler + DCD COMP1_Handler ; 16+92: COMP1 Handler + DCD COMP2_Handler ; 16+93: COMP2 Handler + DCD COMP3_Handler ; 16+94: COMP3 Handler + DCD COMP4_Handler ; 16+95: COMP4 Handler + DCD COMP5_Handler ; 16+96: COMP5 Handler + DCD COMP6_Handler ; 16+97: COMP6 Handler + DCD ICACHE_Handler ; 16+98: ICACHE Handler + DCD DCACHE_Handler ; 16+99: DCACHE Handler + DCD UART7_Handler ; 16+100: UART7 Handler + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_Handler + B WWDG_Handler + + PUBWEAK PVD_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_Handler + B PVD_Handler + + PUBWEAK TAMP_STAMP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_Handler + B TAMP_STAMP_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Handler + B RTC_Handler + + PUBWEAK FLASH_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_Handler + B FLASH_Handler + + PUBWEAK RCC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_Handler + B RCC_Handler + + PUBWEAK EXTI0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_Handler + B EXTI0_Handler + + PUBWEAK EXTI1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_Handler + B EXTI1_Handler + + PUBWEAK EXTI2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_Handler + B EXTI2_Handler + + PUBWEAK EXTI3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_Handler + B EXTI3_Handler + + PUBWEAK EXTI4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_Handler + B EXTI4_Handler + + PUBWEAK DMA1_CH0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH0_Handler + B DMA1_CH0_Handler + + PUBWEAK DMA1_CH1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH1_Handler + B DMA1_CH1_Handler + + PUBWEAK DMA1_CH2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH2_Handler + B DMA1_CH2_Handler + + PUBWEAK DMA1_CH3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH3_Handler + B DMA1_CH3_Handler + + PUBWEAK DMA1_CH4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH4_Handler + B DMA1_CH4_Handler + + PUBWEAK DMA1_CH5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH5_Handler + B DMA1_CH5_Handler + + PUBWEAK DMA1_CH6_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH6_Handler + B DMA1_CH6_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC_Handler + B ADC_Handler + + PUBWEAK CAN1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN1_Handler + B CAN1_Handler + + PUBWEAK CAN2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN2_Handler + B CAN2_Handler + + PUBWEAK CAN3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN3_Handler + B CAN3_Handler + + PUBWEAK CAN4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN4_Handler + B CAN4_Handler + + PUBWEAK EXTI9_5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_Handler + B EXTI9_5_Handler + + PUBWEAK TIM1_BRK_TIM9_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM9_Handler + B TIM1_BRK_TIM9_Handler + + PUBWEAK TIM1_UP_TIM1O_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM1O_Handler + B TIM1_UP_TIM1O_Handler + + PUBWEAK TIM1_TRG_COM_TIM11_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM11_Handler + B TIM1_TRG_COM_TIM11_Handler + + PUBWEAK TIM1_CC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_Handler + B TIM1_CC_Handler + + PUBWEAK TIM2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_Handler + B TIM2_Handler + + PUBWEAK TIM3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_Handler + B TIM3_Handler + + PUBWEAK TIM4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_Handler + B TIM4_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK I2C2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_Handler + B I2C2_Handler + + PUBWEAK QSPI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +QSPI_Handler + B QSPI_Handler + + PUBWEAK SPI1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_Handler + B SPI1_Handler + + PUBWEAK SPI2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_Handler + B SPI2_Handler + + PUBWEAK USART1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_Handler + B USART1_Handler + + PUBWEAK USART2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_Handler + B USART2_Handler + + PUBWEAK USART3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_Handler + B USART3_Handler + + PUBWEAK EXTI15_10_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_Handler + B EXTI15_10_Handler + + PUBWEAK RTCAlarm_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +RTCAlarm_Handler + B RTCAlarm_Handler + + PUBWEAK OTG_FS_WKUP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_WKUP_Handler + B OTG_FS_WKUP_Handler + + PUBWEAK TIM8_BRK_TIM12_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_TIM12_Handler + B TIM8_BRK_TIM12_Handler + + PUBWEAK TIM8_UP_TIM13_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_TIM13_Handler + B TIM8_UP_TIM13_Handler + + PUBWEAK TIM8_TRG_COM_TIM14_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_TIM14_Handler + B TIM8_TRG_COM_TIM14_Handler + + PUBWEAK TIM8_CC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_Handler + B TIM8_CC_Handler + + PUBWEAK DMA1_CH7_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_CH7_Handler + B DMA1_CH7_Handler + + PUBWEAK FMC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +FMC_Handler + B FMC_Handler + + PUBWEAK SDIO_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SDIO_Handler + B SDIO_Handler + + PUBWEAK TIM5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM5_Handler + B TIM5_Handler + + PUBWEAK SPI3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_Handler + B SPI3_Handler + + PUBWEAK UART4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_Handler + B UART4_Handler + + PUBWEAK UART5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_Handler + B UART5_Handler + + PUBWEAK TIM6_DAC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_Handler + B TIM6_DAC_Handler + + PUBWEAK TIM7_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_Handler + B TIM7_Handler + + PUBWEAK DMA2_CH0_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH0_Handler + B DMA2_CH0_Handler + + PUBWEAK DMA2_CH1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH1_Handler + B DMA2_CH1_Handler + + PUBWEAK DMA2_CH2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH2_Handler + B DMA2_CH2_Handler + + PUBWEAK DMA2_CH3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH3_Handler + B DMA2_CH3_Handler + + PUBWEAK DMA2_CH4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH4_Handler + B DMA2_CH4_Handler + + PUBWEAK OTG_FS_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_FS_Handler + B OTG_FS_Handler + + PUBWEAK DMA2_CH5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH5_Handler + B DMA2_CH5_Handler + + PUBWEAK DMA2_CH6_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH6_Handler + B DMA2_CH6_Handler + + PUBWEAK DMA2_CH7_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_CH7_Handler + B DMA2_CH7_Handler + + PUBWEAK USART6_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +USART6_Handler + B USART6_Handler + + PUBWEAK I2C3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C3_Handler + B I2C3_Handler + + PUBWEAK OTG_HS_EP1_OUT_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_OUT_Handler + B OTG_HS_EP1_OUT_Handler + + PUBWEAK OTG_HS_EP1_IN_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_EP1_IN_Handler + B OTG_HS_EP1_IN_Handler + + PUBWEAK OTG_HS_WKUP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_WKUP_Handler + B OTG_HS_WKUP_Handler + + PUBWEAK OTG_HS_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +OTG_HS_Handler + B OTG_HS_Handler + + PUBWEAK RNG_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +RNG_Handler + B RNG_Handler + + PUBWEAK FPU_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_Handler + B FPU_Handler + + PUBWEAK CRS_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +CRS_Handler + B CRS_Handler + + PUBWEAK SPDIF_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SPDIF_Handler + B SPDIF_Handler + + PUBWEAK SSI_AC97_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SSI_AC97_Handler + B SSI_AC97_Handler + + PUBWEAK ETH_WKUP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_WKUP_Handler + B ETH_WKUP_Handler + + PUBWEAK LPUART_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +LPUART_Handler + B LPUART_Handler + + PUBWEAK LPTIM_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +LPTIM_Handler + B LPTIM_Handler + + PUBWEAK ETH_SBD_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_SBD_Handler + B ETH_SBD_Handler + + PUBWEAK ETH_PERCHTX_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_PERCHTX_Handler + B ETH_PERCHTX_Handler + + PUBWEAK ETH_PERCHRX_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ETH_PERCHRX_Handler + B ETH_PERCHRX_Handler + + PUBWEAK EPWM1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM1_Handler + B EPWM1_Handler + + PUBWEAK EPWM1_TZ_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM1_TZ_Handler + B EPWM1_TZ_Handler + + PUBWEAK EPWM2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM2_Handler + B EPWM2_Handler + + PUBWEAK EPWM2_TZ_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM2_TZ_Handler + B EPWM2_TZ_Handler + + PUBWEAK EPWM3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM3_Handler + B EPWM3_Handler + + PUBWEAK EPWM3_TZ_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM3_TZ_Handler + B EPWM3_TZ_Handler + + PUBWEAK EPWM4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM4_Handler + B EPWM4_Handler + + PUBWEAK EPWM4_TZ_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EPWM4_TZ_Handler + B EPWM4_TZ_Handler + + PUBWEAK ECAP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ECAP_Handler + B ECAP_Handler + + PUBWEAK EQEP_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +EQEP_Handler + B EQEP_Handler + + PUBWEAK DLL_CAL_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DLL_CAL_Handler + B DLL_CAL_Handler + + PUBWEAK COMP1_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_Handler + B COMP1_Handler + + PUBWEAK COMP2_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP2_Handler + B COMP2_Handler + + PUBWEAK COMP3_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP3_Handler + B COMP3_Handler + + PUBWEAK COMP4_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP4_Handler + B COMP4_Handler + + PUBWEAK COMP5_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP5_Handler + B COMP5_Handler + + PUBWEAK COMP6_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP6_Handler + B COMP6_Handler + + PUBWEAK ICACHE_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +ICACHE_Handler + B ICACHE_Handler + + PUBWEAK DCACHE_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DCACHE_Handler + B DCACHE_Handler + + PUBWEAK UART7_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UART7_Handler + B UART7_Handler + + END +;************************ (C) COPYRIGHT Fremontmicro *****END OF FILE***** diff --git a/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/system_ft32f4xx.c b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/system_ft32f4xx.c new file mode 100644 index 00000000000..6d2bb8f55fb --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/CMSIS/FT32F4xx/source/system_ft32f4xx.c @@ -0,0 +1,561 @@ +/** + ****************************************************************************** + * @file system_ft32f4xx.h + * @author FMD AE + * @brief CMSIS FT32F4xx Device Peripheral Access Layer Header File. + * @version V1.0.0 + * @data 2025-03-03 + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup FT32f4xx_system + * @{ + */ + +/** @addtogroup FT32f114xx_System_Private_Includes + * @{ + */ + +#include "ft32f4xx.h" + +/** + * @} + */ + +/** @addtogroup FT32f114xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FT32F114xx_System_Private_Defines + * @{ + */ + +// #define SYSCLK_FREQ_HSE HSI_VALUE +// #define SYSCLK_FREQ_105MHz 105000000 /* Value of Internal clk in Hz */ +// #define SYSCLK_FREQ_180MHz 180000000 /* Value of Internal clk in Hz */ +#define SYSCLK_FREQ_210MHz 210000000 /* Value of Internal clk in Hz */ +/** + * @} + */ + +/** @addtogroup FT32f114xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup FT32f114xx_System_Private_Variables + * @{ + */ +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ +#ifdef SYSCLK_FREQ_HSE + uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_105MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_105MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_180MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_180MHz; /*!< System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_210MHz + uint32_t SystemCoreClock = SYSCLK_FREQ_210MHz; /*!< System Clock Frequency (Core Clock) */ +#else /*!< HSI Selected as System Clock source */ + uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ +#endif +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup FT32f114xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE + static void SetSysClockToHSE(void); +#elif defined SYSCLK_FREQ_105MHz + static void SetSysClockTo105(void); +#elif defined SYSCLK_FREQ_180MHz + static void SetSysClockTo180(void); +#elif defined SYSCLK_FREQ_210MHz + static void SetSysClockTo210(void); +#endif +/** + * @} + */ + +/** @addtogroup FT32f114xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */ +#endif + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PREE2[2:0] and MCOSEL[2:0] bits */ + RCC->CFGR &= (uint32_t)0x80FFC00C; + + /* Reset HSEON, CSSON , PLLON and PLL2ON bits */ + RCC->CR &= (uint32_t)0xFAF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLR[2:0], PLLREN, PLLQ[3:0], PLLQEN, PLLP[2:0], + * PLLPEN, PLLSRC, PLLN[7:0], PLLM[4:0] bits */ + RCC->PLLCFGR &= (uint32_t)0xE0008020; + + /* Reset PLL2R[2:0], PLL2REN, PLL2Q[3:0], PLL2QEN, PLL2SRC, PLL2N[7:0] and PLL2M[4:0] bits */ + RCC->PLL2CFGR &= (uint32_t)0xE00F8020; + + /* Reset HSI48ON bit */ + RCC->CR2 &= (uint32_t)0xFFFEFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ + SetSysClock(); + + RCC->APB1ENR |= RCC_APB1ENR_CRSEN; + CRS->CR &= ~(0x3F << 8); + CRS->CR |= (((*(uint32_t*)0x1FFF0A28) & 0x3F) << 8); + RCC->APB1ENR &= ~RCC_APB1ENR_CRSEN; + + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN; + if ((VREFBUF->VREFBUF_CSR & 0x4) == 0x4) //2.5V + { + VREFBUF->VREFBUF_CCR = 0; + VREFBUF->VREFBUF_CCR = ((*(uint32_t*)0x1FFF0A20) & 0x3F00) >> 16; + ADC1->CALFACT = (*(uint32_t*)0x1FFF0A3C); + ADC2->CALFACT = (*(uint32_t*)0x1FFF0A40); + ADC3->CALFACT = (*(uint32_t*)0x1FFF0A44); + } + else // 2.048V + { + VREFBUF->VREFBUF_CCR = 0; + VREFBUF->VREFBUF_CCR = ((*(uint32_t*)0x1FFF0A20) & 0x3F); + ADC1->CALFACT = (*(uint32_t*)0x1FFF0A30); + ADC2->CALFACT = (*(uint32_t*)0x1FFF0A34); + ADC3->CALFACT = (*(uint32_t*)0x1FFF0A38); + } + RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN | RCC_APB2ENR_ADCEN); +} + +/** + * @brief Update SystemCoreClock according to Clock Register Values + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in FT32f4xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in FT32f4xx.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllm = 0, plln = 0, pllp = 0, pllvco = 0, pllsource = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x01: /* HSE used as system clock */ + SystemCoreClock = HSE_VALUE; + break; + case 0x02: /* PLL used as system clock */ + /* PLL_VCO = (HSI_VALUE / PLLM ) * PLLN ---------------------- + * SYSCLK = PLL_VCO / PLLP + * */ + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + plln = (RCC->PLLCFGR & RCC_PLLCFGR_PLLN >> 6); + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC >> 14); + + if (pllsource == 0) /* HSI uses as PLL clock source */ + { + + pllvco = (HSI_VALUE / pllm); + } + else /* HSE uses as PLL clock source */ + { + pllvco = (HSE_VALUE / pllm); + } + + if (RCC->PLLCFGR & RCC_PLLCFGR_PLLP >> 17) /* PLLP != 0 */ + { + pllp = (RCC->PLLCFGR & RCC_PLLCFGR_PLLP >> 17) + 1U; + } + else /* PLLP == 0 , prescaler is 2 */ + { + pllp = (RCC->PLLCFGR & RCC_PLLCFGR_PLLP >> 17) + 2U; + } + + pllvco = pllvco * plln ; + SystemCoreClock = pllvco / pllp; + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + + +/** + * @brief Configures the System clock frequency, HCLK, PCLK prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_105MHz + SetSysClockTo105(); +#elif defined SYSCLK_FREQ_180MHz + SetSysClockTo180(); +#elif defined SYSCLK_FREQ_210MHz + SetSysClockTo210(); +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + source (default after reset) */ +} + +#ifdef SYSCLK_FREQ_HSE +/** + * @brief Selects HSE as System clock source and configure HCLK, PCLK + * prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } + while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer and set Flash Latency */ + if (HSE_VALUE <= 30000000) /* clk <= 30MHz ,latancy=0 */ + { + FLASH->RDC = FLASH_ACR_PRFTBE | ((uint32_t)0x00000000); + } + else /* clk > 30MHz ,latancy=1 */ + { + FLASH->RDC = FLASH_ACR_PRFTBE | ((uint32_t)0x00000001); + } + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK1 = HCLK/2, PCLK2 = HCLK/2 */ + RCC->CFGR |= (uint32_t)(RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2); + + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSE) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} + +#elif defined SYSCLK_FREQ_105MHz +/** + * @brief Sets System clock frequency to 105MHz and configure HCLK, PCLK + * prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo105(void) +{ + __IO uint32_t StartUpCounter = 0, HSIStatus = 0; + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSI */ + RCC->CR |= ((uint32_t)RCC_CR_HSION); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CR & RCC_CR_HSIRDY; + StartUpCounter++; + } + while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSIRDY) != RESET) + { + HSIStatus = (uint32_t)0x01; + } + else + { + HSIStatus = (uint32_t)0x00; + } + + if (HSIStatus == (uint32_t)0x01) + { + + RCC->PLLCFGR |= (uint32_t)((105 << 6) | // PLLN=105 + RCC_PLLCFGR_PLLSRC_HSI | // Source : HSI + RCC_PLLCFGR_PLLPEN | // Enable PLLP + (8 << 0)) ; // PLLM=8, PLLPCLK=VCO/8 + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while (((RCC->CR) & (uint32_t)RCC_CR_PLLRDY) != (uint32_t)RCC_CR_PLLRDY) //wait PLLRDY + { + } + + /* Enable Prefetch Buffer(default is enable) and set Flash Latency */ + FLASH->RDC |= (uint32_t)(0x3 << 0); + + /* Select PLL as system clock source */ + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while (((RCC->CFGR) & (uint32_t)RCC_CFGR_SWS_PLL) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + +} +else +{ + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ +} +} +#elif defined SYSCLK_FREQ_180MHz +/** + * @brief Sets System clock frequency to 180MHz and configure HCLK, PCLK + * prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo180(void) +{ + __IO uint32_t StartUpCounter = 0, HSIStatus = 0; + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSI */ + RCC->CR |= ((uint32_t)RCC_CR_HSION); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CR & RCC_CR_HSIRDY; + StartUpCounter++; + } + while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSIRDY) != RESET) + { + HSIStatus = (uint32_t)0x01; + } + else + { + HSIStatus = (uint32_t)0x00; + } + + if (HSIStatus == (uint32_t)0x01) + { + + RCC->PLLCFGR |= (uint32_t)((45 << 6) | // PLLN=45 + RCC_PLLCFGR_PLLSRC_HSI | // Source : HSI + RCC_PLLCFGR_PLLPEN | // Enable PLLP + (2 << 0)) ; // PLLM=2, PLLPCLK=VCO/2 + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while (((RCC->CR) & (uint32_t)RCC_CR_PLLRDY) != (uint32_t)RCC_CR_PLLRDY) //wait PLLRDY + { + } + + /* Enable Prefetch Buffer(default is enable) and set Flash Latency */ + FLASH->RDC |= (uint32_t)(0x5 << 0); + + /* Select PLL as system clock source */ + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while (((RCC->CFGR) & (uint32_t)RCC_CFGR_SWS_PLL) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#elif defined SYSCLK_FREQ_210MHz +/** + * @brief Sets System clock frequency to 210MHz and configure HCLK, PCLK + * prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +static void SetSysClockTo210(void) +{ + __IO uint32_t StartUpCounter = 0, HSIStatus = 0; + + /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ + /* Enable HSI */ + RCC->CR |= ((uint32_t)RCC_CR_HSION); + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CR & RCC_CR_HSIRDY; + StartUpCounter++; + } + while ((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSIRDY) != RESET) + { + HSIStatus = (uint32_t)0x01; + } + else + { + HSIStatus = (uint32_t)0x00; + } + + if (HSIStatus == (uint32_t)0x01) + { + + RCC->PLLCFGR |= (uint32_t)((105 << 6) | // PLLN=105 + RCC_PLLCFGR_PLLSRC_HSI | // Source : HSI + RCC_PLLCFGR_PLLPEN | // Enable PLLP + (4 << 0)) ; // PLLM=4, PLLPCLK=VCO/2 + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while (((RCC->CR) & (uint32_t)RCC_CR_PLLRDY) != (uint32_t)RCC_CR_PLLRDY) //wait PLLRDY + { + } + + /* Enable Prefetch Buffer(default is enable) and set Flash Latency */ + FLASH->RDC |= (uint32_t)(0x6 << 0); + + /* Select PLL as system clock source */ + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while (((RCC->CFGR) & (uint32_t)RCC_CFGR_SWS_PLL) != (uint32_t)RCC_CFGR_SWS_PLL) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_adc.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_adc.h new file mode 100644 index 00000000000..e48a3c2fbbc --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_adc.h @@ -0,0 +1,1855 @@ +/** + ****************************************************************************** + * @file ft32f4xx_adc.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the ADC firmware + * library + * @version V1.0.0 + * @data 2025-04-08 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_ADC_H +#define __FT32F4XX_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup ADC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ADC group regular oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_OVS_RATIO */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_OVS_SHIFT */ + + uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. + This parameter can be a value of @ref ADC_OVS_DISCONT_MODE */ + + uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. + The oversampling is either temporary stopped or reset upon an injected + sequence interruption. + If oversampling is enabled on both regular and injected groups, this + parameter is discarded and forced to setting + "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed + during injection sequence). + This parameter can be a value of @ref ADC_OVS_SCOPE_REG */ +} ADC_OversamplingTypeDef; + + + +/** + * @brief ADC group injected oversampling structure definition + */ +typedef struct +{ + uint32_t Ratio; /*!< Configures the oversampling ratio. + This parameter can be a value of @ref ADC_OVS_RATIO */ + + uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. + This parameter can be a value of @ref ADC_OVS_SHIFT */ + +} ADC_InjOversamplingTypeDef; + + +/** + * @brief Structure definition of ADC instance. + * @note Parameters of this structure are shared within 3 scopes: + * - Scope entire ADC (affects ADC groups regular and injected): Resolution, DataAlign, + * GainCompensation, AutoDelayedConvMode. + * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, ExternalTrigConv, ExternalTrigConvEdge, + * DiscontinuousConvMode, NbrOfDiscConversion, DMAMode, Overrun, OversamplingMode, Oversampling, + * SamplingMode. + * - Scope ADC group injected: InjectedDiscontinuousConvMode, AutoInjectedConv, QueueInjectedContext, + * QueueMode. + */ +typedef struct +{ + uint32_t Resolution; /*!< Selects the resolution of the conversion. + This parameter can be a value of @ref ADC_Resolution */ + + FunctionalState ContinuousConvMode; /*!< Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint32_t GainCompensation; /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion + data, based on following formula: + DATA = DATA(raw) * (gain compensation coef) / 4096 + "2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa + Gain step is 1/4096 = 0.000244 + Gain range is 0.0000 to 3.999756 + This parameter value can be + 0 Gain compensation will be disabled and coefficient set to 0 + 1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified + value + Note: Gain compensation when enabled is applied to all channels. */ + + uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group + sequencer. + This parameter must be a number between Min_Data = 1 and Max_Data = 16. + Note: This parameter must be modified when no conversion is on going on regular + group (ADC disabled, or ADC stop conversion). */ + + uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the + trigger of a regular group. This parameter can be a value + of @ref ADC_regular_external_trigger_edge */ + + uint32_t ExternalTrigConv; /*!< Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC12_external_trigger_sources + or ADC3_external_trigger_sources */ + + FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed + in Complete-sequence/Discontinuous-sequence (main sequence subdivided in + successive parts). + Discontinuous mode is used only if sequencer is enabled. If sequencer + is disabled, this parameter is discarded. + Discontinuous mode can be enabled only if continuous mode is disabled. + If continuous mode is enabled, this parameter setting is discarded. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence + of ADC group regular (parameter NbrOfConversion) will be subdivided. + If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. + This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ + + uint32_t DMAMode; /*!< Specify whether the DMA requests are performed in one shot mode (DMA + transfer stops when number of conversions is reached) or in continuous + mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be set to ADC_DMAMODE_ONESHOT or ADC_DMAMODE_CIRCULAR. + Note: In continuous mode, DMA must be configured in circular mode. + Otherwise an overrun will be triggered when DMA buffer maximum + pointer is reached. */ + + FunctionalState AutoDelayedConvMode; /*!< Enables or disables the Wait conversion mode. + When the CPU clock is not fast enough to manage the data rate, a + Hardware delay can be introduced between ADC conversions to reduce + this data rate. + The Hardware delay is inserted after each conversions and until the + previous data is read from the ADC data register + This is a way to automatically adapt the speed of the ADC to the speed + of the system which will read the data. + Any hardware triggers wich occur while a conversion is on going or + while the automatic Delay is applied are ignored + ADCx: where x can be 1/2/3 to select the ADCx peripheral. + NewState: new state of the ADCx Auto-Delay. + This parameter can be: ENABLE or DISABLE. */ + + uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). + This parameter applies to ADC group regular only. + This parameter can be set to ADC_OVR_MODE_PRESERVED or ADC_OVR_MODE_OVERWRITTEN. + Note: In case of overrun set to data preserved and usage with programming model + with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of + conversion flags, this induces the release of the preserved data. If + needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), + placed in user program code (called before end of conversion flags clear) + Note: Error reporting with respect to the conversion mode: + - Usage with ADC conversion by polling for event or interruption: Error is + reported only if overrun is set to data preserved. If overrun is set to + data overwritten, user can willingly not read all the converted data, + this is not considered as an erroneous case. + - Usage with ADC conversion by DMA: Error is reported whatever overrun + setting (DMA is expected to process all data from data register). */ + + + FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected + is performed in Complete-sequence/Discontinuous-sequence + (main sequence subdivided in successive parts). + Discontinuous mode can be enabled only if continuous mode is disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). + Note: For injected group, discontinuous mode converts the sequence + channel by channel (discontinuous length fixed to 1 rank). */ + + FunctionalState AutoInjectedConvMode; /*!< Enables or disables the selected ADC group injected automatic conversion + after regular one + This parameter can be set to ENABLE or DISABLE. + Note: To use Automatic injected conversion, discontinuous mode must + be disabled ('DiscontinuousConvMode' and + 'InjectedDiscontinuousConvMode' set to DISABLE) + Note: To use Automatic injected conversion, injected group external + triggers must be disabled ('ExternalTrigInjecConv' set to + ADC_INJECTED_SOFTWARE_START) */ + + FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. + This parameter can be set to ENABLE or DISABLE. + If context queue is enabled, injected sequencer&channels configurations + are queued on up to 2 contexts. If a new injected context is set when + queue is full, error is triggered by interruption. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). */ + + FunctionalState QueueMode; /*!< Specifies how an empty Queue is managed. + This parameter can be set to JSQR mode 0 or JSQR mode 1. + JSQR mode 0 : The Queue is never empty and maintains the last written + configuration into JSQR. + JSQR mode 1 : The Queue can be empty and when this occurs, the software + and hardware triggers of the injected sequence are both + internally disabled just after the completion of the last + valid injected sequence. + Note: The software is allowed to write this bit only when JADSTART=0 + (which ensures that no injected conversion is ongoing). + When dual mode is enabled (Dual bits in ADC_Common->CCR register + are not equal to zero), the bit JQM of the slave ADC is no more + writable and its content is equal to the bit JQM of the master + ADC. */ + + uint32_t SamplingMode; /*!< Select the sampling mode to be used for ADC group regular conversion. + This parameter can be a value of @ref ADC_regular_sampling_mode */ + + uint32_t SamplingPlusTime; /*!< Addition of one clock cycle to the sampling time value to be set + for the ADC_SMPRx registers. + This parameter can be a value of @ref ADC_sampling_plus_times + Unit: ADC clock cycles. + Minimum sampling clock period, can select 1.5, 2.5, 3.5 or 4.5 clock cycles. + Note: To make sure no conversion is ongoing, the software is allowed + to write this bit only when this bit only when ADSTART=0 and + JADSTART=0 */ + + FunctionalState OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared). */ + + ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. + Caution: this setting overwrites the previous oversampling configuration + if oversampling is already enabled. + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared).*/ + +} ADC_InitTypeDef; + + +/** + * @brief ADC group regular Channel Init structure definition + */ +typedef struct +{ + uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. + This parameter can be a value of @ref ADC_channels + Note: Depending on devices and ADC instances, some channels may not be available + on device package pins. Refer to device datasheet for channels + availability. */ + + uint32_t Rank; /*!< Specify the rank in the regular group sequencer. + This parameter can be a value of @ref ADC_reg_seq_ranks + Note: to disable a channel or change order of conversion sequencer, rank + containing a previous channel setting can be overwritten by the new channel + setting (or parameter number of conversions adjusted) */ + + uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles + Conversion time is the addition of sampling time and processing time + This parameter can be a value of @ref ADC_sampling_times + Caution: This parameter applies to a channel that can be used into regular + and/or injected group. It overwrites the last setting. + Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...), + sampling time constraints must be respected (sampling time can be adjusted + in function of ADC clock frequency and sampling time setting). + Refer to device datasheet for timings values. */ + + uint32_t SingleDiff; /*!< Select single-ended or differential input. + In differential mode: Differential measurement is carried out between the + selected channel 'i' (positive input) and channel 'i+1' (negative input). + Only channel 'i' has to be configured, channel 'i+1' is configured automatically + This parameter must be a value of @ref ADC_channel_single_diff_ending + Caution: This parameter applies to a channel that can be used in a regular + and/or injected group. + It overwrites the last setting. + Note: Refer to Reference Manual to ensure the selected channel is available in + differential mode. + Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is + not usable separately. + Note: This parameter must be modified when ADC is disabled (before ADC start + conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error + reporting (as it can be the expected behavior in case of another parameter + update on the fly) */ + + uint32_t OffsetNumber; /*!< Select the offset number + This parameter can be a value of @ref ADC_offset_number + Caution: Only one offset is allowed per channel. This parameter overwrites the + last setting. */ + + uint32_t Offset; /*!< Define the offset to be applied on the raw converted data. + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter + must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + 0x3FF, 0xFF or 0x3F respectively. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion). */ + + uint32_t OffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive + sign) from or to the raw converted data. + This parameter can be a value of @ref ADC_OffsetSign. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion).*/ + + FunctionalState OffsetSaturation;/*!< Define if the offset should be saturated upon under or over flow. + This parameter value can be ENABLE or DISABLE. + Note: This parameter must be modified when no conversion is on going on both + regular and injected groups (ADC disabled, or ADC enabled without + continuous mode or external trigger that could launch a conversion). */ + +} ADC_ChannelConfTypeDef; + + +/** + * @brief ADC group injected Init structure definition + */ +typedef struct +{ + + uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group + injected sequencer. + To use the injected group sequencer and convert several ranks, parameter + 'ScanConvMode' must be enabled. + This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ + + uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. + This parameter can be a value of @ref ADC_channels + Note: Depending on devices and ADC instances, some channels may not be + available on device package pins. Refer to device datasheet for + channels availability. */ + + uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. + This parameter must be a value of @ref ADC_injected_seq_ranks. + Note: to disable a channel or change order of conversion sequencer, + rank containing a previous channel setting can be overwritten by + the new channel setting (or parameter number of conversions + adjusted) */ + + uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. + This parameter can be a value of @ref ADC_injected_external_trigger_edge. + If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter + is discarded. */ + + uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of + injected group. + If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled + and software trigger is used instead. + This parameter can be a value of @ref ADC12_injected_external_trigger_sources or + ADC3_injected_external_trigger_sources. */ + + + + FunctionalState InjectedOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. + This parameter can be set to ENABLE or DISABLE. + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared). */ + + ADC_InjOversamplingTypeDef InjectedOversampling; /*!< Specifies the Oversampling parameters. + Caution: this setting overwrites the previous oversampling + configuration if oversampling already enabled. + Note: This parameter can be modified only if there is no + conversion is ongoing (both ADSTART and JADSTART cleared).*/ + + uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. + Unit: ADC clock cycles. + Conversion time is the addition of sampling time and processing time + (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, + 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). + This parameter can be a value of @ref ADC_sampling_times. + Caution: This parameter applies to a channel that can be used in a + regular and/or injected group. It overwrites the last setting. + Note: In case of usage of internal measurement channels (VrefInt, ...), + sampling time constraints must be respected (sampling time can be + adjusted in function of ADC clock frequency and sampling time + setting). Refer to device datasheet for timings values. */ + + uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. + In differential mode: Differential measurement is between the selected + channel 'i' (positive input) and channel 'i+1' (negative input). + Only channel 'i' has to be configured, channel 'i+1' is configured + automatically. + This parameter must be a value of + @ref ADC_channel_single_diff_ending. + Caution: This parameter applies to a channel that can be used in a + regular and/or injected group. It overwrites the last setting. + Note: Refer to Reference Manual to ensure the selected channel is + available in differential mode. + Note: When configuring a channel 'i' in differential mode, the channel + 'i+1' is not usable separately. + Note: This parameter must be modified when ADC is disabled (before ADC + start conversion or after ADC stop conversion). + If ADC is enabled, this parameter setting is bypassed without error + reporting (as it can be the expected behavior in case of another + parameter update on the fly) */ + + uint32_t InjectedOffsetNumber; /*!< Selects the offset number. + This parameter can be a value of @ref ADC_offset_number. + Caution: Only one offset is allowed per channel. This parameter + overwrites the last setting. */ + + uint32_t InjectedOffset; /*!< Defines the offset to be applied on the raw converted data. + Offset value must be a positive number. + Depending of ADC resolution selected (12, 10, 8 or 6 bits), this + parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, + 0x3FF, 0xFF or 0x3F respectively. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC enabled + without continuous mode or external trigger that could launch a + conversion). */ + + uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added + (positive sign) from or to the raw converted data. + This parameter can be a value of @ref ADCEx_OffsetSign. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC + enabled without continuous mode or external trigger that could + launch a conversion). */ + + FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. + This parameter value can be ENABLE or DISABLE. + Note: This parameter must be modified when no conversion is on going + on both regular and injected groups (ADC disabled, or ADC enabled + without continuous mode or external trigger that could launch a + conversion). */ +} ADC_InjectedConfTypeDef; + + +/** + * @brief Structure definition of ADC analog watchdog + * @note The setting of these parameters by function ADC_AnalogWDGConfig() is conditioned to ADC state. + * ADC state can be either: + * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion + on going on ADC groups regular and injected. + * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and + injected groups. + */ +typedef struct +{ + uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. + For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels + by setting parameter 'WatchdogMode') + For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls + of 'ADC_AnalogWDGConfig()' for each channel) + This parameter can be a value of @ref ADCx_AnalogWatchdog_X_Selection. */ + + uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. + For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all + channels, ADC groups regular and-or injected. + For Analog Watchdog 2 and 3: No need to configure the ADC analog watchdog mode. + This parameter can be a value of @ref ADCx_AnalogWatchdog_1_Channel_Mode_Selection. */ + + uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. + For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' + is configured on single channel (only 1 channel can be + monitored). + This parameter can be a value of @ref ADC_channels for Analog Watchdog 1. + For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, + call successively the function ADC_AnalogWDGConfig() + for each channel to be added (or removed with value + 'ADC_ANALOGWATCHDOG_NONE'). + This parameter can be a value of @ref ADCx_AnalogWatchdog_2_3_Channel_Selection + for Analog Watchdog 2 and 3. */ + + FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits). For Analog watchdog 1, this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. For Analog watchdog 2 and 3, this parameter must be a + number between Min_Data = 0x00 and Max_Data = 0xFF. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [11:4] (12 most significant bits). */ + + uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. + Depending of ADC resolution selected (12, 10, 8 or 6 bits). For Analog watchdog 1, this parameter must be a + number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F + respectively. For Analog watchdog 2 and 3, this parameter must be a + number between Min_Data = 0x00 and Max_Data = 0xFF. + Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC + resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + impacted: the comparison of analog watchdog thresholds is done on + oversampling final computation (after ratio and shift application): + ADC data register bitfield [11:4] (12 most significant bits).*/ + + uint32_t FilteringConfig; /*!< Specify whether filtering should be use and the number of samples to consider. + Before setting flag or raising interrupt, analog watchdog can wait to have several + consecutive out-of-window samples. This parameter allows to configure this number. + This parameter only applies to Analog watchdog 1. For others, use value + ADC_AWD_FILTERING_NONE. + This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */ +} ADC_AnalogWDGConfTypeDef; + + + +/** + * @brief Structure definition of ADC multimode + * @note The setting of these parameters by function ADCx_MultiModeConfigChannel() is conditioned by ADCs state + * (both Master and Slave ADCs). + * Both Master and Slave ADCs must be disabled. + */ +typedef struct +{ + uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. + This parameter can be a value of @ref ADC_MULTI_MODE. */ + + uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: + selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel + (one DMA channel for both ADC, DMA of ADC master). + This parameter can be a value of @ref ADC_MULTI_DMA_TRANSFER_RESOLUTION. */ + + uint32_t DMAMode; /*!< Specify whether the DMA requests are performed in one shot mode (DMA + transfer stops when number of conversions is reached) or in continuous + mode (DMA transfer unlimited, whatever number of conversions). + This parameter can be a value of @ref ADC_MULTI_DMA_MODE. + Note: In continuous mode, DMA must be configured in circular mode. + Otherwise an overrun will be triggered when DMA buffer maximum + pointer is reached. */ + + uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. + This parameter can be a value of @ref ADC_MULTI_TWOSMP_DELAY. + Delay range from 1 to 16 clock cycles */ +} ADC_MultiModeTypeDef; + + + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup ADC_Exported_Constants + * @{ + */ +#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \ + ((PERIPH) == ADC2) || \ + ((PERIPH) == ADC3)) +/** + * @} + */ + +/** @defgroup ADC_ClockMode - ClockPreScaler + * @{ + */ +#define ADC_CLOCK_SYNC_HCLK_DIV1 (uint32_t)ADC_CCR_CKMODE_0 /*!< Synchronous clock mode no divided */ +#define ADC_CLOCK_SYNC_HCLK_DIV2 (uint32_t)ADC_CCR_CKMODE_1 /*!< Synchronous clock mode divided by 2 */ +#define ADC_CLOCK_SYNC_HCLK_DIV4 (uint32_t)ADC_CCR_CKMODE /*!< Synchronous clock mode divided by 4 */ + +#define ADC_CLOCK_ASYNC_DIV1 (uint32_t)0x00000000 /*!< ADC asynchronous clock without prescaler */ +#define ADC_CLOCK_ASYNC_DIV2 ((uint32_t)ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2 */ +#define ADC_CLOCK_ASYNC_DIV4 ((uint32_t)ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 4 */ +#define ADC_CLOCK_ASYNC_DIV6 ((uint32_t)(ADC_CCR_PRESC_0|ADC_CCR_PRESC_1)) /*!< ADC asynchronous clock with prescaler division by 6 */ +#define ADC_CLOCK_ASYNC_DIV8 ((uint32_t)ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with prescaler division by 8 */ +#define ADC_CLOCK_ASYNC_DIV10 ((uint32_t)(ADC_CCR_PRESC_0|ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock with prescaler division by 10 */ +#define ADC_CLOCK_ASYNC_DIV12 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock with prescaler division by 12 */ +#define ADC_CLOCK_ASYNC_DIV16 ((uint32_t)(ADC_CCR_PRESC_0|ADC_CCR_PRESC_1|ADC_CCR_PRESC_2)) /*!< ADC asynchronous clock with prescaler division by 16 */ +#define ADC_CLOCK_ASYNC_DIV32 ((uint32_t)ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32 */ +#define ADC_CLOCK_ASYNC_DIV64 ((uint32_t)(ADC_CCR_PRESC_0|ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock with prescaler division by 64 */ +#define ADC_CLOCK_ASYNC_DIV128 ((uint32_t)(ADC_CCR_PRESC_1|ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock with prescaler division by 128 */ +#define ADC_CLOCK_ASYNC_DIV256 ((uint32_t)(ADC_CCR_PRESC_0|ADC_CCR_PRESC_1|ADC_CCR_PRESC_3)) /*!< ADC asynchronous clock with prescaler division by 256 */ + +#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_HCLK_DIV1 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_HCLK_DIV2 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_HCLK_DIV4 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ + ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256 ) ) +/** + * @} + */ + +/** @defgroup ADC_Resolution + * @{ + */ +#define ADC_RESOLUTION_6B ((uint32_t)0x00000000) /*!< ADC resolution 6 bits */ +#define ADC_RESOLUTION_8B ADC_CFGR1_RES_0 /*!< ADC resolution 8 bits */ +#define ADC_RESOLUTION_10B ADC_CFGR1_RES_1 /*!< ADC resolution 10 bits */ +#define ADC_RESOLUTION_12B ADC_CFGR1_RES /*!< ADC resolution 12 bits */ + +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B)) +/** + * @} + */ + +/** @defgroup ADC_data_align ADC conversion data alignment + * @{ + */ +#define ADC_DATAALIGN_RIGHT (uint32_t)0x00000000 /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define ADC_DATAALIGN_LEFT ADC_CFGR1_ALIGN /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ + +#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ + ((ALIGN) == ADC_DATAALIGN_LEFT)) +/** + * @} + */ + +/** @efgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) + * @{ + */ +#define ADC_SOFTWARE_START ((uint32_t)0x00000000) /*!< ADC group regular trigger + disabled (SW start)*/ +#define ADC_EXTERNALTRIGCONVEDGE_RISING ADC_CFGR1_EXTEN_0 /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ADC_CFGR1_EXTEN_1 /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ADC_CFGR1_EXTEN /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ + +#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_SOFTWARE_START ) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING ) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING ) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) +/** + * @} + */ + +/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) + * @{ + */ +#define ADC_INJECTED_SOFTWARE_START ((uint32_t)0x00000000)/*!< Injected conversions trigger + disabled (SW start)*/ +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions trigger + polarity set to rising edge */ +#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions trigger + polarity set to falling edge */ +#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions trigger + polarity set to both rising and falling edges */ + +#define IS_ADC_EXTTRIG_INJEC_EDGE(EDGE) (((EDGE) == ADC_INJECTED_SOFTWARE_START ) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING ) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING)) +/** + * @} + */ + +/** @defgroup ADC12_external_trigger_sources for ADC1/2 regular channels conversion + * @{ + */ +#define ADC12_EXTERNALTRIG_TIM1_CC1 ((uint32_t)0x00000000) +#define ADC12_EXTERNALTRIG_TIM1_CC2 ((uint32_t)ADC_CFGR1_EXTSEL_0) +#define ADC12_EXTERNALTRIG_TIM1_CC3 ((uint32_t)ADC_CFGR1_EXTSEL_1) +#define ADC12_EXTERNALTRIG_TIM2_CC2 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1)) +#define ADC12_EXTERNALTRIG_TIM3_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) +#define ADC12_EXTERNALTRIG_TIM4_CC4 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_2)) +#define ADC12_EXTERNALTRIG_TIM8_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2)) +#define ADC12_EXTERNALTRIG_TIM8_TRGO2 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2)) +#define ADC12_EXTERNALTRIG_TIM1_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_3) +#define ADC12_EXTERNALTRIG_TIM1_TRGO2 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_3)) +#define ADC12_EXTERNALTRIG_TIM2_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_3)) +#define ADC12_EXTERNALTRIG_TIM4_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_3)) +#define ADC12_EXTERNALTRIG_TIM6_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC12_EXTERNALTRIG_TIM3_CC4 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC12_EXTERNALTRIG_EPWM1_SOCA ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC12_EXTERNALTRIG_EPWM2_SOCA ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC12_EXTERNALTRIG_EPWM3_SOCA ((uint32_t)ADC_CFGR1_EXTSEL_4) +#define ADC12_EXTERNALTRIG_EPWM3_SOCB ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_4)) +#define ADC12_EXTERNALTRIG_EPWM4_SOCA ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_4)) +#define ADC12_EXTERNALTRIG_EPWM4_SOCB ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_4)) +#define ADC12_EXTERNALTRIG_LPTIM_OUT ((uint32_t)(ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_4)) +#define ADC12_EXTERNALTRIG_TIM7_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_4)) +#define ADC12_EXTERNALTRIG_EXTI11 ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_4)) + +#define IS_ADC12_REGULAR_EXTTRIG_SOURCE(SOURCE) (((SOURCE) == ADC12_EXTERNALTRIG_TIM1_CC1 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM1_CC2 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM1_CC3 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM2_CC2 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM3_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM4_CC4 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM8_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM8_TRGO2 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM1_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM1_TRGO2 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM2_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM4_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM6_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM3_CC4 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_EPWM1_SOCA ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_EPWM2_SOCA ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_EPWM3_SOCA ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_EPWM3_SOCB ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_EPWM4_SOCA ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_EPWM4_SOCB ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_LPTIM_OUT ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_TIM7_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_EXTI11 ) ) +/** + * @} + */ + +/** @defgroup ADC3_external_trigger_sources for ADC3 regular channels conversion + * @{ + */ +#define ADC3_EXTERNALTRIG_TIM3_CC1 ((uint32_t)0x00000000) +#define ADC3_EXTERNALTRIG_TIM2_CC3 ((uint32_t)ADC_CFGR1_EXTSEL_0) +#define ADC3_EXTERNALTRIG_TIM1_CC3 ((uint32_t)ADC_CFGR1_EXTSEL_1) +#define ADC3_EXTERNALTRIG_TIM8_CC1 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1)) +#define ADC3_EXTERNALTRIG_TIM3_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_2) +#define ADC3_EXTERNALTRIG_TIM4_CC1 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_2)) +#define ADC3_EXTERNALTRIG_TIM8_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2)) +#define ADC3_EXTERNALTRIG_TIM8_TRGO2 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2)) +#define ADC3_EXTERNALTRIG_TIM1_TRGO ((uint32_t)ADC_CFGR1_EXTSEL_3) +#define ADC3_EXTERNALTRIG_TIM1_TRGO2 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_3)) +#define ADC3_EXTERNALTRIG_TIM2_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_3)) +#define ADC3_EXTERNALTRIG_TIM4_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_3)) +#define ADC3_EXTERNALTRIG_TIM6_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC3_EXTERNALTRIG_TIM2_CC1 ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC3_EXTERNALTRIG_EPWM1_SOCB ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC3_EXTERNALTRIG_EPWM2_SOCB ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_3)) +#define ADC3_EXTERNALTRIG_EPWM1_SOCA ((uint32_t)ADC_CFGR1_EXTSEL_4) +#define ADC3_EXTERNALTRIG_EPWM2_SOCA ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_4)) +#define ADC3_EXTERNALTRIG_EPWM3_SOCA ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_4)) +#define ADC3_EXTERNALTRIG_EPWM3_SOCB ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_4)) +#define ADC3_EXTERNALTRIG_EPWM4_SOCA ((uint32_t)(ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_4)) +#define ADC3_EXTERNALTRIG_EPWM4_SOCB ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_4)) +#define ADC3_EXTERNALTRIG_LPTIM_OUT ((uint32_t)(ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_4)) +#define ADC3_EXTERNALTRIG_TIM7_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0|ADC_CFGR1_EXTSEL_1|ADC_CFGR1_EXTSEL_2|ADC_CFGR1_EXTSEL_4)) +#define ADC3_EXTERNALTRIG_EXTI2 ((uint32_t)(ADC_CFGR1_EXTSEL_3|ADC_CFGR1_EXTSEL_4)) + +#define IS_ADC3_REGULAR_EXTTRIG_SOURCE(SOURCE) (((SOURCE) == ADC3_EXTERNALTRIG_TIM3_CC1 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM2_CC3 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM1_CC3 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM8_CC1 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM3_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM4_CC1 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM8_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM8_TRGO2 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM1_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM1_TRGO2 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM2_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM4_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM6_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM2_CC1 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM1_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM2_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM1_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM2_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM3_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM3_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM4_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EPWM4_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_LPTIM_OUT ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_TIM7_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_EXTI2 ) ) +/** + * @} + */ + + +#define IS_ADC_REGULAR_EXTTRIG_SOURCE(ADCx, SOURCE) ((((ADCx == ADC1) || (ADCx == ADC2)) && IS_ADC12_REGULAR_EXTTRIG_SOURCE(SOURCE)) || \ + ((ADCx == ADC3) && IS_ADC3_REGULAR_EXTTRIG_SOURCE(SOURCE))) + + + + +/** @defgroup ADC12_injected_external_trigger_sources for ADC1/2 injected channels conversion + * @{ + */ +#define ADC12_EXTERNALTRIG_INJ_TIM1_CC1 ((uint32_t)0x00000000) +#define ADC12_EXTERNALTRIG_INJ_TIM1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) +#define ADC12_EXTERNALTRIG_INJ_TIM2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) +#define ADC12_EXTERNALTRIG_INJ_TIM2_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1)) +#define ADC12_EXTERNALTRIG_INJ_TIM3_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_2) +#define ADC12_EXTERNALTRIG_INJ_TIM4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_2)) +#define ADC12_EXTERNALTRIG_INJ_TIM8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2)) +#define ADC12_EXTERNALTRIG_INJ_TIM1_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2)) +#define ADC12_EXTERNALTRIG_INJ_TIM8_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_3) +#define ADC12_EXTERNALTRIG_INJ_TIM8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_3)) +#define ADC12_EXTERNALTRIG_INJ_TIM3_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_3)) +#define ADC12_EXTERNALTRIG_INJ_TIM3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_3)) +#define ADC12_EXTERNALTRIG_INJ_TIM3_CC1 ((uint32_t)(ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC12_EXTERNALTRIG_INJ_TIM6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC12_EXTERNALTRIG_INJ_EPWM1_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC12_EXTERNALTRIG_INJ_EPWM2_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC12_EXTERNALTRIG_INJ_EPWM3_SOCA ((uint32_t)ADC_JSQR_JEXTSEL_4) +#define ADC12_EXTERNALTRIG_INJ_EPWM3_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_4)) +#define ADC12_EXTERNALTRIG_INJ_EPWM4_SOCA ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_4)) +#define ADC12_EXTERNALTRIG_INJ_EPWM4_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_4)) +#define ADC12_EXTERNALTRIG_INJ_LPTIM_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_4)) +#define ADC12_EXTERNALTRIG_INJ_TIM7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_4)) +#define ADC12_EXTERNALTRIG_INJ_EXTI15 ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_4)) + +#define IS_ADC12_INJECTED_EXTTRIG_SOURCE(SOURCE) (((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM1_CC1 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM1_CC4 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM2_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM2_CC1 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM3_CC4 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM4_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM8_CC4 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM1_TRGO2 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM8_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM8_TRGO2 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM3_CC3 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM3_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM3_CC1 ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM6_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_EPWM1_SOCB ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_EPWM2_SOCB ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_EPWM3_SOCA ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_EPWM3_SOCB ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_EPWM4_SOCA ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_EPWM4_SOCB ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_LPTIM_OUT ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_TIM7_TRGO ) ||\ + ((SOURCE) == ADC12_EXTERNALTRIG_INJ_EXTI15 ) ) +/** + * @} + */ + +/** @defgroup ADC3_injected_external_trigger_sources for ADC3 injected channels conversion + * @{ + */ +#define ADC3_EXTERNALTRIG_INJ_TIM1_TRGO ((uint32_t)0x00000000) +#define ADC3_EXTERNALTRIG_INJ_TIM1_CC4 ((uint32_t)ADC_JSQR_JEXTSEL_0) +#define ADC3_EXTERNALTRIG_INJ_TIM2_TRGO ((uint32_t)ADC_JSQR_JEXTSEL_1) +#define ADC3_EXTERNALTRIG_INJ_TIM8_CC2 ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1)) +#define ADC3_EXTERNALTRIG_INJ_TIM4_CC3 ((uint32_t)ADC_JSQR_JEXTSEL_2) +#define ADC3_EXTERNALTRIG_INJ_TIM4_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_2)) +#define ADC3_EXTERNALTRIG_INJ_TIM4_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2)) +#define ADC3_EXTERNALTRIG_INJ_TIM8_CC4 ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2)) +#define ADC3_EXTERNALTRIG_INJ_TIM1_TRGO2 ((uint32_t)ADC_JSQR_JEXTSEL_3) +#define ADC3_EXTERNALTRIG_INJ_TIM8_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_3)) +#define ADC3_EXTERNALTRIG_INJ_TIM8_TRGO2 ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_3)) +#define ADC3_EXTERNALTRIG_INJ_TIM1_CC3 ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_3)) +#define ADC3_EXTERNALTRIG_INJ_TIM3_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC3_EXTERNALTRIG_INJ_TIM6_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC3_EXTERNALTRIG_INJ_EPWM1_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC3_EXTERNALTRIG_INJ_EPWM2_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_3)) +#define ADC3_EXTERNALTRIG_INJ_EPWM3_SOCA ((uint32_t)ADC_JSQR_JEXTSEL_4) +#define ADC3_EXTERNALTRIG_INJ_EPWM3_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_4)) +#define ADC3_EXTERNALTRIG_INJ_EPWM4_SOCA ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_4)) +#define ADC3_EXTERNALTRIG_INJ_EPWM4_SOCB ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_4)) +#define ADC3_EXTERNALTRIG_INJ_EPWM1_SOCA ((uint32_t)(ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_4)) +#define ADC3_EXTERNALTRIG_INJ_EPWM2_SOCA ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_4)) +#define ADC3_EXTERNALTRIG_INJ_LPTIM_OUT ((uint32_t)(ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_4)) +#define ADC3_EXTERNALTRIG_INJ_TIM7_TRGO ((uint32_t)(ADC_JSQR_JEXTSEL_0|ADC_JSQR_JEXTSEL_1|ADC_JSQR_JEXTSEL_2|ADC_JSQR_JEXTSEL_4)) +#define ADC3_EXTERNALTRIG_INJ_EXTI3 ((uint32_t)(ADC_JSQR_JEXTSEL_3|ADC_JSQR_JEXTSEL_4)) + +#define IS_ADC3_INJECTED_EXTTRIG_SOURCE(SOURCE) (((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM1_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM1_CC4 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM2_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM8_CC2 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM4_CC3 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM4_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM4_CC4 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM8_CC4 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM1_TRGO2 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM8_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM8_TRGO2 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM1_CC3 ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM3_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM6_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM1_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM2_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM3_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM3_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM4_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM4_SOCB ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM1_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EPWM2_SOCA ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_LPTIM_OUT ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_TIM7_TRGO ) ||\ + ((SOURCE) == ADC3_EXTERNALTRIG_INJ_EXTI3 ) ) +/** + * @} + */ + +#define IS_ADC_INJECTED_EXTTRIG_SOURCE(ADCx, SOURCE) ((((ADCx == ADC1) || (ADCx == ADC2)) && IS_ADC12_INJECTED_EXTTRIG_SOURCE(SOURCE)) || \ + ((ADCx == ADC3) && IS_ADC3_INJECTED_EXTTRIG_SOURCE(SOURCE))) + + + + +/** @defgroup ADC_DMA_Mode + * @{ + */ + +#define ADC_DMAMODE_ONESHOT ((uint32_t)0x00000000) +#define ADC_DMAMODE_CIRCULAR ADC_CFGR1_DMACFG + +#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMODE_ONESHOT) || \ + ((MODE) == ADC_DMAMODE_CIRCULAR)) +/** + * @} + */ + + +/** @defgroup ADCx_AnalogWatchdog_X_Selection + * @{ + */ +#define ADC_ANALOGWATCHDOG_1 ((uint32_t)0x00000001) +#define ADC_ANALOGWATCHDOG_2 ((uint32_t)0x00000002) +#define ADC_ANALOGWATCHDOG_3 ((uint32_t)0x00000004) + +#define IS_ADC_ANALOG_WATCHDOG_NUMBER(NUMBER) (((NUMBER) == ADC_ANALOGWATCHDOG_1) ||\ + ((NUMBER) == ADC_ANALOGWATCHDOG_2) ||\ + ((NUMBER) == ADC_ANALOGWATCHDOG_3)) + + +/** + * @} + */ + +/** @defgroup ADCx_AnalogWatchdog_1_Channel_Mode_Selection + * @{ + */ +#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000) +/*!< ADC AWD not selected */ + +#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWD1SGL|ADC_CFGR1_AWD1EN)) +/*!< ADC AWD applied to a regular group single channel */ + +#define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CFGR1_AWD1SGL|ADC_CFGR1_JAWD1EN)) +/*!< ADC AWD applied to an injected group single channel */ + +#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CFGR1_AWD1SGL|ADC_CFGR1_AWD1EN|ADC_CFGR1_JAWD1EN)) +/*!< ADC AWD applied to a regular and injected groups single channel */ + +#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CFGR1_AWD1EN) +/*!< ADC AWD applied to regular group all channels */ + +#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CFGR1_JAWD1EN) +/*!< ADC AWD applied to injected group all channels */ + +#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CFGR1_AWD1EN|ADC_CFGR1_JAWD1EN)) +/*!< ADC AWD applied to regular and injected groups all channels */ + + +#define IS_ADC_ANALOG_WATCHDOG_1_MODE(MODE) (((MODE) == ADC_ANALOGWATCHDOG_NONE) ||\ + ((MODE) == ADC_ANALOGWATCHDOG_SINGLE_REG) ||\ + ((MODE) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||\ + ((MODE) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ||\ + ((MODE) == ADC_ANALOGWATCHDOG_ALL_REG) ||\ + ((MODE) == ADC_ANALOGWATCHDOG_ALL_INJEC) ||\ + ((MODE) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)) +/** + * @} + */ + +/** @defgroup ADCx_AnalogWatchdog_2_3_Channel_Selection + * @{ + */ +#define ADC_ANALOGWATCHDOG23_CHANNEL_0 ADC_AWD2CR_AWD2CH_0 +#define ADC_ANALOGWATCHDOG23_CHANNEL_1 ADC_AWD2CR_AWD2CH_1 +#define ADC_ANALOGWATCHDOG23_CHANNEL_2 ADC_AWD2CR_AWD2CH_2 +#define ADC_ANALOGWATCHDOG23_CHANNEL_3 ADC_AWD2CR_AWD2CH_3 +#define ADC_ANALOGWATCHDOG23_CHANNEL_4 ADC_AWD2CR_AWD2CH_4 +#define ADC_ANALOGWATCHDOG23_CHANNEL_5 ADC_AWD2CR_AWD2CH_5 +#define ADC_ANALOGWATCHDOG23_CHANNEL_6 ADC_AWD2CR_AWD2CH_6 +#define ADC_ANALOGWATCHDOG23_CHANNEL_7 ADC_AWD2CR_AWD2CH_7 +#define ADC_ANALOGWATCHDOG23_CHANNEL_8 ADC_AWD2CR_AWD2CH_8 +#define ADC_ANALOGWATCHDOG23_CHANNEL_9 ADC_AWD2CR_AWD2CH_9 +#define ADC_ANALOGWATCHDOG23_CHANNEL_10 ADC_AWD2CR_AWD2CH_10 +#define ADC_ANALOGWATCHDOG23_CHANNEL_11 ADC_AWD2CR_AWD2CH_11 +#define ADC_ANALOGWATCHDOG23_CHANNEL_12 ADC_AWD2CR_AWD2CH_12 +#define ADC_ANALOGWATCHDOG23_CHANNEL_13 ADC_AWD2CR_AWD2CH_13 +#define ADC_ANALOGWATCHDOG23_CHANNEL_14 ADC_AWD2CR_AWD2CH_14 +#define ADC_ANALOGWATCHDOG23_CHANNEL_15 ADC_AWD2CR_AWD2CH_15 +#define ADC_ANALOGWATCHDOG23_CHANNEL_16 ADC_AWD2CR_AWD2CH_17 +#define ADC_ANALOGWATCHDOG23_CHANNEL_18 ADC_AWD2CR_AWD2CH_18 + + +#define IS_ADC_ANALOGWATCHDOG23_CHANNEL_SEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog23_Channel_0) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_1) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_2) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_3) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_4) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_5) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_6) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_7) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_8) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_9) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_10) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_11) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_12) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_13) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_14) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_15) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_16) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_17) || \ + ((CHANNEL) == ADC_AnalogWatchdog23_Channel_18)) +/** + * @} + */ + +/** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration + * @{ + */ +#define ADC_AWD_FILTERING_NONE (0x00000000UL) /*!< ADC AWD no filtering, one + out-of-window sample to raise flag or interrupt */ +#define ADC_AWD_FILTERING_2SAMPLES ((ADC_TR1_AWDFILT_0)) /*!< ADC AWD 2 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_3SAMPLES ((ADC_TR1_AWDFILT_1)) /*!< ADC AWD 3 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_4SAMPLES ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_5SAMPLES ((ADC_TR1_AWDFILT_2)) /*!< ADC AWD 5 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_6SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_7SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives + out-of-window samples to raise flag or interrupt */ +#define ADC_AWD_FILTERING_8SAMPLES ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 |\ + ADC_TR1_AWDFILT_0)) /*!< ADC AWD 8 consecutives + out-of-window samples to raise flag or interrupt */ + +#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(FILTERING) (((FILTERING) == ADC_AWD_FILTERING_NONE) ||\ + ((FILTERING) == ADC_AWD_FILTERING_2SAMPLES) ||\ + ((FILTERING) == ADC_AWD_FILTERING_3SAMPLES) ||\ + ((FILTERING) == ADC_AWD_FILTERING_4SAMPLES) ||\ + ((FILTERING) == ADC_AWD_FILTERING_5SAMPLES) ||\ + ((FILTERING) == ADC_AWD_FILTERING_6SAMPLES) ||\ + ((FILTERING) == ADC_AWD_FILTERING_7SAMPLES) ||\ + ((FILTERING) == ADC_AWD_FILTERING_8SAMPLES) ) +/** + * @} + */ + +/** @defgroup ADC_sampling_plus_times + * @{ + */ +#define ADC_SAMPLETIMEPLUS_1_5CYCLES ((uint32_t)0x00000000) +#define ADC_SAMPLETIMEPLUS_2_5CYCLES ((uint32_t)ADC_SMPR1_SMPLUS_0) +#define ADC_SAMPLETIMEPLUS_3_5CYCLES ((uint32_t)ADC_SMPR1_SMPLUS_1) +#define ADC_SAMPLETIMEPLUS_4_5CYCLES ((uint32_t)ADC_SMPR1_SMPLUS) + +#define IS_ADC_SAMPLE_PLUS_TIME(PLUS_TIME) (((PLUS_TIME) == ADC_SAMPLETIMEPLUS_1_5CYCLES) || \ + ((PLUS_TIME) == ADC_SAMPLETIMEPLUS_2_5CYCLES) || \ + ((PLUS_TIME) == ADC_SAMPLETIMEPLUS_3_5CYCLES) || \ + ((PLUS_TIME) == ADC_SAMPLETIMEPLUS_4_5CYCLES)) +/** + * @} + */ + +/** @defgroup ADC_sampling_times + * @{ + */ +#define ADC_SAMPLETIME_1_5CYCLES ((uint32_t)0x00000000) +#define ADC_SAMPLETIME_6_5CYCLES ((uint32_t)0x00000001) +#define ADC_SAMPLETIME_12_5CYCLES ((uint32_t)0x00000002) +#define ADC_SAMPLETIME_24_5CYCLES ((uint32_t)0x00000003) +#define ADC_SAMPLETIME_47_5CYCLES ((uint32_t)0x00000004) +#define ADC_SAMPLETIME_92_5CYCLES ((uint32_t)0x00000005) +#define ADC_SAMPLETIME_247_5CYCLES ((uint32_t)0x00000006) +#define ADC_SAMPLETIME_640_5CYCLES ((uint32_t)0x00000007) + +#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1_5CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_6_5CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_12_5CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_24_5CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_47_5CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_92_5CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_247_5CYCLES) || \ + ((TIME) == ADC_SAMPLETIME_640_5CYCLES) ) +/** + * @} + */ + +/** @defgroup ADC_thresholds + * @{ + */ +#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF) +/** + * @} + */ + +/** @defgroup ADC_reg_seq_ranks ADC group regular - Sequencer ranks + * @{ + */ +#define ADC_REGULAR_RANK_1 (uint32_t)0x00000000 /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (uint32_t)0x00000001 /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (uint32_t)0x00000002 /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (uint32_t)0x00000003 /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (uint32_t)0x00000004 /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (uint32_t)0x00000005 /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (uint32_t)0x00000006 /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (uint32_t)0x00000007 /*!< ADC group regular sequencer rank 8 */ +#define ADC_REGULAR_RANK_9 (uint32_t)0x00000008 /*!< ADC group regular sequencer rank 9 */ +#define ADC_REGULAR_RANK_10 (uint32_t)0x00000009 /*!< ADC group regular sequencer rank 10 */ +#define ADC_REGULAR_RANK_11 (uint32_t)0x0000000a /*!< ADC group regular sequencer rank 11 */ +#define ADC_REGULAR_RANK_12 (uint32_t)0x0000000b /*!< ADC group regular sequencer rank 12 */ +#define ADC_REGULAR_RANK_13 (uint32_t)0x0000000c /*!< ADC group regular sequencer rank 13 */ +#define ADC_REGULAR_RANK_14 (uint32_t)0x0000000d /*!< ADC group regular sequencer rank 14 */ +#define ADC_REGULAR_RANK_15 (uint32_t)0x0000000e /*!< ADC group regular sequencer rank 15 */ +#define ADC_REGULAR_RANK_16 (uint32_t)0x0000000f /*!< ADC group regular sequencer rank 16 */ + +#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) ||\ + ((RANK) == ADC_REGULAR_RANK_2 ) ||\ + ((RANK) == ADC_REGULAR_RANK_3 ) ||\ + ((RANK) == ADC_REGULAR_RANK_4 ) ||\ + ((RANK) == ADC_REGULAR_RANK_5 ) ||\ + ((RANK) == ADC_REGULAR_RANK_6 ) ||\ + ((RANK) == ADC_REGULAR_RANK_7 ) ||\ + ((RANK) == ADC_REGULAR_RANK_8 ) ||\ + ((RANK) == ADC_REGULAR_RANK_9 ) ||\ + ((RANK) == ADC_REGULAR_RANK_10) ||\ + ((RANK) == ADC_REGULAR_RANK_11) ||\ + ((RANK) == ADC_REGULAR_RANK_12) ||\ + ((RANK) == ADC_REGULAR_RANK_13) ||\ + ((RANK) == ADC_REGULAR_RANK_14) ||\ + ((RANK) == ADC_REGULAR_RANK_15) ||\ + ((RANK) == ADC_REGULAR_RANK_16) ) + +/** + * @} + */ + +/** @defgroup ADC_channels + * @{ + */ +#define ADC_CHANNEL_RESET ((uint32_t)0x0000001f) +#define ADC_CHANNEL_0 ((uint32_t)0x00000000) +#define ADC_CHANNEL_1 ((uint32_t)0x00000001) +#define ADC_CHANNEL_2 ((uint32_t)0x00000002) +#define ADC_CHANNEL_3 ((uint32_t)0x00000003) +#define ADC_CHANNEL_4 ((uint32_t)0x00000004) +#define ADC_CHANNEL_5 ((uint32_t)0x00000005) +#define ADC_CHANNEL_6 ((uint32_t)0x00000006) +#define ADC_CHANNEL_7 ((uint32_t)0x00000007) +#define ADC_CHANNEL_8 ((uint32_t)0x00000008) +#define ADC_CHANNEL_9 ((uint32_t)0x00000009) +#define ADC_CHANNEL_10 ((uint32_t)0x0000000a) +#define ADC_CHANNEL_11 ((uint32_t)0x0000000b) +#define ADC_CHANNEL_12 ((uint32_t)0x0000000c) +#define ADC_CHANNEL_13 ((uint32_t)0x0000000d) +#define ADC_CHANNEL_14 ((uint32_t)0x0000000e) +#define ADC_CHANNEL_15 ((uint32_t)0x0000000f) +#define ADC_CHANNEL_16 ((uint32_t)0x00000010) +#define ADC_CHANNEL_17 ((uint32_t)0x00000011) +#define ADC_CHANNEL_18 ((uint32_t)0x00000012) +#define ADC_CHANNEL_19 ((uint32_t)0x00000013) +#define ADC_CHANNEL_20 ((uint32_t)0x00000014) +#define ADC_CHANNEL_21 ((uint32_t)0x00000015) + +#define ADC1_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_0) +#define ADC13_CHANNEL_TENOSENSOR ((uint32_t)ADC_CHANNEL_17) +#define ADC13_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18) + +#define ADC12_CHANNEL_OP1 ((uint32_t)ADC_CHANNEL_19) +#define ADC12_CHANNEL_OP2 ((uint32_t)ADC_CHANNEL_20) +#define ADC12_CHANNEL_OP3 ((uint32_t)ADC_CHANNEL_21) + +#define ADC12_CHANNEL_DAC1 ((uint32_t)ADC_CHANNEL_17) +#define ADC12_CHANNEL_DAC2 ((uint32_t)ADC_CHANNEL_18) + +#define ADC3_CHANNEL_DAC1 ((uint32_t)ADC_CHANNEL_14) +#define ADC3_CHANNEL_DAC2 ((uint32_t)ADC_CHANNEL_15) + +#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ + ((CHANNEL) == ADC_CHANNEL_1) || \ + ((CHANNEL) == ADC_CHANNEL_2) || \ + ((CHANNEL) == ADC_CHANNEL_3) || \ + ((CHANNEL) == ADC_CHANNEL_4) || \ + ((CHANNEL) == ADC_CHANNEL_5) || \ + ((CHANNEL) == ADC_CHANNEL_6) || \ + ((CHANNEL) == ADC_CHANNEL_7) || \ + ((CHANNEL) == ADC_CHANNEL_8) || \ + ((CHANNEL) == ADC_CHANNEL_9) || \ + ((CHANNEL) == ADC_CHANNEL_10) || \ + ((CHANNEL) == ADC_CHANNEL_11) || \ + ((CHANNEL) == ADC_CHANNEL_12) || \ + ((CHANNEL) == ADC_CHANNEL_13) || \ + ((CHANNEL) == ADC_CHANNEL_14) || \ + ((CHANNEL) == ADC_CHANNEL_15) || \ + ((CHANNEL) == ADC_CHANNEL_16) || \ + ((CHANNEL) == ADC_CHANNEL_17) || \ + ((CHANNEL) == ADC_CHANNEL_18) || \ + ((CHANNEL) == ADC_CHANNEL_19) || \ + ((CHANNEL) == ADC_CHANNEL_20) || \ + ((CHANNEL) == ADC_CHANNEL_21) || \ + ((CHANNEL) == ADC1_CHANNEL_VREFINT) || \ + ((CHANNEL) == ADC13_CHANNEL_TENOSENSOR) || \ + ((CHANNEL) == ADC13_CHANNEL_VBAT) || \ + ((CHANNEL) == ADC12_CHANNEL_OP1) || \ + ((CHANNEL) == ADC12_CHANNEL_OP2) || \ + ((CHANNEL) == ADC12_CHANNEL_OP3) || \ + ((CHANNEL) == ADC12_CHANNEL_DAC1) || \ + ((CHANNEL) == ADC12_CHANNEL_DAC2) || \ + ((CHANNEL) == ADC3_CHANNEL_DAC1) || \ + ((CHANNEL) == ADC3_CHANNEL_DAC2) ) +/** + * @} + */ + +/** @defgroup ADC_injected_seq_ranks ADC group injected - Sequencer ranks + * @{ + */ +#define ADC_INJECTED_RANK_1 (uint32_t)0x00000000 /*!< ADC group injected sequencer rank 1 */ +#define ADC_INJECTED_RANK_2 (uint32_t)0x00000001 /*!< ADC group injected sequencer rank 2 */ +#define ADC_INJECTED_RANK_3 (uint32_t)0x00000002 /*!< ADC group injected sequencer rank 3 */ +#define ADC_INJECTED_RANK_4 (uint32_t)0x00000003 /*!< ADC group injected sequencer rank 4 */ + +#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \ + ((CHANNEL) == ADC_INJECTED_RANK_2) || \ + ((CHANNEL) == ADC_INJECTED_RANK_3) || \ + ((CHANNEL) == ADC_INJECTED_RANK_4) ) +/** + * @} + */ + +/** @defgroup ADC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define ADC_REG_SEQ_DISCONT_DISABLE (uint32_t)0x00000000 /*!< ADC group regular sequencer + discontinuous mode disable */ +#define ADC_REG_SEQ_DISCNUM_1_CHANNEL (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with + sequence interruption every rank */ +#define ADC_REG_SEQ_DISCNUM_2_CHANNELS (ADC_CFGR1_DISCNUM_0 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enabled with + sequence interruption every 2 ranks */ +#define ADC_REG_SEQ_DISCNUM_3_CHANNELS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with + sequence interruption every 3 ranks */ +#define ADC_REG_SEQ_DISCNUM_4_CHANNELS (ADC_CFGR1_DISCNUM_1 | ADC_CFGR1_DISCNUM_0 \ + | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with + sequence interruption every 4 ranks */ +#define ADC_REG_SEQ_DISCNUM_5_CHANNELS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with + sequence interruption every 5 ranks */ +#define ADC_REG_SEQ_DISCNUM_6_CHANNELS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_0 \ + | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with + sequence interruption every 6 ranks */ +#define ADC_REG_SEQ_DISCNUM_7_CHANNELS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \ + | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with + sequence interruption every 7 ranks */ +#define ADC_REG_SEQ_DISCNUM_8_CHANNELS (ADC_CFGR1_DISCNUM_2 | ADC_CFGR1_DISCNUM_1 \ + | ADC_CFGR1_DISCNUM_0 \ + | ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with + sequence interruption every 8 ranks */ + +#define ADC_REG_SEQ_DISCNUM(DISCNUM) (((DISCNUM) == ADC_REG_SEQ_DISCONT_DISABLE) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_1_CHANNEL) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_2_CHANNELS) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_3_CHANNELS) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_4_CHANNELS) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_5_CHANNELS) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_6_CHANNELS) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_7_CHANNELS) || \ + ((DISCNUM) == ADC_REG_SEQ_DISCNUM_8_CHANNELS) ) + +/** + * @} + */ + +/** @defgroup ADC_OVS_RATIO Oversampling - Ratio + * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed + * to result as the ADC oversampling conversion data (before potential shift) + */ +#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000) /*!< ADC oversampling ratio 2 */ +#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio 4 */ +#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio 8 */ +#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)(ADC_CFGR2_OVSR_0|ADC_CFGR2_OVSR_1)) /*!< ADC oversampling ratio 16 */ +#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio 32 */ +#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)(ADC_CFGR2_OVSR_0|ADC_CFGR2_OVSR_2)) /*!< ADC oversampling ratio 64 */ +#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)(ADC_CFGR2_OVSR_1|ADC_CFGR2_OVSR_2)) /*!< ADC oversampling ratio 128 */ +#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)(ADC_CFGR2_OVSR_0|ADC_CFGR2_OVSR_1|ADC_CFGR2_OVSR_2)) /*!< ADC oversampling ratio 256 */ + + +#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2) ||\ + ((RATIO) == ADC_OVERSAMPLING_RATIO_4) ||\ + ((RATIO) == ADC_OVERSAMPLING_RATIO_8) ||\ + ((RATIO) == ADC_OVERSAMPLING_RATIO_16) ||\ + ((RATIO) == ADC_OVERSAMPLING_RATIO_32) ||\ + ((RATIO) == ADC_OVERSAMPLING_RATIO_64) ||\ + ((RATIO) == ADC_OVERSAMPLING_RATIO_128) ||\ + ((RATIO) == ADC_OVERSAMPLING_RATIO_256)) +/** + * @} + */ + +/** @defgroup ADC_OVS_SHIFT Oversampling - Data shift + * @{ + */ +/** + * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling + * conversion data) + */ +#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000) /*!< ADC oversampling no shift */ +#define ADC_RIGHTBITSHIFT_1 ((uint32_t)ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 ranks */ +#define ADC_RIGHTBITSHIFT_2 ((uint32_t)ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 ranks */ +#define ADC_RIGHTBITSHIFT_3 ((uint32_t)(ADC_CFGR2_OVSS_0|ADC_CFGR2_OVSS_1)) /*!< ADC oversampling right shift of 3 ranks */ +#define ADC_RIGHTBITSHIFT_4 ((uint32_t)ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 ranks */ +#define ADC_RIGHTBITSHIFT_5 ((uint32_t)(ADC_CFGR2_OVSS_0|ADC_CFGR2_OVSS_2)) /*!< ADC oversampling right shift of 5 ranks */ +#define ADC_RIGHTBITSHIFT_6 ((uint32_t)(ADC_CFGR2_OVSS_1|ADC_CFGR2_OVSS_2)) /*!< ADC oversampling right shift of 6 ranks */ +#define ADC_RIGHTBITSHIFT_7 ((uint32_t)(ADC_CFGR2_OVSS_0|ADC_CFGR2_OVSS_1|ADC_CFGR2_OVSS_2)) /*!< ADC oversampling right shift of 7 ranks */ +#define ADC_RIGHTBITSHIFT_8 ((uint32_t)ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 ranks */ + +#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_1) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_2) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_3) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_4) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_5) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_6) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_7) ||\ + ((SHIFT) == ADC_RIGHTBITSHIFT_8) ) +/** + * @} + */ + +/** @defgroup ADC_OVS_DISCONT_MODE Oversampling - Discontinuous mode + * @{ + */ +#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (0x00000000UL) /*!< ADC oversampling discontinuous mode: + continuous mode (all conversions of OVS ratio are done from 1 trigger) */ +#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (ADC_CFGR2_TROVS) /*!< ADC oversampling discontinuous mode: + discontinuous mode (each conversion of OVS ratio needs a trigger) */ + +#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) ||\ + ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER)) +/** + * @} + */ + +/** @defgroup ADC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular + * @{ + */ +#define ADC_REGOVERSAMPLING_CONTINUED_MODE (0x00000000UL) /*!< Oversampling buffer maintained + during injection sequence */ +#define ADC_REGOVERSAMPLING_RESUMED_MODE (ADC_CFGR2_ROVSM) /*!< Oversampling buffer zeroed during + injection sequence */ + +#define IS_ADC_REGOVERSAMPLING_MODE(MODE) (((MODE) == ADC_REGOVERSAMPLING_CONTINUED_MODE) ||\ + ((MODE) == ADC_REGOVERSAMPLING_RESUMED_MODE)) +/** + * @} + */ + + +/** @defgroup ADC_interrupts_definition + * @{ + */ + +#define ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ +#define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_JQOV ADC_IER_JQOVIE /*!< ADC Injected Context Queue Overflow interrupt source */ + +#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFF800) == (uint32_t)RESET)) + +#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \ + ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOS) || \ + ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_JEOC) || \ + ((IT) == ADC_IT_JEOS) || ((IT) == ADC_IT_AWD1) || \ + ((IT) == ADC_IT_AWD2) || ((IT) == ADC_IT_AWD3) || \ + ((IT) == ADC_IT_JQOV)) + +#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFF800) == (uint32_t)RESET)) + +/** + * @} + */ + +/** @defgroup ADC_flags_definition + * @{ + */ + +#define ADC_FLAG_ADRDY ADC_ISR_ADRDY +#define ADC_FLAG_EOSMP ADC_ISR_EOSMP +#define ADC_FLAG_EOC ADC_ISR_EOC +#define ADC_FLAG_EOS ADC_ISR_EOS +#define ADC_FLAG_OVR ADC_ISR_OVR +#define ADC_FLAG_JEOC ADC_ISR_JEOC +#define ADC_FLAG_JEOS ADC_ISR_JEOS +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 +#define ADC_FLAG_JQOVF ADC_ISR_JQOVF + +#define ADC_FLAG_ADEN ((uint32_t)0x01000001) +#define ADC_FLAG_ADDIS ((uint32_t)0x01000002) +#define ADC_FLAG_ADSTART ((uint32_t)0x01000004) +#define ADC_FLAG_JADSTART ((uint32_t)0x01000008) +#define ADC_FLAG_ADSTP ((uint32_t)0x01000010) +#define ADC_FLAG_JADSTP ((uint32_t)0x01000020) +#define ADC_FLAG_ADCAL ((uint32_t)0x81000000) + +#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFF800) == (uint32_t)RESET)) + +#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \ + ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOS) || \ + ((FLAG) == ADC_FLAG_OVR) || ((FLAG) == ADC_FLAG_JEOC) || \ + ((FLAG) == ADC_FLAG_JEOS) || ((FLAG) == ADC_FLAG_AWD1) || \ + ((FLAG) == ADC_FLAG_AWD2) || ((FLAG) == ADC_FLAG_AWD3) || \ + ((FLAG) == ADC_FLAG_JQOVF) || \ + ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \ + ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_JADSTART) || \ + ((FLAG) == ADC_FLAG_ADSTP) || ((FLAG) == ADC_FLAG_JADSTP) || \ + ((FLAG) == ADC_FLAG_ADCAL)) +/** + * @} + */ + + +/** @defgroup ADC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data + * @{ + */ +#define ADC_OVR_MODE_PRESERVED ((uint32_t)0x00000000) /*!< ADC group regular behavior in case + of overrun: data preserved */ +#define ADC_OVR_MODE_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case + of overrun: data overwritten */ + +#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_MODE_PRESERVED) ||\ + ((OVR) == ADC_OVR_MODE_OVERWRITTEN)) +/** + * @} + */ + +/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode + * @{ + */ +#define ADC_SAMPLING_MODE_NORMAL ((uint32_t)0x00000000) /*!< ADC conversions sampling phase duration is + defined using @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */ +#define ADC_SAMPLING_MODE_BULB (ADC_CFGR2_BULB) /*!< ADC conversions sampling phase starts + immediately after end of conversion, and stops upon trigger event. + Note: First conversion is using minimal sampling time + (see @ref ADC_CHANNEL_SAMPLINGTIME) */ +#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled + by trigger events: + Trigger rising edge = start sampling + Trigger falling edge = stop sampling and start conversion */ + +#define IS_ADC_SAMPLINGMODE(SAMPLINGMODE) (((SAMPLINGMODE) == ADC_SAMPLING_MODE_NORMAL) || \ + ((SAMPLINGMODE) == ADC_SAMPLING_MODE_BULB) || \ + ((SAMPLINGMODE) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED)) + +/** + * @} + */ + +/** @defgroup ADC_channel_single_diff_ending Channel - Single or differential ending + * @{ + */ +#define ADC_SINGLE_ENDED ((uint32_t)0x00000000) /*!< ADC channel ending set to single ended */ +#define ADC_DIFFERENTIAL_ENDED ((uint32_t)0x00000001) /*!< ADC channel ending set to differential */ + +#define IS_ADC_SINGLE_DIFFERENTIAL(SING_DIFF) (((SING_DIFF) == ADC_SINGLE_ENDED) || \ + ((SING_DIFF) == ADC_DIFFERENTIAL_ENDED) ) +/** + * @} + */ + +/** @defgroup ADC_offset_number ADC instance - Offset number + * @{ + */ +#define ADC_OFFSET_NONE ((uint32_t)0x00000000) /*!< ADC offset disabled: no offset correction for the selected + ADC channel */ +#define ADC_OFFSET_1 ((uint32_t)0x00000001) /*!< ADC offset number 1: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_2 ((uint32_t)0x00000002) /*!< ADC offset number 2: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_3 ((uint32_t)0x00000004) /*!< ADC offset number 3: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ +#define ADC_OFFSET_4 ((uint32_t)0x00000008) /*!< ADC offset number 4: ADC channel and offset level to which + the offset programmed will be applied (independently of channel mapped + on ADC group regular or group injected) */ + +#define IS_ADC_OFFSET_NUMBER(NUMBER) (((NUMBER) == ADC_OFFSET_NONE) || \ + ((NUMBER) == ADC_OFFSET_1) || \ + ((NUMBER) == ADC_OFFSET_2) || \ + ((NUMBER) == ADC_OFFSET_3) || \ + ((NUMBER) == ADC_OFFSET_4) ) +/** + * @} + */ + + +/** @defgroup ADC_OffsetSign ADC Extended Offset Sign + * @{ + */ +#define ADC_OFFSET_SIGN_NEGATIVE ((uint32_t)0x00000000) /*!< Offset sign negative, offset is subtracted */ +#define ADC_OFFSET_SIGN_POSITIVE (ADC_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ + +#define IS_ADC_OFFSET_SIGN(SIGN) (((SIGN) == ADC_OFFSET_SIGN_NEGATIVE) ||\ + ((SIGN) == ADC_OFFSET_SIGN_POSITIVE)) +/** + * @} + */ + + +/** @defgroup ADC_CFGR_fields ADCx CFGR fields + * @{ + */ +#define ADC_CFGR_FIELDS (ADC_CFGR1_AWD1CH | ADC_CFGR1_JAUTO | ADC_CFGR1_JAWD1EN |\ + ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_JQM |\ + ADC_CFGR1_JDISCEN | ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN |\ + ADC_CFGR1_AUTDLY | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD |\ + ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN |\ + ADC_CFGR1_RES | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ) +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup ADC_MULTI_MODE Multimode - Mode + * @{ + */ +#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000) +/*!< ADC dual mode disabled (ADC independent + mode) */ + +#define ADC_DUAL_MODE_REGSIMULT (uint32_t)(ADC_CCR_MULTI_2|ADC_CCR_MULTI_1) +/*!< ADC dual mode enabled: group regular + simultaneous */ + +#define ADC_DUAL_MODE_INTERL (uint32_t)(ADC_CCR_MULTI_2|ADC_CCR_MULTI_1|ADC_CCR_MULTI_0) +/*!< ADC dual mode enabled: Combined + group regular interleaved */ + +#define ADC_DUAL_MODE_INJECSIMULT (uint32_t)(ADC_CCR_MULTI_2|ADC_CCR_MULTI_0) +/*!< ADC dual mode enabled: group + injected simultaneous */ + +#define ADC_DUAL_MODE_ALTERTRIG (uint32_t)(ADC_CCR_MULTI_3|ADC_CCR_MULTI_0) +/*!< ADC dual mode enabled: group injected + alternate trigger. Works only with external + triggers (not internal SW start) */ + +#define ADC_DUAL_MODE_REGSIMULT_INJECSIMULT (uint32_t)(ADC_CCR_MULTI_0) +/*!< ADC dual mode enabled: Combined + group regular simultaneous + group + injected simultaneous */ + +#define ADC_DUAL_MODE_REGSIMULT_ALTERTRIG (uint32_t)(ADC_CCR_MULTI_1) +/*!< ADC dual mode enabled: Combined + group regular simultaneous + group + injected alternate trigger */ + + +#define ADC_TRIPLE_MODE_REGSIMULT (uint32_t)(ADC_CCR_MULTI_4|ADC_CCR_MULTI_2|ADC_CCR_MULTI_1) +/*!< ADC triple mode enabled: group regular + simultaneous */ + + +#define ADC_TRIPLE_MODE_INTERL (uint32_t)(ADC_CCR_MULTI_4|ADC_CCR_MULTI_2|ADC_CCR_MULTI_1|ADC_CCR_MULTI_0) +/*!< ADC triple mode enabled: Combined + group regular interleaved */ + +#define ADC_TRIPLE_MODE_INJECSIMULT (uint32_t)(ADC_CCR_MULTI_4|ADC_CCR_MULTI_2|ADC_CCR_MULTI_0) +/*!< ADC triple mode enabled: group + injected simultaneous */ + + +#define ADC_TRIPLE_MODE_ALTERTRIG (uint32_t)(ADC_CCR_MULTI_4|ADC_CCR_MULTI_3|ADC_CCR_MULTI_0) +/*!< ADC triple mode enabled: group injected + alternate trigger. Works only with external + triggers (not internal SW start) */ + +#define ADC_TRIPLE_MODE_REGSIMULT_INJECSIMULT (uint32_t)(ADC_CCR_MULTI_4|ADC_CCR_MULTI_0) +/*!< ADC triple mode enabled: Combined + group regular simultaneous + group + injected simultaneous */ + + +#define ADC_TRIPLE_MODE_REGSIMULT_ALTERTRIG (uint32_t)(ADC_CCR_MULTI_4|ADC_CCR_MULTI_1) +/*!< ADC triple mode enabled: Combined + group regular simultaneous + group + injected alternate trigger */ + + +#define IS_ADC_MULTIMODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \ + ((MODE) == ADC_DUAL_MODE_REGSIMULT_INJECSIMULT) || \ + ((MODE) == ADC_DUAL_MODE_REGSIMULT_ALTERTRIG) || \ + ((MODE) == ADC_DUAL_MODE_INJECSIMULT) || \ + ((MODE) == ADC_DUAL_MODE_REGSIMULT) || \ + ((MODE) == ADC_DUAL_MODE_INTERL) || \ + ((MODE) == ADC_DUAL_MODE_ALTERTRIG) || \ + ((MODE) == ADC_TRIPLE_MODE_REGSIMULT_INJECSIMULT) || \ + ((MODE) == ADC_TRIPLE_MODE_REGSIMULT_ALTERTRIG) || \ + ((MODE) == ADC_TRIPLE_MODE_INJECSIMULT) || \ + ((MODE) == ADC_TRIPLE_MODE_REGSIMULT) || \ + ((MODE) == ADC_TRIPLE_MODE_INTERL) || \ + ((MODE) == ADC_TRIPLE_MODE_ALTERTRIG) ) +/** + * @} + */ + +/** @defgroup ADC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution + * @{ + */ +#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA multimode disabled: each ADC uses its own + DMA channel */ +#define ADC_DMAACCESSMODE_1 (ADC_CCR_MDMA_0) /*!< DMA multimode enabled (2/3 half-words one by one - 1 then 2 then 3) */ +#define ADC_DMAACCESSMODE_2 (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (2/3 half-words by pairs - 2&1 then 1&3 then 3&2) */ +#define ADC_DMAACCESSMODE_3 (ADC_CCR_MDMA) /*!< DMA multimode enabled (2/3 bytes by pairs - 2&1 then 1&3 then 3&2) */ + +#define IS_ADC_DMA_ACCESS_MULTIMODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \ + ((MODE) == ADC_DMAACCESSMODE_1) || \ + ((MODE) == ADC_DMAACCESSMODE_2) || \ + ((MODE) == ADC_DMAACCESSMODE_3 )) +/** + * @} + */ + +/** @defgroup ADC_MULTI_DMA_MODE + * @{ + */ +#define ADC_MULTI_DMAMODE_ONESHOT ((uint32_t)0x00000000) +#define ADC_MULTI_DMAMODE_CIRCULAR ADC_CCR_DMACFG + +#define IS_ADC_MULTI_DMA_MODE(MODE) (((MODE) == ADC_MULTI_DMAMODE_ONESHOT) || \ + ((MODE) == ADC_MULTI_DMAMODE_CIRCULAR)) +/** + * @} + */ + + +/** @defgroup ADC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases + * @{ + */ +#define ADC_TWOSAMPLINGDELAY_1CYCLE ((uint32_t)0x00000000) +/*!< ADC multimode delay between two + sampling phases: 1 ADC clock cycle */ +#define ADC_TWOSAMPLINGDELAY_2CYCLES ((uint32_t)ADC_CCR_DELAY_0) +/*!< ADC multimode delay between two + sampling phases: 2 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_3CYCLES ((uint32_t)ADC_CCR_DELAY_1) +/*!< ADC multimode delay between two + sampling phases: 3 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_4CYCLES ((uint32_t)(ADC_CCR_DELAY_0|ADC_CCR_DELAY_1)) +/*!< ADC multimode delay between two + sampling phases: 4 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES (ADC_CCR_DELAY_2) +/*!< ADC multimode delay between two + sampling phases: 5 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)(ADC_CCR_DELAY_0|ADC_CCR_DELAY_2)) +/*!< ADC multimode delay between two + sampling phases: 6 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)(ADC_CCR_DELAY_1|ADC_CCR_DELAY_2)) +/*!< ADC multimode delay between two + sampling phases: 7 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_0|ADC_CCR_DELAY_1|ADC_CCR_DELAY_2)) +/*!< ADC multimode delay between two + sampling phases: 8 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_3) +/*!< ADC multimode delay between two + sampling phases: 9 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_0|ADC_CCR_DELAY_3)) +/*!< ADC multimode delay between two + sampling phases: 10 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_1|ADC_CCR_DELAY_3)) +/*!< ADC multimode delay between two + sampling phases: 11 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_0|ADC_CCR_DELAY_1|ADC_CCR_DELAY_3)) +/*!< ADC multimode delay between two + sampling phases: 12 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)(ADC_CCR_DELAY_2|ADC_CCR_DELAY_3)) +/*!< ADC multimode delay between two + sampling phases: 13 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_0|ADC_CCR_DELAY_2|ADC_CCR_DELAY_3)) +/*!< ADC multimode delay between two + sampling phases: 14 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_1|ADC_CCR_DELAY_2|ADC_CCR_DELAY_3)) +/*!< ADC multimode delay between two + sampling phases: 15 ADC clock cycles */ +#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_0|ADC_CCR_DELAY_1|ADC_CCR_DELAY_2|ADC_CCR_DELAY_3)) +/*!< ADC multimode delay between two + sampling phases: 16 ADC clock cycles */ + + +#define IS_ADC_TWOSAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) ) +/** + * @} + */ + +/** + * @brief Verify the length of the scheduled regular conversions group. + * @param LENGTH number of programmed conversions. + * @retval SET (LENGTH is within the maximum number of possible programmable regular conversions) + * or RESET (LENGTH is null or too large) + */ +#define IS_ADC_REGULAR_NUMBER(LENGTH) (((LENGTH) >= (uint32_t)(1)) && ((LENGTH) <= (uint32_t)(16))) +/** + * @} + */ + + +/** + * @brief Verify the length of the scheduled injected conversions group. + * @param LENGTH number of programmed conversions. + * @retval SET (LENGTH is within the maximum number of possible programmable regular conversions) + * or RESET (LENGTH is null or too large) + */ +#define IS_ADC_INJECTED_NUMBER(LENGTH) (((LENGTH) >= (uint32_t)(1)) && ((LENGTH) <= (uint32_t)(4))) +/** + * @} + */ + + +/** + * @brief Verify the number of scheduled regular conversions in discontinuous mode. + * @param NUMBER number of scheduled regular conversions in discontinuous mode. + * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) + * or RESET (NUMBER is null or too large) + */ +#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (uint32_t)(1)) && ((NUMBER) <= (uint32_t)(8))) +/** + * @} + */ + +/** + * @brief Verify the ADC gain compensation. + * @param GAIN_COMPENSATION programmed ADC gain compensation coefficient. + * @retval SET (GAIN_COMPENSATION is a valid value) or RESET (GAIN_COMPENSATION is invalid) + */ +#define IS_ADC_GAIN_COMPENSATION(GAIN_COMPENSATION) ((GAIN_COMPENSATION) <= ((uint32_t)16383)) +/** + * @} + */ + + + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the ADC configuration to the default reset state *****/ +void ADC_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_InjectedStructInit(ADC_InjectedConfTypeDef* ADC_InjectedConf); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ClockModeConfig(uint32_t ClockMode); +void ADC_MultiModeConfig(ADC_MultiModeTypeDef* MultiMode); + +/* Power saving functions *****************************************************/ +void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ADC_AutDlyModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DeepPWDModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InternalRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState); + +/* Analog Watchdog configuration functions ************************************/ +void ADC_AnalogWDGConfig(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); + +/* Temperature Sensor , Vrefint and Vbat management function ... ******************/ +void ADC_TempSensorCmd(FunctionalState NewState); +void ADC_VrefintCmd(FunctionalState NewState); +void ADC_VbatCmd(FunctionalState NewState); +void ADC_BatteryAutoChargingCmd(FunctionalState NewState); +void ADC_AWD2MonitorVbatCmd(FunctionalState NewState); +void ADC_AWD3MonitorVbatCmd(FunctionalState NewState); + +/* Channels Configuration functions *******************************************/ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, ADC_ChannelConfTypeDef* RegularConfig); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, ADC_InjectedConfTypeDef* InjectedConfig); +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_AutoDelayModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_AutoInjectedModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_REG_DiscModeCmd(ADC_TypeDef* ADCx, uint32_t DiscontNum); +void ADC_INJ_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint32_t ADC_StartSingleCalibration(ADC_TypeDef* ADCx); +uint32_t ADC_StartDiffCalibration(ADC_TypeDef* ADCx); +uint32_t ADC_GetSingleCalibrationFactor(ADC_TypeDef* ADCx); +uint32_t ADC_GetDiffCalibrationFactor(ADC_TypeDef* ADCx); +void ADC_SetSingleCalibrationFactor(ADC_TypeDef* ADCx, uint32_t Calfact_S); +void ADC_SetDiffCalibrationFactor(ADC_TypeDef* ADCx, uint32_t Calfact_D); +void ADC_REG_StartOfConversion(ADC_TypeDef* ADCx); +void ADC_REG_StopOfConversion(ADC_TypeDef* ADCx); +void ADC_INJ_StartOfConversion(ADC_TypeDef* ADCx); +void ADC_INJ_StopOfConversion(ADC_TypeDef* ADCx); +uint16_t ADC_REG_GetConversionValue(ADC_TypeDef* ADCx); +uint16_t ADC_INJ_GetConversionValue(ADC_TypeDef* ADCx, uint32_t INJ_RANK); +uint32_t ADC_ReadMultiConversionData32(void); +void ADC_StartSamplingPhase(ADC_TypeDef* ADCx); +void ADC_StoptSamplingPhase(ADC_TypeDef* ADCx); + +/* Regular Channels DMA Configuration functions *******************************/ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode); + +/* Interrupts and flags management functions **********************************/ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); +FlagStatus ADC_GetMultiFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT); + + +#ifdef __cplusplus +} +#endif + +#endif /*__ft32f4XX_ADC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_comp.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_comp.h new file mode 100644 index 00000000000..c8d2a35fac3 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_comp.h @@ -0,0 +1,441 @@ +/** + ****************************************************************************** + * @file ft32f4xx_comp.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the comparator + * firmware library. + * @version V1.0.0 + * @date 2025-03-20 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_COMP_H +#define __FT32F4XX_COMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +/* Exported types ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Types COMP Exported Types + * @{ + */ + +/** + * @brief COMP Init structure definition + */ +typedef struct +{ + + uint32_t COMP_VipSel; /*!< Select the positive input of the comparator. + This parameter can be a value of @ref COMP_VipSel */ + + uint32_t COMP_VinSel; /*!< Select the negative input of the comparator. + This parameter can be a value of @ref COMP_VinSel */ + + uint32_t COMP_Hysteresis_Sel; /*!< Set comparator COMP_hysteresis mode of the input minus. + This parameter can be a value of @ref COMP_Hysteresis */ + + uint32_t COMP_Blanking_Sel; /*!< Set comparator blanking source. + This parameter can be a value of @ref COMP_BlankingSrce */ + + uint32_t COMP_Pol; /*!< Select the output polarity of the comparator. + This parameter can be a value of @ref COMP_Pol */ +} COMP_InitTypeDef; + +/** + * @brief HAL COMP state machine: HAL COMP states definition + */ + + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup COMP_Exported_Constants + * @{ + */ + +/** @defgroup COMP_Selection + * @{ + */ +#define COMP_Selection_COMP1 ((uint32_t)0x00000001) /*!< COMP1 Selection */ +#define COMP_Selection_COMP2 ((uint32_t)0x00000002) /*!< COMP2 Selection */ +#define COMP_Selection_COMP3 ((uint32_t)0x00000003) /*!< COMP3 Selection */ +#define COMP_Selection_COMP4 ((uint32_t)0x00000004) /*!< COMP4 Selection */ +#define COMP_Selection_COMP5 ((uint32_t)0x00000005) /*!< COMP5 Selection */ +#define COMP_Selection_COMP6 ((uint32_t)0x00000006) /*!< COMP6 Selection */ + +#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ + ((PERIPH) == COMP_Selection_COMP2) || \ + ((PERIPH) == COMP_Selection_COMP3) || \ + ((PERIPH) == COMP_Selection_COMP4) || \ + ((PERIPH) == COMP_Selection_COMP5) || \ + ((PERIPH) == COMP_Selection_COMP6)) + +/** @defgroup COMP_WIN_Selection + * @{comp3 comp4 comp5 comp6 + */ +#define COMP_WIN_Selection_COMP3 ((uint32_t)0x00000003) /*!< COMP3 Selection */ +#define COMP_WIN_Selection_COMP4 ((uint32_t)0x00000004) /*!< COMP4 Selection */ +#define COMP_WIN_Selection_COMP5 ((uint32_t)0x00000005) /*!< COMP5 Selection */ +#define COMP_WIN_Selection_COMP6 ((uint32_t)0x00000006) /*!< COMP6 Selection */ + +#define IS_COMP_WIN_PERIPH(PERIPH) (((PERIPH) == COMP_WIN_Selection_COMP3) || \ + ((PERIPH) == COMP_WIN_Selection_COMP4) || \ + ((PERIPH) == COMP_WIN_Selection_COMP5) || \ + ((PERIPH) == COMP_WIN_Selection_COMP6)) + + +/** @defgroup COMP_1_2_Selection + * @{comp1 comp2 + */ +#define COMP_1_2_Selection_COMP1 ((uint32_t)0x00000001) /*!< COMP3 Selection */ +#define COMP_1_2_Selection_COMP2 ((uint32_t)0x00000002) /*!< COMP4 Selection */ + +#define IS_COMP_1_2_PERIPH(PERIPH) (((PERIPH) == COMP_1_2_Selection_COMP1) || \ + ((PERIPH) == COMP_1_2_Selection_COMP2)) + + +/** @defgroup COMP_qualsel + * @{ x= 1/2 (comp1 comp2) + */ +#define COMPx_QUALSEL_NONE ((uint32_t)0x00000000) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_1C ((uint32_t)0x00000200) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_2C ((uint32_t)0x00000400) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_3C ((uint32_t)0x00000600) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_4C ((uint32_t)0x00000800) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_5C ((uint32_t)0x00000a00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_6C ((uint32_t)0x00000c00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_7C ((uint32_t)0x00000e00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_8C ((uint32_t)0x00001000) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_9C ((uint32_t)0x00001200) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_10C ((uint32_t)0x00001400) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_11C ((uint32_t)0x00001600) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_12C ((uint32_t)0x00001800) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_13C ((uint32_t)0x00001a00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_14C ((uint32_t)0x00001c00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_15C ((uint32_t)0x00001e00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_16C ((uint32_t)0x00002000) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_17C ((uint32_t)0x00002200) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_18C ((uint32_t)0x00002400) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_19C ((uint32_t)0x00002600) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_20C ((uint32_t)0x00002800) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_21C ((uint32_t)0x00002a00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_22C ((uint32_t)0x00002c00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_23C ((uint32_t)0x00002e00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_24C ((uint32_t)0x00003000) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_25C ((uint32_t)0x00003200) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_26C ((uint32_t)0x00003400) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_27C ((uint32_t)0x00003600) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_28C ((uint32_t)0x00003800) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_29C ((uint32_t)0x00003a00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_30C ((uint32_t)0x00003c00) /*!< COMPx_QUALICIFATION */ +#define COMPx_QUALSEL_31C ((uint32_t)0x00003e00) /*!< COMPx_QUALICIFATION */ + +#define IS_COMP_QUALSER_PERIPH(QUALSEL) (((QUALSEL) == COMPx_QUALSEL_NONE) || \ + ((QUALSEL) == COMPx_QUALSEL_1C ) || \ + ((QUALSEL) == COMPx_QUALSEL_2C ) || \ + ((QUALSEL) == COMPx_QUALSEL_3C ) || \ + ((QUALSEL) == COMPx_QUALSEL_4C ) || \ + ((QUALSEL) == COMPx_QUALSEL_5C ) || \ + ((QUALSEL) == COMPx_QUALSEL_6C ) || \ + ((QUALSEL) == COMPx_QUALSEL_7C ) || \ + ((QUALSEL) == COMPx_QUALSEL_8C ) || \ + ((QUALSEL) == COMPx_QUALSEL_9C ) || \ + ((QUALSEL) == COMPx_QUALSEL_10C ) || \ + ((QUALSEL) == COMPx_QUALSEL_11C ) || \ + ((QUALSEL) == COMPx_QUALSEL_12C ) || \ + ((QUALSEL) == COMPx_QUALSEL_13C ) || \ + ((QUALSEL) == COMPx_QUALSEL_14C ) || \ + ((QUALSEL) == COMPx_QUALSEL_15C ) || \ + ((QUALSEL) == COMPx_QUALSEL_16C ) || \ + ((QUALSEL) == COMPx_QUALSEL_17C ) || \ + ((QUALSEL) == COMPx_QUALSEL_18C ) || \ + ((QUALSEL) == COMPx_QUALSEL_19C ) || \ + ((QUALSEL) == COMPx_QUALSEL_20C ) || \ + ((QUALSEL) == COMPx_QUALSEL_21C ) || \ + ((QUALSEL) == COMPx_QUALSEL_22C ) || \ + ((QUALSEL) == COMPx_QUALSEL_23C ) || \ + ((QUALSEL) == COMPx_QUALSEL_24C ) || \ + ((QUALSEL) == COMPx_QUALSEL_25C ) || \ + ((QUALSEL) == COMPx_QUALSEL_26C ) || \ + ((QUALSEL) == COMPx_QUALSEL_27C ) || \ + ((QUALSEL) == COMPx_QUALSEL_28C ) || \ + ((QUALSEL) == COMPx_QUALSEL_29C ) || \ + ((QUALSEL) == COMPx_QUALSEL_30C ) || \ + ((QUALSEL) == COMPx_QUALSEL_31C ) ) + + +/** @defgroup COMP_VipSel + * @{ + */ +#define COMP1_VIP_SEL_PAD_PC5 ((uint32_t)0x00000000) +#define COMP1_VIP_SEL_PAD_PB2 ((uint32_t)0x00000100) + +#define COMP2_VIP_SEL_PAD_PB4 ((uint32_t)0x00000000) +#define COMP2_VIP_SEL_PAD_PB6 ((uint32_t)0x00000100) + +#define COMP3_VIP_SEL_PAD_PA0 ((uint32_t)0x00000000) +#define COMP3_VIP_SEL_PAD_PC1 ((uint32_t)0x00000100) +#define COMP3_VIP_SEL_PAD_PA2 ((uint32_t)0x00000200) +#define COMP3_VIP_SEL_PAD_PA5 ((uint32_t)0x00000300) + +#define COMP4_VIP_SEL_PAD_PA2 ((uint32_t)0x00000000) +#define COMP4_VIP_SEL_PAD_PA5 ((uint32_t)0x00000100) +#define COMP4_VIP_SEL_PAD_PA0 ((uint32_t)0x00000200) +#define COMP4_VIP_SEL_PAD_PC1 ((uint32_t)0x00000300) + +#define COMP5_VIP_SEL_PAD_PB11 ((uint32_t)0x00000000) +#define COMP5_VIP_SEL_PAD_PB14 ((uint32_t)0x00000100) +#define COMP5_VIP_SEL_PAD_PA15 ((uint32_t)0x00000200) +#define COMP5_VIP_SEL_PAD_PC11 ((uint32_t)0x00000300) + +#define COMP6_VIP_SEL_PAD_PA15 ((uint32_t)0x00000000) +#define COMP6_VIP_SEL_PAD_PC11 ((uint32_t)0x00000100) +#define COMP6_VIP_SEL_PAD_PB11 ((uint32_t)0x00000200) +#define COMP6_VIP_SEL_PAD_PB14 ((uint32_t)0x00000300) + + +#define IS_COMP1_VIP_SEL(INPUT) (((INPUT) ==COMP1_VIP_SEL_PAD_PC5 ) || \ + ((INPUT) ==COMP1_VIP_SEL_PAD_PB2 ) ) + +#define IS_COMP2_VIP_SEL(INPUT) (((INPUT) ==COMP2_VIP_SEL_PAD_PB4 ) || \ + ((INPUT) ==COMP2_VIP_SEL_PAD_PB6 ) ) + +#define IS_COMP3_VIP_SEL(INPUT) (((INPUT) ==COMP3_VIP_SEL_PAD_PA0 ) || \ + ((INPUT) ==COMP3_VIP_SEL_PAD_PC1 ) || \ + ((INPUT) ==COMP3_VIP_SEL_PAD_PA2 ) || \ + ((INPUT) ==COMP3_VIP_SEL_PAD_PA5 ) ) + +#define IS_COMP4_VIP_SEL(INPUT) (((INPUT) == COMP4_VIP_SEL_PAD_PA2) || \ + ((INPUT) ==COMP4_VIP_SEL_PAD_PA5 ) || \ + ((INPUT) ==COMP4_VIP_SEL_PAD_PA0 ) || \ + ((INPUT) ==COMP4_VIP_SEL_PAD_PC1 ) ) + +#define IS_COMP5_VIP_SEL(INPUT) (((INPUT) ==COMP5_VIP_SEL_PAD_PB11 ) || \ + ((INPUT) ==COMP5_VIP_SEL_PAD_PB14 ) || \ + ((INPUT) ==COMP5_VIP_SEL_PAD_PA15 ) || \ + ((INPUT) ==COMP5_VIP_SEL_PAD_PC11 ) ) + +#define IS_COMP6_VIP_SEL(INPUT) (((INPUT) == COMP6_VIP_SEL_PAD_PA15) || \ + ((INPUT) ==COMP6_VIP_SEL_PAD_PC11 ) || \ + ((INPUT) ==COMP6_VIP_SEL_PAD_PB11 ) || \ + ((INPUT) ==COMP6_VIP_SEL_PAD_PB14 ) ) + +/** @defgroup COMP_VinSel + * @{ + */ +#define COMP1_VIN_1_4VREFINT ((uint32_t)0x00000000 | VREFEN) +#define COMP1_VIN_1_2VREFINT ((uint32_t)0x00000010 | VREFEN) +#define COMP1_VIN_3_4VREFINT ((uint32_t)0x00000020 | VREFEN) +#define COMP1_VIN_VREFINT ((uint32_t)0x00000030 | VREFEN) +#define COMP1_VIN_DAC1_CH1 ((uint32_t)0x00000040) +#define COMP1_VIN_DAC2_CH1 ((uint32_t)0x00000050) +#define COMP1_VIN_SEL_PAD_PB1 ((uint32_t)0x00000060) +#define COMP1_VIN_SEL_PAD_PC4 ((uint32_t)0x00000070) + +#define COMP2_VIN_1_4VREFINT ((uint32_t)0x00000000 | VREFEN) +#define COMP2_VIN_1_2VREFINT ((uint32_t)0x00000010 | VREFEN) +#define COMP2_VIN_3_4VREFINT ((uint32_t)0x00000020 | VREFEN) +#define COMP2_VIN_VREFINT ((uint32_t)0x00000030 | VREFEN) +#define COMP2_VIN_DAC1_CH1 ((uint32_t)0x00000040) +#define COMP2_VIN_DAC2_CH1 ((uint32_t)0x00000050) +#define COMP2_VIN_SEL_PAD_PB3 ((uint32_t)0x00000060) +#define COMP2_VIN_SEL_PAD_PB7 ((uint32_t)0x00000070) + +#define COMP3_VIN_3_4VREFINT ((uint32_t)0x00000020 | VREFEN) +#define COMP3_VIN_VREFINT ((uint32_t)0x00000030 | VREFEN) +#define COMP3_VIN_DAC1_CH1 ((uint32_t)0x00000040) +#define COMP3_VIN_DAC2_CH1 ((uint32_t)0x00000050) +#define COMP3_VIN_SEL_PAD_PC3 ((uint32_t)0x00000060) +#define COMP3_VIN_SEL_PAD_PC0 ((uint32_t)0x00000070) + +#define COMP4_VIN_1_4VREFINT ((uint32_t)0x00000000 | VREFEN) +#define COMP4_VIN_1_2VREFINT ((uint32_t)0x00000010 | VREFEN) +#define COMP4_VIN_3_4VREFINT ((uint32_t)0x00000020 | VREFEN) +#define COMP4_VIN_VREFINT ((uint32_t)0x00000030 | VREFEN) +#define COMP4_VIN_DAC1_CH1 ((uint32_t)0x00000040) +#define COMP4_VIN_DAC2_CH1 ((uint32_t)0x00000050) +#define COMP4_VIN_SEL_PAD_PA1 ((uint32_t)0x00000060) +#define COMP4_VIN_SEL_PAD_PA4 ((uint32_t)0x00000070) + +#define COMP5_VIN_3_4VREFINT ((uint32_t)0x00000020 | VREFEN) +#define COMP5_VIN_VREFINT ((uint32_t)0x00000030 | VREFEN) +#define COMP5_VIN_DAC1_CH1 ((uint32_t)0x00000040) +#define COMP5_VIN_DAC2_CH1 ((uint32_t)0x00000050) +#define COMP5_VIN_SEL_PAD_PB10 ((uint32_t)0x00000060) +#define COMP5_VIN_SEL_PAD_PB15 ((uint32_t)0x00000070) + +#define COMP6_VIN_1_4VREFINT ((uint32_t)0x00000000 | VREFEN) +#define COMP6_VIN_1_2VREFINT ((uint32_t)0x00000010 | VREFEN) +#define COMP6_VIN_3_4VREFINT ((uint32_t)0x00000020 | VREFEN) +#define COMP6_VIN_VREFINT ((uint32_t)0x00000030 | VREFEN) +#define COMP6_VIN_DAC1_CH1 ((uint32_t)0x00000040) +#define COMP6_VIN_DAC2_CH1 ((uint32_t)0x00000050) +#define COMP6_VIN_SEL_PAD_PC10 ((uint32_t)0x00000060) +#define COMP6_VIN_SEL_PAD_PC12 ((uint32_t)0x00000070) + + +#define IS_COMP1_VIN_SEL(INPUT) (((INPUT) ==COMP1_VIN_1_4VREFINT ) || \ + ((INPUT) == COMP1_VIN_1_2VREFINT ) || \ + ((INPUT) == COMP1_VIN_3_4VREFINT ) || \ + ((INPUT) == COMP1_VIN_VREFINT ) || \ + ((INPUT) == COMP1_VIN_DAC1_CH1 ) || \ + ((INPUT) == COMP1_VIN_DAC2_CH1 ) || \ + ((INPUT) == COMP1_VIN_SEL_PAD_PB1) || \ + ((INPUT) == COMP1_VIN_SEL_PAD_PC4) ) + +#define IS_COMP2_VIN_SEL(INPUT) (((INPUT) == COMP2_VIN_1_4VREFINT ) || \ + ((INPUT) ==COMP2_VIN_1_2VREFINT ) || \ + ((INPUT) ==COMP2_VIN_3_4VREFINT ) || \ + ((INPUT) ==COMP2_VIN_VREFINT ) || \ + ((INPUT) ==COMP2_VIN_DAC1_CH1 ) || \ + ((INPUT) ==COMP2_VIN_DAC2_CH1 ) || \ + ((INPUT) ==COMP2_VIN_SEL_PAD_PB3 ) || \ + ((INPUT) ==COMP2_VIN_SEL_PAD_PB7 ) ) + +#define IS_COMP3_VIN_SEL(INPUT) (((INPUT) == COMP3_VIN_3_4VREFINT ) || \ + ((INPUT) ==COMP3_VIN_VREFINT ) || \ + ((INPUT) ==COMP3_VIN_DAC1_CH1 ) || \ + ((INPUT) ==COMP3_VIN_DAC2_CH1 ) || \ + ((INPUT) ==COMP3_VIN_SEL_PAD_PC3 ) || \ + ((INPUT) ==COMP3_VIN_SEL_PAD_PC0 ) ) + +#define IS_COMP4_VIN_SEL(INPUT) (((INPUT) ==COMP4_VIN_1_4VREFINT ) || \ + ((INPUT) ==COMP4_VIN_1_2VREFINT ) || \ + ((INPUT) ==COMP4_VIN_3_4VREFINT ) || \ + ((INPUT) ==COMP4_VIN_VREFINT ) || \ + ((INPUT) ==COMP4_VIN_DAC1_CH1 ) || \ + ((INPUT) ==COMP4_VIN_DAC2_CH1 ) || \ + ((INPUT) ==COMP4_VIN_SEL_PAD_PA1 ) || \ + ((INPUT) ==COMP4_VIN_SEL_PAD_PA4 ) ) + +#define IS_COMP5_VIN_SEL(INPUT) (((INPUT) ==COMP5_VIN_3_4VREFINT ) || \ + ((INPUT) ==COMP5_VIN_VREFINT ) || \ + ((INPUT) ==COMP5_VIN_DAC1_CH1 ) || \ + ((INPUT) ==COMP5_VIN_DAC2_CH1 ) || \ + ((INPUT) ==COMP5_VIN_SEL_PAD_PB10 ) || \ + ((INPUT) ==COMP5_VIN_SEL_PAD_PB15 ) ) + +#define IS_COMP6_VIN_SEL(INPUT) (((INPUT) ==COMP6_VIN_1_4VREFINT ) || \ + ((INPUT) ==COMP6_VIN_1_2VREFINT ) || \ + ((INPUT) ==COMP6_VIN_3_4VREFINT ) || \ + ((INPUT) ==COMP6_VIN_VREFINT ) || \ + ((INPUT) ==COMP6_VIN_DAC1_CH1 ) || \ + ((INPUT) ==COMP6_VIN_DAC2_CH1 ) || \ + ((INPUT) ==COMP6_VIN_SEL_PAD_PC10 ) || \ + ((INPUT) ==COMP6_VIN_SEL_PAD_PC12 )) + +/** @defgroup COMP_Blanking_Sel + * @{ COMPx = comp1 /comp2/ comp3/ comp4/ comp5 /comp6 + */ +#define COMPx_BLANKING_NONE ((uint32_t)0x00000000) +#define COMPx_BLANKING_TIM1 ((uint32_t)0x00100000) +#define COMPx_BLANKING_TIM2 ((uint32_t)0x00200000) +#define COMPx_BLANKING_TIM3 ((uint32_t)0x00300000) +#define COMPx_BLANKING_TIM4 ((uint32_t)0x00400000) +#define COMPx_BLANKING_TIM8 ((uint32_t)0x00700000) +#define IS_COMP_BLANKING(INPUT) (((INPUT) == COMPx_BLANKING_NONE ) || \ + ((INPUT) == COMPx_BLANKING_TIM1 ) || \ + ((INPUT) == COMPx_BLANKING_TIM2 ) || \ + ((INPUT) == COMPx_BLANKING_TIM3 ) || \ + ((INPUT) == COMPx_BLANKING_TIM4 ) || \ + ((INPUT) == COMPx_BLANKING_TIM8 )) + +/** @defgroup COMP_Hysteresis_Sel + * @{ COMPx = comp1 /comp2/ comp3/ comp4/ comp5 /comp6 + */ +#define COMPx_HYST_NONE ((uint32_t)0x00000000) +#define COMPx_HYST_18MV ((uint32_t)0x00020000) +#define COMPx_HYST_36MV ((uint32_t)0x00040000) +#define COMPx_HYST_54MV ((uint32_t)0x00060000) +#define IS_COMP_HYSTERESIS(INPUT) (((INPUT) == COMPx_HYST_NONE ) || \ + ((INPUT) == COMPx_HYST_18MV ) || \ + ((INPUT) == COMPx_HYST_36MV ) || \ + ((INPUT) == COMPx_HYST_54MV )) + +/** @defgroup COMP_Pol + * @{COMPx = comp1 /comp2/ comp3/ comp4/ comp5 /comp6 + */ +#define COMPx_POL_NOT_INVERT ((uint32_t)0x00000000) +#define COMPx_POL_INVERT ((uint32_t)0x00008000) + +#define IS_COMP_POL(POL) (((POL) == COMPx_POL_NOT_INVERT)|| \ + ( (POL) == COMPx_POL_INVERT) ) + +/** @defgroup COMP_RAMP_SEL + * @{COMPx = comp1 /comp2 + */ +#define COMPx_RAMPSRC_PWM1 ((uint32_t)0x00000000) +#define COMPx_RAMPSRC_PWM2 ((uint32_t)0x01000000) +#define COMPx_RAMPSRC_PWM3 ((uint32_t)0x02000000) +#define COMPx_RAMPSRC_PWM4 ((uint32_t)0x03000000) + +#define IS_COMP_RAMPSRC(EPWM) (((EPWM) == COMPx_RAMPSRC_PWM1)|| \ + ((EPWM) == COMPx_RAMPSRC_PWM2)|| \ + ((EPWM) == COMPx_RAMPSRC_PWM3)|| \ + ((EPWM) == COMPx_RAMPSRC_PWM4)) + + + +/** @defgroup COMP_OutputLevel + * @{ + */ +/* When output polarity is not inverted, comparator output is high when + the non-inverting input is at a higher voltage than the inverting input */ +#define COMP_OutputLevel_High ((uint32_t)0x40000000) +/* When output polarity is not inverted, comparator output is low when + the non-inverting input is at a lower voltage than the inverting input*/ +#define COMP_OutputLevel_Low ((uint32_t)0x00000000) + + +#define IS_COMP_OUTPUT_LEVEL(LEVEL) (((LEVEL) == COMP_CSR_COMP1OUT) || \ + ((LEVEL) == COMP_CSR_COMP2OUT)) + + + + + +/* Initialization and Configuration functions *********************************/ +void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); +void COMP_DeInit(uint32_t COMP_Selection); + +/* Function used to set the COMP configuration to the default reset state ****/ +void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); +void COMP_WindowCmd(FunctionalState NewState, uint32_t COMP_Selection); +void COMPx_RAMP_EPWM_SEL(uint32_t COMP_1_2_Selection, uint32_t COMP_RAMP_SEL); +void COMPx_RAMP_RMPRLDIS(FunctionalState NewState, uint32_t COMP_1_2_Selection); +void COMP_RAMPVAL_SHADOW_LOAD(uint32_t COMP_1_2_Selection, uint16_t COMPx_RAMPDECVAL_SHADOW, uint16_t COMPx_RAMPMAXREF_SHADOW); + +void COMPx_QUALIFICATION(FunctionalState NewState, uint32_t COMP_1_2_Selection, uint32_t COMP_qualsel); +void COMPx_Resistor(FunctionalState NewState, uint32_t COMP_1_2_Selection); +void COMP_LockConfig(uint32_t COMP_Selection); +uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F0XX_COMP_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ + + + + + + + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_crc.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_crc.h new file mode 100644 index 00000000000..947da3cc98c --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_crc.h @@ -0,0 +1,97 @@ +/** + ****************************************************************************** + * @file ft32f4xx_crc.h + * @author FMD AE + * @brief This file contains all the functions prototypes for + * the CRC firmware library. + * @version V1.0.0 + * @date 2025-03-25 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_CRC_H +#define __FT32F4XX_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*!< Includes ----------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup CRC + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Constants I2S Exported Constants + * @{ + */ + +/** @defgroup CRC_ReverseInputData + * @{ + */ +#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ +#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ +#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ +#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ + +#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ + ((DATA) == CRC_ReverseInputData_8bits) || \ + ((DATA) == CRC_ReverseInputData_16bits) || \ + ((DATA) == CRC_ReverseInputData_32bits)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions ------------------------------------------------------- */ +/** @addtogroup CRC_Exported_Functions + * @{ + */ +/* Configuration of the CRC computation unit **********************************/ +void CRC_DeInit(void); +void CRC_ResetDR(void); +void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); +void CRC_ReverseOutputDataCmd(FunctionalState NewState); +void CRC_SetINITRegister(uint32_t CRC_InitValue); +void CRC_SetCRegister(uint32_t CRC_CRValue); + +/* CRC computation ************************************************************/ +uint32_t CRC_CalcCRC(uint32_t CRC_Data); +uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); +uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); + +/* Independent register (IDR) access (write/read) *****************************/ +void CRC_SetIDRegister(uint8_t CRC_IDValue); +uint8_t CRC_GetIDRegister(void); + +/* Control register (CR) access (read) *****************************/ +uint32_t CRC_GetCRegister(void); + +/* Initial value register (INIT) access (read) *****************************/ +uint32_t CRC_GetINITRegister(void); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_CRC_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_crs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_crs.h new file mode 100644 index 00000000000..ccaab2dc75d --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_crs.h @@ -0,0 +1,141 @@ +/** + ****************************************************************************** + * @file ft32f4xx_crs.h + ****************************************************************************** +**/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_CRS_H +#define __FT32F4XX_CRS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*!< Includes ----------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRS_Interrupt_Sources + * @{ + */ +#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ +#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ +#define CRS_IT_ERR CRS_ISR_ERRF /*!< error */ +#define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ +#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ +#define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ + +#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ + ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC)) + +#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ + ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \ + ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \ + ((IT) == CRS_IT_SYNCMISS)) + +#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00) + + +/** @defgroup CRS_Flags + * @{ + */ +#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ +#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ +#define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */ +#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ +#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ +#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ +#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ + +#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \ + ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \ + ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \ + ((FLAG) == CRS_FLAG_SYNCMISS)) + + +/** @defgroup CRS_Synchro_Source + * @{ + */ +#define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ +#define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ +#define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */ + +#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \ + ((SOURCE) == CRS_SYNCSource_LSE) ||\ + ((SOURCE) == CRS_SYNCSource_USB)) + + +/** @defgroup CRS_SynchroDivider + * @{ + */ +#define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */ +#define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ +#define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ +#define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ +#define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ +#define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ +#define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ +#define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ + +#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\ + ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \ + ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \ + ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128)) + + +/** @defgroup CRS_SynchroPolarity + * @{ + */ +#define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */ +#define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ + +#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \ + ((POLARITY) == CRS_SYNCPolarity_Falling)) + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Configuration of the CRS **********************************/ +void CRS_DeInit(void); +void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue); +void CRS_FrequencyErrorCounterCmd(FunctionalState NewState); +void CRS_AutomaticCalibrationCmd(FunctionalState NewState); +void CRS_SoftwareSynchronizationGenerate(void); +void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue); +void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue); +void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler); +void CRS_SynchronizationSourceConfig(uint32_t CRS_Source); +void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity); +uint32_t CRS_GetReloadValue(void); +uint32_t CRS_GetHSI48CalibrationValue(void); +uint32_t CRS_GetFrequencyErrorValue(void); +uint32_t CRS_GetFrequencyErrorDirection(void); + +/* Interrupts and flags management functions **********************************/ +void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState); +FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG); +void CRS_ClearFlag(uint32_t CRS_FLAG); +ITStatus CRS_GetITStatus(uint32_t CRS_IT); +void CRS_ClearITPendingBit(uint32_t CRS_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_CRS_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_dac.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_dac.h new file mode 100644 index 00000000000..54ff328a18e --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_dac.h @@ -0,0 +1,208 @@ +/** + ****************************************************************************** + * @file ft32f4xx_dac.h + * @author FMD xzhang + * @brief This file contains all the functions prototypes for the DAC + * firmware library. + * @version V1.0.0 + * @data 2025-03-26 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_DAC_H +#define __FT32F4XX_DAC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +/* Exported types ------------------------------------------------------------*/ +/** @defgroup dac Exported_Types dac Exported Types + * @{ + */ +/** + * @brief DAC Init structure definition + */ +typedef struct +{ + + uint32_t DAC_Trigger; /*!< Select the DAC trigger source from Timer or Exti. + This parameter can be a value of @ref DAC_Trigger */ + uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_OutputBuffer */ + uint32_t DAC_Input_sel; /*!< Select the DAC input source. + This parameter can be a value of @ref DAC_Input_sel */ + + uint32_t DAC_Output_sel; /*!< Select the DAC output pins. + This parameter can be a value of @ref DAC_Output_sel*/ + +} DAC_InitTypeDef; + + + +/** @defgroup DAC_1_2_Selection + * @{DAC1 ,DAC2 ,DAC12( dac double) + */ +#define DAC_CHANNEL_1 ((uint32_t)0x00000000) /*!< DAC1 Selection */ +#define DAC_CHANNEL_2 ((uint32_t)0x00000010) /*!< DAC2 Selection */ +#define DAC_CHANNEL_D12 ((uint32_t)0x00000011) /*!< DAC double Selection */ + +#define IS_DAC_1_2_PERIPH(PERIPH) (((PERIPH) == DAC_CHANNEL_1) || \ + ((PERIPH) == DAC_CHANNEL_2) || \ + ((PERIPH) == DAC_CHANNEL_D12)) + + +/** @defgroup Alignment DAC_data_alignment + * @{ + */ +#define DAC_ALIGN_12B_R 0x00000000U +#define DAC_ALIGN_12B_L 0x00000004U +#define DAC_ALIGN_8B_R 0x00000008U + +#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ + ((ALIGN) == DAC_ALIGN_12B_L) || \ + ((ALIGN) == DAC_ALIGN_8B_R)) + + +/** @defgroup DAC_Trigger DAC trigger selection + * @{ DAC1 and DAC2 + */ +#define DAC_TRIGGER_NONE 0x00000000UL /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T2_TRGO (TSEL1_2 | TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T4_TRGO (TSEL1_2 | TSEL1_0 | TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T5_TRGO ( TSEL1_1 | TSEL1_0 | TEN1) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T6_TRGO ( TEN1) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ( TSEL1_1 | TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T8_TRGO ( TSEL1_0 | TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 (TSEL1_2 | TSEL1_1 | TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE (DAC_CR_TSEL1_Msk | TEN1) /*!< Conversion started by software trigger for DAC channel */ + +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T5_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) + + +/** @defgroup amplitude :DACEx_triangle_amplitude DACEx lfsrunmask triangle amplitude + * @{ + */ +#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUNMASK_BITS1_0 ( MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS2_0 ( MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS3_0 ( MAMP1_1 | MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS4_0 ( MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS5_0 ( MAMP1_2 | MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS6_0 ( MAMP1_2 | MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS7_0 ( MAMP1_2 | MAMP1_1 | MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS8_0 (MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS9_0 (MAMP1_3 | MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS10_0 (MAMP1_3 | MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUNMASK_BITS11_0 (MAMP1_3 | MAMP1_1 | MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */ +#define DAC_TRIANGLEAMPLITUDE_3 ( MAMP1_0) /*!< Select max triangle amplitude of 3 */ +#define DAC_TRIANGLEAMPLITUDE_7 ( MAMP1_1 ) /*!< Select max triangle amplitude of 7 */ +#define DAC_TRIANGLEAMPLITUDE_15 ( MAMP1_1 | MAMP1_0) /*!< Select max triangle amplitude of 15 */ +#define DAC_TRIANGLEAMPLITUDE_31 ( MAMP1_2 ) /*!< Select max triangle amplitude of 31 */ +#define DAC_TRIANGLEAMPLITUDE_63 ( MAMP1_2 | MAMP1_0) /*!< Select max triangle amplitude of 63 */ +#define DAC_TRIANGLEAMPLITUDE_127 ( MAMP1_2 | MAMP1_1 ) /*!< Select max triangle amplitude of 127 */ +#define DAC_TRIANGLEAMPLITUDE_255 ( MAMP1_2 | MAMP1_1 | MAMP1_0) /*!< Select max triangle amplitude of 255 */ +#define DAC_TRIANGLEAMPLITUDE_511 (MAMP1_3 ) /*!< Select max triangle amplitude of 511 */ +#define DAC_TRIANGLEAMPLITUDE_1023 (MAMP1_3 | MAMP1_0) /*!< Select max triangle amplitude of 1023 */ +#define DAC_TRIANGLEAMPLITUDE_2047 (MAMP1_3 | MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */ +#define DAC_TRIANGLEAMPLITUDE_4095 (MAMP1_3 | MAMP1_1 | MAMP1_0) /*!< Select max triangle amplitude of 4095 */ + + + +#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \ + ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \ + ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095)) + +/** @defgroup DAC_OutputBuffer + * @{ + */ +#define DAC_OUTPUTBUFFER_ENABLE 0x00000002U +#define DAC_OUTPUTBUFFER_DISABLE 0x00000000U + +#define IS_DAC_BUFFER(BUFFER) (((BUFFER) == DAC_OUTPUTBUFFER_ENABLE)|| \ + ( (BUFFER) == DAC_OUTPUTBUFFER_DISABLE)) + + +/** @defgroup DAC_Input_sel + * @{ + */ +#define DAC_INPUT_SEL_DOR 0x00000000U +#define DAC_INPUT_SEL_RAMP 0x00004000U + + +#define IS_DAC_INPUT(input) (((INPUT) ==DAC_INPUT_SEL_DOR ) || \ + ((INPUT) == DAC_INPUT_SEL_RAMP)) + + +/** @defgroup DAC_Output_sel + * @{ + */ +#define DAC_OUTPUT_SEL_PAD 0x00000000U +#define DAC_OUTPUT_SEL_Analog 0x00008000U + +#define IS_DAC_OUTPUT(output) (((output) == DAC_OUTPUT_SEL_PAD) || \ + ((output) == DAC_OUTPUT_SEL_Analog)) + + +/* Initialization and Configuration functions *********************************/ +void DAC_Init(uint32_t DAC_1_2_Selection, DAC_InitTypeDef* DAC_InitStruct); +void DAC_DeInit(uint32_t DAC_1_2_Selection); +void DAC_Start(uint32_t DAC_1_2_Selection); +void DAC_STOP(uint32_t DAC_1_2_Selection); +/* Function used to set the DAC configuration to the default reset state ****/ +void DAC_SetValue(uint32_t DAC_1_2_Selection, uint32_t Alignment, uint32_t Data); +uint32_t DAC_GetValue(uint32_t DAC_1_2_Selection); +void DAC_Start_DMA(uint32_t DAC_1_2_Selection, FunctionalState NewState); +void DAC_Stop_DMA(uint32_t DAC_1_2_Selection); +void DAC_TriangleWaveGenerate(uint32_t DAC_1_2_Selection, uint32_t Amplitude); +void DAC_NoiseWaveGenerate(uint32_t DAC_1_2_Selection, uint32_t Amplitude); +void Delay_read (void) ; + +#ifdef __cplusplus +} +#endif + +#endif /*__ft32f4XX_DAC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_debug.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_debug.h new file mode 100644 index 00000000000..b841aac399a --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_debug.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file ft32f4xx_debug.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the DBGMCU firmware + * library. + * @version V1.0.0 + * @data 2025-04-08 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_DBGMCU_H +#define __FT32F4XX_DBGMCU_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup DBGMCU + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup DBGMCU_Exported_Constants + * @{ + */ + +#define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP +#define DBGMCU_STOP DBGMCU_CR_DBG_STOP +#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY + +#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) + +/* DEBUG MCU APB1 Freeze Register bits */ +#define DBGMCU_CAN4_STOP DBG_CAN4_STOP +#define DBGMCU_CAN3_STOP DBG_CAN3_STOP +#define DBGMCU_CAN2_STOP DBG_CAN2_STOP +#define DBGMCU_CAN1_STOP DBG_CAN1_STOP +#define DBGMCU_I2C3_SMBUS_TIMEOUT_STOP DBG_I2C3_SMBUS_STOP +#define DBGMCU_I2C2_SMBUS_TIMEOUT_STOP DBG_I2C2_SMBUS_STOP +#define DBGMCU_I2C1_SMBUS_TIMEOUT_STOP DBG_I2C1_SMBUS_STOP +#define DBGMCU_WWDG_STOP DBG_WWDG_STOP +#define DBGMCU_IWDG_STOP DBG_IWDG_STOP +#define DBGMCU_RTC_STOP DBG_RTC_STOP +#define DBGMCU_TIM14_STOP DBG_TIM14_STOP +#define DBGMCU_TIM13_STOP DBG_TIM13_STOP +#define DBGMCU_TIM12_STOP DBG_TIM12_STOP +#define DBGMCU_TIM7_STOP DBG_TIM7_STOP +#define DBGMCU_TIM6_STOP DBG_TIM6_STOP +#define DBGMCU_TIM5_STOP DBG_TIM5_STOP +#define DBGMCU_TIM4_STOP DBG_TIM4_STOP +#define DBGMCU_TIM3_STOP DBG_TIM3_STOP +#define DBGMCU_TIM2_STOP DBG_TIM2_STOP + +#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xE11FE200) == 0x00) && ((PERIPH) != 0x00)) + +/* DEBUG MCU APB2 Freeze Register bits */ +#define DBGMCU_EPWM4_STOP DBG_EPWM4_STOP +#define DBGMCU_EPWM3_STOP DBG_EPWM3_STOP +#define DBGMCU_EPWM2_STOP DBG_EPWM2_STOP +#define DBGMCU_EPWM1_STOP DBG_EPWM1_STOP +#define DBGMCU_TIM10_STOP DBG_TIM10_STOP +#define DBGMCU_TIM9_STOP DBG_TIM9_STOP +#define DBGMCU_LPTIM_STOP DBG_LPTIM_STOP +#define DBGMCU_TIM8_STOP DBG_TIM8_STOP +#define DBGMCU_TIM1_STOP DBG_TIM1_STOP + +#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0x87F8FFF8) == 0x00) && ((PERIPH) != 0x00)) + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Device and Revision ID management functions ********************************/ +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); + +/* Peripherals Configuration functions ****************************************/ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_DBGMCU_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_dma.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_dma.h new file mode 100644 index 00000000000..bb670c0e255 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_dma.h @@ -0,0 +1,743 @@ +/** + ****************************************************************************** + * @file ft32f4xx_dma.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the DMA firmware + * library. + * @version V1.0.0 + * @data 2025-04-15 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_DMA_H +#define __FT32F4XX_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup DMA + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief DMA Init structures definition + */ +typedef struct +{ + uint32_t SrcAddress; /*!< Specifies the source address for DMAy Channelx. */ + uint32_t DstAddress; /*!< Specifies the destination address for DMAy Channelx. */ + + uint32_t BlockTransSize; /*!< Specifies the block transfer size for DMAy Channelx. + This parameter must be a number between 1 and 65535 + @ref DMA_block_transfer_size */ + + uint32_t SrcDstMasterSel; /*!< Specifies the source/destination master select for DMAy Channelx. + This parameter can be a value of @ref DMA_src_dst_master_select */ + + uint32_t TransferTypeFlowCtl; /*!< Specifies the transfer type and flow control for DMAy Channelx. + This parameter can be a value of @ref DMA_trans_type_flow_control */ + + uint32_t SrcBurstTransferLength; /*!< Specifies the source burst transaction length for DMAy Channelx. + The number of data with a width of DMA_SrcTransWidth. + This parameter can be a value of @ref DMA_src_burst_trans_length */ + + uint32_t DstBurstTransferLength; /*!< Specifies the destination burst transaction length for DMAy Channelx. + The number of data with a width of DMA_DstTransWidth. + This parameter can be a value of @ref DMA_dst_burst_trans_length */ + + uint32_t SrcAddrMode; /*!< Specifies the source address increment for DMAy Channelx. + This parameter can be a value of @ref DMA_src_addr_increment_mode */ + + uint32_t DstAddrMode; /*!< Specifies the destination address increment for DMAy Channelx. + This parameter can be a value of @ref DMA_dst_addr_increment_mode */ + + uint32_t SrcTransferWidth; /*!< Specifies the srouce transfer width for DMAy Channelx. + This parameter can be a value of @ref DMA_src_trans_width */ + + uint32_t DstTransferWidth; /*!< Specifies the destination transfer width for DMAy Channelx. + This parameter can be a value of @ref DMA_dst_trans_width */ + + + uint32_t DstHardwareInterface; /*!< Specifies a hardware handshaking interface to the destination of DMAy Channelx + if the CFGx.HS_SEL_DST field is 0. + Each channel is equipped with 8 destination hardware handshaking interfaces, such as: + DMA_DST_HARDWARE_INTERFACE_0 + ... + DMA_DST_HARDWARE_INTERFACE_7 + By configuring the DstHsIfPeriphSel field, each destination hardware handshaking interface + can be selectively assigned to support up to 8 peripheral requests. For example, + DMA_DST_HARDWARE_INTERFACE_0 of DMA1 provieds configurable options inculding: + SPI3_RX + I2C1_RX + TIM4_CH1 + LPUART_RX + UART5_RX + TIM5_CH3 + TIM5_UP + This parameter can be a value of @ref DMA_dst_hardware_interface */ + + uint32_t SrcHardwareInterface; /*!< Specifies a hardware handshaking interface to the source of DMAy Channelx + if the CFGx.HS_SEL_SRC field is 0. + Each channel is equipped with 8 source hardware handshaking interfaces, such as: + DMA_SRC_HARDWARE_INTERFACE_0 + ... + DMA_SRC_HARDWARE_INTERFACE_7 + By configuring the SrcHsIfPeriphSel field, each source hardware handshaking interface + can be selectively assigned to support up to 8 peripheral requests. For example, + DMA_SRC_HARDWARE_INTERFACE_0 of DMA2 provieds configurable options inculding: + ADC1 + ADC3 + SPI1_RX + SPDIF_CB + TIM1_TRIG + This parameter can be a value of @ref DMA_src_hardware_interface */ + + FunctionalState FIFOMode; /*!< Specifies the FIFO mode select for DMAy Channelx. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState FlowCtlMode; /*!< Specifies the flow control mode for DMAy Channelx. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReloadDst; /*!< Specifies the automatic destination reload for DMAy Channelx. + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState ReloadSrc; /*!< Specifies the automatic source reload for DMAy Channelx. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t MaxBurstLength; /*!< Specifies the maximum AMBA burst length for DMAy Channelx. + A value of 0 indicates that software is not limiting the + maximum AMBA burst length for DMA transfers on this channel. + This parameter can be a number greater than the maximum values + of src_burst_size_bytes and dst_burst_size_bytes. + +src_burst_size_bytes=SRC_MSIZE*SRC_TR_WIDTH; + +dst_burst_size_bytes=DST_MSIZE*DST_TR_WIDTH. */ + + uint32_t SrcHsIfPol; /*!< Specifies the source handshaking interface polarity for DMAy Channelx. + This parameter can be a value of @ref DMA_src_hs_if_polarity */ + + uint32_t DstHsIfPol; /*!< Specifies the destination handshaking interface polarity for DMAy Channelx. + This parameter can be a value of @ref DMA_dst_hs_if_polarity */ + + uint32_t SrcHsSel; /*!< Specifies the source software or handware handshaking select for DMAy Channelx. + This parameter can be a value of @ref DMA_src_hs_select */ + + uint32_t DstHsSel; /*!< Specifies the destination software or handware handshaking select for DMAy Channelx. + This parameter can be a value of @ref DMA_dst_hs_select */ + + uint32_t Polarity; /*!< Specifies the channel polarity for DMAy Channelx. + This parameter can be a value of @ref DMA_channel_polarity */ + + uint32_t SrcHsIfPeriphSel; /*!< Specifies the peripheral request for the handshake interface. + This parameter can be a value of @ref DMA_src_handshake_interface_channel_select */ + + uint32_t DstHsIfPeriphSel; /*!< Specifies the peripheral request for the handshake interface. + This parameter can be a value of @ref DMA_dst_handshake_interface_channel_select */ + +} DMA_InitTypeDef; + + +/** + * @brief DMA base address and channel index definition + */ +typedef struct +{ + DMA_TypeDef *BaseAddress; + uint32_t ChannelIndex; +} DMA_BaseAddressAndChannelIndex; + + +/** + * @brief DMA Software Request definition + */ +typedef enum +{ + DMA_SW_REQUEST_SRC = 0x00U, // + DMA_SW_REQUEST_DST = 0x01U, + DMA_SW_REQUEST_SRC_SGL = 0x02U, + DMA_SW_REQUEST_DST_SGL = 0x03U, + DMA_SW_REQUEST_SRC_LST = 0x04U, + DMA_SW_REQUEST_DST_LST = 0x05U +} DMA_SoftwareRequestTypeDef; + +#define IS_DMA_SOFTWARE_REQUEST(TYPE) (((TYPE) == DMA_SW_REQUEST_SRC) || \ + ((TYPE) == DMA_SW_REQUEST_DST) || \ + ((TYPE) == DMA_SW_REQUEST_SRC_SGL) || \ + ((TYPE) == DMA_SW_REQUEST_DST_SGL) || \ + ((TYPE) == DMA_SW_REQUEST_SRC_LST) || \ + ((TYPE) == DMA_SW_REQUEST_DST_LST) ) + +/** + * @brief DMA_interrupts_definition DMA_IT + */ +#define DMA_IT_TFR 0x01U +#define DMA_IT_BLOCK 0x02U +#define DMA_IT_SRC 0x04U +#define DMA_IT_DST 0x08U +#define DMA_IT_ERR 0x10U + +#define IS_DMA_IT(TYPE) (((TYPE) == DMA_IT_TFR) || \ + ((TYPE) == DMA_IT_BLOCK) || \ + ((TYPE) == DMA_IT_SRC) || \ + ((TYPE) == DMA_IT_DST) || \ + ((TYPE) == DMA_IT_ERR)) + + +/** + * @brief DMA_interrupts_flag_definition DMA_FLAG + */ +#define DMA_FLAG_TFR 0x01U +#define DMA_FLAG_BLOCK 0x02U +#define DMA_FLAG_SRC 0x04U +#define DMA_FLAG_DST 0x08U +#define DMA_FLAG_ERR 0x10U + +#define IS_DMA_FLAG(FLAG) (((FLAG) == DMA_FLAG_TFR) || \ + ((FLAG) == DMA_FLAG_BLOCK) || \ + ((FLAG) == DMA_FLAG_SRC) || \ + ((FLAG) == DMA_FLAG_DST) || \ + ((FLAG) == DMA_FLAG_ERR)) + + +/** + * @brief Enable the specified DMA. + * @param DMAx DMA base address + * @retval None + */ +#define DMA_ENABLE(DMAx) ((DMAx)->DMACFG |= DMA_DMACFG_DMA_EN) + + +/** + * @brief Disable the specified DMA. + * @param DMAx DMA base address + * @retval None + */ +#define DMA_DISABLE(DMAx) ((DMAx)->DMACFG &= ~DMA_DMACFG_DMA_EN) + + +/** @defgroup DMA_block_transfer_size + * @{ + */ +#define IS_DMA_BLOCK_TRANSFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) <= 0xFFFFU)) + +/** + * @} + */ + + +/** @defgroup DMA_src_dst_master_select + * @{ + */ +#define DMA_SRCMASTER1_DSTMASTER1 0U +#define DMA_SRCMASTER1_DSTMASTER2 DMA_CTL_DMS +#define DMA_SRCMASTER2_DSTMASTER1 DMA_CTL_SMS +#define DMA_SRCMASTER2_DSTMASTER2 (DMA_CTL_SMS | DMA_CTL_DMS) + +#define IS_DMA_SRC_DST_MASTER_SEL(MASTER) (((MASTER) == DMA_SRCMASTER1_DSTMASTER1) || \ + ((MASTER) == DMA_SRCMASTER1_DSTMASTER2) || \ + ((MASTER) == DMA_SRCMASTER2_DSTMASTER1) || \ + ((MASTER) == DMA_SRCMASTER2_DSTMASTER2)) +/** + * @} + */ + +/** @defgroup DMA_trans_type_flow_control + * @{ + */ +#define DMA_TRANSFERTYPE_FLOWCTL_M2M_DMA 0U +#define DMA_TRANSFERTYPE_FLOWCTL_M2P_DMA DMA_CTL_TT_FC_0 +#define DMA_TRANSFERTYPE_FLOWCTL_P2M_DMA DMA_CTL_TT_FC_1 +#define DMA_TRANSFERTYPE_FLOWCTL_P2P_DMA (DMA_CTL_TT_FC_0 | DMA_CTL_TT_FC_1) +#define DMA_TRANSFERTYPE_FLOWCTL_P2M_PRE DMA_CTL_TT_FC_2 +#define DMA_TRANSFERTYPE_FLOWCTL_P2P_SRCPRE (DMA_CTL_TT_FC_0 | DMA_CTL_TT_FC_2) +#define DMA_TRANSFERTYPE_FLOWCTL_M2P_PRE (DMA_CTL_TT_FC_1 | DMA_CTL_TT_FC_2) +#define DMA_TRANSFERTYPE_FLOWCTL_P2P_DSTPRE DMA_CTL_TT_FC + +#define IS_DMA_TRANS_TYPE_FLOW_CTL(TYPE) (((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_M2M_DMA ) || \ + ((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_M2P_DMA ) || \ + ((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_P2M_DMA ) || \ + ((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_P2P_DMA ) || \ + ((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_P2M_PRE ) || \ + ((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_P2P_SRCPRE) || \ + ((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_M2P_PRE ) || \ + ((TYPE) == DMA_TRANSFERTYPE_FLOWCTL_P2P_DSTPRE)) +/** + * @} + */ + + +/** @defgroup DMA_src_burst_trans_length + * @{ + */ +#define DMA_SRC_BURSTTRANSFERLENGTH_1 0U +#define DMA_SRC_BURSTTRANSFERLENGTH_4 DMA_CTL_SRC_MSIZE_0 +#define DMA_SRC_BURSTTRANSFERLENGTH_8 DMA_CTL_SRC_MSIZE_1 +#define DMA_SRC_BURSTTRANSFERLENGTH_16 DMA_CTL_SRC_MSIZE + +#define IS_DMA_SRC_BURST_TRANS_LENGTH(LENGTH) (((LENGTH) == DMA_SRC_BURSTTRANSFERLENGTH_1 ) || \ + ((LENGTH) == DMA_SRC_BURSTTRANSFERLENGTH_4 ) || \ + ((LENGTH) == DMA_SRC_BURSTTRANSFERLENGTH_8 ) || \ + ((LENGTH) == DMA_SRC_BURSTTRANSFERLENGTH_16)) +/** + * @} + */ + + +/** @defgroup DMA_dst_burst_trans_length + * @{ + */ +#define DMA_DST_BURSTTRANSFERLENGTH_1 0U +#define DMA_DST_BURSTTRANSFERLENGTH_4 DMA_CTL_SRC_MSIZE_0 +#define DMA_DST_BURSTTRANSFERLENGTH_8 DMA_CTL_SRC_MSIZE_1 +#define DMA_DST_BURSTTRANSFERLENGTH_16 DMA_CTL_DEST_MSIZE + +#define IS_DMA_DST_BURST_TRANS_LENGTH(LENGTH) (((LENGTH) == DMA_DST_BURSTTRANSFERLENGTH_1 ) || \ + ((LENGTH) == DMA_DST_BURSTTRANSFERLENGTH_4 ) || \ + ((LENGTH) == DMA_DST_BURSTTRANSFERLENGTH_8 ) || \ + ((LENGTH) == DMA_DST_BURSTTRANSFERLENGTH_16)) +/** + * @} + */ + + +/** @defgroup DMA_src_addr_increment_mode + * @{ + */ +#define DMA_SRC_ADDRMODE_INC 0U +#define DMA_SRC_ADDRMODE_DEC DMA_CTL_SINC_0 +#define DMA_SRC_ADDRMODE_HOLD DMA_CTL_SINC_1 + +#define IS_DMA_SRC_ADDR_MODE(MODE) (((MODE) == DMA_SRC_ADDRMODE_INC ) || \ + ((MODE) == DMA_SRC_ADDRMODE_DEC ) || \ + ((MODE) == DMA_SRC_ADDRMODE_HOLD)) +/** + * @} + */ + + +/** @defgroup DMA_dst_addr_increment_mode + * @{ + */ +#define DMA_DST_ADDRMODE_INC 0U +#define DMA_DST_ADDRMODE_DEC DMA_CTL_DINC_0 +#define DMA_DST_ADDRMODE_HOLD DMA_CTL_DINC_1 + +#define IS_DMA_DST_ADDR_MODE(MODE) (((MODE) == DMA_DST_ADDRMODE_INC ) || \ + ((MODE) == DMA_DST_ADDRMODE_DEC ) || \ + ((MODE) == DMA_DST_ADDRMODE_HOLD)) +/** + * @} + */ + + +/** @defgroup DMA_src_trans_width + * @{ + */ +#define DMA_SRC_TRANSFERWIDTH_8BITS 0U +#define DMA_SRC_TRANSFERWIDTH_16BITS DMA_CTL_SRC_TR_WIDTH_0 +#define DMA_SRC_TRANSFERWIDTH_32BITS DMA_CTL_SRC_TR_WIDTH_1 + +#define IS_DMA_SRC_TRANS_WIDTH(WIDTH) (((WIDTH) == DMA_SRC_TRANSFERWIDTH_8BITS ) || \ + ((WIDTH) == DMA_SRC_TRANSFERWIDTH_16BITS) || \ + ((WIDTH) == DMA_SRC_TRANSFERWIDTH_32BITS)) +/** + * @} + */ + + +/** @defgroup DMA_dst_trans_width + * @{ + */ +#define DMA_DST_TRANSFERWIDTH_8BITS 0U +#define DMA_DST_TRANSFERWIDTH_16BITS DMA_CTL_DST_TR_WIDTH_0 +#define DMA_DST_TRANSFERWIDTH_32BITS DMA_CTL_DST_TR_WIDTH_1 + +#define IS_DMA_DST_TRANS_WIDTH(WIDTH) (((WIDTH) == DMA_DST_TRANSFERWIDTH_8BITS ) || \ + ((WIDTH) == DMA_DST_TRANSFERWIDTH_16BITS) || \ + ((WIDTH) == DMA_DST_TRANSFERWIDTH_32BITS)) +/** + * @} + */ + + +/** @defgroup DMA_dst_hardware_interface + * @{ + */ +#define DMA_DST_HARDWARE_INTERFACE_0 0U +#define DMA_DST_HARDWARE_INTERFACE_1 1U +#define DMA_DST_HARDWARE_INTERFACE_2 2U +#define DMA_DST_HARDWARE_INTERFACE_3 3U +#define DMA_DST_HARDWARE_INTERFACE_4 4U +#define DMA_DST_HARDWARE_INTERFACE_5 5U +#define DMA_DST_HARDWARE_INTERFACE_6 6U +#define DMA_DST_HARDWARE_INTERFACE_7 7U + +#define IS_DMA_DST_HW_IF(IF) (((IF) == DMA_DST_HARDWARE_INTERFACE_0) || \ + ((IF) == DMA_DST_HARDWARE_INTERFACE_1) || \ + ((IF) == DMA_DST_HARDWARE_INTERFACE_2) || \ + ((IF) == DMA_DST_HARDWARE_INTERFACE_3) || \ + ((IF) == DMA_DST_HARDWARE_INTERFACE_4) || \ + ((IF) == DMA_DST_HARDWARE_INTERFACE_5) || \ + ((IF) == DMA_DST_HARDWARE_INTERFACE_6) || \ + ((IF) == DMA_DST_HARDWARE_INTERFACE_7)) +/** + * @} + */ + + +/** @defgroup DMA_src_hardware_interface + * @{ + */ +#define DMA_SRC_HARDWARE_INTERFACE_0 0U +#define DMA_SRC_HARDWARE_INTERFACE_1 1U +#define DMA_SRC_HARDWARE_INTERFACE_2 2U +#define DMA_SRC_HARDWARE_INTERFACE_3 3U +#define DMA_SRC_HARDWARE_INTERFACE_4 4U +#define DMA_SRC_HARDWARE_INTERFACE_5 5U +#define DMA_SRC_HARDWARE_INTERFACE_6 6U +#define DMA_SRC_HARDWARE_INTERFACE_7 7U + +#define IS_DMA_SRC_HW_IF(IF) (((IF) == DMA_SRC_HARDWARE_INTERFACE_0) || \ + ((IF) == DMA_SRC_HARDWARE_INTERFACE_1) || \ + ((IF) == DMA_SRC_HARDWARE_INTERFACE_2) || \ + ((IF) == DMA_SRC_HARDWARE_INTERFACE_3) || \ + ((IF) == DMA_SRC_HARDWARE_INTERFACE_4) || \ + ((IF) == DMA_SRC_HARDWARE_INTERFACE_5) || \ + ((IF) == DMA_SRC_HARDWARE_INTERFACE_6) || \ + ((IF) == DMA_SRC_HARDWARE_INTERFACE_7)) +/** + * @} + */ + + +///** @defgroup DMA_fifo_mode_select +// * @{ +// */ +//#define DMA_FIFOMODE_DISABLE 0U +//#define DMA_FIFOMODE_ENABLE 1U +////#define DMA_FIFOMODE_ENABLE DMA_CFG_FIFO_MODE +// +//#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE) || \ +// ((STATE) == DMA_FIFOMODE_ENABLE )) +///** +// * @} +// */ + + +///** @defgroup DMA_fc_mode +// * @{ +// */ +//#define DMA_FLOWCTLMODE_DISABLE 0U +//#define DMA_FLOWCTLMODE_ENABLE 1U +////#define DMA_FLOWCTLMODE_ENABLE DMA_CFG_FCMODE +// +//#define IS_DMA_FCMODE_STATE(STATE) (((STATE) == DMA_FLOWCTLMODE_DISABLE) || \ +// ((STATE) == DMA_FLOWCTLMODE_ENABLE )) +///** +// * @} +// */ + + +///** @defgroup DMA_reload_destination +// * @{ +// */ +//#define DMA_RELOADDST_DISABLE 0U +//#define DMA_RELOADDST_ENABLE 1U +// +//#define IS_DMA_RELOAD_DST_STATE(STATE) (((STATE) == DMA_RELOADDST_DISABLE) || \ +// ((STATE) == DMA_RELOADDST_ENABLE )) +///** +// * @} +// */ +// +// +///** @defgroup DMA_reload_source +// * @{ +// */ +//#define DMA_RELOADSRC_DISABLE 0U +//#define DMA_RELOADSRC_ENABLE 1U +// +//#define IS_DMA_RELOAD_SRC_STATE(STATE) (((STATE) == DMA_RELOADSRC_DISABLE) || \ +// ((STATE) == DMA_RELOADSRC_ENABLE )) +///** +// * @} +// */ + + +/** @defgroup DMA_src_hs_if_polarity + * @{ + */ +#define DMA_SRCHSIFPOL_HIGH 0U +#define DMA_SRCHSIFPOL_LOW 1U + +#define IS_DMA_SRC_HS_IF_POL(MODE) (((MODE) == DMA_SRCHSIFPOL_HIGH) || \ + ((MODE) == DMA_SRCHSIFPOL_LOW )) +/** + * @} + */ + + +/** @defgroup DMA_dst_hs_if_polarity + * @{ + */ +#define DMA_DSTHSIFPOL_HIGH 0U +#define DMA_DSTHSIFPOL_LOW 1U + +#define IS_DMA_DST_HS_IF_POL(MODE) (((MODE) == DMA_DSTHSIFPOL_HIGH) || \ + ((MODE) == DMA_DSTHSIFPOL_LOW )) +/** + * @} + */ + + +/** @defgroup DMA_src_hs_select + * @{ + */ +#define DMA_SRCHSSEL_HARDWARE 0U +#define DMA_SRCHSSEL_SOFTWARE 1U + +#define IS_DMA_SRC_HS_SEL(MODE) (((MODE) == DMA_SRCHSSEL_HARDWARE) || \ + ((MODE) == DMA_SRCHSSEL_SOFTWARE)) +/** + * @} + */ + + +/** @defgroup DMA_dst_hs_select + * @{ + */ +#define DMA_DSTHSSEL_HARDWARE 0U +#define DMA_DSTHSSEL_SOFTWARE 1U + +#define IS_DMA_DST_HS_SEL(MODE) (((MODE) == DMA_DSTHSSEL_HARDWARE) || \ + ((MODE) == DMA_DSTHSSEL_SOFTWARE)) +/** + * @} + */ + + +/** @defgroup DMA_channel_suspend + * @{ + */ +#define DMA_CHANNELSUSPEND_DISABLE 0U +#define DMA_CHANNELSUSPEND_ENABLE 1U + +#define IS_DMA_CHANNEL_SUSPEND_STATE(STATE) (((STATE) == DMA_CHANNELSUSPEND_DISABLE) || \ + ((STATE) == DMA_CHANNELSUSPEND_ENABLE )) +/** + * @} + */ + + +/** @defgroup DMA_channel_polarity + * @{ + */ +#define DMA_CH_POLARITY_0 0U +#define DMA_CH_POLARITY_1 1U +#define DMA_CH_POLARITY_2 2U +#define DMA_CH_POLARITY_3 3U +#define DMA_CH_POLARITY_4 4U +#define DMA_CH_POLARITY_5 5U +#define DMA_CH_POLARITY_6 6U +#define DMA_CH_POLARITY_7 7U + +#define IS_DMA_CHANNEL_POLARITY(POLARITY) (((POLARITY) == DMA_CH_POLARITY_0) || \ + ((POLARITY) == DMA_CH_POLARITY_1) || \ + ((POLARITY) == DMA_CH_POLARITY_2) || \ + ((POLARITY) == DMA_CH_POLARITY_3) || \ + ((POLARITY) == DMA_CH_POLARITY_4) || \ + ((POLARITY) == DMA_CH_POLARITY_5) || \ + ((POLARITY) == DMA_CH_POLARITY_6) || \ + ((POLARITY) == DMA_CH_POLARITY_7)) +/** + * @} + */ + + +/** @defgroup DMA_enable + * @{ + */ +#define DMA_Disable ((uint64_t)0x0000000000000000) +#define DMA_Enable ((uint64_t)0x0000000000000001) + +#define IS_DMA_ENABLE(STATUS) (((STATUS) == DMA_Disable) || ((STATUS) == DMA_Enable)) +/** + * @} + */ + + +/** @defgroup DMA_channel_enable_write + * @{ + */ +#define DMA_ChannelEnable_EN_0 ((uint64_t)0x0000000000000100) +#define DMA_ChannelEnable_EN_1 ((uint64_t)0x0000000000000200) +#define DMA_ChannelEnable_EN_2 ((uint64_t)0x0000000000000400) +#define DMA_ChannelEnable_EN_3 ((uint64_t)0x0000000000000800) +#define DMA_ChannelEnable_EN_4 ((uint64_t)0x0000000000001000) +#define DMA_ChannelEnable_EN_5 ((uint64_t)0x0000000000002000) +#define DMA_ChannelEnable_EN_6 ((uint64_t)0x0000000000004000) +#define DMA_ChannelEnable_EN_7 ((uint64_t)0x0000000000008000) + +#define IS_DMA_CHANNEL_ENABLE_EN(CHANNEL) (((CHANNEL) == DMA_ChannelEnable_EN_0) || \ + ((CHANNEL) == DMA_ChannelEnable_EN_1) || \ + ((CHANNEL) == DMA_ChannelEnable_EN_2) || \ + ((CHANNEL) == DMA_ChannelEnable_EN_3) || \ + ((CHANNEL) == DMA_ChannelEnable_EN_4) || \ + ((CHANNEL) == DMA_ChannelEnable_EN_5) || \ + ((CHANNEL) == DMA_ChannelEnable_EN_6) || \ + ((CHANNEL) == DMA_ChannelEnable_EN_7)) + +/** + * @} + */ + +/** @defgroup DMA_channel_enable + * @{ + */ +#define DMA_ChannelEnable_0 ((uint64_t)0x0000000000000001) +#define DMA_ChannelEnable_1 ((uint64_t)0x0000000000000002) +#define DMA_ChannelEnable_2 ((uint64_t)0x0000000000000004) +#define DMA_ChannelEnable_3 ((uint64_t)0x0000000000000008) +#define DMA_ChannelEnable_4 ((uint64_t)0x0000000000000010) +#define DMA_ChannelEnable_5 ((uint64_t)0x0000000000000020) +#define DMA_ChannelEnable_6 ((uint64_t)0x0000000000000040) +#define DMA_ChannelEnable_7 ((uint64_t)0x0000000000000080) + +#define IS_DMA_CHANNEL_ENABLE(CHANNEL) (((CHANNEL) == DMA_ChannelEnable_0) || \ + ((CHANNEL) == DMA_ChannelEnable_1) || \ + ((CHANNEL) == DMA_ChannelEnable_2) || \ + ((CHANNEL) == DMA_ChannelEnable_3) || \ + ((CHANNEL) == DMA_ChannelEnable_4) || \ + ((CHANNEL) == DMA_ChannelEnable_5) || \ + ((CHANNEL) == DMA_ChannelEnable_6) || \ + ((CHANNEL) == DMA_ChannelEnable_7)) + +/** + * @} + */ + +/** @defgroup DMA_src_handshake_interface_channel_select + * @{ + */ +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_0 0U +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_1 1U +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_2 2U +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_3 3U +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_4 4U +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_5 5U +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_6 6U +#define DMA_SRC_HANDSHAKE_INTERFACE_SEL_7 7U + +#define IS_DMA_SRC_HANDSHAKE_INTERFACE_SEL(CH) (((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_0) || \ + ((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_1) || \ + ((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_2) || \ + ((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_3) || \ + ((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_4) || \ + ((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_5) || \ + ((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_6) || \ + ((CH) == DMA_SRC_HANDSHAKE_INTERFACE_SEL_7) ) + +/** + * @} + */ + +/** @defgroup DMA_dst_handshake_interface_channel_select + * @{ + */ +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_0 0U +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_1 1U +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_2 2U +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_3 3U +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_4 4U +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_5 5U +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_6 6U +#define DMA_DST_HANDSHAKE_INTERFACE_SEL_7 7U + +#define IS_DMA_DST_HANDSHAKE_INTERFACE_SEL(CH) (((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_0) || \ + ((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_1) || \ + ((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_2) || \ + ((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_3) || \ + ((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_4) || \ + ((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_5) || \ + ((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_6) || \ + ((CH) == DMA_DST_HANDSHAKE_INTERFACE_SEL_7) ) + +/** + * @} + */ + + +/** @defgroup DMA_Instances_definition + * @{ + */ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel0) || \ + ((INSTANCE) == DMA1_Channel1) || \ + ((INSTANCE) == DMA1_Channel2) || \ + ((INSTANCE) == DMA1_Channel3) || \ + ((INSTANCE) == DMA1_Channel4) || \ + ((INSTANCE) == DMA1_Channel5) || \ + ((INSTANCE) == DMA1_Channel6) || \ + ((INSTANCE) == DMA1_Channel7) || \ + ((INSTANCE) == DMA2_Channel0) || \ + ((INSTANCE) == DMA2_Channel1) || \ + ((INSTANCE) == DMA2_Channel2) || \ + ((INSTANCE) == DMA2_Channel3) || \ + ((INSTANCE) == DMA2_Channel4) || \ + ((INSTANCE) == DMA2_Channel5) || \ + ((INSTANCE) == DMA2_Channel6) || \ + ((INSTANCE) == DMA2_Channel7)) +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + +/* Function used to set the DMA configuration to the default reset state ******/ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); + +/* Initialization and Configuration functions *********************************/ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* Init); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); + +/* DMA and channel enable functions *********************************/ +void DMA_Channel_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); + +/* Data Counter function******************************************************/ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); + +/* DMA software request function **********************************/ +void DMA_SoftWare_Request(DMA_Channel_TypeDef* DMAy_Channelx, DMA_SoftwareRequestTypeDef SoftwareRequest); + +/* DMA base address and channel index calculate function **********************************/ +DMA_BaseAddressAndChannelIndex CalBaseAddressAndChannelIndex(DMA_Channel_TypeDef* DMAy_Channelx); + +/* Interrupts and flags management functions **********************************/ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_IT, FunctionalState NewState); +void DMA_ClearFlagStatus(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_IT); +ITStatus DMA_GetITStatus(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_IT); +FlagStatus DMA_GetFlagStatus(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_FLAG); + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_DMA_H */ + + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_ecap.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_ecap.h new file mode 100644 index 00000000000..7e70d1fcbaa --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_ecap.h @@ -0,0 +1,422 @@ +/** + ****************************************************************************** + * @file ft32f4xx_ecap.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the eCAP firmware + * library. + * @version V1.0.0 + * @data 2025-04-17 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_ECAP_H +#define __FT32F4XX_ECAP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup ECAP + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief ECAP Init structures definition + */ +typedef struct +{ + uint32_t ECAPMode; /*!< Specifies the mode of operation for ecap. + This parameter can be a value of @ref ECAP_mode */ + uint32_t EventPrescaler; /*!< Specifies the event filter prescale of capture mode. + This parameter can be a value of @ref ECAP_event_prescaler */ + FunctionalState CaptureLoad; /*!< Specifies the enable loading of CAP1-4 registers on a capture event. + This parameter can be set to ENABLE or DISABLE. */ + FunctionalState CaptureEvent4Reset; /*!< Specifies whether the counter should be reset at capture event 4. + This parameter can be set to ENABLE or DISABLE */ + FunctionalState CaptureEvent3Reset; /*!< Specifies whether the counter should be reset at capture event 3. + This parameter can be set to ENABLE or DISABLE */ + FunctionalState CaptureEvent2Reset; /*!< Specifies whether the counter should be reset at capture event 2. + This parameter can be set to ENABLE or DISABLE */ + FunctionalState CaptureEvent1Reset; /*!< Specifies whether the counter should be reset at capture event 1. + This parameter can be set to ENABLE or DISABLE */ + uint32_t CaptureEvent4Polarity; /*!< Specifies the polarity of capture event 4. + This parameter can be a value of @ref ECAP_event_polarity */ + uint32_t CaptureEvent3Polarity; /*!< Specifies the polarity of capture event 3. + This parameter can be a value of @ref ECAP_event_polarity */ + uint32_t CaptureEvent2Polarity; /*!< Specifies the polarity of capture event 2. + This parameter can be a value of @ref ECAP_event_polarity */ + uint32_t CaptureEvent1Polarity; /*!< Specifies the polarity of capture event 1. + This parameter can be a value of @ref ECAP_event_polarity */ + FunctionalState CounterSyncIn; /*!< Specifies the Counter Sync-In select mode. + This parameter can be set to ENABLE or DISABLE */ + uint32_t ModCounterStopWrap; /*!< Specifies the stop value for one-shot mode, and wrap value for continuous mode. + This parameter can be a value of @ref ECAP_mod_counter_stop_wrap */ + uint32_t ModCounterMode; /*!< Specifies the one-shot or continuous mode for Mod4 counter. + This parameter can be a value of @ref ECAP_mod_counter_mode */ + uint32_t APWMPolarity; /*!< Specifies the polarity of APWM output. + This parameter can be a value of @ref ECAP_apwm_output_polarity + Note: This parameter is only valid if the ECAPMode is selected as APWM mode.*/ + uint32_t CounterValue; /*!< Specifies the counter value for ecap. + This parameter can be a value of @ref ECAP_counter_value + Note: This parameter is only valid if the ECAPMode is selected as APWM mode.*/ + uint32_t CounterPhaseValue; /*!< Specifies the counter phase offset value for ecap. + This parameter can be a value of @ref ECAP_counter_phase_value + Note: This parameter is only valid if the ECAPMode is selected as APWM mode.*/ + uint32_t Capture1RegisterValue; /*!< Specifies the capture 1 register value for ecap. + This parameter can be a value of @ref ECAP_capture1_register_value + Note: This parameter is only valid if the ECAPMode is selected as APWM mode.*/ + uint32_t Capture2RegisterValue; /*!< Specifies the capture 2 register value for ecap. + This parameter can be a value of @ref ECAP_capture2_register_value + Note: This parameter is only valid if the ECAPMode is selected as APWM mode.*/ + +} ECAP_InitTypeDef; + + + + +/** + * @brief ECAP_data_registers_definition + */ +#define ECAP_DATA_REG_TSCTR ((uint8_t)0x00U) +#define ECAP_DATA_REG_CTRPHS ((uint8_t)0x01U) +#define ECAP_DATA_REG_CAP1 ((uint8_t)0x02U) +#define ECAP_DATA_REG_CAP2 ((uint8_t)0x03U) +#define ECAP_DATA_REG_CAP3 ((uint8_t)0x04U) +#define ECAP_DATA_REG_CAP4 ((uint8_t)0x05U) + +#define IS_ECAP_DATA_REG(TYPE) (((TYPE) == ECAP_DATA_REG_TSCTR ) || \ + ((TYPE) == ECAP_DATA_REG_CTRPHS) || \ + ((TYPE) == ECAP_DATA_REG_CAP1 ) || \ + ((TYPE) == ECAP_DATA_REG_CAP2 ) || \ + ((TYPE) == ECAP_DATA_REG_CAP3 ) || \ + ((TYPE) == ECAP_DATA_REG_CAP4 )) + + + + +/** @defgroup ECAP_interrupts_definition ECAP_IT + * @{ + */ +#define ECAP_IT_CEVT1 ECAP_ECEINT_CEVT1 +#define ECAP_IT_CEVT2 ECAP_ECEINT_CEVT2 +#define ECAP_IT_CEVT3 ECAP_ECEINT_CEVT3 +#define ECAP_IT_CEVT4 ECAP_ECEINT_CEVT4 +#define ECAP_IT_CTROVF ECAP_ECEINT_CTROVF +#define ECAP_IT_CTRPRD ECAP_ECEINT_CTR_EQ_PRD +#define ECAP_IT_CTRCMP ECAP_ECEINT_CTR_EQ_CMP + +#define IS_ECAP_IT(IT) (((IT) == ECAP_IT_CEVT1 ) || \ + ((IT) == ECAP_IT_CEVT2 ) || \ + ((IT) == ECAP_IT_CEVT3 ) || \ + ((IT) == ECAP_IT_CEVT4 ) || \ + ((IT) == ECAP_IT_CTROVF ) || \ + ((IT) == ECAP_IT_CTRPRD ) || \ + ((IT) == ECAP_IT_CTRCMP ) ) + +/** + * @} + */ + + + +/** @defgroup ECAP_flags_definition + * @{ + */ +#define ECAP_FLAG_INT ECAP_ECFLG_INT +#define ECAP_FLAG_CEVT1 ECAP_ECFLG_CEVT1 +#define ECAP_FLAG_CEVT2 ECAP_ECFLG_CEVT2 +#define ECAP_FLAG_CEVT3 ECAP_ECFLG_CEVT3 +#define ECAP_FLAG_CEVT4 ECAP_ECFLG_CEVT4 +#define ECAP_FLAG_CTROVF ECAP_ECFLG_CTROVF +#define ECAP_FLAG_CTRPRD ECAP_ECFLG_CTR_PRD +#define ECAP_FLAG_CTRCMP ECAP_ECFLG_CTR_CMP + +#define IS_ECAP_FLAG(FLAG) (((FLAG) == ECAP_FLAG_INT ) || \ + ((FLAG) == ECAP_FLAG_CEVT1 ) || \ + ((FLAG) == ECAP_FLAG_CEVT2 ) || \ + ((FLAG) == ECAP_FLAG_CEVT3 ) || \ + ((FLAG) == ECAP_FLAG_CEVT4 ) || \ + ((FLAG) == ECAP_FLAG_CTROVF) || \ + ((FLAG) == ECAP_FLAG_CTRPRD) || \ + ((FLAG) == ECAP_FLAG_CTRCMP) ) + +//#define ECAP_FLAG_MASK ((uint32_t)(ECAP_FLAG_INT | \ +// ECAP_FLAG_CEVT1 | \ +// ECAP_FLAG_CEVT2 | \ +// ECAP_FLAG_CEVT3 | \ +// ECAP_FLAG_CEVT4 | \ +// ECAP_FLAG_CTROVF | \ +// ECAP_FLAG_CTRPRD | \ +// ECAP_FLAG_CTRCMP )) +/** + * @} + */ + + +/** @defgroup ECAP_mode + * @{ + */ +#define ECAP_MODE_CAPTURE 0U +#define ECAP_MODE_APWM ECAP_ECCTL2_CAP_APWM + +#define IS_ECAP_MODE(MODE) (((MODE) == ECAP_MODE_CAPTURE) || ((MODE) == ECAP_MODE_APWM)) + +/** + * @} + */ + +/** @defgroup ECAP_event_prescaler + * @{ + */ +#define ECAP_EVENT_PRESCALER_1 0x00U +#define ECAP_EVENT_PRESCALER_2 0x01U +#define ECAP_EVENT_PRESCALER_4 0x02U +#define ECAP_EVENT_PRESCALER_6 0x03U +#define ECAP_EVENT_PRESCALER_8 0x04U +#define ECAP_EVENT_PRESCALER_10 0x05U +#define ECAP_EVENT_PRESCALER_12 0x06U +#define ECAP_EVENT_PRESCALER_14 0x07U +#define ECAP_EVENT_PRESCALER_16 0x08U +#define ECAP_EVENT_PRESCALER_18 0x09U +#define ECAP_EVENT_PRESCALER_20 0x0AU +#define ECAP_EVENT_PRESCALER_22 0x0BU +#define ECAP_EVENT_PRESCALER_24 0x0CU +#define ECAP_EVENT_PRESCALER_26 0x0DU +#define ECAP_EVENT_PRESCALER_28 0x0EU +#define ECAP_EVENT_PRESCALER_30 0x0FU +#define ECAP_EVENT_PRESCALER_32 0x10U +#define ECAP_EVENT_PRESCALER_34 0x11U +#define ECAP_EVENT_PRESCALER_36 0x12U +#define ECAP_EVENT_PRESCALER_38 0x13U +#define ECAP_EVENT_PRESCALER_40 0x14U +#define ECAP_EVENT_PRESCALER_42 0x15U +#define ECAP_EVENT_PRESCALER_44 0x16U +#define ECAP_EVENT_PRESCALER_46 0x17U +#define ECAP_EVENT_PRESCALER_48 0x18U +#define ECAP_EVENT_PRESCALER_50 0x19U +#define ECAP_EVENT_PRESCALER_52 0x1AU +#define ECAP_EVENT_PRESCALER_54 0x1BU +#define ECAP_EVENT_PRESCALER_56 0x1CU +#define ECAP_EVENT_PRESCALER_58 0x1DU +#define ECAP_EVENT_PRESCALER_60 0x1EU +#define ECAP_EVENT_PRESCALER_62 0x1FU + +#define IS_ECAP_EVENT_PRESCALER(PRESCALER) (((PRESCALER) == ECAP_EVENT_PRESCALER_1 ) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_2 ) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_4 ) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_6 ) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_8 ) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_10) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_12) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_14) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_16) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_18) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_20) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_22) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_24) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_26) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_28) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_30) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_32) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_34) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_36) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_38) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_40) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_42) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_44) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_46) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_48) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_50) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_52) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_54) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_56) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_58) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_60) || \ + ((PRESCALER) == ECAP_EVENT_PRESCALER_62) ) +/** + * @} + */ + + +///** @defgroup ECAP_capture_load +// * @{ +// */ +//#define ECAP_CAPTURE_LOAD_DISABLE 0U +//#define ECAP_CAPTURE_LOAD_ENABLE 1U +// +//#define IS_ECAP_CAPTURE_LOAD(TYPE) (((TYPE) == ECAP_CAPTURE_LOAD_DISABLE) || ((TYPE) == ECAP_CAPTURE_LOAD_ENABLE)) +// +///** +// * @} +// */ + + +///** @defgroup ECAP_counter_reset_event +// * @{ +// */ +//#define ECAP_COUNTER_RESET_DISABLE 0U +//#define ECAP_COUNTER_RESET_ENABLE 1U +// +//#define IS_ECAP_COUNTER_RESET(STATE) (((STATE) == ECAP_COUNTER_RESET_DISABLE) || \ +// ((STATE) == ECAP_COUNTER_RESET_ENABLE )) + +/** + * @} + */ + + +/** @defgroup ECAP_event_polarity + * @{ + */ +#define ECAP_EVENT_POLARITY_RE 0U //Capture event 4 triggered on a rising edge(RE) +#define ECAP_EVENT_POLARITY_FE 1U //Capture event 4 triggered on a falling edge(FE) + +#define IS_ECAP_EVENT_POLARITY(TYPE) (((TYPE) == ECAP_EVENT_POLARITY_RE) || ((TYPE) == ECAP_EVENT_POLARITY_FE)) + +/** + * @} + */ + + +/** @defgroup ECAP_apwm_output_polarity + * @{ + */ +#define ECAP_APWM_POLARITY_HIGH 0U +#define ECAP_APWM_POLARITY_LOW ECAP_ECCTL2_APWMPOL + +#define IS_ECAP_APWM_POLARITY(TYPE) (((TYPE) == ECAP_APWM_POLARITY_HIGH) || \ + ((TYPE) == ECAP_APWM_POLARITY_LOW )) + +/** + * @} + */ + + +///** @defgroup ECAP_counter_syncin_select +// * @{ +// */ +//#define ECAP_COUNTER_SYNCIN_DISABLE 0U +//#define ECAP_COUNTER_SYNCIN_ENABLE 1U +// +//#define IS_ECAP_COUNTER_SYNCIN(STATE) (((STATE) == ECAP_COUNTER_SYNCIN_DISABLE) || \ +// ((STATE) == ECAP_COUNTER_SYNCIN_ENABLE )) + +/** + * @} + */ + + +/** @defgroup ECAP_mod_counter_stop_wrap + * @{ + */ +#define ECAP_STOP_WRAP_EVENT1 0U +#define ECAP_STOP_WRAP_EVENT2 ECAP_ECCTL2_STOP_WRAP_0 +#define ECAP_STOP_WRAP_EVENT3 ECAP_ECCTL2_STOP_WRAP_1 +#define ECAP_STOP_WRAP_EVENT4 ECAP_ECCTL2_STOP_WRAP + +#define IS_ECAP_MOD_COUNTER_STOP_WRAP(SEL) (((SEL) == ECAP_STOP_WRAP_EVENT1) || \ + ((SEL) == ECAP_STOP_WRAP_EVENT2) || \ + ((SEL) == ECAP_STOP_WRAP_EVENT3) || \ + ((SEL) == ECAP_STOP_WRAP_EVENT4) ) + +/** + * @} + */ + +/** @defgroup ECAP_mod_counter_mode + * @{ + */ +#define ECAP_MOD_COUNTER_CONT 0U +#define ECAP_MOD_COUNTER_ONESHOT ECAP_ECCTL2_CONT_ONESHT + +#define IS_ECAP_MOD_COUNTER_MODE(MODE) (((MODE) == ECAP_MOD_COUNTER_CONT) || ((MODE) == ECAP_MOD_COUNTER_ONESHOT)) + + +/** + * @} + */ + +/** @defgroup ECAP_counter_value + * @{ + */ +#define IS_ECAP_COUNTER_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + +/** @defgroup ECAP_counter_phase_value + * @{ + */ +#define IS_ECAP_COUNTER_PHASE_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + +/** @defgroup ECAP_capture1_register_value + * @{ + */ +#define IS_ECAP_CAPTURE1_REGISTER_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + +/** @defgroup ECAP_capture2_register_value + * @{ + */ +#define IS_ECAP_CAPTURE2_REGISTER_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the ECAP configuration to the default reset state ******/ +void ECAP_DeInit(); + +/* Initialization and Configuration functions *********************************/ +void ECAP_Init(ECAP_InitTypeDef* ECAP_InitStruct); +void ECAP_StructInit(ECAP_InitTypeDef* ECAP_InitStruct); + +/* ECAP control functions *********************************/ +void ECAP_Cmd(FunctionalState NewState); +void ECAP_ReArm(); +void ECAP_SoftwareForceSync(); + +/* Data register access function***********************************************/ +uint32_t ECAP_GetDataRegister(uint8_t ECAP_DATA_REG); +void ECAP_WriteDataRegister(uint8_t ECAP_DATA_REG, uint32_t Value); + +/* Interrupts and flags management functions **********************************/ +void ECAP_ITConfig(uint8_t ECAP_IT, FunctionalState NewState); +void ECAP_ClearFlag(uint8_t ECAP_FLAG); +void ECAP_ITForce(uint8_t ECAP_IT); +ITStatus ECAP_GetITStatus(uint8_t ECAP_IT); +FlagStatus ECAP_GetFlagStatus(uint8_t ECAP_FLAG); + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_ECAP_H */ + + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_epwm.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_epwm.h new file mode 100644 index 00000000000..c85bf471e94 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_epwm.h @@ -0,0 +1,779 @@ +/** + ****************************************************************************** + * @file ft32f4xx_epwm.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the EPWM + * firmware library. + * @version V1.0.0 + * @data 2025-03-25 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_EPWM_H +#define __FT32F4XX_EPWM_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup EPWM + * @{ + */ + + + + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief Enumeration to define the pulse width modulation (PWM) action + */ +typedef enum +{ + EPWM_ActionQual_Disabled = 0, + EPWM_ActionQual_Clear, + EPWM_ActionQual_Set, + EPWM_ActionQual_Toggle +} EPWM_ActionQual_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) high speed + */ +typedef enum +{ + EPWM_HspClkDiv_by_1 = (0 << 7), + EPWM_HspClkDiv_by_2 = (1 << 7), + EPWM_HspClkDiv_by_4 = (2 << 7), + EPWM_HspClkDiv_by_6 = (3 << 7), + EPWM_HspClkDiv_by_8 = (4 << 7), + EPWM_HspClkDiv_by_10 = (5 << 7), + EPWM_HspClkDiv_by_12 = (6 << 7), + EPWM_HspClkDiv_by_14 = (7 << 7) +} EPWM_HspClkDiv_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) clock + */ +typedef enum +{ + EPWM_ClkDiv_by_1 = (0 << 10), + EPWM_ClkDiv_by_2 = (1 << 10), + EPWM_ClkDiv_by_4 = (2 << 10), + EPWM_ClkDiv_by_8 = (3 << 10), + EPWM_ClkDiv_by_16 = (4 << 10), + EPWM_ClkDiv_by_32 = (5 << 10), + EPWM_ClkDiv_by_64 = (6 << 10), + EPWM_ClkDiv_by_128 = (7 << 10) +} EPWM_ClkDiv_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) chopping + */ +typedef enum +{ + EPWM_ChoppingClkFreq_SysClkOut_by_1 = (0 << 5), + EPWM_ChoppingClkFreq_SysClkOut_by_2 = (1 << 5), + EPWM_ChoppingClkFreq_SysClkOut_by_3 = (2 << 5), + EPWM_ChoppingClkFreq_SysClkOut_by_4 = (3 << 5), + EPWM_ChoppingClkFreq_SysClkOut_by_5 = (4 << 5), + EPWM_ChoppingClkFreq_SysClkOut_by_6 = (5 << 5), + EPWM_ChoppingClkFreq_SysClkOut_by_7 = (6 << 5), + EPWM_ChoppingClkFreq_SysClkOut_by_8 = (7 << 5) +} EPWM_ChoppingClkFreq_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) chopping + */ +typedef enum +{ + EPWM_ChoppingDutyCycle_One_Eighth = (0 << 8), + EPWM_ChoppingDutyCycle_Two_Eighths = (1 << 8), + EPWM_ChoppingDutyCycle_Three_Eighths = (2 << 8), + EPWM_ChoppingDutyCycle_Four_Eighths = (3 << 8), + EPWM_ChoppingDutyCycle_Five_Eighths = (4 << 8), + EPWM_ChoppingDutyCycle_Six_Eighths = (5 << 8), + EPWM_ChoppingDutyCycle_Seven_Eighths = (6 << 8) +} EPWM_ChoppingDutyCycle_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) chopping + */ +typedef enum +{ + EPWM_ChoppingPulseWidth_One_Eighth_SysClkOut = (0 << 1), + EPWM_ChoppingPulseWidth_Two_Eighths_SysClkOut = (1 << 1), + EPWM_ChoppingPulseWidth_Three_Eighths_SysClkOut = (2 << 1), + EPWM_ChoppingPulseWidth_Four_Eighths_SysClkOut = (3 << 1), + EPWM_ChoppingPulseWidth_Five_Eighths_SysClkOut = (4 << 1), + EPWM_ChoppingPulseWidth_Six_Eighths_SysClkOut = (5 << 1), + EPWM_ChoppingPulseWidth_Seven_Eighths_SysClkOut = (6 << 1), + EPWM_ChoppingPulseWidth_Eight_Eighths_SysClkOut = (7 << 1), + EPWM_ChoppingPulseWidth_Nine_Eighths_SysClkOut = (8 << 1), + EPWM_ChoppingPulseWidth_Ten_Eighths_SysClkOut = (9 << 1), + EPWM_ChoppingPulseWidth_Eleven_Eighths_SysClkOut = (10 << 1), + EPWM_ChoppingPulseWidth_Twelve_Eighths_SysClkOut = (11 << 1), + EPWM_ChoppingPulseWidth_Thirteen_Eighths_SysClkOut = (12 << 1), + EPWM_ChoppingPulseWidth_Fourteen_Eighths_SysClkOut = (13 << 1), + EPWM_ChoppingPulseWidth_Fifteen_Eighths_SysClkOut = (14 << 1), + EPWM_ChoppingPulseWidth_Sixteen_Eighths_SysClkOut = (15 << 1) +} EPWM_ChoppingPulseWidth_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) counter modes + */ +typedef enum +{ + EPWM_CounterMode_Up = (0 << 0), + EPWM_CounterMode_Down = (1 << 0), + EPWM_CounterMode_UpDown = (2 << 0), + EPWM_CounterMode_Stop = (3 << 0) +} EPWM_CounterMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) deadband + */ +typedef enum +{ + EPWM_DeadBandInputMode_EPWMxA_Rising_and_Falling = (0 << 4), + EPWM_DeadBandInputMode_EPWMxA_Falling_EPWMxB_Rising = (1 << 4), + EPWM_DeadBandInputMode_EPWMxA_Rising_EPWMxB_Falling = (2 << 4), + EPWM_DeadBandInputMode_EPWMxB_Rising_and_Falling = (3 << 4) +} EPWM_DeadBandInputMode_e; + + +/** + * @brief Enumeration to define the pulse width modulation (PWM) deadband + */ +typedef enum +{ + EPWM_DeadBandOutputMode_Bypass = (0 << 0), + EPWM_DeadBandOutputMode_EPWMxA_Disable_EPWMxB_Falling = (1 << 0), + EPWM_DeadBandOutputMode_EPWMxA_Rising_EPWMxB_Disable = (2 << 0), + EPWM_DeadBandOutputMode_EPWMxA_Rising_EPWMxB_Falling = (3 << 0) +} EPWM_DeadBandOutputMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) deadband + */ +typedef enum +{ + EPWM_DeadBandPolarity_EPWMxA_EPWMxB = (0 << 2), + EPWM_DeadBandPolarity_EPWMxA_Inverted = (1 << 2), + EPWM_DeadBandPolarity_EPWMxB_Inverted = (2 << 2), + EPWM_DeadBandPolarity_EPWMxA_Inverted_EPWMxB_Inverted = (3 << 2) +} EPWM_DeadBandPolarity_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) digital + */ +typedef enum +{ + EPWM_DigitalCompare_A_High = 0, + EPWM_DigitalCompare_A_Low = 4, + EPWM_DigitalCompare_B_High = 8, + EPWM_DigitalCompare_B_Low = 12 +} EPWM_DigitalCompare_Input_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) digital + */ +typedef enum +{ + EPWM_DigitalCompare_InputSel_TZ1 = (0 << 0), + EPWM_DigitalCompare_InputSel_TZ2 = (1 << 0), + EPWM_DigitalCompare_InputSel_TZ3 = (2 << 0), + EPWM_DigitalCompare_InputSel_COMP1OUT = (8 << 0), + EPWM_DigitalCompare_InputSel_COMP2OUT = (9 << 0), + EPWM_DigitalCompare_InputSel_COMP3OUT = (10 << 0) +} EPWM_DigitalCompare_InputSel_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) digital + */ +typedef enum +{ + EPWM_DigitalCompare_FilterSrc_DCAEVT1 = 0, + EPWM_DigitalCompare_FilterSrc_DCAEVT2, + EPWM_DigitalCompare_FilterSrc_DCBEVT1, + EPWM_DigitalCompare_FilterSrc_DCBEVT2 +} EPWM_DigitalCompare_FilterSrc_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) digital + */ +typedef enum +{ + EPWM_DigitalCompare_PulseSel_CTRPRD = 0, + EPWM_DigitalCompare_PulseSel_CTR0 +} EPWM_DigitalCompare_PulseSel_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) high + */ +typedef enum +{ + EPWM_HrControlMode_Duty = (0 << 2), + EPWM_HrControlMode_Phase = (1 << 2) +} EPWM_HrControlMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) high + */ +typedef enum +{ + EPWM_HrEdgeMode_Disabled = (0 << 0), + EPWM_HrEdgeMode_Rising = (1 << 0), + EPWM_HrEdgeMode_Falling = (2 << 0), + EPWM_HrEdgeMode_Both = (3 << 0) +} EPWM_HrEdgeMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) high + */ +typedef enum +{ + EPWM_HrShadowMode_CTR_EQ_0 = (0 << 3), + EPWM_HrShadowMode_CTR_EQ_PRD = (1 << 3), + EPWM_HrShadowMode_CTR_EQ_0_OR_PRD = (2 << 3) +} EPWM_HrShadowMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) interrupt + */ +typedef enum +{ + EPWM_IntMode_CounterEqualZero = (1 << 0), + EPWM_IntMode_CounterEqualPeriod = (2 << 0), + EPWM_IntMode_CounterEqualZeroOrPeriod = (3 << 0), + EPWM_IntMode_CounterEqualCmpAIncr = (4 << 0), + EPWM_IntMode_CounterEqualCmpADecr = (5 << 0), + EPWM_IntMode_CounterEqualCmpBIncr = (6 << 0), + EPWM_IntMode_CounterEqualCmpBDecr = (7 << 0) +} EPWM_IntMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) interrupt + */ +typedef enum +{ + EPWM_IntPeriod_Disable = (0 << 0), + EPWM_IntPeriod_FirstEvent = (1 << 0), + EPWM_IntPeriod_SecondEvent = (2 << 0), + EPWM_IntPeriod_ThirdEvent = (3 << 0) +} EPWM_IntPeriod_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) load modes + */ +typedef enum +{ + EPWM_LoadMode_Zero = 0, + EPWM_LoadMode_Period, + EPWM_LoadMode_Either, + EPWM_LoadMode_Freeze +} EPWM_LoadMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) numbers + */ +typedef enum +{ + EPWM_Number_1 = 0, + EPWM_Number_2, + EPWM_Number_3, + EPWM_Number_4, + EPWM_Number_5, + EPWM_Number_6, + EPWM_Number_7 +} EPWM_Number_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) period load + */ +typedef enum +{ + EPWM_PeriodLoad_Shadow = (0 << 3), + EPWM_PeriodLoad_Immediate = (1 << 3) +} EPWM_PeriodLoad_e; + + +/** + * @brief Enumeration to define the pulse width modulation (PWM) phase + */ +typedef enum +{ + EPWM_PhaseDir_CountDown = (0 << 13), + EPWM_PhaseDir_CountUp = (1 << 13) +} EPWM_PhaseDir_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) run modes + */ +//typedef enum +//{ +// EPWM_RunMode_SoftStopAfterIncr=(0 << 14), +// EPWM_RunMode_SoftStopAfterDecr=(0 << 14), +// EPWM_RunMode_SoftStopAfterCycle=(1 << 14), +// EPWM_RunMode_FreeRun=(2 << 14) +//} EPWM_RunMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) shadow modes + */ +typedef enum +{ + EPWM_ShadowMode_Shadow = 0, + EPWM_ShadowMode_Immediate +} EPWM_ShadowMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) shadow status + */ +typedef enum +{ + EPWM_ShadowStatus_NotFull = 0, + EPWM_ShadowStatus_Full +} EPWM_ShadowStatus_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) start of + */ +typedef enum +{ + EPWM_SocPeriod_Disable = 0, + EPWM_SocPeriod_FirstEvent, + EPWM_SocPeriod_SecondEvent, + EPWM_SocPeriod_ThirdEvent +} EPWM_SocPeriod_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) start of + */ +typedef enum +{ + EPWM_SocPulseSrc_DcEvt = 0, + EPWM_SocPulseSrc_CounterEqualZero, + EPWM_SocPulseSrc_CounterEqualPeriod, + EPWM_SocPulseSrc_CounterEqualZeroOrPeriod, + EPWM_SocPulseSrc_CounterEqualCmpAIncr, + EPWM_SocPulseSrc_CounterEqualCmpADecr, + EPWM_SocPulseSrc_CounterEqualCmpBIncr, + EPWM_SocPulseSrc_CounterEqualCmpBDecr +} EPWM_SocPulseSrc_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) sync modes + */ +typedef enum +{ + EPWM_SyncMode_EPWMxSYNC = (0 << 4), + EPWM_SyncMode_CounterEqualZero = (1 << 4), + EPWM_SyncMode_CounterEqualCounterCompareZero = (2 << 4), + EPWM_SyncMode_Disable = (3 << 4) +} EPWM_SyncMode_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) trip zone + */ +typedef enum +{ + EPWM_TripZoneSrc_CycleByCycle_TZ1_NOT = (1 << 0), + EPWM_TripZoneSrc_CycleByCycle_TZ2_NOT = (1 << 1), + EPWM_TripZoneSrc_CycleByCycle_TZ3_NOT = (1 << 2), + EPWM_TripZoneSrc_CycleByCycle_TZ4_NOT = (1 << 3), + EPWM_TripZoneSrc_CycleByCycle_TZ5_NOT = (1 << 4), + EPWM_TripZoneSrc_CycleByCycle_TZ6_NOT = (1 << 5), + EPWM_TripZoneSrc_CycleByCycle_CmpA = (1 << 6), + EPWM_TripZoneSrc_CycleByCycle_CmpB = (1 << 7), + EPWM_TripZoneSrc_OneShot_TZ1_NOT = (1 << 8), + EPWM_TripZoneSrc_OneShot_TZ2_NOT = (1 << 9), + EPWM_TripZoneSrc_OneShot_TZ3_NOT = (1 << 10), + EPWM_TripZoneSrc_OneShot_TZ4_NOT = (1 << 11), + EPWM_TripZoneSrc_OneShot_TZ5_NOT = (1 << 12), + EPWM_TripZoneSrc_OneShot_TZ6_NOT = (1 << 13), + EPWM_TripZoneSrc_OneShot_CmpA = (1 << 14), + EPWM_TripZoneSrc_OneShot_CmpB = (1 << 15) +} EPWM_TripZoneSrc_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) trip zone + */ +typedef enum +{ + EPWM_TripZoneState_HighImp = 0, + EPWM_TripZoneState_EPWM_High, + EPWM_TripZoneState_EPWM_Low, + EPWM_TripZoneState_DoNothing +} EPWM_TripZoneState_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) trip zone + */ +typedef enum +{ + EPWM_TripZoneFlag_Global = (1 << 0), //!< Global Trip Zone flag + EPWM_TripZoneFlag_CBC = (1 << 1), //!< Cycle by cycle Trip Zone flag + EPWM_TripZoneFlag_OST = (1 << 2), //!< One Shot Trip Zone flag + EPWM_TripZoneFlag_DCAEVT1 = (1 << 3), //!< Digital Compare A Event 1 Trip Zone flag + EPWM_TripZoneFlag_DCAEVT2 = (1 << 4), //!< Digital Compare A Event 2 Trip Zone flag + EPWM_TripZoneFlag_DCBEVT1 = (1 << 5), //!< Digital Compare B Event 1 Trip Zone flag + EPWM_TripZoneFlag_DCBEVT2 = (1 << 6) //!< Digital Compare B Event 2 Trip Zone flag +} EPWM_TripZoneFlag_e; + +/** + * @brief Enumeration to define the pulse width modulation (PWM) trip zone + */ +typedef enum +{ + EPWM_TripZoneDCEventSel_Disabled = (0 << 0), //!< Event Disabled + EPWM_TripZoneDCEventSel_DCxHL_DCxLX = (1 << 0), //!< Compare H = Low, Compare L = Don't Care + EPWM_TripZoneDCEventSel_DCxHH_DCxLX = (2 << 0), //!< Compare H = High, Compare L = Don't Care + EPWM_TripZoneDCEventSel_DCxHX_DCxLL = (3 << 0), //!< Compare H = Don't Care, Compare L = Low + EPWM_TripZoneDCEventSel_DCxHX_DCxLH = (4 << 0), //!< Compare H = Don't Care, Compare L = High + EPWM_TripZoneDCEventSel_DCxHL_DCxLH = (5 << 0) //!< Compare H = Low, Compare L = High +} EPWM_TripZoneDCEventSel_e; + + + + + + + +/* Exported constants --------------------------------------------------------*/ + +#define EPWM_AQCTL_ZRO_BITS (3 << 0) +#define EPWM_AQCTL_PRD_BITS (3 << 2) +#define EPWM_AQCTL_CAU_BITS (3 << 4) +#define EPWM_AQCTL_CAD_BITS (3 << 6) +#define EPWM_AQCTL_CBU_BITS (3 << 8) +#define EPWM_AQCTL_CBD_BITS (3 << 10) +#define EPWM_CMPCTL_LOADAMODE_BITS (3 << 0) +#define EPWM_CMPCTL_LOADBMODE_BITS (3 << 2) +#define EPWM_CMPCTL_SHDWAMODE_BITS (1 << 4) +#define EPWM_CMPCTL_SHDWBMODE_BITS (1 << 6) +#define EPWM_CMPCTL_SHDWAFULL_BITS (1 << 5) +#define EPWM_CMPCTL_SHDWBFULL_BITS (1 << 7) +#define EPWM_DBCTL_OUTMODE_BITS (3 << 0) +#define EPWM_DBCTL_POLSEL_BITS (3 << 2) +#define EPWM_DBCTL_INMODE_BITS (3 << 4) +#define EPWM_DBCTL_HALFCYCLE_BITS (1 << 15) +#define EPWM_ETCLR_INT_BITS (1 << 0) +#define EPWM_ETCLR_SOCA_BITS (1 << 2) +#define EPWM_ETCLR_SOCB_BITS (1 << 3) +#define EPWM_ETPS_INTPRD_BITS (3 << 0) +#define EPWM_ETPS_INTCNT_BITS (3 << 2) +#define EPWM_ETPS_SOCAPRD_BITS (3 << 8) +#define EPWM_ETPS_SOCACNT_BITS (3 << 10) +#define EPWM_ETPS_SOCBPRD_BITS (3 << 12) +#define EPWM_ETPS_SOCBCNT_BITS (3 << 14) +#define EPWM_ETSEL_INTSEL_BITS (7 << 0) +#define EPWM_ETSEL_INTEN_BITS (1 << 3) +#define EPWM_ETSEL_SOCASEL_BITS (7 << 8) +#define EPWM_ETSEL_SOCAEN_BITS (1 << 11) +#define EPWM_ETSEL_SOCBSEL_BITS (7 << 12) +#define EPWM_ETSEL_SOCBEN_BITS (1 << 15) +#define EPWM_PCCTL_CHPEN_BITS (1 << 0) +#define EPWM_PCCTL_OSHTWTH_BITS (15 << 1) +#define EPWM_PCCTL_CHPFREQ_BITS (7 << 5) +#define EPWM_PCCTL_CHPDUTY_BITS (7 << 8) +#define EPWM_HRCNFG_EDGMODE_BITS (3 << 0) +#define EPWM_HRCNFG_CTLMODE_BITS (1 << 2) +#define EPWM_HRCNFG_HRLOAD_BITS (3 << 3) +#define EPWM_HRCNFG_SELOUTB_BITS (1 << 5) +#define EPWM_HRCNFG_AUTOCONV_BITS (1 << 6) +#define EPWM_HRCNFG_SWAPAB_BITS (1 << 7) +#define EPWM_HRPPWR_MEPOFF_BITS (1 << 0) +#define EPWM_HRPPWR_MEPSFO_BITS (1 << 1) +#define EPWM_HRPCTL_HRPE_BITS (1 << 0) +#define EPWM_HRPCTL_EPWMSYNCSEL_BITS (1 << 1) +#define EPWM_HRPCTL_TBPHSHRLOADE_BITS (1 << 2) +#define EPWM_TBCTL_CTRMODE_BITS (3 << 0) +#define EPWM_TBCTL_PHSEN_BITS (1 << 2) +#define EPWM_TBCTL_PRDLD_BITS (1 << 3) +#define EPWM_TBCTL_SYNCOSEL_BITS (3 << 4) +#define EPWM_TBCTL_SWFSYNC_BITS (1 << 6) +#define EPWM_TBCTL_HSPCLKDIV_BITS (7 << 7) +#define EPWM_TBCTL_CLKDIV_BITS (7 << 10) +#define EPWM_TBCTL_PHSDIR_BITS (1 << 13) +#define EPWM_TBCTL_FREESOFT_BITS (3 << 14) +#define EPWM_TZCLR_INT_BITS (1 << 0) +#define EPWM_TZCLR_CBC_BITS (1 << 1) +#define EPWM_TZCLR_OST_BITS (1 << 2) +#define EPWM_TZCLR_DCAEVT1_BITS (1 << 3) +#define EPWM_TZCLR_DCAEVT2_BITS (1 << 4) +#define EPWM_TZCLR_DCBEVT1_BITS (1 << 5) +#define EPWM_TZCLR_DCBEVT2_BITS (1 << 6) +#define EPWM_TZCTL_TZA_BITS (3 << 0) +#define EPWM_TZCTL_TZB_BITS (3 << 2) +#define EPWM_TZCTL_DCAEVT1_BITS (3 << 4) +#define EPWM_TZCTL_DCAEVT2_BITS (3 << 6) +#define EPWM_TZCTL_DCBEVT1_BITS (3 << 8) +#define EPWM_TZCTL_DCBEVT2_BITS (3 << 10) +#define EPWM_TZFRC_CBC_BITS (1 << 1) +#define EPWM_TZFRC_OST_BITS (1 << 2) +#define EPWM_TZFRC_DCAEVT1_BITS (1 << 3) +#define EPWM_TZFRC_DCAEVT2_BITS (1 << 4) +#define EPWM_TZFRC_DCBEVT1_BITS (1 << 5) +#define EPWM_TZFRC_DCBEVT2_BITS (1 << 6) +#define EPWM_TZDCSEL_DCAEVT1_BITS (7 << 0) +#define EPWM_TZDCSEL_DCAEVT2_BITS (7 << 3) +#define EPWM_TZDCSEL_DCBEVT1_BITS (7 << 6) +#define EPWM_TZDCSEL_DCBEVT2_BITS (7 << 9) +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_BITS (15 << 0) +#define EPWM_DCTRIPSEL_DCALCOMPSEL_BITS (15 << 4) +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_BITS (15 << 8) +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_BITS (15 << 12) +#define EPWM_DCFCTL_SRCSEL_BITS (3 << 0) +#define EPWM_DCFCTL_BLANKE_BITS (1 << 2) +#define EPWM_DCFCTL_BLANKINV_BITS (1 << 3) +#define EPWM_DCFCTL_PULSESEL_BITS (3 << 4) + + +#define EPWM_TBCTL_EALLOW_BITS TBCTL_EALLOW +#define EPWM_MEP_INT_BITS MEPINT_MEPCAL + +/** @defgroup EPWM_TZ_flags_definition + * @{ + */ + +#define EPWM_TZ_FLAG_INT TZFLG_INT +#define EPWM_TZ_FLAG_CBC TZFLG_CBC +#define EPWM_TZ_FLAG_OST TZFLG_OST +#define EPWM_TZ_FLAG_DCAEVT1 TZFLG_DCAEVT1 +#define EPWM_TZ_FLAG_DCAEVT2 TZFLG_DCAEVT2 +#define EPWM_TZ_FLAG_DCBEVT1 TZFLG_DCBEVT1 +#define EPWM_TZ_FLAG_DCBEVT2 TZFLG_DCBEVT2 + +#define IS_EPWM_TZ_GET_FLAG(FLAG) (((FLAG) == EPWM_TZ_FLAG_INT) || \ + ((FLAG) == EPWM_TZ_FLAG_CBC) || \ + ((FLAG) == EPWM_TZ_FLAG_OST) || \ + ((FLAG) == EPWM_TZ_FLAG_DCAEVT1) || \ + ((FLAG) == EPWM_TZ_FLAG_DCAEVT2) || \ + ((FLAG) == EPWM_TZ_FLAG_DCBEVT1) || \ + ((FLAG) == EPWM_TZ_FLAG_DCBEVT2)) +/** + * @} + */ + + + +/** @defgroup EPWM_ET_flags_definition + * @{ + */ +#define EPWM_ET_FLAG_INT ETFLG_INT +#define EPWM_ET_FLAG_SOCA ETFLG_SOCA +#define EPWM_ET_FLAG_SOCB ETFLG_SOCB + +#define IS_EPWM_ET_GET_FLAG(FLAG) (((FLAG) == EPWM_ET_FLAG_INT) || \ + ((FLAG) == EPWM_ET_FLAG_SOCA) || \ + ((FLAG) == EPWM_ET_FLAG_SOCB)) +/** + * @} + */ + + +/** @defgroup EPWM_MEP_flags_definition + * @{ + */ + +#define EPWM_MEP_FLAG_INT MEPFLG_MEPCAL + +#define IS_EPWM_MEP_GET_FLAG(FLAG) ((FLAG) == EPWM_MEP_FLAG_INT) +/** + * @} + */ + + + + +/** + * @brief Defines the pulse width modulation (PWM) handle + */ +typedef struct _EPWM_Obj_ *EPWM_Handle; + + +/* Exported functions ------------------------------------------------------- */ + +/* Time-Base Configuration functions *********************************/ +void EALLOW(EPWM_TypeDef* EPWMx); +void EDIS(EPWM_TypeDef* EPWMx); +void EPWM_setPhaseDir(EPWM_TypeDef* EPWMx, const EPWM_PhaseDir_e phaseDir); +void EPWM_setClkDiv(EPWM_TypeDef* EPWMx, const EPWM_ClkDiv_e clkDiv); +void EPWM_setHighSpeedClkDiv(EPWM_TypeDef* EPWMx, const EPWM_HspClkDiv_e clkDiv); +void EPWM_setSwSync(EPWM_TypeDef* EPWMx); +void EPWM_forceSync(EPWM_TypeDef* EPWMx); +void EPWM_setSyncMode(EPWM_TypeDef* EPWMx, const EPWM_SyncMode_e syncMode); +void EPWM_setPeriodLoad(EPWM_TypeDef* EPWMx, const EPWM_PeriodLoad_e periodLoad); +void EPWM_disableCounterLoad(EPWM_TypeDef* EPWMx); +void EPWM_enableCounterLoad(EPWM_TypeDef* EPWMx); +void EPWM_setCounterMode(EPWM_TypeDef* EPWMx, const EPWM_CounterMode_e counterMode); + +void EPWM_setCount(EPWM_TypeDef* EPWMx, const uint16_t count); +void EPWM_setPeriod(EPWM_TypeDef* EPWMx, const uint16_t period); +void EPWM_setPeriodHr(EPWM_TypeDef* EPWMx, const uint16_t period); +void EPWM_setPhase(EPWM_TypeDef* EPWMx, const uint16_t phase); +//void EPWM_setRunMode(EPWM_TypeDef* EPWMx, const EPWM_RunMode_e runMode); + +uint16_t EPWM_getPeriod(EPWM_TypeDef* EPWMx); + + +/* Counter-Compare Configuration functions *********************************/ +void EPWM_setCmpA(EPWM_TypeDef* EPWMx, const uint16_t pwmData); +void EPWM_setCmpB(EPWM_TypeDef* EPWMx, const uint16_t pwmData); +void EPWM_setCmpAHr(EPWM_TypeDef* EPWMx, const uint16_t pwmData); +void EPWM_write_CmpA(EPWM_TypeDef* EPWMx, const int16_t pwmData); +void EPWM_write_CmpB(EPWM_TypeDef* EPWMx, const int16_t pwmData); +void EPWM_setShadowMode_CmpA(EPWM_TypeDef* EPWMx, const EPWM_ShadowMode_e shadowMode); +void EPWM_setShadowMode_CmpB(EPWM_TypeDef* EPWMx, const EPWM_ShadowMode_e shadowMode); +void EPWM_setLoadMode_CmpA(EPWM_TypeDef* EPWMx, const EPWM_LoadMode_e loadMode); +void EPWM_setLoadMode_CmpB(EPWM_TypeDef* EPWMx, const EPWM_LoadMode_e loadMode); + +uint16_t EPWM_getCmpA(EPWM_TypeDef* EPWMx); +uint16_t EPWM_getCmpAHr(EPWM_TypeDef* EPWMx); +uint16_t EPWM_getCmpB(EPWM_TypeDef* EPWMx); + + +//EPWM_Handle EPWM_init(void *pMemory, const size_t numBytes); + + +/* Action-Qualifier Configuration functions *********************************/ +void EPWM_setActionQual_CntDown_CmpA_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_CntDown_CmpA_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_CntDown_CmpB_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_CntDown_CmpB_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_CntUp_CmpA_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_CntUp_CmpA_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_CntUp_CmpB_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_CntUp_CmpB_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_Period_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_Period_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_Zero_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); +void EPWM_setActionQual_Zero_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual); + + +/* PWM-Chopper Configuration functions *********************************/ +void EPWM_enableChopping(EPWM_TypeDef* EPWMx); +void EPWM_disableChopping(EPWM_TypeDef* EPWMx); +void EPWM_setChoppingClkFreq(EPWM_TypeDef* EPWMx, const EPWM_ChoppingClkFreq_e clkFreq); +void EPWM_setChoppingDutyCycle(EPWM_TypeDef* EPWMx, const EPWM_ChoppingDutyCycle_e dutyCycle); +void EPWM_setChoppingPulseWidth(EPWM_TypeDef* EPWMx, const EPWM_ChoppingPulseWidth_e pulseWidth); + + +/* Dead-Band Configuration functions *********************************/ +void EPWM_decrementDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx); +void EPWM_decrementDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx); +void EPWM_setDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx, const uint16_t delay); +void EPWM_setDeadBandInputMode(EPWM_TypeDef* EPWMx, const EPWM_DeadBandInputMode_e inputMode); +void EPWM_setDeadBandOutputMode(EPWM_TypeDef* EPWMx, const EPWM_DeadBandOutputMode_e outputMode); +void EPWM_setDeadBandPolarity(EPWM_TypeDef* EPWMx, const EPWM_DeadBandPolarity_e polarity); +void EPWM_setDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx, const uint16_t delay); +void EPWM_disableDeadBand(EPWM_TypeDef* EPWMx); +void EPWM_disableDeadBandHalfCycle(EPWM_TypeDef* EPWMx); +void EPWM_enableDeadBandHalfCycle(EPWM_TypeDef* EPWMx); +void EPWM_incrementDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx); +void EPWM_incrementDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx); + +uint16_t EPWM_getDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx); +uint16_t EPWM_getDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx); + + +/* Trip-Zone Configuration functions *********************************/ +void EPWM_setTripZoneFilter(EPWM_TypeDef* EPWMx, uint8_t FILTER); +void EPWM_setTripZoneDCEventSelect_DCAEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent); +void EPWM_setTripZoneDCEventSelect_DCAEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent); +void EPWM_setTripZoneDCEventSelect_DCBEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent); +void EPWM_setTripZoneDCEventSelect_DCBEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent); +void EPWM_setTripZoneState_DCAEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState); +void EPWM_setTripZoneState_DCAEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState); +void EPWM_setTripZoneState_DCBEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState); +void EPWM_setTripZoneState_DCBEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState); +void EPWM_setTripZoneState_TZA(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState); +void EPWM_setTripZoneState_TZB(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState); +void EPWM_setOneShotTrip(EPWM_TypeDef* EPWMx); +void EPWM_clearOneShotTrip(EPWM_TypeDef* EPWMx); +void EPWM_clearTripZone(EPWM_TypeDef* EPWMx, const EPWM_TripZoneFlag_e tripZoneFlag); +void EPWM_disableTripZones(EPWM_TypeDef* EPWMx); +void EPWM_disableTripZoneInt(EPWM_TypeDef* EPWMx, const EPWM_TripZoneFlag_e interruptSource); +void EPWM_disableTripZoneSrc(EPWM_TypeDef* EPWMx, const EPWM_TripZoneSrc_e src); +void EPWM_enableTripZoneInt(EPWM_TypeDef* EPWMx, const EPWM_TripZoneFlag_e interruptSource); +void EPWM_enableTripZoneSrc(EPWM_TypeDef* EPWMx, const EPWM_TripZoneSrc_e src); + +FlagStatus EPWM_TripZone_GetFlagStatus(EPWM_TypeDef* EPWMx, uint16_t TZ_FLAG); + + +/* Event-Trigger Configuration functions *********************************/ +void EPWM_clearIntFlag(EPWM_TypeDef* EPWMx); +void EPWM_clearSocAFlag(EPWM_TypeDef* EPWMx); +void EPWM_clearSocBFlag(EPWM_TypeDef* EPWMx); +void EPWM_setSocAPeriod(EPWM_TypeDef* EPWMx, const EPWM_SocPeriod_e intPeriod); +void EPWM_setSocAPulseSrc(EPWM_TypeDef* EPWMx, const EPWM_SocPulseSrc_e pulseSrc); +void EPWM_setSocBPeriod(EPWM_TypeDef* EPWMx, const EPWM_SocPeriod_e intPeriod); +void EPWM_setSocBPulseSrc(EPWM_TypeDef* EPWMx, const EPWM_SocPulseSrc_e pulseSrc); +void EPWM_setIntMode(EPWM_TypeDef* EPWMx, const EPWM_IntMode_e intMode); +void EPWM_setIntPeriod(EPWM_TypeDef* EPWMx, const EPWM_IntPeriod_e intPeriod); +void EPWM_disableInt(EPWM_TypeDef* EPWMx); +void EPWM_disableSocAPulse(EPWM_TypeDef* EPWMx); +void EPWM_disableSocBPulse(EPWM_TypeDef* EPWMx); +void EPWM_enableInt(EPWM_TypeDef* EPWMx); +void EPWM_enableSocAPulse(EPWM_TypeDef* EPWMx); +void EPWM_enableSocBPulse(EPWM_TypeDef* EPWMx); + +uint16_t EPWM_getIntCount(EPWM_TypeDef* EPWMx); +uint16_t EPWM_getSocACount(EPWM_TypeDef* EPWMx); +uint16_t EPWM_getSocBCount(EPWM_TypeDef* EPWMx); + +FlagStatus EPWM_EventTrigger_GetFlagStatus(EPWM_TypeDef* EPWMx, uint16_t ET_FLAG); + + +/* Digital-Compare Configuration functions *********************************/ +void EPWM_setDigitalCompareFilterSource(EPWM_TypeDef* EPWMx, const EPWM_DigitalCompare_FilterSrc_e input); +void EPWM_setDigitalCompareBlankingPulse(EPWM_TypeDef* EPWMx, const EPWM_DigitalCompare_PulseSel_e pulseSelect); +void EPWM_setDigitalCompareFilterOffset(EPWM_TypeDef* EPWMx, const uint16_t offset); +void EPWM_setDigitalCompareFilterWindow(EPWM_TypeDef* EPWMx, const uint16_t window); +void EPWM_setDigitalCompareInput(EPWM_TypeDef* EPWMx, const EPWM_DigitalCompare_Input_e input, const EPWM_DigitalCompare_InputSel_e inputSel); +void EPWM_setDigitalCompareAEvent1(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync, const uint16_t enableSoc, const uint16_t generateSync); +void EPWM_setDigitalCompareAEvent2(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync); +void EPWM_setDigitalCompareBEvent1(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync, const uint16_t enableSoc, const uint16_t generateSync); +void EPWM_setDigitalCompareBEvent2(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync); +void EPWM_disableDigitalCompareBlankingWindow(EPWM_TypeDef* EPWMx); +void EPWM_disableDigitalCompareBlankingWindowInversion(EPWM_TypeDef* EPWMx); +void EPWM_enableDigitalCompareBlankingWindow(EPWM_TypeDef* EPWMx); +void EPWM_enableDigitalCompareBlankingWindowInversion(EPWM_TypeDef* EPWMx); + + +/* HR-PWM Configuration functions *********************************/ +void EPWM_disableAutoConvert(EPWM_TypeDef* EPWMx); +void EPWM_disableHrPeriod(EPWM_TypeDef* EPWMx); +void EPWM_disableHrPhaseSync(EPWM_TypeDef* EPWMx); +void EPWM_disableMEPCalibrationOff(EPWM_TypeDef* EPWMx); +void EPWM_enableAutoConvert(EPWM_TypeDef* EPWMx); +void EPWM_enableHrPeriod(EPWM_TypeDef* EPWMx); +void EPWM_enableHrPhaseSync(EPWM_TypeDef* EPWMx); +void EPWM_enableMEPCalibrationOff(EPWM_TypeDef* EPWMx); +void EPWM_setHrControlMode(EPWM_TypeDef* EPWMx, const EPWM_HrControlMode_e controlMode); +void EPWM_setHrEdgeMode(EPWM_TypeDef* EPWMx, const EPWM_HrEdgeMode_e edgeMode); +void EPWM_setHrShadowMode(EPWM_TypeDef* EPWMx, const EPWM_HrShadowMode_e shadowMode); + +void EPWM_clearMepFlag(EPWM_TypeDef* EPWMx); +FlagStatus EPWM_MepCalibration_GetFlagStatus(EPWM_TypeDef* EPWMx, uint16_t MEP_FLAG); +uint8_t EPWM_enableMEPSFO(EPWM_TypeDef* EPWMx); +void EPWM_disableMEPSFO(EPWM_TypeDef* EPWMx); + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_EPWM_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_eqep.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_eqep.h new file mode 100644 index 00000000000..90c55abcc75 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_eqep.h @@ -0,0 +1,895 @@ +/** + ****************************************************************************** + * @file ft32f4xx_eqep.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the eQEP firmware + * library. + * @version V1.0.0 + * @date 2025-04-17 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_EQEP_H +#define __FT32F4XX_EQEP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup EQEP + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief EQEP quadrature decoder unit structures definition + */ +typedef struct +{ + uint32_t PosCounterSource; /*!< Specifies position counter srource selection. + This parameter can be a value of @ref EQEP_position_counter_source_select */ + + FunctionalState SyncOutput; /*!< Specifies whether synchronous output is enabled. + This parameter can be a value of @ref EQEP_sync_output_select + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t SyncOutputPin; /*!< Specifies which pin is used for synchronous output. + This parameter can be a value of @ref EQEP_sync_output_pin_select */ + + uint32_t ExternalClockRate; /*!< Specifies the external clock rate. + This parameter can be a value of @ref EQEP_external_clock_rate_select */ + + FunctionalState ClockDirSwap; /*!< Specifies whether the quadrature clock inputs are swapped. + This parameter can be a value of @ref EQEP_clock_dir_swap + This parameter can be set to ENABLE or DISABLE. */ + + FunctionalState IndexGate; /*!< Specifies the index pulse gating option. + This parameter can be a value of @ref EQEP_index_gate_option + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t QEPAPolarity; /*!< Specifies the input polarity of QEPA. + This parameter can be a value of @ref EQEP_qepa_polarity */ + + uint32_t QEPBPolarity; /*!< Specifies the input polarity of QEPB. + This parameter can be a value of @ref EQEP_qepb_polarity */ + + uint32_t QEPIPolarity; /*!< Specifies the input polarity of QEPI. + This parameter can be a value of @ref EQEP_qepi_polarity */ + + uint32_t QEPSPolarity; /*!< Specifies the input polarity of QEPS. + This parameter can be a value of @ref EQEP_qeps_polarity */ + +} EQEP_QDUInitTypeDef; + + +/** + * @brief EQEP position counter control structures definition + */ +typedef struct +{ + uint32_t PosCounterResetSrc; /*!< Specifies the reset source for the position counter. + This parameter can be a value of @ref EQEP_postion_counter_reset_source */ + + uint32_t SEInitPosCounter; /*!< Specifies the strobe event initialization of position counter. + This parameter can be a value of @ref EQEP_strobe_event_init_position_counter */ + + uint32_t IEInitPosCounter; /*!< Specifies the index event initialization of position counter. + This parameter can be a value of @ref EQEP_index_event_init_position_counter */ + + //uint32_t SWInitPosCounter; /*!< Specifies the software initialization of position counter. + // This parameter can be a value of @ref EQEP_software_init_position_counter */ + + uint32_t SELatchPosCounter; /*!< Specifies the strobe event latch of position counter. + This parameter can be a value of @ref EQEP_strobe_event_latch_position_counter */ + + uint32_t IELatchPosCounter; /*!< Specifies the index event latch of position counter. + This parameter can be a value of @ref EQEP_index_event_latch_position_counter */ + + //uint32_t PosCounter; /*!< Specifies the position counter enable or software reset. + // This parameter can be a value of @ref EQEP_position_counter_enable */ + + uint32_t CaptureLatchMode; /*!< Specifies the QEP capture latch mode. + This parameter can be a value of @ref EQEP_capture_latch_mode */ + + //uint32_t UnitTimer; /*!< Specifies the QEP unit timer enable. + // This parameter can be a value of @ref EQEP_unit_timer_enable */ + + //uint32_t WatchDog; /*!< Specifies the QEP watchdog enable. + // This parameter can be a value of @ref EQEP_watchdog_enable */ + + uint32_t PosCounterValue; /*!< Specifies the value of the position counter. + This parameter can be a value of @ref EQEP_position_counter_value */ + + uint32_t PosCounterInitValue; /*!< Specifies the initialization value of the position counter. + The value is used to initialize the position counter based on external strobe or + index event. The position counter can be initialized through software(QEPCTL.SWI). + This parameter can be a value of @ref EQEP_position_counter_init_value */ + + uint32_t PosCounterMaxValue; /*!< Specifies the maximum value of the position counter. + This parameter can be a value of @ref EQEP_position_counter_max_value */ + + uint32_t PosCounterCmpValue; /*!< Specifies the compare value of the position counter. + The position compare value in this register is compared with the position + counter(QPOSCNT) to generate sync output and/or interrupt on compare match. + This parameter can be a value of @ref EQEP_position_counter_cmp_value */ + + uint32_t UnitTimerPeriodValue; /*!< Specifies the period value of the unit timer. + The period value for the unit timer to generate periodic unit time events. + This parameter can be a value of @ref EQEP_unit_timer_period_value */ + + uint32_t WdgTimerPeriodValue; /*!< Specifies the period value of the watch dog timer. + This parameter can be a value of @ref EQEP_wdg_timer_period_value */ + + +} EQEP_InitTypeDef; + + +/** + * @brief EQEP capture control structures definition + */ +typedef struct +{ + //uint32_t Capture; /*!< Specifies the QEP capture enable. + // This parameter can be a value of @ref EQEP_capture_enable */ + + uint32_t CaptureClockPrescaler; /*!< Specifies the QEP capture timer clock prescaler. + This parameter can be a value of @ref EQEP_capture_timer_clock_prescaler */ + + uint32_t UnitPosEventPrescaler; /*!< Specifies the unit position event prescaler. + This parameter can be a value of @ref EQEP_unit_position_event_prescaler */ + + uint32_t CapturePeriodValue; /*!< Specifies the period value of the capture timer. + This parameter can be a value of @ref EQEP_capture_period_value */ + +} EQEP_CAPInitTypeDef; + + +/** + * @brief EQEP position compare structures definition + */ +typedef struct +{ + FunctionalState PosCompareShadow; /*!< Specifies the position compare of shadow enable. + This parameter can be a value of @ref EQEP_position_compare_shadow_enable + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t PosCompareShadowLoad; /*!< Specifies the position compare of shadow load. + This parameter can be a value of @ref EQEP_position_compare_shadow_load */ + + uint32_t SyncOutPolarity; /*!< Specifies the polarity of the position compare sync output. + This parameter can be a value of @ref EQEP_sync_out_polarity */ + + FunctionalState PosCompare; /*!< Specifies the position compare enable. + This parameter can be a value of @ref EQEP_position_compare_enable + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t SyncOutPulseWidth; /*!< Specifies the pulse width of the position compare sync output. + This parameter can be a value of @ref EQEP_sync_out_pulse_width */ + +} EQEP_PosCmpInitTypeDef; + + + + + +/** @defgroup EQEP_position_counter_source_select + * @{ + */ +#define EQEP_POSCNTSRC_QUADRATURE_COUNT 0x00000000U +#define EQEP_POSCNTSRC_DIRECTION_COUNT EQEP_QDECCTL_QSRC_0 +#define EQEP_POSCNTSRC_UP_COUNT EQEP_QDECCTL_QSRC_1 +#define EQEP_POSCNTSRC_DOWN_COUNT EQEP_QDECCTL_QSRC + +#define IS_EQEP_POSCNTSRC_MODE(MODE) (((MODE) == EQEP_POSCNTSRC_QUADRATURE_COUNT) || \ + ((MODE) == EQEP_POSCNTSRC_DIRECTION_COUNT ) || \ + ((MODE) == EQEP_POSCNTSRC_UP_COUNT ) || \ + ((MODE) == EQEP_POSCNTSRC_DOWN_COUNT ) ) + +/** + * @} + */ + + +///** @defgroup EQEP_sync_output_select +// * @{ +// */ +//#define EQEP_SYNC_OUTPUT_DISABLE 0x00000000U +//#define EQEP_SYNC_OUTPUT_ENABLE EQEP_QDECCTL_SOEN +// +//#define IS_EQEP_SYNC_OUTPUT_STATE(STATE) (((STATE) == EQEP_SYNC_OUTPUT_DISABLE) || \ +// ((STATE) == EQEP_SYNC_OUTPUT_ENABLE ) ) +// +///** +// * @} +// */ + + +/** @defgroup EQEP_sync_output_pin_select + * @{ + */ +#define EQEP_PIN_INDEX 0x00000000U +#define EQEP_PIN_STROBE EQEP_QDECCTL_SPSEL + +#define IS_EQEP_SYNC_OUTPUT_PIN(PIN) (((PIN) == EQEP_PIN_INDEX ) || \ + ((PIN) == EQEP_PIN_STROBE) ) + +/** + * @} + */ + + +/** @defgroup EQEP_external_clock_rate_select + * @{ + */ +#define EQEP_EXTERNAL_CLOCK_RATE_2x 0x00000000U +#define EQEP_EXTERNAL_CLOCK_RATE_1x EQEP_QDECCTL_XCR + +#define IS_EQEP_EXTERNAL_CLOCK_RATE(RATE) (((RATE) == EQEP_EXTERNAL_CLOCK_RATE_2x) || \ + ((RATE) == EQEP_EXTERNAL_CLOCK_RATE_1x) ) + +/** + * @} + */ + + +///** @defgroup EQEP_clock_dir_swap +// * @{ +// */ +//#define EQEP_CLOCK_DIR_SWAP_DISABLE 0x00000000U +//#define EQEP_CLOCK_DIR_SWAP_ENABLE EQEP_QDECCTL_SWAP +// +//#define IS_EQEP_CLOCK_DIR_SWAP_STATE(STATE) (((STATE) == EQEP_CLOCK_DIR_SWAP_DISABLE) || \ +// ((STATE) == EQEP_CLOCK_DIR_SWAP_ENABLE ) ) +// +///** +// * @} +// */ + + +///** @defgroup EQEP_index_gate_option +// * @{ +// */ +//#define EQEP_INDEX_GATE_DISABLE 0x00000000U +//#define EQEP_INDEX_GATE_ENABLE EQEP_QDECCTL_IGATE +// +//#define IS_EQEP_INDEX_GATE_STATE(STATE) (((STATE) == EQEP_INDEX_GATE_DISABLE) || \ +// ((STATE) == EQEP_INDEX_GATE_ENABLE ) ) +// +///** +// * @} +// */ + + +/** @defgroup EQEP_qepa_polarity + * @{ + */ +#define EQEP_QEPA_INPUT_NO_EFFECT 0x00000000U +#define EQEP_QEPA_INPUT_NEGATE EQEP_QDECCTL_QAP + +#define IS_EQEP_QEPA_POLARITY(STATE) (((STATE) == EQEP_QEPA_INPUT_NO_EFFECT) || \ + ((STATE) == EQEP_QEPA_INPUT_NEGATE ) ) + +/** + * @} + */ + + +/** @defgroup EQEP_qepb_polarity + * @{ + */ +#define EQEP_QEPB_INPUT_NO_EFFECT 0x00000000U +#define EQEP_QEPB_INPUT_NEGATE EQEP_QDECCTL_QBP + +#define IS_EQEP_QEPB_POLARITY(STATE) (((STATE) == EQEP_QEPB_INPUT_NO_EFFECT) || \ + ((STATE) == EQEP_QEPB_INPUT_NEGATE ) ) + +/** + * @} + */ + + +/** @defgroup EQEP_qepi_polarity + * @{ + */ +#define EQEP_QEPI_INPUT_NO_EFFECT 0x00000000U +#define EQEP_QEPI_INPUT_NEGATE EQEP_QDECCTL_QIP + +#define IS_EQEP_QEPI_POLARITY(STATE) (((STATE) == EQEP_QEPI_INPUT_NO_EFFECT) || \ + ((STATE) == EQEP_QEPI_INPUT_NEGATE ) ) + +/** + * @} + */ + + +/** @defgroup EQEP_qeps_polarity + * @{ + */ +#define EQEP_QEPS_INPUT_NO_EFFECT 0x00000000U +#define EQEP_QEPS_INPUT_NEGATE EQEP_QDECCTL_QSP + +#define IS_EQEP_QEPS_POLARITY(STATE) (((STATE) == EQEP_QEPS_INPUT_NO_EFFECT) || \ + ((STATE) == EQEP_QEPS_INPUT_NEGATE ) ) + +/** + * @} + */ + + + + + + + + +/** @defgroup EQEP_postion_counter_reset_source + * @{ + */ +#define EQEP_RESET_SOURCE_INDEX 0x00000000U +#define EQEP_RESET_SOURCE_MAX EQEP_QEPCTL_PCRM_0 +#define EQEP_RESET_SOURCE_FIRST EQEP_QEPCTL_PCRM_1 +#define EQEP_RESET_SOURCE_UNIT EQEP_QEPCTL_PCRM + +#define IS_EQEP_RESET_SOURCE(SEL) (((SEL) == EQEP_RESET_SOURCE_INDEX) || \ + ((SEL) == EQEP_RESET_SOURCE_MAX ) || \ + ((SEL) == EQEP_RESET_SOURCE_FIRST) || \ + ((SEL) == EQEP_RESET_SOURCE_UNIT ) ) + +/** + * @} + */ + + +/** @defgroup EQEP_strobe_event_init_position_counter + * @{ + */ +#define EQEP_SE_INIT_DISABLE 0x00000000U +#define EQEP_SE_INIT_RISING_EDGE EQEP_QEPCTL_SEI_1 +#define EQEP_SE_INIT_DOUBLE_EDGE EQEP_QEPCTL_SEI + +#define IS_EQEP_SE_INIT(MODE) (((MODE) == EQEP_SE_INIT_DISABLE ) || \ + ((MODE) == EQEP_SE_INIT_RISING_EDGE) || \ + ((MODE) == EQEP_SE_INIT_DOUBLE_EDGE) ) + +/** + * @} + */ + + +/** @defgroup EQEP_index_event_init_position_counter + * @{ + */ +#define EQEP_IE_INIT_DISABLE 0x00000000U +#define EQEP_IE_INIT_RISING_EDGE EQEP_QEPCTL_IEI_1 +#define EQEP_IE_INIT_DOUBLE_EDGE EQEP_QEPCTL_IEI + +#define IS_EQEP_IE_INIT(MODE) (((MODE) == EQEP_IE_INIT_DISABLE ) || \ + ((MODE) == EQEP_IE_INIT_RISING_EDGE) || \ + ((MODE) == EQEP_IE_INIT_DOUBLE_EDGE) ) + +/** + * @} + */ + + +///** @defgroup EQEP_software_init_position_counter +// * @{ +// */ +//#define EQEP_SW_INIT_DISABLE 0x00000000U +//#define EQEP_SW_INIT_ENABLE EQEP_QEPCTL_SWI +// +//#define IS_EQEP_SW_INIT(MODE) (((MODE) == EQEP_SW_INIT_DISABLE) || \ +// ((MODE) == EQEP_SW_INIT_ENABLE ) ) +// +///** +// * @} +// */ + + +/** @defgroup EQEP_strobe_event_latch_position_counter + * @{ + */ +#define EQEP_SE_LATCH_RISING_EDGE 0x00000000U +#define EQEP_SE_LATCH_DOUBLE_EDGE EQEP_QEPCTL_SEL + +#define IS_EQEP_SE_LATCH(MODE) (((MODE) == EQEP_SE_LATCH_RISING_EDGE) || \ + ((MODE) == EQEP_SE_LATCH_DOUBLE_EDGE) ) + +/** + * @} + */ + + +/** @defgroup EQEP_index_event_latch_position_counter + * @{ + */ +#define EQEP_IE_LATCH_DISABLE 0x00000000U +#define EQEP_IE_LATCH_RISING_EDGE EQEP_QEPCTL_IEL_0 +#define EQEP_IE_LATCH_FALLING_EDGE EQEP_QEPCTL_IEL_1 +#define EQEP_IE_LATCH_SOFTWAREMARKER EQEP_QEPCTL_IEL + +#define IS_EQEP_IE_LATCH(MODE) (((MODE) == EQEP_IE_LATCH_DISABLE ) || \ + ((MODE) == EQEP_IE_LATCH_RISING_EDGE ) || \ + ((MODE) == EQEP_IE_LATCH_FALLING_EDGE ) || \ + ((MODE) == EQEP_IE_LATCH_SOFTWAREMARKER) ) + +/** + * @} + */ + + +///** @defgroup EQEP_position_counter_enable +// * @{ +// */ +//#define EQEP_POSCOUNTER_DISABLE 0x00000000U +//#define EQEP_POSCOUNTER_ENABLE EQEP_QEPCTL_QPEN +// +//#define IS_EQEP_POSCOUNTER(STATE) (((STATE) == EQEP_POSCOUNTER_DISABLE) || \ +// ((STATE) == EQEP_POSCOUNTER_ENABLE ) ) +// +///** +// * @} +// */ + + +/** @defgroup EQEP_capture_latch_mode + * @{ + */ +#define EQEP_CAPTURELATCH_CPU 0x00000000U +#define EQEP_CAPTURELATCH_TIMEOUT EQEP_QEPCTL_QCLM + +#define IS_EQEP_CAPTURELATCH_MODE(MODE) (((MODE) == EQEP_CAPTURELATCH_CPU ) || \ + ((MODE) == EQEP_CAPTURELATCH_TIMEOUT) ) + +/** + * @} + */ + + +/** @defgroup EQEP_position_counter_value + * @{ + */ +#define IS_EQEP_POS_COUNTER_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + + +/** @defgroup EQEP_position_counter_init_value + * @{ + */ +#define IS_EQEP_POS_COUNTER_INIT_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + + +/** @defgroup EQEP_position_counter_max_value + * @{ + */ +#define IS_EQEP_POS_COUNTER_MAX_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + + +/** @defgroup EQEP_position_counter_cmp_value + * @{ + */ +#define IS_EQEP_POS_COUNTER_CMP_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + + +/** @defgroup EQEP_unit_timer_period_value + * @{ + */ +#define IS_EQEP_UNIT_TIMER_PERIOD_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFFFFFU)) + +/** + * @} + */ + + +/** @defgroup EQEP_wdg_timer_period_value + * @{ + */ +#define IS_EQEP_WDG_TIMER_PERIOD_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFU)) + +/** + * @} + */ + + + + + +///** @defgroup EQEP_unit_timer_enable +// * @{ +// */ +//#define EQEP_UNITTIMER_DISABLE 0x00000000U +//#define EQEP_UNITTIMER_ENABLE EQEP_QEPCTL_UTE +// +//#define IS_EQEP_UNITTIMER(STATE) (((STATE) == EQEP_UNITTIMER_DISABLE) || \ +// ((STATE) == EQEP_UNITTIMER_ENABLE ) ) +// +///** +// * @} +// */ +// +// +///** @defgroup EQEP_watchdog_enable +// * @{ +// */ +//#define EQEP_WATCHDOG_DISABLE 0x00000000U +//#define EQEP_WATCHDOG_ENABLE EQEP_QEPCTL_WDE +// +//#define IS_EQEP_WATCHDOG(STATE) (((STATE) == EQEP_WATCHDOG_DISABLE) || \ +// ((STATE) == EQEP_WATCHDOG_ENABLE ) ) +// +///** +// * @} +// */ + + + + + + +///** @defgroup EQEP_capture_enable +// * @{ +// */ +//#define EQEP_CAPTURE_DISABLE 0x00000000U +//#define EQEP_CAPTURE_ENABLE EQEP_QCAPCTL_CEN +// +//#define IS_EQEP_CAPTURE(STATE) (((STATE) == EQEP_CAPTURE_DISABLE) || \ +// ((STATE) == EQEP_CAPTURE_ENABLE ) ) +// +///** +// * @} +// */ + + +/** @defgroup EQEP_capture_timer_clock_prescaler + * @{ + */ +#define EQEP_CLOCKPRESCALER_1 0x00000000U +#define EQEP_CLOCKPRESCALER_2 EQEP_QCAPCTL_CCPS_0 +#define EQEP_CLOCKPRESCALER_4 EQEP_QCAPCTL_CCPS_1 +#define EQEP_CLOCKPRESCALER_8 (EQEP_QCAPCTL_CCPS_0 | EQEP_QCAPCTL_CCPS_1) +#define EQEP_CLOCKPRESCALER_16 EQEP_QCAPCTL_CCPS_2 +#define EQEP_CLOCKPRESCALER_32 (EQEP_QCAPCTL_CCPS_0 | EQEP_QCAPCTL_CCPS_2) +#define EQEP_CLOCKPRESCALER_64 (EQEP_QCAPCTL_CCPS_1 | EQEP_QCAPCTL_CCPS_2) +#define EQEP_CLOCKPRESCALER_128 EQEP_QCAPCTL_CCPS + +#define IS_EQEP_CLOCKPRESCALER(PRE) (((PRE) == EQEP_CLOCKPRESCALER_1 ) || \ + ((PRE) == EQEP_CLOCKPRESCALER_2 ) || \ + ((PRE) == EQEP_CLOCKPRESCALER_4 ) || \ + ((PRE) == EQEP_CLOCKPRESCALER_8 ) || \ + ((PRE) == EQEP_CLOCKPRESCALER_16 ) || \ + ((PRE) == EQEP_CLOCKPRESCALER_32 ) || \ + ((PRE) == EQEP_CLOCKPRESCALER_64 ) || \ + ((PRE) == EQEP_CLOCKPRESCALER_128) ) + +/** + * @} + */ + + +/** @defgroup EQEP_unit_position_event_prescaler + * @{ + */ +#define EQEP_EVENTPRESCALER_1 0x00000000U +#define EQEP_EVENTPRESCALER_2 0x00000001U +#define EQEP_EVENTPRESCALER_4 0x00000002U +#define EQEP_EVENTPRESCALER_8 0x00000003U +#define EQEP_EVENTPRESCALER_16 0x00000004U +#define EQEP_EVENTPRESCALER_32 0x00000005U +#define EQEP_EVENTPRESCALER_64 0x00000006U +#define EQEP_EVENTPRESCALER_128 0x00000007U +#define EQEP_EVENTPRESCALER_256 0x00000008U +#define EQEP_EVENTPRESCALER_512 0x00000009U +#define EQEP_EVENTPRESCALER_1024 0x0000000AU +#define EQEP_EVENTPRESCALER_2048 0x0000000BU + +#define IS_EQEP_EVENTPRESCALER(PRE) (((PRE) == EQEP_EVENTPRESCALER_1 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_2 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_4 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_8 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_16 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_32 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_64 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_128 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_256 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_512 ) || \ + ((PRE) == EQEP_EVENTPRESCALER_1024) || \ + ((PRE) == EQEP_EVENTPRESCALER_2048) ) + +/** + * @} + */ + + +/** @defgroup EQEP_capture_period_value + * @{ + */ +#define IS_EQEP_CAPTURE_PERIOD_VALUE(VALUE) (((VALUE) >= 0x0U) && ((VALUE) <= 0xFFFFU)) + +/** + * @} + */ + + + +///** @defgroup EQEP_position_compare_shadow_enable +// * @{ +// */ +//#define EQEP_POSCMP_SHADOW_DISABLE 0x00000000U +//#define EQEP_POSCMP_SHADOW_ENABLE EQEP_QPOSCTL_PCSHDW +// +//#define IS_EQEP_POSCMP_SHADOW(STATE) (((STATE) == EQEP_POSCMP_SHADOW_DISABLE) || \ +// ((STATE) == EQEP_POSCMP_SHADOW_ENABLE ) ) +// +///** +// * @} +// */ + + +/** @defgroup EQEP_position_compare_shadow_load + * @{ + */ +#define EQEP_POSCMP_LOAD_CNTZERO 0x00000000U +#define EQEP_POSCMP_LOAD_CNTCMP EQEP_QPOSCTL_PCLOAD + +#define IS_EQEP_POSCMP_LOAD(STATE) (((STATE) == EQEP_POSCMP_LOAD_CNTZERO) || \ + ((STATE) == EQEP_POSCMP_LOAD_CNTCMP ) ) + +/** + * @} + */ + + +/** @defgroup EQEP_sync_out_polarity + * @{ + */ +#define EQEP_SYNCOUT_POLARITY_HIGH 0x00000000U +#define EQEP_SYNCOUT_POLARITY_LOW EQEP_QPOSCTL_PCPOL + +#define IS_EQEP_SYNCOUT_POLARITY(POLARITY) (((POLARITY) == EQEP_SYNCOUT_POLARITY_HIGH) || \ + ((POLARITY) == EQEP_SYNCOUT_POLARITY_LOW ) ) + +/** + * @} + */ + + +///** @defgroup EQEP_position_compare_enable +// * @{ +// */ +//#define EQEP_POSCOMPARE_DISABLE 0x00000000U +//#define EQEP_POSCOMPARE_ENABLE EQEP_QPOSCTL_PCMPE +// +//#define IS_EQEP_POSCOMPARE(STATE) (((STATE) == EQEP_POSCOMPARE_DISABLE) || \ +// ((STATE) == EQEP_POSCOMPARE_ENABLE ) ) +// +///** +// * @} +// */ + + +/** @defgroup EQEP_sync_out_pulse_width + * @{ + */ +#define IS_EQEP_SYNCOUT_PULSE_WIDTH(WIDTH) (((WIDTH) >= 0x0U) && ((WIDTH) <= 0xFFFU)) + +/** + * @} + */ + + + +/** @defgroup EQEP_interrupt_definition EQEP_IT + * @{ + */ +#define EQEP_IT_PCE EQEP_QEINT_PCE +#define EQEP_IT_PHE EQEP_QEINT_PHE +#define EQEP_IT_QDC EQEP_QEINT_QDC +#define EQEP_IT_WTO EQEP_QEINT_WTO +#define EQEP_IT_PCU EQEP_QEINT_PCU +#define EQEP_IT_PCO EQEP_QEINT_PCO +#define EQEP_IT_PCR EQEP_QEINT_PCR +#define EQEP_IT_PCM EQEP_QEINT_PCM +#define EQEP_IT_SEL EQEP_QEINT_SEL +#define EQEP_IT_IEL EQEP_QEINT_IEL +#define EQEP_IT_UTO EQEP_QEINT_UTO + +#define IS_EQEP_IT(TYPE) (((TYPE) == EQEP_IT_PCE) || \ + ((TYPE) == EQEP_IT_PHE) || \ + ((TYPE) == EQEP_IT_QDC) || \ + ((TYPE) == EQEP_IT_WTO) || \ + ((TYPE) == EQEP_IT_PCU) || \ + ((TYPE) == EQEP_IT_PCO) || \ + ((TYPE) == EQEP_IT_PCR) || \ + ((TYPE) == EQEP_IT_PCM) || \ + ((TYPE) == EQEP_IT_SEL) || \ + ((TYPE) == EQEP_IT_IEL) || \ + ((TYPE) == EQEP_IT_UTO) ) +/** + * @} + */ + + + +/** @defgroup EQEP_flags_definition EQEP_FLAG + * @{ + */ +#define EQEP_FLAG_INT EQEP_QFLG_INT +#define EQEP_FLAG_PCE EQEP_QFLG_PCE +#define EQEP_FLAG_PHE EQEP_QFLG_PHE +#define EQEP_FLAG_QDC EQEP_QFLG_QDC +#define EQEP_FLAG_WTO EQEP_QFLG_WTO +#define EQEP_FLAG_PCU EQEP_QFLG_PCU +#define EQEP_FLAG_PCO EQEP_QFLG_PCO +#define EQEP_FLAG_PCR EQEP_QFLG_PCR +#define EQEP_FLAG_PCM EQEP_QFLG_PCM +#define EQEP_FLAG_SEL EQEP_QFLG_SEL +#define EQEP_FLAG_IEL EQEP_QFLG_IEL +#define EQEP_FLAG_UTO EQEP_QFLG_UTO + +#define IS_EQEP_FLAG(TYPE) (((TYPE) == EQEP_FLAG_INT ) || \ + ((TYPE) == EQEP_FLAG_PCE) || \ + ((TYPE) == EQEP_FLAG_PHE) || \ + ((TYPE) == EQEP_FLAG_QDC) || \ + ((TYPE) == EQEP_FLAG_WTO) || \ + ((TYPE) == EQEP_FLAG_PCU) || \ + ((TYPE) == EQEP_FLAG_PCO) || \ + ((TYPE) == EQEP_FLAG_PCR) || \ + ((TYPE) == EQEP_FLAG_PCM) || \ + ((TYPE) == EQEP_FLAG_SEL) || \ + ((TYPE) == EQEP_FLAG_IEL) || \ + ((TYPE) == EQEP_FLAG_UTO) ) + +#define EQEP_IT_MASK 0x00000FFFU +/** + * @} + */ + + +/** @defgroup EQEP_status_definition EQEP_STATUS + * @{ + */ +#define EQEP_STATUS_UPEVNT EQEP_QEPSTS_UPEVNT +#define EQEP_STATUS_FIDF EQEP_QEPSTS_FIDF +#define EQEP_STATUS_QDF EQEP_QEPSTS_QDF +#define EQEP_STATUS_QDLF EQEP_QEPSTS_QDLF +#define EQEP_STATUS_COEF EQEP_QEPSTS_COEF +#define EQEP_STATUS_CDEF EQEP_QEPSTS_CDEF +#define EQEP_STATUS_FIMF EQEP_QEPSTS_FIMF +#define EQEP_STATUS_PCEF EQEP_QEPSTS_PCEF + +#define IS_EQEP_STATUS(STATUS) (((STATUS) == EQEP_STATUS_UPEVNT) || \ + ((STATUS) == EQEP_STATUS_FIDF ) || \ + ((STATUS) == EQEP_STATUS_QDF ) || \ + ((STATUS) == EQEP_STATUS_QDLF ) || \ + ((STATUS) == EQEP_STATUS_COEF ) || \ + ((STATUS) == EQEP_STATUS_CDEF ) || \ + ((STATUS) == EQEP_STATUS_FIMF ) || \ + ((STATUS) == EQEP_STATUS_PCEF ) ) +/** + * @} + */ + + +/** + * @brief EQEP_register_type_definition EQEP_REG_TYPE + */ +#define EQEP_QPOSCNT ((uint16_t)0x0001U) +#define EQEP_QUTMR ((uint16_t)0x0002U) +#define EQEP_QWDTMR ((uint16_t)0x0004U) +#define EQEP_QCTMR ((uint16_t)0x0008U) +#define EQEP_QPOSINIT ((uint16_t)0x0010U) +#define EQEP_QPOSMAX ((uint16_t)0x0020U) +#define EQEP_QPOSCMP ((uint16_t)0x0040U) +#define EQEP_QPOSILAT ((uint16_t)0x0080U) +#define EQEP_QPOSSLAT ((uint16_t)0x0100U) +#define EQEP_QPOSLAT ((uint16_t)0x0200U) +#define EQEP_QUPRD ((uint16_t)0x0400U) +#define EQEP_QWDPRD ((uint16_t)0x0800U) +#define EQEP_QCPRD ((uint16_t)0x1000U) +#define EQEP_QCTMRLAT ((uint16_t)0x2000U) +#define EQEP_QCPRDLAT ((uint16_t)0x4000U) + +#define IS_EQEP_REG_TYPE(TYPE) (((TYPE) == EQEP_QPOSCNT ) || \ + ((TYPE) == EQEP_QUTMR ) || \ + ((TYPE) == EQEP_QWDTMR ) || \ + ((TYPE) == EQEP_QCTMR ) || \ + ((TYPE) == EQEP_QPOSINIT ) || \ + ((TYPE) == EQEP_QPOSMAX ) || \ + ((TYPE) == EQEP_QPOSCMP ) || \ + ((TYPE) == EQEP_QPOSILAT ) || \ + ((TYPE) == EQEP_QPOSSLAT ) || \ + ((TYPE) == EQEP_QPOSLAT ) || \ + ((TYPE) == EQEP_QUPRD ) || \ + ((TYPE) == EQEP_QWDPRD ) || \ + ((TYPE) == EQEP_QCPRD ) || \ + ((TYPE) == EQEP_QCTMRLAT ) || \ + ((TYPE) == EQEP_QCPRDLAT )) + + +/** + * @brief EQEP_submodule_definition EQEP_SUBMDU_TYPE + */ +#define EQEP_POS_CNT ((uint8_t)0x01U) +#define EQEP_UNIT_TMR ((uint8_t)0x02U) +#define EQEP_WTD_TMR ((uint8_t)0x04U) +#define EQEP_CAP_TMR ((uint8_t)0x08U) + +#define IS_EQEP_SUBMDU_TYPE(TYPE) (((TYPE) == EQEP_POS_CNT ) || \ + ((TYPE) == EQEP_UNIT_TMR) || \ + ((TYPE) == EQEP_WTD_TMR ) || \ + ((TYPE) == EQEP_CAP_TMR )) + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the EQEP configuration to the default reset state ******/ +void EQEP_DeInit(); + +/* Initialization and Configuration functions *********************************/ +void EQEP_Init(EQEP_InitTypeDef* EQEP_InitStruct); +void EQEP_QDUInit(EQEP_QDUInitTypeDef* EQEP_QDUInitStruct); +void EQEP_CAPInit(EQEP_CAPInitTypeDef* EQEP_CAPInitStruct); +void EQEP_POSCMPInit(EQEP_PosCmpInitTypeDef* EQEP_PosCmpInitStruct); + +void EQEP_StructInit(EQEP_InitTypeDef* EQEP_InitStruct); +void EQEP_QDUStructInit(EQEP_QDUInitTypeDef* EQEP_QDUInitStruct); +void EQEP_CAPStructInit(EQEP_CAPInitTypeDef* EQEP_CAPInitStruct); +void EQEP_POSCMPStructInit(EQEP_PosCmpInitTypeDef* EQEP_PosCmpInitStruct); + +/* EQEP control functions *********************************/ +void EQEP_Cmd(uint16_t EQEP_REG_TYPE, FunctionalState NewState); //QEPCTL.QPEN +//void EQEP_UnitTimerCmd(FunctionalState NewState); //QEPCTL.UTE +//void EQEP_WdgTimerCmd(FunctionalState NewState); //QEPCTL.WDE +//void EQEP_CaptureCmd(FunctionalState NewState); //QCAPCTL.CEN +////void EQEP_PosCmpCmd(FunctionalState NewState); //QPOSCTL.PCMPE +void EQEP_SoftwareInitPositionCounter(FunctionalState NewState); //QEPCTL.SWI + +/* Data register access function***********************************************/ +void EQEP_WriteDataRegister(uint16_t EQEP_REG_TYPE, uint32_t Value); +uint32_t EQEP_GetDataRegister(uint16_t EQEP_REG_TYPE); + +/* Interrupts and flags management functions **********************************/ +void EQEP_ITConfig(uint16_t EQEP_IT, FunctionalState NewState); +void EQEP_ClearFlag(uint16_t EQEP_FLAG); +void EQEP_ITForce(uint16_t EQEP_IT); +ITStatus EQEP_GetITStatus(uint16_t EQEP_IT); +FlagStatus EQEP_GetFlagStatus(uint16_t EQEP_FLAG); +FlagStatus EQEP_GetStatus(uint8_t EQEP_STATUS); + + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_EQEP_H */ + + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_eth.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_eth.h new file mode 100644 index 00000000000..96c771d9d9d --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_eth.h @@ -0,0 +1,1809 @@ +/** + ****************************************************************************** + * @file ft32f4xx_eth.h + * @author xcao + * @brief Header file of heth module. + ****************************************************************************** + * @attention + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_ETH_H +#define __FT32F4XX_ETH_H + + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +//#if defined(eth) +typedef enum +{ + HAL_OK = 0x0U, + HAL_ERROR = 0x1U, + HAL_BUSY = 0x2U, + HAL_TIMEOUT = 0x3U +} HAL_StatusTypeDef; +/** @addtogroup FT32F4xx_Driver + * @{ + */ + +/** @addtogroup heth + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef ETH_TX_DESC_CNT +#define ETH_TX_DESC_CNT 4U +#endif /* ETH_TX_DESC_CNT */ + +#ifndef ETH_RX_DESC_CNT +#define ETH_RX_DESC_CNT 4U +#endif /* ETH_RX_DESC_CNT */ + +#ifndef ETH_SWRESET_TIMEOUT +#define ETH_SWRESET_TIMEOUT 500U +#endif /* ETH_SWRESET_TIMEOUT */ + +#ifndef ETH_MDIO_BUS_TIMEOUT +#define ETH_MDIO_BUS_TIMEOUT 1000U +#endif /* ETH_MDIO_BUS_TIMEOUT */ + +#ifndef ETH_MAC_US_TICK +#define ETH_MAC_US_TICK 1000000U +#endif /* ETH_MAC_US_TICK */ + +/*********************** Common state type defination **************************/ +/*TODO START*/ +/*Need to be defined at high level header file*/ +//typedef enum +//{ +// DISABLE = 0, +// ENABLE = !DISABLE +//}FunctionalState; + +/*********************** Descriptors struct def section ************************/ +/** @defgroup ETH_Exported_Types heth Exported Types + * @{ + */ + +/** + * @brief heth DMA Descriptor structure definition + */ +typedef struct +{ + __IO uint32_t DESC0; + __IO uint32_t DESC1; + __IO uint32_t DESC2; + __IO uint32_t DESC3; + uint32_t BackupAddr0; /* used to store rx buffer 1 address */ + uint32_t BackupAddr1; /* used to store rx buffer 2 address */ +} ETH_DMADescTypeDef; +/** + * + */ + +/** + * @brief heth Buffers List structure definition + */ +typedef struct __ETH_BufferTypeDef +{ + uint8_t *buffer; /*gState = ETH_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) +#else +#define __ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = ETH_STATE_RESET; \ + } while(0) +#endif /*USE_ETH_REGISTER_CALLBACKS */ + +/** + * @brief Enables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : heth Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * enabled @ref ETH_DMA_Interrupts + * @retval None + */ +#define __ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ETH_DMA_INTRENA |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET DMA interrupts. + * @param __HANDLE__ : heth Handle + * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be + * disabled. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ETH_DMA_INTRENA &= ~(__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT source enabled or disabled. + * @param __HANDLE__ : heth Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The heth DMA IT Source enabled or disabled + */ +#define __ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->ETH_DMA_INTRENA & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Gets the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : heth Handle + * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts + * @retval The state of heth DMA IT (SET or RESET) + */ +#define __ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) \ + (((__HANDLE__)->Instance->ETH_DMA_STU & (__INTERRUPT__)) == (__INTERRUPT__)) + +/** + * @brief Clears the ETHERNET DMA IT pending bit. + * @param __HANDLE__ : heth Handle + * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts + * @retval None + */ +#define __ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ETH_DMA_STU = (__INTERRUPT__)) + +/** + * @brief Checks wether the specified ETHERNET DMA flag is set or not. + * @param __HANDLE__: heth Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of heth DMA FLAG (SET or RESET). + */ +#define __ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ETH_DMA_STU &( __FLAG__)) == ( __FLAG__)) + +/** + * @brief Clears the specified ETHERNET DMA flag. + * @param __HANDLE__: heth Handle + * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags + * @retval The state of heth DMA FLAG (SET or RESET). + */ +#define __ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ETH_DMA_STU = ( __FLAG__)) + +/** + * @brief Enables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : heth Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ + +#define __ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ETH_MAC_IREN |= (__INTERRUPT__)) + +/** + * @brief Disables the specified ETHERNET MAC interrupts. + * @param __HANDLE__ : heth Handle + * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be + * enabled @ref ETH_MAC_Interrupts + * @retval None + */ +#define __ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->ETH_MAC_IREN &= ~(__INTERRUPT__)) + +/** + * @brief Checks wether the specified ETHERNET MAC flag is set or not. + * @param __HANDLE__: heth Handle + * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts + * @retval The state of heth MAC IT (SET or RESET). + */ +#define __ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ETH_MAC_IRSTU &\ + ( __INTERRUPT__)) == ( __INTERRUPT__)) + +/*!< External interrupt line 19 Connected to the heth wakeup EXTI Line */ +#define ETH_WAKEUP_EXTI_LINE 0x00080000U + +/** + * @brief Enable the heth WAKEUP Exti Line. + * @param __EXTI_LINE__: specifies the heth WAKEUP Exti sources to be enabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI->IMR |= (__EXTI_LINE__)) + +/** + * @brief checks wether the specified heth WAKEUP Exti interrupt flag is set or not. + * @param __EXTI_LINE__: specifies the heth WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval EXTI heth WAKEUP Line Status. + */ +#define __ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__)) + +/** + * @brief Clear the heth WAKEUP Exti flag. + * @param __EXTI_LINE__: specifies the heth WAKEUP Exti sources to be cleared. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None. + */ +#define __ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__)) + + +/** + * @brief enable rising edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the heth WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR &= ~(__EXTI_LINE__)); \ + (EXTI->RTSR |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the heth WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR &= ~(__EXTI_LINE__));\ + (EXTI->FTSR |= (__EXTI_LINE__)) + +/** + * @brief enable falling edge interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the heth WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR |= (__EXTI_LINE__));\ + (EXTI->FTSR |= (__EXTI_LINE__)) + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param __EXTI_LINE__: specifies the heth WAKEUP EXTI sources to be disabled. + * @arg ETH_WAKEUP_EXTI_LINE + * @retval None + */ +#define __ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) + +#define __ETH_GET_PTP_CONTROL(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ETH_PTP_TSCTL) & \ + (__FLAG__)) == (__FLAG__)) ? SET : RESET) + +#define __ETH_SET_PTP_CONTROL(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ETH_PTP_TSCTL |= (__FLAG__)) + +/** + * @} + */ + +/* Include heth Extension module */ +//#include "ft32_eth_ex.h" + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup ETH_Exported_Functions + * @{ + */ + +/** @addtogroup ETH_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de initialization functions **********************************/ +uint32_t ETH_Init(ETH_HandleTypeDef *heth); +uint32_t ETH_DeInit(ETH_HandleTypeDef *heth); +void ETH_MspInit(ETH_HandleTypeDef *heth); +void ETH_MspDeInit(ETH_HandleTypeDef *heth); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_ETH_REGISTER_CALLBACKS == 1) +StatusTypeDef ETH_RegisterCallback(ETH_HandleTypeDef *heth, ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); +StatusTypeDef ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, ETH_CallbackIDTypeDef CallbackID); +#endif /* USE_ETH_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *******************************************************/ +uint32_t ETH_Start(ETH_HandleTypeDef *heth); +uint32_t ETH_Start_IT(ETH_HandleTypeDef *heth); +uint32_t ETH_Stop(ETH_HandleTypeDef *heth); +uint32_t ETH_Stop_IT(ETH_HandleTypeDef *heth); + +uint32_t ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff); +uint32_t ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, pETH_rxAllocateCallbackTypeDef rxAllocateCallback); +void ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth); +uint32_t ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback); +void ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth); +void ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode); +uint32_t ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback); +void ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth); +void ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth); + +#ifdef ETH_USE_PTP +uint32_t ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +uint32_t ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig); +uint32_t ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +uint32_t ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time); +uint32_t ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset); +uint32_t ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth); +uint32_t ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +uint32_t ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp); +uint32_t ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback); +uint32_t ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth); +#endif /* ETH_USE_PTP */ + +uint32_t ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout); +uint32_t ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig); + +uint32_t ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue); +uint32_t ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); + +void ETH_IRQHandler(ETH_HandleTypeDef *heth); +void ETH_TxCpltCallback(ETH_HandleTypeDef *heth); +void ETH_RxCpltCallback(ETH_HandleTypeDef *heth); +void ETH_ErrorCallback(ETH_HandleTypeDef *heth); +void ETH_PMTCallback(ETH_HandleTypeDef *heth); +void ETH_WakeUpCallback(ETH_HandleTypeDef *heth); +void ETH_RxAllocateCallback(uint8_t **buff); +void ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length); +void ETH_TxFreeCallback(uint32_t *buff); +void ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp); +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control functions **********************************************/ +/* MAC & DMA Configuration APIs **********************************************/ +static void HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf); +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf); +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth); +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth); +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth); +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, + uint32_t ItMode); +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth); +uint32_t ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +uint32_t ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf); +uint32_t ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf); +void ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth); + +/* MAC VLAN Processing APIs ************************************************/ +void ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier); + +/* MAC L2 Packet Filtering APIs **********************************************/ +uint32_t ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig); +uint32_t ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig); +uint32_t ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable); +uint32_t ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, const uint8_t *pMACAddr); + +/* MAC Power Down APIs *****************************************************/ +void ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig); +void ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth); +uint32_t ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count); + +/** + * @} + */ + +/** @addtogroup ETH_Exported_Functions_Group4 + * @{ + */ +/* Peripheral State functions **************************************************/ +uint32_t ETH_GetState(const ETH_HandleTypeDef *heth); +uint32_t ETH_GetError(const ETH_HandleTypeDef *heth); +uint32_t ETH_GetDMAError(const ETH_HandleTypeDef *heth); +uint32_t ETH_GetMACError(const ETH_HandleTypeDef *heth); +uint32_t ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +//#endif /* heth */ + +#ifdef __cplusplus +} +#endif + +#endif /* FT32F4xx_ETH_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_exti.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_exti.h new file mode 100644 index 00000000000..ce51ea43a88 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_exti.h @@ -0,0 +1,186 @@ +/** + ****************************************************************************** + * @file ft32f4xx_exti.h + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_EXTI_H +#define __FT32F4XX_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief EXTI mode enumeration + */ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTIMode_TypeDef; + +#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) + + +/** + * @brief EXTI Trigger enumeration + */ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTITrigger_TypeDef; + +#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ + ((TRIGGER) == EXTI_Trigger_Falling) || \ + ((TRIGGER) == EXTI_Trigger_Rising_Falling)) + +/** + * @brief EXTI Init Structure definition + */ + +typedef struct +{ + uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +} EXTI_InitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup EXTI_Exported_Constants + * @{ + */ +/** @defgroup EXTI_Lines + * @{ + */ + +#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x00010000) /*!< Internal interrupt line 16 + connected to the PVD + event */ +#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 + Connected to the RTC Alarm + event */ +#define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18 + Connected to the USB OTG FS wakeup + event*/ +#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19 + Connected to the Ethernet wakeup + events */ +#define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20 + Connected to the USB OTG HS wakeup + event */ +#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21 + Connected to the RTC Tamper and Time Stamp + event */ +#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22 + Connected to the RTC wakeup + event*/ +#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23 + Connected to the Comparator 1 + event*/ +#define EXTI_Line24 ((uint32_t)0x01000000) /*!< Internal interrupt line 23 + Connected to the Comparator 2 + event*/ +#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25 + Connected to the Comparator 3 + event */ +#define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26 + Connected to the Comparator 4 + event*/ +#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27 + Connected to the Comparator 5 + event */ +#define EXTI_Line28 ((uint32_t)0x10000000) /*!< Internal interrupt line 31 + Connected to the Comparator 6 + event */ +#define EXTI_Line29 ((uint32_t)0x20000000) /*!< Internal interrupt line 31 + Connected to the LPTIM wakeup + event */ +#define EXTI_Line30 ((uint32_t)0x40000000) /*!< Internal interrupt line 31 + Connected to the LPUART wakeup + event */ + +#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ + ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ + ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ + ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ + ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ + ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ + ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ + ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ + ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ + ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ + ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ + ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \ + ((LINE) == EXTI_Line24) || ((LINE) == EXTI_Line25) || \ + ((LINE) == EXTI_Line26) || ((LINE) == EXTI_Line27) || \ + ((LINE) == EXTI_Line28) || ((LINE) == EXTI_Line29) || \ + ((LINE) == EXTI_Line30)) + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the EXTI configuration to the default reset state *****/ +void EXTI_DeInit(void); + +/* Initialization and Configuration functions *********************************/ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); + +/* Interrupts and flags management functions **********************************/ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_EXTI_H */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_fdcan.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_fdcan.h new file mode 100644 index 00000000000..62f6584cf18 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_fdcan.h @@ -0,0 +1,816 @@ +/** + ****************************************************************************** + * @file ft32f4xx_fdcan.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the FDCAN firmware + * library. + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_FDCAN_H +#define __FT32F4XX_FDCAN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup FDCAN + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief FDCAN Init structure definition + */ +typedef struct +{ + + uint32_t Mode; /*!< Specifies the FDCAN mode. + This parameter can be a value of @ref FDCAN_operating_mode */ + + uint32_t FrameFormat; /*!< Specifies the FDCAN frame format. + This parameter can be a value of @ref FDCAN_frame_format + Be used config CAN_F_SEG_UNIT_SET register */ + + FunctionalState AutoPrimaryRetransmission; /*!< Enable or disable the automatic retransmission mode for PTB. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState AutoSecondaryRetransmission; /*!< Enable or disable the automatic retransmission mode for STB. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState TTCANMode; /*!< Enable or disable the Time Trigger CAN. + This parameter can be set to ENABLE or DISABLE*/ + + uint32_t FDCANSACK; /*!< Specifies the Self-ACKnowledge in External LoopBack mode. + This parameter can be a value of @ref FDCAN_SACK */ + + uint32_t ReceiveBufferStoreAllFrames; /*!< Specifies the receive buffer stores all frames or normal frames. + This parameter can be a value of @FDCAN_ReceiveBufferStoreAllFrames */ + + uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the nominal bit time quanta. + This parameter must be a number between 1 and 255 */ + + uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a bit to perform + resynchronization. + This parameter must be a number between 2 and 127 */ + + uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1. + This parameter must be a number between 3 and 255 */ + + uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2. + This parameter must be a number between 2 and 127 */ + + uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is + divided for generating the data bit time quanta. + This parameter must be a number between 1 and 255 */ + + uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN + hardware is allowed to lengthen or shorten a data bit to + perform resynchronization. + This parameter must be a number between 2 and 15 */ + + uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1. + This parameter must be a number between 3 and 31 */ + + uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2. + This parameter must be a number between 2 and 15 */ + + uint32_t TimeTriggerPrescaler; /*!< Specifies the value by which bit time is divided for + time trigger timer. + This parameter can be a value of @ref Time_Trigger_Prescaler */ + + uint32_t TriggerTime; /*!< Specifies the cycle time for a trigger. + This paramter must be a value between 0 and 255 */ + + uint32_t TransmitEnableWindow; /*!< Specifies the ticks of transmit enable window. + This paramter must be a value between 0 and 15 */ + + uint32_t TimeTriggerType; /*!< Specifies the kind of trigger in Time Trigger mode. + This paramter can be a value of @ref FDCAN_Trigger_Type */ + + uint32_t TransmitTriggerTbSolt; /*!< Specifies the TTPTR */ + + uint32_t WatchTriggerTime; /*!< Specifies the cycle time for a watch trigger. + This paramter must be a value between 0 and 255 */ + +} FDCAN_InitTypeDef; + + +/** + * @brief FDCAN filter structure definition + */ +typedef struct +{ + uint32_t FilterAddress; /*!< Specifies the filter which will be initialized. + This parameter must be a number between: + - 0 and 15 */ + + FunctionalState SelectAcceptanceMask; /*!< Enable or disable the filter mask. + This parameter can be set to ENABLE or DISABLE */ + + uint32_t FilterAcceptanceCODE; /*!< Specifies the filter identification. + This parameter must be a number between: + - 0 and 0x7FF for standard frames + - 0 and 0x1FFFFFFF for extended frames */ + + uint32_t FilterAcceptanceMASK; /*!< Specifies the filter acceptance mask. + 1 : acceptance check for these bis of receive ID disable + 0 : acceptance check for these bis of receive ID enable + This parameter must be a number between: + - 0 and 0x7FF for standard frames + - 0 and 0x1FFFFFFF for extended frames */ + + uint32_t FilterAcceptanceMaskIDECheck; /*!< Specifies the filter acceptance mask IDE bit check enable. + This parameter can be a value of @Acceptance_Mask_IDE_Check_Enable */ + + uint32_t FilterAcceptanceMaskIDE; /*!< Specifies the filter acceptance mask IDE bit value. + This parameter can be a value of @Acceptance_Mask_IDE_Type, + only valid if FilterAcceptanceMaskIDECheck is enable. */ + +} FDCAN_FilterTypeDef; + + + +/** + * @brief FDCAN Tx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type for the transmitted message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the length of the transmitted frame. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + uint32_t TTSEN; /*!< Specifies the enable if transmit Time-Stamp in CiA 603. + This patameter can be a value of @ref Transmit_Time_Stamp_Enable */ + +} FDCAN_TxHeaderTypeDef; + +/** + * @brief FDCAN Rx header structure definition + */ +typedef struct +{ + uint32_t Identifier; /*!< Specifies the identifier. + This parameter must be a number between: + - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */ + + uint32_t IdType; /*!< Specifies the identifier type of the received message. + This parameter can be a value of @ref FDCAN_id_type */ + + uint32_t RxFrameType; /*!< Specifies the the received message frame type. + This parameter can be a value of @ref FDCAN_frame_type */ + + uint32_t DataLength; /*!< Specifies the received frame length. + This parameter can be a value of @ref FDCAN_data_length_code */ + + uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator. + This parameter can be a value of @ref FDCAN_error_state_indicator */ + + uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit + rate switching. + This parameter can be a value of @ref FDCAN_bit_rate_switching */ + + uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD + format. + This parameter can be a value of @ref FDCAN_format */ + + + uint32_t RxKOER; /*!< Specifies the kind of ERROR of receive frames. + This parameter can be a value of @ref FDCAN_Error_Kind */ + + uint32_t CycleTime; /*!< Specifies the time-stamp cycle time only in TTCAN mode. + This parameter must be a number between 0 and 0xFFFF */ + +} FDCAN_RxHeaderTypeDef; + +/** + * @brief FDCAN Error and Arbitration structure definition + */ +typedef struct +{ + uint32_t ArbitrationLostCapture; /*!< Specifies the bit position in the frame where the arbitration + has been lost. + This parameter must be a number between 0 and 31 */ + +} FDCAN_ArbitrationLostCaptureTypeDef; + +/** + * @brief FDCAN Error Counters structure definition + */ +typedef struct +{ + uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value. + This parameter can be a number between 0 and 255 */ + + uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value. + This parameter can be a number between 0 and 255 */ + + uint32_t KOER; /*!< Specifies the kind of Error. + This parameter can be a value of @ref FDCAN_Error_Kind */ + +} FDCAN_ErrorCountersTypeDef; + +#define Empty ((uint32_t)0x00000000U) +#define Less_HalfFull ((uint32_t)0x00000001U) +#define More_HalfFull ((uint32_t)0x00000002U) +#define Full ((uint32_t)0x00000003U) + +#define CAN_INT_FLAG1_MASK ((uint32_t)0xFFEA00FFU) + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FDCAN_operating_mode + * @{ + */ +#define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */ +#define FDCAN_MODE_LOM ((uint32_t)0x00004000U) /*!< Listen Only mode */ +#define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000020U) /*!< Internal LoopBack mode */ +#define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000040U) /*!< External LoopBack mode */ +/** + * @} + */ + +/** @defgroup FDCAN_frame_format + * @{ + */ +#define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */ +#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)0x00000001U) /*!< FD mode without BitRate Switching */ +#define FDCAN_FRAME_FD_BRS ((uint32_t)0x00000002U) /*!< FD mode with BitRate Switching */ +/** + * @} + */ + + +/** @defgroup TBUF_select + * @{ + */ +#define FDCAN_SELECT_PTB ((uint32_t)0x00000000U) /*!< Select PTB */ +#define FDCAN_SELECT_STB ((uint32_t)CAN_CMD_CTRL_TBSEL) /*!< Select STB */ +/** + * @} + */ + +/** @defgroup FDCAN_STBFifoPriority_Mode + * @{ + */ +#define FDCAN_STB_FIFO ((uint32_t)0x00000000U) /*!< FIFO mode for STB */ +#define FDCAN_STB_PRIORITY ((uint32_t)CAN_CMD_CTRL_TSMODE) /*!< Priority decision mode for STB */ +/** + * @} + */ + +/** @defgroup FDCAN_STBTransmitOneAll_Mode + * @{ + */ +#define FDCAN_STB_NO_TRANSMIT ((uint32_t)0x00000000U) /*!< No transmission for the STB */ +#define FDCAN_STB_NO_TRANSMIT_ONE ((uint32_t)CAN_CMD_CTRL_TSONE) /*!< Transmisson enable of one in the STB */ +#define FDCAN_STB_NO_TRANSMIT_ALL ((uint32_t)CAN_CMD_CTRL_TSALL) /*!< Transmisson enable of all messages in the STB */ +/** + * @} + */ + +/** @defgroup FDCAN_SACK + * @{ + */ +#define FDCAN_NO_SACK ((uint32_t)0x00000000U) /*!< No self-ACK */ +#define FDCAN_SACK ((uint32_t)CAN_CMD_CTRL_SACK) /*!< Self-ACK when LBME=1(External LoopBack mode) */ +/** + * @} + */ + +/** @defgroup FDCAN_ReceiveBufferOverflow_Mode + * @{ + */ +#define FDCAN_RECEIVE_OVERFLOW_OVERWRITTEN ((uint32_t)0x00000000U) /*!< The oldest message will be overwritten */ +#define FDCAN_RECEIVE_OVERFLOW_DISCARD ((uint32_t)CAN_CMD_CTRL_ROM) /*!< The new message will not be stored */ +#define IS_RECEIVE_BUFFER_OVERFLOW_MODE(ROM) (((ROM)==FDCAN_RECEIVE_OVERFLOW_OVERWRITTEN) || \ + ((ROM)==FDCAN_RECEIVE_OVERFLOW_DISCARD) ) + + +/** + * @} + */ + +/** @defgroup FDCAN_ReceiveBufferStoreAllFrames + * @{ + */ +#define FDCAN_RBUF_STORE_NORMAL_OPERATION ((uint32_t)0x00000000U) /*!< Receive buffer only store valid data frames */ +#define FDCAN_RBUF_STORE_ALL_DATA_FRAMES ((uint32_t)CAN_CMD_CTRL_RBALL) /*!< Receive buffer store correct data frames as well as data frame with error */ +/** + * @} + */ + + + +/** @defgroup Acceptance_Mask_IDE_Check_Enable + * @{ + */ +#define FDCAN_ACCEP_MASK_AIDE_DISABLE ((uint32_t)0x00000000U) /*!< Acceptance filter accepts frame both standard or extended */ +#define FDCAN_ACCEP_MASK_AIDE_ENABLE ((uint32_t)CAN_ACF_AIDEE) /*!< Acceptance filter accepts frame define by FilterAcceptanceMaskIDE */ +/** + * @} + */ + +/** @defgroup Acceptance_Mask_IDE_Type + * @{ + */ +#define FDCAN_ACCEP_MASK_IDE_STANDARD ((uint32_t)0x00000000U) /*!< Acceptance filter accepts only extended frames */ +#define FDCAN_ACCEP_MASK_IDE_EXTENDED ((uint32_t)CAN_ACF_AIDE) /*!< Acceptance filter accepts only standard frames */ +/** + * @} + */ + +/** @defgroup FDCAN_id_type + * @{ + */ +#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */ +#define FDCAN_EXTENDED_ID ((uint32_t)0x00000080U) /*!< Extended ID element */ +#define IS_FDCAN_IDTYPE(TYPE) (((TYPE)==FDCAN_STANDARD_ID) | \ + ((TYPE)==FDCAN_EXTENDED_ID) ) + +/** + * @} + */ + +/** @defgroup FDCAN_frame_type + * @{ + */ +#define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */ +#define FDCAN_REMOTE_FRAME ((uint32_t)0x00000040U) /*!< Remote frame */ +#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE)==FDCAN_DATA_FRAME) || \ + ((TYPE)==FDCAN_REMOTE_FRAME) ) +/** + * @} + */ + +/** @defgroup FDCAN_data_length_code + * @{ + */ +#define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */ +#define FDCAN_DLC_BYTES_1 ((uint32_t)0x00000001U) /*!< 1 bytes data field */ +#define FDCAN_DLC_BYTES_2 ((uint32_t)0x00000002U) /*!< 2 bytes data field */ +#define FDCAN_DLC_BYTES_3 ((uint32_t)0x00000003U) /*!< 3 bytes data field */ +#define FDCAN_DLC_BYTES_4 ((uint32_t)0x00000004U) /*!< 4 bytes data field */ +#define FDCAN_DLC_BYTES_5 ((uint32_t)0x00000005U) /*!< 5 bytes data field */ +#define FDCAN_DLC_BYTES_6 ((uint32_t)0x00000006U) /*!< 6 bytes data field */ +#define FDCAN_DLC_BYTES_7 ((uint32_t)0x00000007U) /*!< 7 bytes data field */ +#define FDCAN_DLC_BYTES_8 ((uint32_t)0x00000008U) /*!< 8 bytes data field */ +#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00000009U) /*!< 12 bytes data field */ +#define FDCAN_DLC_BYTES_16 ((uint32_t)0x0000000AU) /*!< 16 bytes data field */ +#define FDCAN_DLC_BYTES_20 ((uint32_t)0x0000000BU) /*!< 20 bytes data field */ +#define FDCAN_DLC_BYTES_24 ((uint32_t)0x0000000CU) /*!< 24 bytes data field */ +#define FDCAN_DLC_BYTES_32 ((uint32_t)0x0000000DU) /*!< 32 bytes data field */ +#define FDCAN_DLC_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */ +#define FDCAN_DLC_BYTES_64 ((uint32_t)0x0000000FU) /*!< 64 bytes data field */ +#define IS_FDCAN_DATA_LENGTH(LENGTH) ((LENGTH==FDCAN_DLC_BYTES_0) || (LENGTH == FDCAN_DLC_BYTES_1) || \ + (LENGTH==FDCAN_DLC_BYTES_2) || (LENGTH == FDCAN_DLC_BYTES_3) || \ + (LENGTH==FDCAN_DLC_BYTES_4) || (LENGTH == FDCAN_DLC_BYTES_5) || \ + (LENGTH==FDCAN_DLC_BYTES_6) || (LENGTH == FDCAN_DLC_BYTES_7) || \ + (LENGTH==FDCAN_DLC_BYTES_8) || (LENGTH == FDCAN_DLC_BYTES_12) || \ + (LENGTH==FDCAN_DLC_BYTES_16) || (LENGTH == FDCAN_DLC_BYTES_20) || \ + (LENGTH==FDCAN_DLC_BYTES_24) || (LENGTH == FDCAN_DLC_BYTES_32) || \ + (LENGTH==FDCAN_DLC_BYTES_48) || (LENGTH == FDCAN_DLC_BYTES_64)) +/** + * @} + */ + +/** @defgroup FDCAN_bit_rate_switching + * @{ + */ +#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */ +#define FDCAN_BRS_ON ((uint32_t)0x00000010U) /*!< FDCAN frames transmitted/received with bit rate switching */ +#define IS_FDCAN_BRS(BRS) ((BRS == FDCAN_BRS_OFF) || (BRS == FDCAN_BRS_ON)) +/** + * @} + */ + +/** @defgroup FDCAN_format + * @{ + */ +#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */ +#define FDCAN_FD_CAN ((uint32_t)0x00000020U) /*!< Frame transmitted/received in FDCAN format */ +#define IS_FDCAN_TYPE(TYPE) ((TYPE == FDCAN_CLASSIC_CAN) || (TYPE == FDCAN_FD_CAN)) +/** + * @} + */ + +/** @defgroup Transmit_Time_Stamp_Enable + * @{ + */ +#define FDCAN_TTS_DISABLE ((uint32_t)0x00000000U) /*!< No acquisition of a transmit time stamp for this frame */ +#define FDCAN_TTS_ENABLE ((uint32_t)0x80000000U) /*!< TTS update enabled */ +#define IS_FDCAN_TTS_STATE(STATE) ((STATE ==FDCAN_TTS_DISABLE) || (STATE ==FDCAN_TTS_ENABLE)) +/** + * @} + */ + +/** @defgroup FDCAN_error_state_indicator + * @{ + */ +#define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< CAN node is error active */ +#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< CAN node is error passive */ +#define IS_FDCAN_ERROR_STATE_INDICATOR(STATE) ((STATE == FDCAN_ESI_ACTIVE) || (STATE == FDCAN_ESI_PASSIVE)) +/** + * @} + */ + +/** @defgroup FDCAN_Error_Kind + * @{ + */ +#define FDCAN_NO_ERROR ((uint32_t)0x00000000U) /*!< No error */ +#define FDCAN_BIT_ERROR ((uint32_t)0x00000001U) /*!< Bit error */ +#define FDCAN_FORM_ERROR ((uint32_t)0x00000002U) /*!< Form error */ +#define FDCAN_STUFF_ERROR ((uint32_t)0x00000003U) /*!< Stuff error */ +#define FDCAN_ACK_ERROR ((uint32_t)0x00000004U) /*!< Acknowledgement error */ +#define FDCAN_CRC_ERROR ((uint32_t)0x00000005U) /*!< CRC error */ +#define FDCAN_OTHER_ERROR ((uint32_t)0x00000006U) /*!< Other error */ +#define FDCAN_NOT_USED ((uint32_t)0x00000007U) /*!< Not used */ +/** + * @} + */ + +/** @defgroup Time_Trigger_Prescaler + * @{ + */ +#define FDCAN_TIME_TRIGGER_PRESCALER_1 ((uint32_t)0x00000000U) /*!< No prescaler */ +#define FDCAN_TIME_TRIGGER_PRESCALER_2 ((uint32_t)0x02000000U) /*!< Divide 2 */ +#define FDCAN_TIME_TRIGGER_PRESCALER_4 ((uint32_t)0x04000000U) /*!< Divide 4 */ +#define FDCAN_TIME_TRIGGER_PRESCALER_8 ((uint32_t)0x06000000U) /*!< Divide 8 */ +/** + * @} + */ + +/** @defgroup FDCAN_Trigger_Type + * @{ + */ +#define FDCAN_TTCAN_IMMEDIATE_TRIG ((uint32_t)0x00000000U) /*!< Immediate Trigger */ +#define FDCAN_TTCAN_TIME_TRIG ((uint32_t)0x00000100U) /*!< Time Trigger */ +#define FDCAN_TTCAN_SINGLE_SHOT_TRIG ((uint32_t)0x00000200U) /*!< Single Shot Transmit Trigger */ +#define FDCAN_TTCAN_TRANSMIT_START_TRIG ((uint32_t)0x00000300U) /*!< Transmit start Trigger */ +#define FDCAN_TTCAN_TRANSMIT_STOP_TRIG ((uint32_t)0x00000400U) /*!< Transmit stop Trigger */ +/** + * @} + */ + + + +/** @defgroup + * @{ + */ + +/** + * @} + */ + +/** @defgroup FDCAN_Interrupts + * @{ + */ +#define FDCAN_IT_RECEIVE CAN_INT_FLAG1_RIE /*!< Receive */ +#define FDCAN_IT_RBUF_OVERRUN CAN_INT_FLAG1_ROIE /*!< RBUF overrun */ +#define FDCAN_IT_RBUF_FULL CAN_INT_FLAG1_RFIE /*!< RBUF full */ +#define FDCAN_IT_RB_ALMOST_FULL CAN_INT_FLAG1_RAFIE /*!< RBUF almost full */ +#define FDCAN_IT_TRANSMISSION_PRIMARY CAN_INT_FLAG1_TPIE /*!< Transmission primary successfully */ +#define FDCAN_IT_TRANSMISSION_SECONDARY CAN_INT_FLAG1_TSIE /*!< Transmission secondary successfully */ +#define FDCAN_IT_ERROR CAN_INT_FLAG1_EIE /*!< Error */ +#define FDCAN_IT_ERROR_PASSIVE CAN_INT_FLAG1_EPIE /*!< Node is error passive */ +#define FDCAN_IT_ARBITRATION_LOST CAN_INT_FLAG1_ALIE /*!< Lost arbitration */ +#define FDCAN_IT_BUS_ERROR CAN_INT_FLAG1_BEIE /*!< Bus error */ +#define FDCAN_IT_TIME_TRIGGER CAN_INT_FLAG2_TTIE /*!< Time Trigger */ +#define FDCAN_IT_WATCH_TRIGGER CAN_INT_FLAG2_WTIE /*!< Watch Trigger */ + +/** @defgroup Interrupt_Masks Interrupt masks + * @{ + */ +#define FDCAN_IR_MASK ((uint32_t)0x902A00FEU) /*!< FDCAN interrupts mask */ + +#define FDCAN_TIMESTAMP_SOF ((uint32_t)0x00000000U) +#define FDCAN_TIMESTAMP_EOF ((uint32_t)0x00000200U) +#define IS_FDCAN_TIME_STAMP_LOCATION(LOC) (((LOC) == FDCAN_TIMESTAMP_SOF) || \ + ((LOC) == FDCAN_TIMESTAMP_EOF) ) +#define FDCAN_TIMESTAMP_DISABLE ((uint32_t)0x00000000U) +#define FDCAN_TIMESTAMP_ENABLE ((uint32_t)0x00000100U) + +#define FDCAN_TXDELAY_DISABLE ((uint32_t)0x00000000U) +#define FDCAN_TXDELAY_ENABLE ((uint32_t)0x00008000U) +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup FDCAN_Exported_Functions + * @{ + */ +/* Initialization and Configuration functions *********************************/ + +/** + * @} + */ + + + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup FDCAN_Private_Macros FDCAN Private Macros + * @{ + */ + +#define IS_FDCAN_ALL_INSTANCE(PERIPH) ((PERIPH == FDCAN1) || \ + (PERIPH == FDCAN2) || \ + (PERIPH == FDCAN3) || \ + (PERIPH == FDCAN4)) +#define IS_FDCAN_MODE(MODE) ((MODE == FDCAN_MODE_NORMAL ) || \ + (MODE == FDCAN_MODE_LOM ) || \ + (MODE == FDCAN_MODE_INTERNAL_LOOPBACK) || \ + (MODE == FDCAN_MODE_EXTERNAL_LOOPBACK)) +#define IS_FDCAN_FRAME_FORMAT(FRAME_FORMAT) ((FRAME_FORMAT == FDCAN_FRAME_CLASSIC ) || \ + (FRAME_FORMAT == FDCAN_FRAME_FD_NO_BRS) || \ + (FRAME_FORMAT == FDCAN_FRAME_FD_BRS )) +#define IS_FDCAN_BUF_SEL(TBUF_SEL) ((TBUF_SEL == FDCAN_SELECT_PTB)|| \ + (TBUF_SEL == FDCAN_SELECT_STB)) +#define IS_FDCAN_STB_FP_MODE(STB_FP_MODE) ((STB_FP_MODE == FDCAN_STB_FIFO ) || \ + (STB_FP_MODE == FDCAN_STB_PRIORITY)) +#define IS_FDCAN_STB_OA_MODE(STB_OA_MODE) ((STB_OA_MODE == FDCAN_STB_NO_TRANSMIT ) || \ + (STB_OA_MODE == FDCAN_STB_NO_TRANSMIT_ONE) || \ + (STB_OA_MODE == FDCAN_STB_NO_TRANSMIT_ALL)) +#define IS_FDCAN_TTCAN_TBUF_MODE(TTCAN_TBUF_MODE) ((TTCAN_TBUF_MODE == FDCAN_TTCAN_TRANSMIT_SEPARATE) || \ + (TTCAN_TBUF_MODE == FDCAN_TTCAN_TRANSMIT_FULL )) +#define IS_FDCAN_FDCANSACK(FDCANSACK) ((FDCANSACK == FDCAN_NO_SACK) || \ + (FDCANSACK == FDCAN_SACK )) +#define IS_FDCAN_RBUF_OVERFLOW_MODE(OVERFLOW_MODE) ((OVERFLOW_MODE == FDCAN_RECEIVE_OVERFLOW_OVERWRITTEN) || \ + (OVERFLOW_MODE == FDCAN_RECEIVE_OVERFLOW_DISCARD )) +#define IS_FDCAN_RBUF_STORE_ALL(STORE_ALL) ((STORE_ALL == FDCAN_RBUF_STORE_NORMAL_OPERATION) || \ + (STORE_ALL == FDCAN_RBUF_STORE_ALL_DATA_FRAMES )) +#define IS_FDCAN_RBUF_AF_LIMIT(AF_LIMIT) ((AF_LIMIT >= 0U) && (AF_LIMIT <= 6U)) +#define IS_FDCAN_PROG_ERROR_WARN_LIMIT(ERROR_WARN_LIMIT) ((ERROR_WARN_LIMIT >= 0U) && (ERROR_WARN_LIMIT <= 15U)) +#define IS_FDCAN_NOMINAL_PRESCALER(N_PRESCALER) ((N_PRESCALER >= 0U) && (N_PRESCALER <= 255U)) +#define IS_FDCAN_NOMINAL_SJW(N_SJW) ((N_SJW >= 0U) && (N_SJW <= 127U)) +#define IS_FDCAN_NOMANAL_SEG1(N_SEG1) ((N_SEG1 >= 0U) && (N_SEG1 <= 255U)) +#define IS_FDCAN_NOMANAL_SEG2(N_SEG2) ((N_SEG2 >= 0U) && (N_SEG2 <= 127U)) +#define IS_FDCAN_DATA_PRESCALER(D_PRESCALER) ((D_PRESCALER >= 0U) && (D_PRESCALER <= 255U)) +#define IS_FDCAN_DATA_SJW(D_SJW) ((D_SJW >= 0U) && (D_SJW <= 15U)) +#define IS_FDCAN_DATA_SEG1(D_SEG1) ((D_SEG1 >= 0U) && (D_SEG1 <= 31U)) +#define IS_FDCAN_DATA_SEG2(D_SEG2) ((D_SEG2 >= 0U) && (D_SEG2 <= 15U)) +#define IS_FDCAN_TTCAN_PRESCALER(TTCAN_PRESCALER) ((TTCAN_PRESCALER == FDCAN_TIME_TRIGGER_PRESCALER_1) || \ + (TTCAN_PRESCALER == FDCAN_TIME_TRIGGER_PRESCALER_2) || \ + (TTCAN_PRESCALER == FDCAN_TIME_TRIGGER_PRESCALER_4) || \ + (TTCAN_PRESCALER == FDCAN_TIME_TRIGGER_PRESCALER_8)) +#define IS_FDCAN_TTCAN_REF_IDE(REF_IDE) ((REF_IDE == FDCAN_STANDARD_ID) || \ + (REF_IDE == FDCAN_EXTENDED_ID)) +#define IS_FDCAN_ID(ID) ((ID >= 0x0U) && (ID <= 0x1FFFFFFFU)) +#define IS_FDCAN_TTCAN_REF_ID(REF_ID) ((REF_ID >= 0x0U) && (REF_ID <= 0x1FFFFFFFU)) +#define IS_FDCAN_TTCAN_TBUF_POINTER(TTCAN_TBUF_POINTER) ((TTCAN_TBUF_POINTER >= 0U) && (TTCAN_TBUF_POINTER <= 3U)) +#define IS_FDCAN_TTCAN_TYPE(TTCAN_TYPE) ((TTCAN_TYPE == FDCAN_TTCAN_IMMEDIATE_TRIG ) || \ + (TTCAN_TYPE == FDCAN_TTCAN_TIME_TRIG ) || \ + (TTCAN_TYPE == FDCAN_TTCAN_SINGLE_SHOT_TRIG ) || \ + (TTCAN_TYPE == FDCAN_TTCAN_TRANSMIT_START_TRIG) || \ + (TTCAN_TYPE == FDCAN_TTCAN_TRANSMIT_STOP_TRIG )) +#define IS_FDCAN_TTCAN_TR_EN_WIN(TTCAN_TR_EN_WIN) ((TTCAN_TR_EN_WIN >= 0U) && (TTCAN_TR_EN_WIN <= 15U)) +#define IS_FDCAN_TTCAN_TRIGGER_TIME(TTCAN_TRIGGER_TIME) ((TTCAN_TRIGGER_TIME >= 0U) && (TTCAN_TRIGGER_TIME <= 0XFFFFU)) +#define IS_FDCAN_TTCAN_WATCH_TIME(TTCAN_WATCH_TIME) ((TTCAN_WATCH_TIME >= 0U) && (TTCAN_WATCH_TIME <= 0XFFFFU)) + +#define IS_FDCAN_FILTER_ADDR(ADDR) ((ADDR >= 0U) && (ADDR <= 15U)) +#define IS_FDCAN_FILTER_ACODE(ACODE) ((ACODE >= 0U) && (ACODE <= 0x1FFFFFFFU)) +#define IS_FDCAN_FILTER_AMASK(AMASK) ((AMASK >= 0U) && (AMASK <= 0x1FFFFFFFU)) +#define IS_FDCAN_FILTER_AMASK_IDEE(AMASK_IDEE) ((AMASK_IDEE == FDCAN_ACCEP_MASK_AIDE_DISABLE) || \ + (AMASK_IDEE == FDCAN_ACCEP_MASK_AIDE_ENABLE )) +#define IS_FDCAN_FILTER_AMASK_IDE(AMASK_IDE) ((AMASK_IDE == FDCAN_ACCEP_MASK_IDE_STANDARD) || \ + (AMASK_IDE == FDCAN_ACCEP_MASK_IDE_EXTENDED)) + + +#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK)) == 0U) + +#define IS_FDCAN_TXDELAY_VALUE(VALUE) ((VALUE >= 0U) && (VALUE <= 0x7FU)) + +#define IS_FDCAN_ARBLOSTCAP_VALUE(VALUE) ((VALUE >= 0U) && (VALUE <= 0x1FU)) + +#define FDCAN_FLAG_ROV FDCAN_ISR_ROV +#define FDCAN_FLAG_RACTIVE FDCAN_ISR_RACTIVE +#define FDCAN_FLAG_TACTIVE FDCAN_ISR_TACTIVE +#define FDCAN_FLAG_EPIF CAN_INT_FLAG1_EPIF +#define FDCAN_FLAG_ALIF CAN_INT_FLAG1_ALIF +#define FDCAN_FLAG_BEIF CAN_INT_FLAG1_BEIF +#define FDCAN_FLAG_RIF CAN_INT_FLAG1_RIF +#define FDCAN_FLAG_ROIF CAN_INT_FLAG1_ROIF +#define FDCAN_FLAG_RFIF CAN_INT_FLAG1_RFIF +#define FDCAN_FLAG_RAFIF CAN_INT_FLAG1_RAFIF +#define FDCAN_FLAG_TPIF CAN_INT_FLAG1_TPIF +#define FDCAN_FLAG_TSIF CAN_INT_FLAG1_TSIF +#define FDCAN_FLAG_EIF CAN_INT_FLAG1_EIF +#define FDCAN_FLAG_AIF CAN_INT_FLAG1_AIF +#define FDCAN_FLAG_WTIF CAN_INT_FLAG2_WTIF +#define FDCAN_FLAG_TEIF CAN_INT_FLAG2_TEIF +#define FDCAN_FLAG_TTIF CAN_INT_FLAG2_TTIF +#define FDCAN_FLAG_RTIF_ALL ((uint32_t)0x0000FF00U) +#define IS_FDCAN_FLAG(FLAG) (((FLAG) == FDCAN_FLAG_RACTIVE) || ((FLAG) == FDCAN_FLAG_TACTIVE) || \ + ((FLAG) == FDCAN_FLAG_ROV) || ((FLAG) == FDCAN_FLAG_EPIF) || \ + ((FLAG) == FDCAN_FLAG_ALIF) || ((FLAG) == FDCAN_FLAG_BEIF) || \ + ((FLAG) == FDCAN_FLAG_RIF) || ((FLAG) == FDCAN_FLAG_ROIF) || \ + ((FLAG) == FDCAN_FLAG_RFIF) || ((FLAG) == FDCAN_FLAG_RAFIF) || \ + ((FLAG) == FDCAN_FLAG_TPIF) || ((FLAG) == FDCAN_FLAG_TSIF) || \ + ((FLAG) == FDCAN_FLAG_EIF) || ((FLAG) == FDCAN_FLAG_AIF) || \ + ((FLAG) == FDCAN_FLAG_WTIF) || ((FLAG) == FDCAN_FLAG_TEIF) || \ + ((FLAG) == FDCAN_FLAG_TTIF) || ((FLAG) == FDCAN_FLAG_RTIF_ALL)) + +#define FDCAN_FLAG_REG_CMD ((uint32_t)0x00000000U) +#define FDCAN_FLAG_REG_FLAG1 ((uint32_t)0x00000001U) +#define FDCAN_FLAG_REG_FLAG2 ((uint32_t)0x00000002U) +#define IS_FDCAN_FLAG_REG(REG) (((REG) == FDCAN_FLAG_REG_CMD) || ((REG) == FDCAN_FLAG_REG_FLAG1) || \ + ((REG) == FDCAN_FLAG_REG_FLAG2)) + +#define FDCAN_INT_REG_FLAG1 ((uint32_t)0x00000001U) +#define FDCAN_INT_REG_FLAG2 ((uint32_t)0x00000002U) +#define IS_FDCAN_INT_REG(REG) (((REG) == FDCAN_INT_REG_FLAG1) || ((REG) == FDCAN_INT_REG_FLAG2)) + +#define FDCAN_TRANS_BUFFER_STAT ((uint32_t)0x00000000U) +#define FDCAN_RECEIVE_BUFFER_STAT ((uint32_t)0x00000001U) +#define FDCAN_TBUF_FULL FDCAN_ISR_TSSTAT +#define FDCAN_RBUF_FULL FDCAN_ISR_RSTAT + +#define FDCAN_CAN_FILTER0 CAN_FILTER_CTRL_AE_0 +#define FDCAN_CAN_FILTER1 CAN_FILTER_CTRL_AE_1 +#define FDCAN_CAN_FILTER2 CAN_FILTER_CTRL_AE_2 +#define FDCAN_CAN_FILTER3 CAN_FILTER_CTRL_AE_3 +#define FDCAN_CAN_FILTER4 CAN_FILTER_CTRL_AE_4 +#define FDCAN_CAN_FILTER5 CAN_FILTER_CTRL_AE_5 +#define FDCAN_CAN_FILTER6 CAN_FILTER_CTRL_AE_6 +#define FDCAN_CAN_FILTER7 CAN_FILTER_CTRL_AE_7 +#define FDCAN_CAN_FILTER8 CAN_FILTER_CTRL_AE_8 +#define FDCAN_CAN_FILTER9 CAN_FILTER_CTRL_AE_9 +#define FDCAN_CAN_FILTER10 CAN_FILTER_CTRL_AE_10 +#define FDCAN_CAN_FILTER11 CAN_FILTER_CTRL_AE_11 +#define FDCAN_CAN_FILTER12 CAN_FILTER_CTRL_AE_12 +#define FDCAN_CAN_FILTER13 CAN_FILTER_CTRL_AE_13 +#define FDCAN_CAN_FILTER14 CAN_FILTER_CTRL_AE_14 +#define FDCAN_CAN_FILTER15 CAN_FILTER_CTRL_AE_15 +#define FDCAN_CAN_FILTER_ALL ((uint32_t)0xFFFF0000U) +#define IS_FDCAN_FILTER_ACE(ACE) (((ACE) == FDCAN_CAN_FILTER0) || ((ACE) == FDCAN_CAN_FILTER1) || \ + ((ACE) == FDCAN_CAN_FILTER2) || ((ACE) == FDCAN_CAN_FILTER3) || \ + ((ACE) == FDCAN_CAN_FILTER4) || ((ACE) == FDCAN_CAN_FILTER5) || \ + ((ACE) == FDCAN_CAN_FILTER6) || ((ACE) == FDCAN_CAN_FILTER7) || \ + ((ACE) == FDCAN_CAN_FILTER8) || ((ACE) == FDCAN_CAN_FILTER9) || \ + ((ACE) == FDCAN_CAN_FILTER10) || ((ACE) == FDCAN_CAN_FILTER11) || \ + ((ACE) == FDCAN_CAN_FILTER12) || ((ACE) == FDCAN_CAN_FILTER13) || \ + ((ACE) == FDCAN_CAN_FILTER14) || ((ACE) == FDCAN_CAN_FILTER15) || \ + ((ACE) == FDCAN_CAN_FILTER_ALL)) + +/** @defgroup FDCAN_REF_MSG_id_type + * @{ + */ +#define FDCAN_REF_MSG_STD ((uint32_t)0x00000000U) /*!< Standard ID element */ +#define FDCAN_REF_MSG_EXT ((uint32_t)0x80000000U) /*!< Extended ID element */ +#define IS_FDCAN_REF_MSG_IDTYPE(TYPE) (((TYPE)==FDCAN_REF_MSG_STD) | \ + ((TYPE)==FDCAN_REF_MSG_EXT) ) + +#define IS_FDCAN_REF_MSG_ID_VALUE(VALUE) ((VALUE >= 0U) && (VALUE <= 0x1FFFFFFFU)) + +#define IS_FDCAN_TBPTR_VALUE(VALUE) ((VALUE >= 0U) && (VALUE <= 0x3FU)) +#define IS_FDCAN_TTPTR_VALUE(VALUE) ((VALUE >= 0U) && (VALUE <= 0x3FU)) + +#define FDCAN_TIMEPOS_SOF ((uint32_t)0x00000000U) /*!< TIME STAMP POSITION IN SOF */ +#define FDCAN_TIMEPOS_EOF ((uint32_t)0x00000200U) /*!< TIME STAMP POSITION IN EOF */ +#define IS_FDCAN_TIME_POS(POS) (((POS)==FDCAN_TIMEPOS_SOF) | \ + ((POS)==FDCAN_TIMEPOS_EOF) ) + + + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------------- */ +/** @addtogroup FDCAN_Exported_Functions + * @{ + */ + +/** @addtogroup FDCAN_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *************************************/ +void FDCAN_Init(FDCAN_TypeDef* fdcan, FDCAN_InitTypeDef* fdcanInit);/*Function used initial fdcan*/ +void FDCAN_DeInit(FDCAN_TypeDef* fdcan);/*Function used de-initial fdcan*/ +void FDCAN_Reset(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used set fdcan in reset*/ +void FDCAN_ConfigMode(FDCAN_TypeDef* fdcan, uint32_t Mode);/*Function used config fdcan mode*/ +void FDCAN_SetRxBufAFWL(FDCAN_TypeDef* fdcan, uint32_t ReceiveBufferAlmostFullWarningLimit);/*Function used set fdcan AFWL*/ +void FDCAN_SetEWL(FDCAN_TypeDef* fdcan, uint32_t ProgrammableErrorWarningLimit);/*Function used set fdcan EWL*/ +void FDCAN_TransBufferSelect(FDCAN_TypeDef* fdcan, uint32_t TransBufferSelect);/*Function used select trans buffer*/ +void FDCAN_TTCANTransBufferMode(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used select TTCAN Trans buffer Mode*/ +void FDCAN_PTBTrans(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used start ptb trans*/ +void FDCAN_PTBAbort(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used abort ptb trans*/ +void FDCAN_TransSTBMode(FDCAN_TypeDef* fdcan, uint32_t STBFifoPriorityMode);/*Function used config tsmode*/ +void FDCAN_STBTrans(FDCAN_TypeDef* fdcan, uint32_t STBTransmitOneAllMode, FunctionalState NewState);/*Function used start stb trans*/ +void FDCAN_STBAbort(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used abort stb trans*/ +uint8_t FDCAN_GetArbLostPosition(FDCAN_TypeDef* fdcan);/* Function use get arbitration lost position */ +uint8_t FDCAN_GetKindOfError(FDCAN_TypeDef* fdcan);/* Function use get Kind Of Error */ +void FDCAN_RxBufRelease(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used Release RxBuffer*/ +void FDCAN_StandbyMode(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used enable can standby*/ +void FDCAN_RbufOverFlowMode(FDCAN_TypeDef* fdcan, uint32_t FDCAN_ReceiveBufferOverflow_Mode);/*Function used config ROM*/ + + + +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group2 + * @{ + */ +/* Configuration functions *************************************/ +void FDCAN_ConfigFilter(FDCAN_TypeDef* fdcan, FDCAN_FilterTypeDef* sFilterConfig);/*Function used config filter*/ +void FDCAN_EnableFilter(FDCAN_TypeDef* fdcan, uint32_t FDCAN_ACE, FunctionalState NewState);/*Function used enable or disable filter*/ +void FDCAN_ConfigRxFifoOverwrite(FDCAN_TypeDef* fdcan, uint32_t FdcanRbOverMode);/*Function used config Receive Buffer write mode while full*/ +void FDCAN_ConfigTimestampLocation(FDCAN_TypeDef* fdcan, uint32_t FdcanTimeStampLocation);/*Function used config timestamp Location*/ +void FDCAN_EnableTimestampCounter(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used enable Fdcan timestamp*/ +void FDCAN_ConfigTxDelayCompensation(FDCAN_TypeDef* fdcan, uint32_t FdcanTxDelayValue);/*Function used config TxDelay value */ +void FDCAN_EnableTxDelayCompensation(FDCAN_TypeDef* fdcan, FunctionalState NewState);/*Function used enable Fdcan TxDelay */ +void FDCAN_EnableISOMode(FDCAN_TypeDef* fdcan);/* Function used select ISO_CAN mode */ +void FDCAN_DisableISOMode(FDCAN_TypeDef* fdcan);/* Function used select BoShi CAN_FD mode */ +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group3 + * @{ + */ +/* Configuration TxBuffer And Get RxBuffer *************************************/ +void FDCAN_ConfigTxBuffer(FDCAN_TypeDef* fdcan, FDCAN_TxHeaderTypeDef* TxHeader, uint8_t message_data[16][4]);/* Function used config TxBuffer */ +void FDCAN_GetRxBuffer(FDCAN_TypeDef* fdcan, FDCAN_RxHeaderTypeDef* RxHeader, uint8_t message_data[16][4]);/* Function used get RxBuffer */ +void FDCAN_GetArbLostCap(FDCAN_TypeDef* fdcan, FDCAN_ArbitrationLostCaptureTypeDef* ArbLostCap);/* Function used get ALC */ +void FDCAN_GetErrorCnt(FDCAN_TypeDef* fdcan, FDCAN_ErrorCountersTypeDef* ErrorCnt);/* Function used get TECNT, RECNT and KOER */ +void FDCAN_ConfigTsnext(FDCAN_TypeDef* fdcan);/* Function used set tsnext=1 and wait auto clear by hardware */ +void FDCAN_ConfigInitialOffset(FDCAN_TypeDef* fdcan);/* Function used set initial offset value */ +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group4 + * @{ + */ +/* Interrupts management *************************************/ +void FDCAN_ActivateNotification(FDCAN_TypeDef* fdcan, uint32_t FDCAN_INT_REG, uint32_t ActiveITs);/* Function used enable interrupt */ +void FDCAN_DeactivateNotification(FDCAN_TypeDef* fdcan, uint32_t FDCAN_INT_REG, uint32_t InactiveITs);/* Function used disable interrupt */ +FlagStatus FDCAN_GetFlagStatus(FDCAN_TypeDef* fdcan, uint32_t FDCAN_FLAG_REG, uint32_t FDCAN_FLAG);/* Function used get flag */ +void FDCAN_ClearInterruptFlag(FDCAN_TypeDef* fdcan, uint32_t FDCAN_FLAG_REG, uint32_t FDCAN_FLAG);/* Function used clear interrupt flag */ +int FDCAN_GetFifoStatus(FDCAN_TypeDef* fdcan, uint32_t FDCAN_BUF_TYPE);/* Function used get tbuf and rbuf status */ +/** + * @} + */ + +/** @addtogroup FDCAN_Exported_Functions_Group5 + * @{ + */ +/* TTCAN management *************************************/ +void FDCAN_RefMessageSet(FDCAN_TypeDef* fdcan, uint32_t FDCAN_REF_MSG_IDE, uint32_t FDCAN_REF_MSG_ID);/* Function used config reference message */ +void FDCAN_TbufSoltPoint(FDCAN_TypeDef* fdcan, uint32_t FDCAN_TBPTR);/* Function used config TBPTR */ +void FDCAN_TransmitSoltPoint(FDCAN_TypeDef* fdcan, uint32_t FDCAN_TTPTR);/* Function used config TTPTR */ +void FDCAN_SetTbufSoltEmpty(FDCAN_TypeDef* fdcan, FunctionalState NewState);/* Function used config TBPTR choose's solt empty*/ +void FDCAN_SetTbufSoltFull(FDCAN_TypeDef* fdcan, FunctionalState NewState);/* Function used config TBPTR choose's solt full*/ +void FDCAN_TimeTrigEnable(FDCAN_TypeDef* fdcan, FunctionalState NewState);/* Function used enbale tten*/ +void FDCAN_TimeStampPosition(FDCAN_TypeDef* fdcan, uint32_t FDCAN_TIMEPOS);/* Function used set timepos*/ +void FDCAN_TimeStampEnable(FDCAN_TypeDef* fdcan, FunctionalState NewState);/* Function used enbale timepos*/ +void FDCAN_GetCanTransmisionTs(FDCAN_TypeDef* fdcan, uint32_t can_transmission_ts[2]);/* Function used get transmision ts */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_FDCAN_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_flash.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_flash.h new file mode 100644 index 00000000000..e9683459ada --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_flash.h @@ -0,0 +1,371 @@ +/** + ****************************************************************************** + * @file ft32f4xx_flash.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the FLASH + * firmware library. + * @version V1.0.0 + * @data 2025-03-13 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_FLASH_H +#define __FT32F4XX_FLASH_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +#define FLASH_KEY1 0x45670123 +#define FLASH_KEY2 0xCDEF89AB + +#define FLASH_OPTKEY1 0x08192A3B +#define FLASH_OPTKEY2 0x4C5D6E7F + +#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS))) +#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS))) +#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS))) +/** @addtogroup FLASH + * @{ + */ +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief FLASH Status + */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_WRP, //write portect error + FLASH_ERROR_PROGRAM, //program error + FLASH_ERROR_PGSERR, //program sequence error + FLASH_COMPLETE, //FLASH idle status + FLASH_TIMEOUT +} FLASH_Status; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup FLASH_Exported_Constants + * @{ + */ + +/** @defgroup FLASH_Latency + * @{ + */ +#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */ +#define FLASH_Latency_1 ((uint32_t)0x00000001) /*!< FLASH One Latency cycle */ +#define FLASH_Latency_2 ((uint32_t)0x00000002) +#define FLASH_Latency_3 ((uint32_t)0x00000003) +#define FLASH_Latency_4 ((uint32_t)0x00000004) +#define FLASH_Latency_5 ((uint32_t)0x00000005) +#define FLASH_Latency_6 ((uint32_t)0x00000006) +#define FLASH_Latency_7 ((uint32_t)0x00000007)//max latency value +/* Other latency value (8-15) not be used*/ +#define FLASH_Latency_8 ((uint32_t)0x00000008) +#define FLASH_Latency_9 ((uint32_t)0x00000009) +#define FLASH_Latency_10 ((uint32_t)0x0000000a) +#define FLASH_Latency_11 ((uint32_t)0x0000000b) +#define FLASH_Latency_12 ((uint32_t)0x0000000c) +#define FLASH_Latency_13 ((uint32_t)0x0000000d) +#define FLASH_Latency_14 ((uint32_t)0x0000000e) +#define FLASH_Latency_15 ((uint32_t)0x0000000f) + +#define IS_FLASH_LATENCY(LATENCY) ( \ + ((LATENCY) == FLASH_Latency_0) || \ + ((LATENCY) == FLASH_Latency_1) || \ + ((LATENCY) == FLASH_Latency_2 ) || \ + ((LATENCY) == FLASH_Latency_3 ) || \ + ((LATENCY) == FLASH_Latency_4 ) || \ + ((LATENCY) == FLASH_Latency_5 ) || \ + ((LATENCY) == FLASH_Latency_6 ) || \ + ((LATENCY) == FLASH_Latency_7 ) || \ + ((LATENCY) == FLASH_Latency_8 ) || \ + ((LATENCY) == FLASH_Latency_9 ) || \ + ((LATENCY) == FLASH_Latency_10) || \ + ((LATENCY) == FLASH_Latency_11) || \ + ((LATENCY) == FLASH_Latency_12) || \ + ((LATENCY) == FLASH_Latency_13) || \ + ((LATENCY) == FLASH_Latency_14) || \ + ((LATENCY) == FLASH_Latency_15)) +/** + * @} + */ + +/** @defgroup FLASH_Interrupts + * @{ + */ +#define FLASH_IT_EOP FLASH_WRC_EOPIE /*!< End of programming interrupt source */ +#define FLASH_IT_ERR FLASH_WRC_ERRIE /*!< Error interrupt source */ +//#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFF3FFFF) == 0x00000000) && (((IT) != 0x00000000))) +#define IS_FLASH_IT(IT) (((IT) == FLASH_IT_EOP) ||\ + ((IT) == FLASH_IT_ERR)) + +/** @defgroup FLASH_FR clear bit + * @{ + */ +#define FLASH_FR_CLEAR ((uint32_t) 0x0000003F) + +/** @defgroup FLASH_Address + * @{ + */ +//#if defined(FT32F4xx) /*512K devices */ +#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0807FFFF)) + +/** @defgroup FLASH_PAGE_number + * @{ + */ +//#if defined(FT32F4xx) /*1023 page */ +#define IS_FLASH_ERASE_PAGE_NUM(PAGE_NUM) (((PAGE_NUM) >= 0x00000000) && ((PAGE_NUM) <= 0x000003FF)) + +/** @defgroup FLASH_Option_Bytes_Write_Protection + * @{ + */ +#define ERASE_SIZE_0 FLASH_WRC_ESIZE//((uint32_t)0x00000000) /* Erase size:512B */ +#define ERASE_SIZE_1 FLASH_WRC_ESIZE_0//((uint32_t)0x00000010) /* Erase size:2KB */ +#define ERASE_SIZE_2 FLASH_WRC_ESIZE_1//((uint32_t)0x00000020) /* Erase size:16KB */ +#define IS_ERASE_SIZE(SIZE) (((SIZE) == ERASE_SIZE_0 ) ||\ + ((SIZE) == ERASE_SIZE_1 ) || \ + ((SIZE) == ERASE_SIZE_2 )) + + +/** @defgroup FLASH_Option_Bytes_Write_Protection + * @{ + */ +#define WRP_PAGE0_31 ((uint32_t)0xfffffffe) /* Write protection of page 0_31 */ +#define WRP_PAGE32_63 ((uint32_t)0xfffffffd) /* Write protection of page 32_63 */ +#define WRP_PAGE64_95 ((uint32_t)0xfffffffb) /* Write protection of page 64_95 */ +#define WRP_PAGE96_127 ((uint32_t)0xfffffff7) /* Write protection of page 96_127 */ +#define WRP_PAGE128_159 ((uint32_t)0xffffffef) /* Write protection of page 128_159 */ +#define WRP_PAGE160_191 ((uint32_t)0xffffffdf) /* Write protection of page 160_191 */ +#define WRP_PAGE192_223 ((uint32_t)0xffffffbf) /* Write protection of page 192_223 */ +#define WRP_PAGE224_255 ((uint32_t)0xffffff7f) /* Write protection of page 224_255 */ +#define WRP_PAGE256_287 ((uint32_t)0xfffffeff) /* Write protection of page 256_287 */ +#define WRP_PAGE288_319 ((uint32_t)0xfffffdff) /* Write protection of page 288_319 */ +#define WRP_PAGE320_351 ((uint32_t)0xfffffbff) /* Write protection of page 320_351 */ +#define WRP_PAGE352_383 ((uint32_t)0xfffff7ff) /* Write protection of page 352_383 */ +#define WRP_PAGE384_415 ((uint32_t)0xffffefff) /* Write protection of page 384_415 */ +#define WRP_PAGE416_447 ((uint32_t)0xffffdfff) /* Write protection of page 416_447 */ +#define WRP_PAGE448_479 ((uint32_t)0xffffbfff) /* Write protection of page 448_479 */ +#define WRP_PAGE480_511 ((uint32_t)0xffff7fff) /* Write protection of page 480_511 */ +#define WRP_PAGE512_543 ((uint32_t)0xfffeffff) /* Write protection of page 512_543 */ +#define WRP_PAGE544_575 ((uint32_t)0xfffdffff) /* Write protection of page 544_575 */ +#define WRP_PAGE576_607 ((uint32_t)0xfffbffff) /* Write protection of page 576_607 */ +#define WRP_PAGE608_639 ((uint32_t)0xfff7ffff) /* Write protection of page 608_639 */ +#define WRP_PAGE640_671 ((uint32_t)0xffefffff) /* Write protection of page 640_671 */ +#define WRP_PAGE672_703 ((uint32_t)0xffdfffff) /* Write protection of page 672_703 */ +#define WRP_PAGE704_735 ((uint32_t)0xffbfffff) /* Write protection of page 704_735 */ +#define WRP_PAGE736_767 ((uint32_t)0xff7fffff) /* Write protection of page 736_767 */ +#define WRP_PAGE768_799 ((uint32_t)0xfeffffff) /* Write protection of page 768_799 */ +#define WRP_PAGE800_831 ((uint32_t)0xfdffffff) /* Write protection of page 800_831 */ +#define WRP_PAGE832_863 ((uint32_t)0xfbffffff) /* Write protection of page 832_863 */ +#define WRP_PAGE864_895 ((uint32_t)0xf7ffffff) /* Write protection of page 864_895 */ +#define WRP_PAGE896_927 ((uint32_t)0xefffffff) /* Write protection of page 896_927 */ +#define WRP_PAGE928_959 ((uint32_t)0xdfffffff) /* Write protection of page 928_959 */ +#define WRP_PAGE960_991 ((uint32_t)0xbfffffff) /* Write protection of page 960_991 */ +#define WRP_PAGE992_1023 ((uint32_t)0x7fffffff) /* Write protection of page 992_1023*/ + +#define WRP_ALLPAGES ((uint32_t)0x00000000) /* Write protection of page 0_1023*/ + +#define IS_WRPR_WRP(PAGE) (((PAGE) == WRP_PAGE0_31 ) ||\ + ((PAGE) ==WRP_PAGE32_63 ) || \ + ((PAGE) ==WRP_PAGE64_95 ) || \ + ((PAGE) ==WRP_PAGE96_127 ) || \ + ((PAGE) ==WRP_PAGE128_159 ) || \ + ((PAGE) ==WRP_PAGE160_191 ) || \ + ((PAGE) ==WRP_PAGE192_223 ) || \ + ((PAGE) ==WRP_PAGE224_255 ) || \ + ((PAGE) ==WRP_PAGE256_287 ) || \ + ((PAGE) ==WRP_PAGE288_319 ) || \ + ((PAGE) ==WRP_PAGE320_351 ) || \ + ((PAGE) ==WRP_PAGE352_383 ) || \ + ((PAGE) ==WRP_PAGE384_415 ) || \ + ((PAGE) ==WRP_PAGE416_447 ) || \ + ((PAGE) ==WRP_PAGE448_479 ) || \ + ((PAGE) ==WRP_PAGE480_511 ) || \ + ((PAGE) ==WRP_PAGE512_543 ) || \ + ((PAGE) ==WRP_PAGE544_575 ) || \ + ((PAGE) ==WRP_PAGE576_607 ) || \ + ((PAGE) ==WRP_PAGE608_639 ) || \ + ((PAGE) ==WRP_PAGE640_671 ) || \ + ((PAGE) ==WRP_PAGE672_703 ) || \ + ((PAGE) ==WRP_PAGE704_735 ) || \ + ((PAGE) ==WRP_PAGE736_767 ) || \ + ((PAGE) ==WRP_PAGE768_799 ) || \ + ((PAGE) ==WRP_PAGE800_831 ) || \ + ((PAGE) ==WRP_PAGE832_863 ) || \ + ((PAGE) ==WRP_PAGE864_895 ) || \ + ((PAGE) ==WRP_PAGE896_927 ) || \ + ((PAGE) ==WRP_PAGE928_959 ) || \ + ((PAGE) ==WRP_PAGE960_991 ) || \ + ((PAGE) ==WRP_PAGE992_1023 ) || \ + ((PAGE) ==WRP_ALLPAGES )) + +/** @defgroup FLASH_Option_Bytes_Read_Protection + * @{ + */ + +/** + * @brief FLASH_Read Protection Level + */ +#define OPBC_RDP_Level_0 ((uint8_t)0xaa) +#define OPBC_RDP_Level_1 ((uint8_t)0xbb) //except "AA" or "CC" +/*!!! Be CAREFUL to USE OPBC_RDP_Level_2!!!*/ +#define OPBC_RDP_Level_2 ((uint8_t)0xcc) //Warning: When enabling read protection level 2 +//it's no more possible to go back to level 1 or 0 +#define IS_OPBC_RDP(LEVEL) (((LEVEL) == OPBC_RDP_Level_0)|| \ + ((LEVEL) == OPBC_RDP_Level_1)|| \ + ((LEVEL) == OPBC_RDP_Level_2)) +/** + * @} + */ +/** @defgroup FLASH_Option_Bytes_IWatchdog + * @{ + */ +#define OPBC_IWDG_SW ((uint8_t)0x20) /*!< Software IWDG selected */ +#define OPBC_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */ +#define IS_OPBC_IWDG_SOURCE(SOURCE) (((SOURCE) == OPBC_IWDG_SW) || ((SOURCE) == OPBC_IWDG_HW)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STOP + * @{ + */ + +#define OPBC_STOP_NoRST ((uint8_t)0x40) /*!< No Reset generated when entering in STOP */ +#define OPBC_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP Automaticly*/ +#define IS_OPBC_STOP_SOURCE(SOURCE) (((SOURCE) == OPBC_STOP_NoRST) || ((SOURCE) == OPBC_STOP_RST)) + +/** + * @} + */ + +/** @defgroup FLASH_Option_Bytes_nRST_STDBY + * @{ + */ + +#define OPBC_STDBY_NoRST ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */ +#define OPBC_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY Automaticly*/ +#define IS_OPBC_STDBY_SOURCE(SOURCE) (((SOURCE) == OPBC_STDBY_NoRST) || ((SOURCE) == OPBC_STDBY_RST)) + + + +/** @defgroup FLASH_Flags + * @{ + */ +#define FLASH_FLAG_BSY FLASH_FR_BSY /*!< FLASH Busy flag */ +#define FLASH_FLAG_PGERR FLASH_FR_PGERR /*!< FLASH Programming error flag */ +#define FLASH_FLAG_PGSERR FLASH_FR_PGSERR /*!< FLASH Programming sequence error flag */ +#define FLASH_FLAG_WRPERR FLASH_FR_WRPRTERR /*!< FLASH Write protected error flag */ +#define FLASH_FLAG_EOP FLASH_FR_EOP /*!< FLASH End of Programming flag */ +#define FLASH_FLAG_OPBERR FLASH_FR_OPBERR /*!< user option and factory are not load correctly flag */ + +#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFC1) == 0x00000000) && ((FLAG) != 0x00000000)) + +#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \ + ((FLAG) == FLASH_FLAG_PGSERR) || ((FLAG) == FLASH_FLAG_WRPERR) || \ + ((FLAG) == FLASH_FLAG_EOP ) || ((FLAG) == FLASH_FLAG_OPBERR)) + +/** @defgroup FLASH_Timeout_definition + * @{ + */ +#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000) //TIM value is user define + + +/** @defgroup BORR_Level + * @{ + */ +#define OPBC_BORR_LEVEL0 ((uint32_t)0x00000000) +#define OPBC_BORR_LEVEL1 ((uint32_t)0x00080000) +#define OPBC_BORR_LEVEL2 ((uint32_t)0x00100000) +#define OPBC_BORR_LEVEL3 ((uint32_t)0x00180000) + +#define IS_OPBC_BORR_LEVEL(Level) (((Level) ==OPBC_BORR_LEVEL0)||\ + ((Level) == OPBC_BORR_LEVEL1)||\ + ((Level) == OPBC_BORR_LEVEL2)||\ + ((Level) == OPBC_BORR_LEVEL3)) + +/** @defgroup BORF_Level + * @{ + */ +#define OPBC_BORF_LEVEL0 ((uint32_t)0x00000000) +#define OPBC_BORF_LEVEL1 ((uint32_t)0x00020000) +#define OPBC_BORF_LEVEL2 ((uint32_t)0x00040000) +#define OPBC_BORF_LEVEL3 ((uint32_t)0x00060000) + +#define IS_OPBC_BORF_LEVEL(Level) (((Level) ==OPBC_BORF_LEVEL0)||\ + ((Level) == OPBC_BORF_LEVEL1)||\ + ((Level) == OPBC_BORF_LEVEL2)||\ + ((Level) == OPBC_BORF_LEVEL3)) + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/** + * @brief FLASH memory functions that can be executed from FLASH. + */ +/* FLASH Interface configuration functions ************************************/ +void FLASH_SetLatency(uint32_t FLASH_Latency); +void FLASH_PrefetchBufferCmd(FunctionalState NewState); +FlagStatus FLASH_GetPrefetchBufferStatus(void); + +/* FLASH Memory Programming functions *****************************************/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address, uint32_t erase_size); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data3, uint32_t Data2, uint32_t Data1, uint32_t Data0); +FLASH_Status FLASH_Program_oneWord(uint32_t Address, uint32_t Data0); +FLASH_Status FLASH_Program_HalfWord(uint32_t Address, uint16_t Data0); +FLASH_Status FLASH_Program_Byte(uint32_t Address, uint8_t Data0); + +/* FLASH Option Bytes Programming functions *****************************************/ +void FLASH_OPBC_Unlock(void); +void FLASH_OPBC_Lock(void); +FLASH_Status FLASH_WRPR_EnableWRP(uint32_t WRPR_WRP); +FLASH_Status FLASH_OPBC_RDPConfig(uint8_t OPBC_RDP); +FLASH_Status FLASH_OPBC_UserConfig(uint8_t OPBC_IWDG, uint8_t OPBC_STOP, uint8_t OPBC_STDBY); +FLASH_Status FLASH_OPBC_BOR_LevelConfig(uint32_t BORR_Level, uint32_t BORF_Level, FunctionalState NewState); +uint32_t FLASH_OPBC_GetWRP(void); +FlagStatus FLASH_OPBC_GetRDP(void); + +/* FLASH Interrupts and flags management functions **********************************/ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F0XX_FLASH_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ + + + + + + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_fmc.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_fmc.h new file mode 100644 index 00000000000..2b21b18c4ed --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_fmc.h @@ -0,0 +1,1132 @@ +/** + ****************************************************************************** + * @file ft32f4xx_fmc.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the FMC + * firmware library + * @version V1.0.0 + * @date 2025-04-15 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_FMC_H +#define __FT32F4XX_FMC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup FMC + * @{ + */ + +/** @addtogroup FMC_Private_Macros + * @{ + */ +#if defined(FMC_Bank1) + +#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \ + ((__BANK__) == FMC_NORSRAM_BANK2) || \ + ((__BANK__) == FMC_NORSRAM_BANK3) || \ + ((__BANK__) == FMC_NORSRAM_BANK4)) +#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \ + ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE)) +#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \ + ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \ + ((__MEMORY__) == FMC_MEMORY_TYPE_NOR)) +#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16)) +#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \ + ((__SIZE__) == FMC_PAGE_SIZE_128) || \ + ((__SIZE__) == FMC_PAGE_SIZE_256) || \ + ((__SIZE__) == FMC_PAGE_SIZE_512) || \ + ((__SIZE__) == FMC_PAGE_SIZE_1024)) +#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \ + ((__MODE__) == FMC_ACCESS_MODE_B) || \ + ((__MODE__) == FMC_ACCESS_MODE_C) || \ + ((__MODE__) == FMC_ACCESS_MODE_D)) +#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \ + ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE)) +#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \ + ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH)) +#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \ + ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS)) +#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \ + ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE)) +#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \ + ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE)) +#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \ + ((__MODE__) == FMC_EXTENDED_MODE_ENABLE)) +#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \ + ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE)) +#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) +#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \ + ((__BURST__) == FMC_WRITE_BURST_ENABLE)) +#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ + ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) +#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) +#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) +#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) +#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) +#define IS_FMC_TURNAROUND_TIME(__TIME__)(((__TIME__) >= 1U) && ((__TIME__) <= 16U)) +#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) +#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE) +#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE) + +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) + +#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \ + ((__BANK__) == FMC_NAND_BANK3)) +#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \ + ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE)) +#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16)) +#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \ + ((__STATE__) == FMC_NAND_ECC_ENABLE)) + +#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ + ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE)) +#define IS_FMC_TCLR_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 16U)) +#define IS_FMC_TAR_TIME(__TIME__) (((__TIME__) >= 1U) && ((__TIME__) <= 16U)) +#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) +#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE) + +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) + +#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \ + ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16)) +#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \ + ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE)) +#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \ + ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3)) +#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \ + ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE)) +#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \ + ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2)) +#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \ + ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE)) +#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \ + ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2)) +#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U)) +#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U)) +#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U)) +#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U) +#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U) +#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE) +#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \ + ((__BANK__) == FMC_SDRAM_BANK2)) +#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \ + ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11)) +#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \ + ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13)) +#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \ + ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4)) +#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \ + ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3)) + +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +/* Exported typedef ----------------------------------------------------------*/ + +/** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types + * @{ + */ + +#if defined(FMC_Bank1) +#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef +#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) +#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef +#endif /* FMC_Bank5_6 */ + +#if defined(FMC_Bank1) +#define FMC_NORSRAM_DEVICE FMC_Bank1 +#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) +#define FMC_NAND_DEVICE FMC_Bank2_3 +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +#define FMC_SDRAM_DEVICE FMC_Bank5_6 +#endif /* FMC_Bank5_6 */ + +#if defined(FMC_Bank1) +/** + * @brief FMC NORSRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. + This parameter can be a value of @ref FMC_NORSRAM_Bank */ + + uint32_t DataAddressMux; /*!< Specifies whether the address and data values are + multiplexed on the data bus or not. + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + + uint32_t MemoryType; /*!< Specifies the type of external memory attached to + the corresponding memory device. + This parameter can be a value of @ref FMC_Memory_Type */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + + uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FMC_Burst_Access_Mode */ + + uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + + uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FMC_Wait_Timing */ + + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ + + uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FMC_Wait_Signal */ + + uint32_t ExtendedMode; /*!< Enables or disables the extended mode. + This parameter can be a value of @ref FMC_Extended_Mode */ + + uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FMC_AsynchronousWait */ + + uint32_t WriteBurst; /*!< Enables or disables the write burst operation. + This parameter can be a value of @ref FMC_Write_Burst */ + + uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. + This parameter is only enabled through the FMC_BCR1 register, + and don't care through FMC_BCR2..4 registers. + This parameter can be a value of @ref FMC_Continous_Clock */ + + uint32_t PageSize; /*!< Specifies the memory page size. + This parameter can be a value of @ref FMC_Page_Size */ +} FMC_NORSRAM_InitTypeDef; + +/** + * @brief FMC NORSRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between Min_Data = 1 and Max_Data = 15. + @note This parameter is not used with synchronous NOR Flash memories. */ + + uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between Min_Data = 1 and Max_Data = 255. + @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed + NOR Flash memories. */ + + uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between Min_Data = 0 and Max_Data = 15. + @note This parameter is only used for multiplexed NOR Flash memories. */ + + uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of + HCLK cycles. This parameter can be a value between Min_Data = 2 and + Max_Data = 16. + @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM + accesses. */ + + uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The parameter value depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between Min_Data = 2 and Max_Data = 17 + in NOR Flash memories with synchronous burst mode enable */ + + uint32_t AccessMode; /*!< Specifies the asynchronous access mode. + This parameter can be a value of @ref FMC_Access_Mode */ +} FMC_NORSRAM_TimingTypeDef; +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) +/** + * @brief FMC NAND Configuration Structure definition + */ +typedef struct +{ + uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. + This parameter can be a value of @ref FMC_NAND_Bank */ + + uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. + This parameter can be any value of @ref FMC_Wait_feature */ + + uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. + This parameter can be any value of @ref FMC_NAND_Data_Width */ + + uint32_t EccComputation; /*!< Enables or disables the ECC computation. + This parameter can be any value of @ref FMC_ECC */ + + uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. + This parameter can be any value of @ref FMC_ECC_Page_Size */ + + uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ + + uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ +} FMC_NAND_InitTypeDef; +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank2_3) +/** + * @brief FMC NAND Timing parameters structure definition + */ +typedef struct +{ + uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ + + uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command de-assertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ + + uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the + data bus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ +} FMC_NAND_TimingTypeDef; +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +/** + * @brief FMC SDRAM Configuration Structure definition + */ +typedef struct +{ + uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used. + This parameter can be a value of @ref FMC_SDRAM_Bank */ + + uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */ + + uint32_t RowBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */ + + uint32_t MemoryDataWidth; /*!< Defines the memory device width. + This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */ + + uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks. + This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */ + + uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles. + This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */ + + uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode. + This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */ + + uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow + to disable the clock before changing frequency. + This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */ + + uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read + commands during the CAS latency and stores data in the Read FIFO. + This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */ + + uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path. + This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */ +} FMC_SDRAM_InitTypeDef; + +/** + * @brief FMC SDRAM Timing parameters structure definition + */ +typedef struct +{ + uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and + an active or Refresh command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to + issuing the Activate command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock + cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command + and the delay between two consecutive Refresh commands in number of + memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command + in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ + + uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write + command in number of memory clock cycles. + This parameter can be a value between Min_Data = 1 and Max_Data = 16 */ +} FMC_SDRAM_TimingTypeDef; + +/** + * @brief SDRAM command parameters structure definition + */ +typedef struct +{ + uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device. + This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */ + + uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to. + This parameter can be a value of @ref FMC_SDRAM_Command_Target. */ + + uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued + in auto refresh mode. + This parameter can be a value between Min_Data = 1 and Max_Data = 15 */ + + uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */ +} FMC_SDRAM_CommandTypeDef; +#endif /* FMC_Bank5_6 */ +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @addtogroup FMC_Exported_Constants FMC Low Layer Exported Constants + * @{ + */ +#if defined(FMC_Bank1) + +/** @defgroup FMC_NOR_SRAM_Controller FMC NOR/SRAM Controller + * @{ + */ + +/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank + * @{ + */ +#define FMC_NORSRAM_BANK1 (0x00000000U) +#define FMC_NORSRAM_BANK2 (0x00000002U) +#define FMC_NORSRAM_BANK3 (0x00000004U) +#define FMC_NORSRAM_BANK4 (0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing + * @{ + */ +#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) +#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_Memory_Type FMC Memory Type + * @{ + */ +#define FMC_MEMORY_TYPE_SRAM (0x00000000U) +#define FMC_MEMORY_TYPE_PSRAM (0x00000004U) +#define FMC_MEMORY_TYPE_NOR (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width + * @{ + */ +#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access + * @{ + */ +#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) +#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) +/** + * @} + */ + +/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode + * @{ + */ +#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) +#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity + * @{ + */ +#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) +#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Timing FMC Wait Timing + * @{ + */ +#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U) +#define FMC_WAIT_TIMING_DURING_WS (0x00000800U) +/** + * @} + */ + +/** @defgroup FMC_Write_Operation FMC Write Operation + * @{ + */ +#define FMC_WRITE_OPERATION_DISABLE (0x00000000U) +#define FMC_WRITE_OPERATION_ENABLE (0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_Wait_Signal FMC Wait Signal + * @{ + */ +#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U) +#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U) +/** + * @} + */ + +/** @defgroup FMC_Extended_Mode FMC Extended Mode + * @{ + */ +#define FMC_EXTENDED_MODE_DISABLE (0x00000000U) +#define FMC_EXTENDED_MODE_ENABLE (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait + * @{ + */ +#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) +#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) +/** + * @} + */ + +/** @defgroup FMC_Page_Size FMC Page Size + * @{ + */ +#define FMC_PAGE_SIZE_NONE (0x00000000U) +#define FMC_PAGE_SIZE_128 FMC_BCR1_CPSIZE_0 +#define FMC_PAGE_SIZE_256 FMC_BCR1_CPSIZE_1 +#define FMC_PAGE_SIZE_512 (FMC_BCR1_CPSIZE_0\ + | FMC_BCR1_CPSIZE_1) +#define FMC_PAGE_SIZE_1024 FMC_BCR1_CPSIZE_2 +/** + * @} + */ + +/** @defgroup FMC_Write_Burst FMC Write Burst + * @{ + */ +#define FMC_WRITE_BURST_DISABLE (0x00000000U) +#define FMC_WRITE_BURST_ENABLE (0x00080000U) +/** + * @} + */ + +/** @defgroup FMC_Continous_Clock FMC Continuous Clock + * @{ + */ +#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) +#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) +/** + * @} + */ + +#if defined(FMC_BCR1_WFDIS) +/** @defgroup FMC_Write_FIFO FMC Write FIFO + * @note These values are available only for the STM32F446/469/479xx devices. + * @{ + */ +#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS +#define FMC_WRITE_FIFO_ENABLE (0x00000000U) +#endif /* FMC_BCR1_WFDIS */ +/** + * @} + */ + +/** @defgroup FMC_Access_Mode FMC Access Mode + * @{ + */ +#define FMC_ACCESS_MODE_A (0x00000000U) +#define FMC_ACCESS_MODE_B (0x10000000U) +#define FMC_ACCESS_MODE_C (0x20000000U) +#define FMC_ACCESS_MODE_D (0x30000000U) +/** + * @} + */ + +/** + * @} + */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) + +/** @defgroup FMC_NAND_Controller FMC NAND Controller + * @{ + */ +/** @defgroup FMC_NAND_Bank FMC NAND Bank + * @{ + */ +#if defined(FMC_Bank2_3) +#define FMC_NAND_BANK2 (0x00000010U) +#endif +#define FMC_NAND_BANK3 (0x00000100U) +/** + * @} + */ + +/** @defgroup FMC_Wait_feature FMC Wait feature + * @{ + */ +#define FMC_NAND_WAIT_FEATURE_DISABLE (0x00000000U) +#define FMC_NAND_WAIT_FEATURE_ENABLE (0x00000002U) +/** + * @} + */ + +/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type + * @{ + */ +#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width + * @{ + */ +#define FMC_NAND_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_NAND_MEM_BUS_WIDTH_16 (0x00000010U) +/** + * @} + */ + +/** @defgroup FMC_ECC FMC ECC + * @{ + */ +#define FMC_NAND_ECC_DISABLE (0x00000000U) +#define FMC_NAND_ECC_ENABLE (0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size + * @{ + */ +#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) +#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) +#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) +#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) +#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) +#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) +/** + * @} + */ + +/** + * @} + */ +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +/** @defgroup FMC_SDRAM_Controller FMC SDRAM Controller + * @{ + */ +/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank + * @{ + */ +#define FMC_SDRAM_BANK1 (0x00000000U) +#define FMC_SDRAM_BANK2 (0x00000001U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number + * @{ + */ +#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U) +#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U) +#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U) +#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number + * @{ + */ +#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U) +#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U) +#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width + * @{ + */ +#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U) +#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number + * @{ + */ +#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U) +#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency + * @{ + */ +#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U) +#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U) +#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection + * @{ + */ +#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U) +#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period + * @{ + */ +#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U) +#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U) +#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst + * @{ + */ +#define FMC_SDRAM_RBURST_DISABLE (0x00000000U) +#define FMC_SDRAM_RBURST_ENABLE (0x00001000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay + * @{ + */ +#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U) +#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U) +#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode + * @{ + */ +#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U) +#define FMC_SDRAM_CMD_PALL (0x00000002U) +#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U) +#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U) +#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U) +#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target + * @{ + */ +#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2 +#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1 +#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U) +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status + * @{ + */ +#define FMC_SDRAM_NORMAL_MODE (0x00000000U) +#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0 +#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1 +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMC_Bank5_6 */ + +/** @defgroup FMC_Interrupt_definition FMC Low Layer Interrupt definition + * @{ + */ +#if defined(FMC_Bank5_6) +#define FMC_IT_REFRESH_ERROR (0x00004000U) +#endif /* FMC_Bank5_6 */ +/** + * @} + */ + +/** @defgroup FMC_Flag_definition FMC Low Layer Flag definition + * @{ + */ +#if defined(FMC_Bank2_3) +#define FMC_FLAG_FEMPT (0x00000040U) +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE +#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY +#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE +#endif /* FMC_Bank5_6 */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/** @defgroup FMC_Private_Macros FMC Private Macros + * @{ + */ +#if defined(FMC_Bank1) +/** @defgroup FMC_NOR_Macros FMC NOR/SRAM Macros + * @brief macros to handle NOR device enable/disable and read/write operations + * @{ + */ + +/** + * @brief Enable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + |= FMC_BCR1_MBKEN) + +/** + * @brief Disable the NORSRAM device access. + * @param __INSTANCE__ FMC_NORSRAM Instance + * @param __BANK__ FMC_NORSRAM Bank + * @retval None + */ +#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ + &= ~FMC_BCR1_MBKEN) + +/** + * @} + */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) +/** @defgroup FMC_NAND_Macros FMC NAND Macros + * @brief macros to handle NAND device enable/disable + * @{ + */ + +/** + * @brief Enable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @retval None + */ +#if defined(FMC_Bank2_3) +#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \ + ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN)) +#endif /* FMC_Bank2_3 */ + +/** + * @brief Disable the NAND device access. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @retval None + */ +#if defined(FMC_Bank2_3) +#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~(FMC_PCR2_PBKEN)): \ + ((__INSTANCE__)->PCR3 &= ~(FMC_PCR3_PBKEN))) +#endif /* FMC_Bank2_3 */ + +/** + * @brief Get flag status of the NAND device. + * @param __INSTANCE__ FMC_NAND Instance + * @param __BANK__ FMC_NAND Bank + * @param __FLAG__ FMC_NAND flag + * This parameter can be any combination of the following values: + * @arg FMC_FLAG_FEMPT: FIFO empty flag. + * @retval The state of FLAG (SET or RESET). + */ +#if defined(FMC_Bank2_3) +#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ + (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) +#endif /* FMC_Bank2_3 */ + +/** + * @} + */ +#endif /* defined(FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +/** @defgroup FMC_SDRAM_Interrupt FMC SDRAM Interrupt + * @brief macros to handle SDRAM interrupts + * @{ + */ + +/** + * @brief Enable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__)) + +/** + * @brief Disable the SDRAM device interrupt. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __INTERRUPT__ FMC_SDRAM interrupt + * This parameter can be any combination of the following values: + * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error + * @retval None + */ +#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__)) + +/** + * @brief Get flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error. + * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag. + * @retval The state of FLAG (SET or RESET). + */ +#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__)) + +/** + * @brief Clear flag status of the SDRAM device. + * @param __INSTANCE__ FMC_SDRAM instance + * @param __FLAG__ FMC_SDRAM flag + * This parameter can be any combination of the following values: + * @arg FMC_SDRAM_FLAG_REFRESH_ERROR + * @retval None + */ +#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__)) + +/** + * @} + */ +#endif /* FMC_Bank5_6 */ +/** + * @} + */ + + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup FMC_Private_Functions FMC Private Functions + * @{ + */ + +#if defined(FMC_Bank1) +/** @defgroup FMC_NORSRAM NOR SRAM + * @{ + */ +/** @defgroup FMC_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions + * @{ + */ +void FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef * FSMC_Data_Address_Bus_MultiplexingDevice, + FMC_NORSRAM_InitTypeDef *Init); +void FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); +void FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode); +void FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions + * @{ + */ +void FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +void FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) +/** @defgroup FMC_NAND NAND + * @{ + */ +/** @defgroup FMC_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions + * @{ + */ +void FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +void FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_TimingTypeDef *Timing, uint32_t Bank); +void FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_TimingTypeDef *Timing, uint32_t Bank); +void FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_NAND_Private_Functions_Group2 NAND Control functions + * @{ + */ +void FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); +void FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); +void FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +/** @defgroup FMC_SDRAM SDRAM + * @{ + */ +/** @defgroup FMC_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions + * @{ + */ +void FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init); +void FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank); +void FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ + +/** @defgroup FMC_SDRAM_Private_Functions_Group2 SDRAM Control functions + * @{ + */ +void FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +void FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank); +void FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command); +void FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate); +void FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber); +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank); +/** + * @} + */ +/** + * @} + */ +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_FMC_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE*******************/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_gpio.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_gpio.h new file mode 100644 index 00000000000..57462b6bbc7 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_gpio.h @@ -0,0 +1,340 @@ +/** + ****************************************************************************** + * @file ft32f4xx_gpio.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the GPIO + * firmware library. + * @version V1.0.0 + * @date 2025-03-27 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_GPIO_H +#define __FT32F4XX_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup GPIO + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \ + ((PERIPH) == GPIOB) || \ + ((PERIPH) == GPIOC) || \ + ((PERIPH) == GPIOD) || \ + ((PERIPH) == GPIOE) || \ + ((PERIPH) == GPIOH)) + +/** @defgroup Configuration_Mode_enumeration + * @{ + */ +typedef enum +{ + GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */ + GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */ + GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */ + GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */ +} GPIOMode_TypeDef; + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || \ + ((MODE) == GPIO_Mode_OUT) || \ + ((MODE) == GPIO_Mode_AF) || \ + ((MODE) == GPIO_Mode_AN)) +/** + * @} + */ + +/** @defgroup Output_type_enumeration + * @{ + */ +typedef enum +{ + GPIO_OType_PP = 0x00, + GPIO_OType_OD = 0x01 +} GPIOOType_TypeDef; + +#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || \ + ((OTYPE) == GPIO_OType_OD)) + +/** + * @} + */ + +/** @defgroup Output_Maximum_frequency_enumeration + * @{ + */ +typedef enum +{ + GPIO_Speed_Level_0 = 0x00, /*!< I/O output speed: Low 4 MHz */ + GPIO_Speed_Level_1 = 0x01, /*!< I/O output speed: Medium 25 MHz */ + GPIO_Speed_Level_2 = 0x02, /*!< I/O output speed: High 50 MHz */ + GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: Very high 100 MHz */ +} GPIOSpeed_TypeDef; + +#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_0) || \ + ((SPEED) == GPIO_Speed_Level_1) || \ + ((SPEED) == GPIO_Speed_Level_2) || \ + ((SPEED) == GPIO_Speed_Level_3)) +/** + * @} + */ + +/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration + * @{ + */ +typedef enum +{ + GPIO_PuPd_NOPULL = 0x00, + GPIO_PuPd_UP = 0x01, + GPIO_PuPd_DOWN = 0x02 +} GPIOPuPd_TypeDef; + +#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || \ + ((PUPD) == GPIO_PuPd_UP) || \ + ((PUPD) == GPIO_PuPd_DOWN)) +/** + * @} + */ + +/** @defgroup Bit_SET_and_Bit_RESET_enumeration + * @{ + */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || \ + ((ACTION) == Bit_SET)) +/** + * @} + */ + +/** @brief GPIO Init structure definition + * @{ + */ +typedef struct +{ + uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ + + GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIOOType_TypeDef */ + + GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIOPuPd_TypeDef */ +} GPIO_InitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup GPIO_Exported_Constants + * @{ + */ + +/** @defgroup GPIO_pins_define + * @{ + */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */ + +#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00) + +#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \ + ((PIN) == GPIO_Pin_1) || \ + ((PIN) == GPIO_Pin_2) || \ + ((PIN) == GPIO_Pin_3) || \ + ((PIN) == GPIO_Pin_4) || \ + ((PIN) == GPIO_Pin_5) || \ + ((PIN) == GPIO_Pin_6) || \ + ((PIN) == GPIO_Pin_7) || \ + ((PIN) == GPIO_Pin_8) || \ + ((PIN) == GPIO_Pin_9) || \ + ((PIN) == GPIO_Pin_10) || \ + ((PIN) == GPIO_Pin_11) || \ + ((PIN) == GPIO_Pin_12) || \ + ((PIN) == GPIO_Pin_13) || \ + ((PIN) == GPIO_Pin_14) || \ + ((PIN) == GPIO_Pin_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Pin_sources + * @{ + */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \ + ((PINSOURCE) == GPIO_PinSource1) || \ + ((PINSOURCE) == GPIO_PinSource2) || \ + ((PINSOURCE) == GPIO_PinSource3) || \ + ((PINSOURCE) == GPIO_PinSource4) || \ + ((PINSOURCE) == GPIO_PinSource5) || \ + ((PINSOURCE) == GPIO_PinSource6) || \ + ((PINSOURCE) == GPIO_PinSource7) || \ + ((PINSOURCE) == GPIO_PinSource8) || \ + ((PINSOURCE) == GPIO_PinSource9) || \ + ((PINSOURCE) == GPIO_PinSource10) || \ + ((PINSOURCE) == GPIO_PinSource11) || \ + ((PINSOURCE) == GPIO_PinSource12) || \ + ((PINSOURCE) == GPIO_PinSource13) || \ + ((PINSOURCE) == GPIO_PinSource14) || \ + ((PINSOURCE) == GPIO_PinSource15)) +/** + * @} + */ + +/** @defgroup GPIO_Alternate_function_selection_define + * @brief AF 0~15 selection + * @{ + */ + +#define GPIO_AF_0 ((uint8_t)0x00) /* SYS */ + +#define GPIO_AF_1 ((uint8_t)0x01) /* TIM1/2, LPTIM */ + +#define GPIO_AF_2 ((uint8_t)0x02) /* TIM3/4/5 */ + +#define GPIO_AF_3 ((uint8_t)0x03) /* TIM8/9/10/11, CRS */ + +#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1/2/3, SPI3, I2S3 */ + +#define GPIO_AF_5 ((uint8_t)0x05) /* SPI1/2, I2S2 */ + +#define GPIO_AF_6 ((uint8_t)0x06) /* SPI3, I2S2, SDIO */ + +#define GPIO_AF_7 ((uint8_t)0x07) /* USART1/2/3, UART7 */ + +#define GPIO_AF_8 ((uint8_t)0x08) /* UART4/5, LPUART, USART6, COMP1/2/3/4/5/6 */ + +#define GPIO_AF_9 ((uint8_t)0x09) /* CAN1/2/3/4, TIM12/13/14 */ + +#define GPIO_AF_10 ((uint8_t)0x0A) /* OTG_FS, QUADSPI */ + +#define GPIO_AF_11 ((uint8_t)0x0B) /* ETH */ + +#define GPIO_AF_12 ((uint8_t)0x0C) /* OTH_HS, FMC */ + +#define GPIO_AF_13 ((uint8_t)0x0D) /* SSI, SPDIF */ + +#define GPIO_AF_14 ((uint8_t)0x0E) /* EPWM, EQEP, ECAP*/ + +#define GPIO_AF_15 ((uint8_t)0x0F) /* EVENTOUT*/ + + +#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \ + ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \ + ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \ + ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7) || \ + ((AF) == GPIO_AF_8) || ((AF) == GPIO_AF_9) || \ + ((AF) == GPIO_AF_10) || ((AF) == GPIO_AF_11) || \ + ((AF) == GPIO_AF_12) || ((AF) == GPIO_AF_13) || \ + ((AF) == GPIO_AF_14) || ((AF) == GPIO_AF_15)) + +/** + * @} + */ + +/** @defgroup GPIO_Speed_Legacy + * @{ + */ + +#define GPIO_Speed_4MHz GPIO_Speed_Level_0 /*!< I/O output speed: Low 4 MHz */ +#define GPIO_Speed_25MHz GPIO_Speed_Level_1 /*!< I/O output speed: Medium 25 MHz */ +#define GPIO_Speed_50MHz GPIO_Speed_Level_2 /*!< I/O output speed: High 50 MHz */ +#define GPIO_Speed_100MHz GPIO_Speed_Level_3 /*!< I/O output speed: Very high 100 MHz */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the GPIO configuration to the default reset state *****/ +void GPIO_DeInit(GPIO_TypeDef* GPIOx); + +/* Initialization and Configuration functions *********************************/ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); + +/* GPIO Read and Write functions **********************************************/ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); + +/* GPIO Alternate functions configuration functions ***************************/ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_GPIO_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE*******************/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_hcd_fs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_hcd_fs.h new file mode 100644 index 00000000000..7fcdd473741 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_hcd_fs.h @@ -0,0 +1,152 @@ +/** + ****************************************************************************** + * @file ft32f4xx_hcd_fs.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the + * >>->-USB_OTG_FS firmware library. + * @version V1.0.0 + * @data 2025-05-28 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_HCD_FS_H +#define __FT32F4XX_HCD_FS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_usb_fs.h" + +#if defined (USB_OTG_FS) + +/* Exported types ------------------------------------------------------------*/ + +typedef enum +{ + HCD_FS_STATE_RESET = 0x00, + HCD_FS_STATE_READY = 0x01, + HCD_FS_STATE_ERROR = 0x02, + HCD_FS_STATE_BUSY = 0x03, + HCD_FS_STATE_TIMEOUT = 0x04, +} HCD_FS_StateTypeDef; + + +typedef USB_OTG_FS_CfgTypeDef HCD_FS_InitTypeDef; +typedef USB_OTG_FS_HEPTypeDef HCD_FS_EPTypeDef; +typedef USB_OTG_FS_URBStateTypeDef HCD_FS_URBStateTypeDef; +typedef USB_OTG_FS_HEPStateTypeDef HCD_FS_EPStateTypeDef; +typedef USB_FS_LockTypeDef HCD_FS_LockTypeDef; + +/** + * @} + */ + +typedef struct +{ + HCD_FS_InitTypeDef Init; /*!< HCD required parameters */ + HCD_FS_EPTypeDef ep[16]; /*!< Host endpoint parameters */ + HCD_FS_LockTypeDef Lock; /*!< HCD peripheral status */ + __IO HCD_FS_StateTypeDef State; /*!< HCD communication state */ + __IO uint32_t ErrorCode; /*!< HCD Error code */ + __IO uint32_t cur_ep; /*!< host current used ep pipe*/ + void *pData; /*!< Pointer Stack Handler */ +} HCD_FS_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HCD_Speed HCD Speed + * @{ + */ +#define HCD_SPEED_FULL USB_FS_SPEED +#define HCD_SPEED_LOW USB_LS_SPEED +/** + * @} + */ + +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ +#define HCD_DEVICE_SPEED_FULL 0U +#define HCD_DEVICE_SPEED_LOW 1U +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +USB_FS_StatusTypeDef HCD_FS_Init(HCD_FS_HandleTypeDef *hhcd); +USB_FS_StatusTypeDef HCD_FS_DeInit(HCD_FS_HandleTypeDef *hhcd); +USB_FS_StatusTypeDef HCD_FS_EP_Init(HCD_FS_HandleTypeDef *hhcd, uint8_t pipe, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, + uint16_t mps); + +void HCD_FS_MspInit(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_MspDeInit(HCD_FS_HandleTypeDef *hhcd); + +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +void HCD_FS_EP_SubmitRequest(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t ctl_state); + +/* Non-Blocking mode: Interrupt */ +void HCD_FS_IRQHandler(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_WKUP_IRQHandler(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_SOF_Callback(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_VBusErr_Callback(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_Session_Callback(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_Babble_Callback(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_Resume_Callback(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_Connect_Callback(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_Disconnect_Callback(HCD_FS_HandleTypeDef *hhcd); +void HCD_FS_EP_NotifyURBChange_Callback(HCD_FS_HandleTypeDef *hhcd, uint8_t epnum, + HCD_FS_URBStateTypeDef urb_state); + + + +/* Peripheral Control functions **********************************************/ +void HCD_FS_ResetPort(void); +USB_FS_StatusTypeDef HCD_FS_Start(HCD_FS_HandleTypeDef *hhcd); +USB_FS_StatusTypeDef HCD_FS_Stop(HCD_FS_HandleTypeDef *hhcd); + + +/* Peripheral State functions ************************************************/ +HCD_FS_StateTypeDef HCD_FS_GetState(HCD_FS_HandleTypeDef *hhcd); +HCD_FS_URBStateTypeDef HCD_FS_EP_GetURBState(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num); +HCD_FS_EPStateTypeDef HCD_FS_EP_GetState(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num); +uint32_t HCD_FS_EP_GetXferCount(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num); +uint32_t HCD_FS_GetCurrEp(HCD_FS_HandleTypeDef *hhcd); +uint32_t HCD_FS_GetCurrentFrame(void); +uint32_t HCD_FS_GetCurrentSpeed(void); + + +#endif /* defined (USB_OTG_FS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* FT32F4XX_HCD_FS_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_hcd_hs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_hcd_hs.h new file mode 100644 index 00000000000..d7cccfd7092 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_hcd_hs.h @@ -0,0 +1,234 @@ +/** + ****************************************************************************** + * @file ft32f4xx_hcd_hs.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the + * >>->-USB_OTG_HS firmware library. + * @version V1.0.0 + * @data 2025-03-26 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_HCD_HS_H +#define __FT32F4XX_HCD_HS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_usb_hs.h" + +#if defined (USB_OTG_HS) +/** @addtogroup ft32f4xx Drive + * @ + */ + +/** @addtogroup HCD_HS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup HCD_HS_Exported_Types HCD Exported Types + * @{ + */ + +/** @defgroup HCD_HS_Exported_Types_Group1 HCD State Structure definition + * @{ + */ +typedef enum +{ + HCD_HS_STATE_RESET = 0x00, + HCD_HS_STATE_READY = 0x01, + HCD_HS_STATE_ERROR = 0x02, + HCD_HS_STATE_BUSY = 0x03, + HCD_HS_STATE_TIMEOUT = 0x04 +} HCD_HS_StateTypeDef; + +typedef USB_OTG_HS_GlobalTypeDef HCD_HS_TypeDef; +typedef USB_OTG_HS_CfgTypeDef HCD_HS_InitTypeDef; +typedef USB_OTG_HS_HCTypeDef HCD_HS_HCTypeDef; +typedef USB_OTG_HS_URBStateTypeDef HCD_HS_URBStateTypeDef; +typedef USB_OTG_HS_HCStateTypeDef HCD_HS_HCStateTypeDef; +typedef USB_HS_LockTypeDef HCD_HS_LockTypeDef; +/** + * @} + */ + +/** @defgroup HCD_HS_Exported_Types_Group2 HCD Handle Structure definition + * @{ + */ +typedef struct +{ + HCD_HS_InitTypeDef Init; /*!< HCD required parameters */ + HCD_HS_HCTypeDef hc[16]; /*!< Host channels parameters */ + HCD_HS_LockTypeDef Lock; /*!< HCD peripheral status */ + __IO HCD_HS_StateTypeDef State; /*!< HCD communication state */ + __IO uint32_t ErrorCode; /*!< HCD Error code */ + void *pData; /*!< Pointer Stack Handler */ +} HCD_HS_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup HCD_HS_Exported_Constants HCD Exported Constants + * @{ + */ + +/** @defgroup HCD_Speed HCD Speed + * @{ + */ +#define HCD_SPEED_HIGH USBH_HS_SPEED +#define HCD_SPEED_FULL USBH_FSLS_SPEED +#define HCD_SPEED_LOW USBH_FSLS_SPEED +/** + * @} + */ + +/** @defgroup HCD_Device_Speed HCD Device Speed + * @{ + */ +#define HCD_DEVICE_SPEED_HIGH 0U +#define HCD_DEVICE_SPEED_FULL 1U +#define HCD_DEVICE_SPEED_LOW 2U +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup HCD_HS_Exported_Macros HCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __HCD_HS_ENABLE() (void)USB_HS_EnableGlobalInt () +#define __HCD_HS_DISABLE() (void)USB_HS_DisableGlobalInt () + +#define __HCD_HS_GET_FLAG(__INTERRUPT__) ((USB_HS_ReadInterrupts()\ + & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HCD_HS_GET_CH_FLAG(__chnum__, __INTERRUPT__) \ + ((USB_HS_ReadChInterrupts(__chnum__)\ + & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HCD_HS_CLEAR_FLAG(__INTERRUPT__) ((USB_HS->GINTSTS) = (__INTERRUPT__)) +#define __HCD_HS_IS_INVALID_INTERRUPT() (USB_HS_ReadInterrupts() == 0U) + +#define __HCD_HS_CLEAR_HC_INT(chnum, __INTERRUPT__) (USB_HS_HC(chnum)->HCINT = (__INTERRUPT__)) +#define __HCD_HS_MASK_HALT_HC_INT(chnum) (USB_HS_HC(chnum)->HCINTMSK &= ~OTG_HS_HCINTMSK_CHHM) +#define __HCD_HS_UNMASK_HALT_HC_INT(chnum) (USB_HS_HC(chnum)->HCINTMSK |= OTG_HS_HCINTMSK_CHHM) +#define __HCD_HS_MASK_ACK_HC_INT(chnum) (USB_HS_HC(chnum)->HCINTMSK &= ~OTG_HS_HCINTMSK_ACKM) +#define __HCD_HS_UNMASK_ACK_HC_INT(chnum) (USB_HS_HC(chnum)->HCINTMSK |= OTG_HS_HCINTMSK_ACKM) +#define __HCD_HS_SET_HC_CSPLT(chnum) (USB_HS_HC(chnum)->HCSPLT |= OTG_HS_HCSPLT_COMPLSPLT) +#define __HCD_HS_CLEAR_HC_CSPLT(chnum) (USB_HS_HC(chnum)->HCSPLT &= ~OTG_HS_HCSPLT_COMPLSPLT) +#define __HCD_HS_CLEAR_HC_SSPLT(chnum) (USB_HS_HC(chnum)->HCSPLT &= ~OTG_HS_HCSPLT_SPLITEN) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup HCD_HS_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_HS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +USB_HS_StatusTypeDef HCD_HS_Init(HCD_HS_HandleTypeDef *hhcd); +USB_HS_StatusTypeDef HCD_HS_DeInit(HCD_HS_HandleTypeDef *hhcd); +USB_HS_StatusTypeDef HCD_HS_HC_Init(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); + +USB_HS_StatusTypeDef HCD_HS_HC_Halt(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num); +void HCD_HS_MspInit(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_MspDeInit(HCD_HS_HandleTypeDef *hhcd); + +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +void HCD_HS_HC_SubmitRequest(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t direction, uint8_t ep_type, + uint8_t token, uint8_t *pbuff, + uint16_t length, uint8_t do_ping); + +void HCD_HS_HC_SetHubInfo(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num, + uint8_t addr, uint8_t PortNbr); + + +void HCD_HS_HC_ClearHubInfo(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num); + +/* Non-Blocking mode: Interrupt */ +void HCD_HS_IRQHandler(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_WKUP_IRQHandler(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_SOF_Callback(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_Connect_Callback(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_Disconnect_Callback(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_PortEnabled_Callback(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_PortDisabled_Callback(HCD_HS_HandleTypeDef *hhcd); +void HCD_HS_HC_NotifyURBChange_Callback(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum, + HCD_HS_URBStateTypeDef urb_state); +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup HCD_HS_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +void HCD_HS_ResetPort(void); +USB_HS_StatusTypeDef HCD_HS_Start(HCD_HS_HandleTypeDef *hhcd); +USB_HS_StatusTypeDef HCD_HS_Stop(HCD_HS_HandleTypeDef *hhcd); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +HCD_HS_StateTypeDef HCD_HS_GetState(HCD_HS_HandleTypeDef *hhcd); +HCD_HS_URBStateTypeDef HCD_HS_HC_GetURBState(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum); +HCD_HS_HCStateTypeDef HCD_HS_HC_GetState(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HCD_HS_HC_GetXferCount(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum); +uint32_t HCD_HS_GetCurrentFrame(void); +uint32_t HCD_HS_GetCurrentSpeed(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* FT32F4XX_HCD_HS_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_i2c.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_i2c.h new file mode 100644 index 00000000000..05cbf0e869a --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_i2c.h @@ -0,0 +1,475 @@ +/** + ****************************************************************************** + * @file ft32f4xx_i2c.h + * @author FMD AE + * @brief This file contains all the functions prototypes for + * the I2C firmware library + * @version V1.0.0 + * @date 2025-03-31 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_I2C_H +#define __FT32F4XX_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup I2C + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/**@brief I2C Init structure definition + * @{ + */ + +typedef struct +{ + uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value */ + + uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter. + This parameter can be a value of @ref I2C_Analog_Filter */ + + uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter. + This parameter can be a number between 0x00 and 0x0F */ + + uint32_t I2C_NoStretchMode; /*!< Specifies if nostretch mode is selected. + This parameter can be a value of @ref I2C_NoStretch_Mode */ + + uint32_t I2C_Mode; /*!< Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1. + This parameter can be a 7-bit or 10-bit address */ + + uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +} I2C_InitTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + + +/** @defgroup I2C_Exported_Constants + * @{ + */ + +#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \ + ((PERIPH) == I2C2) || \ + ((PERIPH) == I2C3)) + + +/** @defgroup I2C_Analog_Filter + * @{ + */ + +#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000) +#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF + +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \ + ((FILTER) == I2C_AnalogFilter_Disable)) +/** + * @} + */ + +/** @defgroup I2C_Digital_Filter + * @{ + */ + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) + +/** + * @} + */ + +/** @defgroup I2C_NoStretch_Mode + * @{ + */ +#define I2C_NoStretch_Disable (0x00000000U) +#define I2C_NoStretch_Enable I2C_CR1_NOSTRETCH + +#define IS_I2C_NoStretch(MODE) (((MODE) == I2C_NoStretch_Enable) || \ + ((MODE) == I2C_NoStretch_Disable)) + +/** + * @} + */ + +/** @defgroup I2C_mode + * @{ + */ + +#define I2C_Mode_I2C ((uint32_t)0x00000000) +#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN +#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN + +#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \ + ((MODE) == I2C_Mode_SMBusDevice) || \ + ((MODE) == I2C_Mode_SMBusHost)) +/** + * @} + */ + +/** @defgroup I2C_acknowledgement + * @{ + */ + +#define I2C_Ack_Enable ((uint32_t)0x00000000) +#define I2C_Ack_Disable I2C_CR2_NACK + +#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \ + ((ACK) == I2C_Ack_Disable)) +/** + * @} + */ + +/** @defgroup I2C_acknowledged_address + * @{ + */ + +#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000) +#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE + +#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \ + ((ADDRESS) == I2C_AcknowledgedAddress_10bit)) +/** + * @} + */ + +/** @defgroup I2C_own_address1 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +/** + * @} + */ + +/** @defgroup I2C_transfer_direction + * @{ + */ + +#define I2C_Direction_Transmitter ((uint16_t)0x0000) +#define I2C_Direction_Receiver ((uint16_t)0x0400) + +#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \ + ((DIRECTION) == I2C_Direction_Receiver)) +/** + * @} + */ + +/** @defgroup I2C_DMA_transfer_requests + * @{ + */ + +#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN +#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN + +#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00)) +/** + * @} + */ + +/** @defgroup I2C_slave_address + * @{ + */ + +#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF) +/** + * @} + */ + + +/** @defgroup I2C_own_address2 + * @{ + */ + +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) + +/** + * @} + */ + +/** @defgroup I2C_own_address2_mask + * @{ + */ + +#define I2C_OA2_NoMask ((uint8_t)0x00) +#define I2C_OA2_Mask01 ((uint8_t)0x01) +#define I2C_OA2_Mask02 ((uint8_t)0x02) +#define I2C_OA2_Mask03 ((uint8_t)0x03) +#define I2C_OA2_Mask04 ((uint8_t)0x04) +#define I2C_OA2_Mask05 ((uint8_t)0x05) +#define I2C_OA2_Mask06 ((uint8_t)0x06) +#define I2C_OA2_Mask07 ((uint8_t)0x07) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \ + ((MASK) == I2C_OA2_Mask01) || \ + ((MASK) == I2C_OA2_Mask02) || \ + ((MASK) == I2C_OA2_Mask03) || \ + ((MASK) == I2C_OA2_Mask04) || \ + ((MASK) == I2C_OA2_Mask05) || \ + ((MASK) == I2C_OA2_Mask06) || \ + ((MASK) == I2C_OA2_Mask07)) + +/** + * @} + */ + +/** @defgroup I2C_timeout + * @{ + */ + +#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF) + +/** + * @} + */ + +/** @defgroup I2C_registers + * @{ + */ + +#define I2C_Register_CR1 ((uint8_t)0x00) +#define I2C_Register_CR2 ((uint8_t)0x04) +#define I2C_Register_OAR1 ((uint8_t)0x08) +#define I2C_Register_OAR2 ((uint8_t)0x0C) +#define I2C_Register_TIMINGR ((uint8_t)0x10) +#define I2C_Register_TIMEOUTR ((uint8_t)0x14) +#define I2C_Register_ISR ((uint8_t)0x18) +#define I2C_Register_ICR ((uint8_t)0x1C) +#define I2C_Register_PECR ((uint8_t)0x20) +#define I2C_Register_RXDR ((uint8_t)0x24) +#define I2C_Register_TXDR ((uint8_t)0x28) + +#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \ + ((REGISTER) == I2C_Register_CR2) || \ + ((REGISTER) == I2C_Register_OAR1) || \ + ((REGISTER) == I2C_Register_OAR2) || \ + ((REGISTER) == I2C_Register_TIMINGR) || \ + ((REGISTER) == I2C_Register_TIMEOUTR) || \ + ((REGISTER) == I2C_Register_ISR) || \ + ((REGISTER) == I2C_Register_ICR) || \ + ((REGISTER) == I2C_Register_PECR) || \ + ((REGISTER) == I2C_Register_RXDR) || \ + ((REGISTER) == I2C_Register_TXDR)) +/** + * @} + */ + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_ERRI I2C_CR1_ERRIE +#define I2C_IT_TCI I2C_CR1_TCIE +#define I2C_IT_STOPI I2C_CR1_STOPIE +#define I2C_IT_NACKI I2C_CR1_NACKIE +#define I2C_IT_ADDRI I2C_CR1_ADDRIE +#define I2C_IT_RXI I2C_CR1_RXIE +#define I2C_IT_TXI I2C_CR1_TXIE + +#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00)) + +/** + * @} + */ + +/** @defgroup I2C_flags_definition + * @{ + */ + +#define I2C_FLAG_TXE I2C_ISR_TXE +#define I2C_FLAG_TXIS I2C_ISR_TXIS +#define I2C_FLAG_RXNE I2C_ISR_RXNE +#define I2C_FLAG_ADDR I2C_ISR_ADDR +#define I2C_FLAG_NACKF I2C_ISR_NACKF +#define I2C_FLAG_STOPF I2C_ISR_STOPF +#define I2C_FLAG_TC I2C_ISR_TC +#define I2C_FLAG_TCR I2C_ISR_TCR +#define I2C_FLAG_BERR I2C_ISR_BERR +#define I2C_FLAG_ARLO I2C_ISR_ARLO +#define I2C_FLAG_OVR I2C_ISR_OVR +#define I2C_FLAG_PECERR I2C_ISR_PECERR +#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_FLAG_ALERT I2C_ISR_ALERT +#define I2C_FLAG_BUSY I2C_ISR_BUSY + +#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00)) + +#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \ + ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \ + ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \ + ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \ + ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \ + ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \ + ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \ + ((FLAG) == I2C_FLAG_BUSY)) + +/** + * @} + */ + + +/** @defgroup I2C_interrupts_definition + * @{ + */ + +#define I2C_IT_TXIS I2C_ISR_TXIS +#define I2C_IT_RXNE I2C_ISR_RXNE +#define I2C_IT_ADDR I2C_ISR_ADDR +#define I2C_IT_NACKF I2C_ISR_NACKF +#define I2C_IT_STOPF I2C_ISR_STOPF +#define I2C_IT_TC I2C_ISR_TC +#define I2C_IT_TCR I2C_ISR_TCR +#define I2C_IT_BERR I2C_ISR_BERR +#define I2C_IT_ARLO I2C_ISR_ARLO +#define I2C_IT_OVR I2C_ISR_OVR +#define I2C_IT_PECERR I2C_ISR_PECERR +#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT +#define I2C_IT_ALERT I2C_ISR_ALERT + +#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00)) + +#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \ + ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \ + ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \ + ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \ + ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \ + ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \ + ((IT) == I2C_IT_ALERT)) + + +/** + * @} + */ + +/** @defgroup I2C_ReloadEndMode_definition + * @{ + */ + +#define I2C_Reload_Mode I2C_CR2_RELOAD +#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND +#define I2C_SoftEnd_Mode ((uint32_t)0x00000000) + + +#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \ + ((MODE) == I2C_AutoEnd_Mode) || \ + ((MODE) == I2C_SoftEnd_Mode)) + + +/** + * @} + */ + +/** @defgroup I2C_StartStopMode_definition + * @{ + */ + +#define I2C_No_StartStop ((uint32_t)0x00000000) +#define I2C_Generate_Stop I2C_CR2_STOP +#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) +#define I2C_Generate_Start_Write I2C_CR2_START + + +#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \ + ((MODE) == I2C_Generate_Start_Read) || \ + ((MODE) == I2C_Generate_Start_Write) || \ + ((MODE) == I2C_No_StartStop)) + + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + + +/* Initialization and Configuration functions *********************************/ +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address); +void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); + +/* Communications handling functions ******************************************/ +void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes); +void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx); +uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx); +void I2C_GenerateTXIS(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateTXE(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode); + +/* SMBUS management functions ************************************************/ +void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); +void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); + +/* I2C registers management functions *****************************************/ +uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); + +/* Data transfers management functions ****************************************/ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); + +/* DMA transfers management functions *****************************************/ +void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_I2C_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE*******************/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_i2s.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_i2s.h new file mode 100644 index 00000000000..605db5c6796 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_i2s.h @@ -0,0 +1,488 @@ +/** + ****************************************************************************** + * @file ft32f4xx_i2s.h + * @author FMD AE + * @brief This file contains all the functions prototypes for + * the I2S firmware library + * @version V1.0.0 + * @date 2025-04-01 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_I2S_H +#define __FT32F4XX_I2S_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup I2S + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t I2S_Channel0; /*!< Specifies the I2S channel 0 operating mode. + This parameter can be a value of @ref I2S_Channel0_Configuration */ + + uint32_t I2S_Channel1; /*!< Specifies the I2S channel 1 operating mode. + This parameter can be a value of @ref I2S_Channel1_Configuration */ + + uint32_t I2S_TranMasterSlaveConfig; /*!< Specifies the I2S transmitter master or slave. + This parameter can be a value of @ref I2S_MASTER_SLAVE */ + + uint32_t I2S_RecMasterSlaveConfig; /*!< Specifies the I2S receiver master or slave. + This parameter can be a value of @ref I2S_MASTER_SLAVE */ + + uint32_t I2S_TranSampleRate; /*!< Specifies the I2S transmit sample rate. + This parameter can be a value of @ref I2S_RATE */ + + uint32_t I2S_TranSampleResolution; /*!< Specifies the I2S transmit sample resolution. + This parameter can be a value of @ref I2S_RESOLUTION */ + + uint32_t I2S_RecSampleRate; /*!< Specifies the I2S receive sample rate. + This parameter can be a value of @ref I2S_RATE */ + + uint32_t I2S_RecSampleResolution; /*!< Specifies the I2S transmit sample resolution. + This parameter can be a value of @ref I2S_RESOLUTION */ + + uint32_t I2S_TFIFOAEmptyThreshold; /*!< Specifies the I2S transmit FIFO almost empty threshold + This parameter can be a value of @ref I2S_FIFO_THRESHOLD */ + + uint32_t I2S_TFIFOAFullThreshold; /*!< Specifies the I2S transmit FIFO almost full threshold + This parameter can be a value of @ref I2S_FIFO_THRESHOLD */ + + uint32_t I2S_RFIFOAEmptyThreshold; /*!< Specifies the I2S receive FIFO almost empty threshold + This parameter can be a value of @ref I2S_FIFO_THRESHOLD */ + + uint32_t I2S_RFIFOAFullThreshold; /*!< Specifies the I2S receive FIFO almost full threshold + This parameter can be a value of @ref I2S_FIFO_THRESHOLD */ + + uint32_t I2S_Standard; /*!< Specifies the standard used for the I2S communication + This parameter can be a value of @ref I2S_STANDARD */ +} I2S_InitTypeDef; +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2S_Exported_Constants I2S Exported Constants + * @{ + */ +/** @defgroup I2S_Periph + * @{ + */ +#define IS_I2S_ALL_PERIPH(PERIPH) (((PERIPH) == I2S2) || \ + ((PERIPH) == I2S3)) +/** + * @} + */ + +/** @defgroup I2S_Channel0_Configuration + * @{ + */ +#define I2S_Ch0_Disable ((uint32_t)0x00000000) +#define I2S_Ch0_Transmitter ((uint32_t)0x00000001) +#define I2S_Ch0_Receiver ((uint32_t)0x00000010) + +#define IS_I2S_CH0_CONFIG(CONFIG) (((CONFIG) == I2S_Ch0_Disable) || \ + ((CONFIG) == I2S_Ch0_Transmitter) || \ + ((CONFIG) == I2S_Ch0_Receiver)) +/** + * @} + */ + +/** @defgroup I2S_Channel1_Configuration + * @{ + */ +#define I2S_Ch1_Disable ((uint32_t)0x00000000) +#define I2S_Ch1_Transmitter ((uint32_t)0x00000001) +#define I2S_Ch1_Receiver ((uint32_t)0x00000010) + +#define IS_I2S_CH1_CONFIG(CONFIG) (((CONFIG) == I2S_Ch1_Disable) || \ + ((CONFIG) == I2S_Ch1_Transmitter) || \ + ((CONFIG) == I2S_Ch1_Receiver)) +/** + * @} + */ + +/** @defgroup I2S_MASTER_SLAVE + * @{ + */ +#define I2S_MASTER 0x00000000 +#define I2S_SLAVE 0x00000001 + + +#define IS_I2S_MASTERSLAVE_STATE(STATE) (((STATE) == I2S_MASTER) || \ + ((STATE) == I2S_SLAVE)) +/** + * @} + */ + +/** @defgroup I2S_SAMPLE_RATE + * @{ + */ +#define IS_I2S_SAMPLE_RATE(SAMPLE_RATE) ((SAMPLE_RATE) <= (uint16_t)0x7FF) +/** + * @} + */ + +/** @defgroup I2S_RESOLUTION + * @{ + */ +#define IS_I2S_RESOLUTION(RESOLUTION) ((RESOLUTION) <= (uint8_t)0x1F) +/** + * @} + */ + +/** @defgroup I2S_FIFO_THRESHOLD + * @{ + */ +#define IS_I2S_FIFO_THRESHOLD(FIFO_THRESHOLD) ((FIFO_THRESHOLD) <= (uint8_t)0x07) +/** + * @} + */ + +/** @defgroup I2S_STANDARD + * @{ + */ +#define I2S_Philips ((uint32_t)0x00000249) +#define I2S_Right_Justified ((uint32_t)0x000004D3) +#define I2S_Left_Justified ((uint32_t)0x000006DB) +#define I2S_DSP ((uint32_t)0x00000A69) + +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Philips) || \ + ((STANDARD) == I2S_Right_Justified) || \ + ((STANDARD) == I2S_Left_Justified) || \ + ((STANDARD) == I2S_DSP)) +/** + * @} + */ + +/** @defgroup I2S_CHANNEL_ENABLE + * @{ + */ +#define I2S_CH0 I2S_CTRL_I2SEN0 +#define I2S_CH1 I2S_CTRL_I2SEN1 + +#define IS_I2S_CHANNEL_SEL(CHy) (((CHy) == I2S_CH0) || \ + ((CHy) == I2S_CH1)) +/** + * @} + */ + +/** @defgroup I2S_CHANNEL_TRANSMITTER_OR_RECEIVER + * @{ + */ +#define I2S_CH0_TRANREC I2S_CTRL_TRCFG0 +#define I2S_CH1_TRANREC I2S_CTRL_TRCFG1 + +#define IS_I2S_CHANNEL_TRANREC(CHy_TRANREC) (((CHy_TRANREC) == I2S_CTRL_TRCFG0) || \ + ((CHy_TRANREC) == I2S_CTRL_TRCFG1)) +/** + * @} + */ +/** @defgroup I2S_TRANSMITTER_RECEIVER + * @{ + */ +#define I2S_TRANSMITTER 0x00000001 +#define I2S_RECEIVER 0x00000000 + +#define IS_I2S_TRANREC_STATE(STATE) (((STATE) == I2S_TRANSMITTER) || \ + ((STATE) == I2S_RECEIVER)) +/** + * @} + */ + +/** @defgroup I2S_CHANNEL_CLOCK_STROBE + * @{ + */ +#define I2S_CH0_CLOCK_STROBE I2S_CID_CTRL_I2SSTROBE0 +#define I2S_CH1_CLOCK_STROBE I2S_CID_CTRL_I2SSTROBE1 + +#define IS_I2S_CHANNEL_CLOCK_STROBE(CHy_CLOCK) (((CHy_CLOCK) == I2S_CID_CTRL_I2SSTROBE0) || \ + ((CHy_CLOCK) == I2S_CID_CTRL_I2SSTROBE1)) +/** + * @} + */ + +/** @defgroup I2S_SCK_POLAR + * @{ + */ +#define I2S_SCK_POLAR_RISE ((uint8_t)0x00) +#define I2S_SCK_POLAR_FALL ((uint8_t)0x01) + +#define IS_I2S_SCK_POLAR(SCK_POLAR) (((SCK_POLAR) == I2S_SCK_POLAR_FALL) || \ + ((SCK_POLAR) == I2S_SCK_POLAR_RISE)) +/** + * @} + */ + +/** @defgroup I2S_WS_POLAR + * @{ + */ +#define I2S_WS_POLAR_0 ((uint8_t)0x00) +#define I2S_WS_POLAR_1 ((uint8_t)0x01) + +#define IS_I2S_WS_POLAR(WS_POLAR) (((WS_POLAR) == I2S_WS_POLAR_0) || \ + ((WS_POLAR) == I2S_WS_POLAR_1)) +/** + * @} + */ + +/** @defgroup I2S_ALIGNMENT + * @{ + */ +#define I2S_ALIGN_LSB ((uint8_t)0x00) +#define I2S_ALIGN_MSB ((uint8_t)0x01) + +#define IS_I2S_ALIGNMENT(ALIGNMENT) (((ALIGNMENT) == I2S_ALIGN_LSB) || \ + ((ALIGNMENT) == I2S_ALIGN_MSB)) +/** + * @} + */ + +/** @defgroup I2S_TRAN_DATA_WS_DEL + * @{ + */ +#define I2S_TRAN_DATA_WS_DEL_0 ((uint8_t)0x00) +#define I2S_TRAN_DATA_WS_DEL_1 ((uint8_t)0x01) + +#define IS_I2S_TRAN_DATA_WS_DEL(DELAY) (((DELAY) == I2S_TRAN_DATA_WS_DEL_0) || \ + ((DELAY) == I2S_TRAN_DATA_WS_DEL_1)) +/** + * @} + */ + +/** @defgroup I2S_REC_DATA_WS_DEL + * @{ + */ +#define I2S_REC_DATA_WS_DEL_0 ((uint8_t)0x00) +#define I2S_REC_DATA_WS_DEL_1 ((uint8_t)0x01) + +#define IS_I2S_REC_DATA_WS_DEL(DELAY) (((DELAY) == I2S_REC_DATA_WS_DEL_0) || \ + ((DELAY) == I2S_REC_DATA_WS_DEL_1)) +/** + * @} + */ + +/** @defgroup I2S_WS_FORMAT + * @{ + */ +#define I2S_WS_PHILIPS ((uint8_t)0x00) +#define I2S_WS_DSP ((uint8_t)0x01) + +#define IS_I2S_WS_FORMAT(FORMAT) (((FORMAT) == I2S_WS_PHILIPS) || \ + ((FORMAT) == I2S_WS_DSP)) +/** + * @} + */ + +/** @defgroup I2S_registers + * @{ + */ +#define I2S_Register_CTRL ((uint8_t)0x00) +#define I2S_Register_INTR_STAT ((uint8_t)0x04) +#define I2S_Register_SRR ((uint8_t)0x08) +#define I2S_Register_CID_CTRL ((uint8_t)0x0C) +#define I2S_Register_TFIFO_STAT ((uint8_t)0x10) +#define I2S_Register_RFIFO_STAT ((uint8_t)0x14) +#define I2S_Register_TFIFO_CTRL ((uint8_t)0x18) +#define I2S_Register_RFIFO_CTRL ((uint8_t)0x1C) +#define I2S_Register_DEV_CONF ((uint8_t)0x20) +#define I2S_Register_POLL_STAT ((uint8_t)0x24) + +#define IS_I2S_REGISTER(REGISTER) (((REGISTER) == I2S_Register_CTRL ) || \ + ((REGISTER) == I2S_Register_INTR_STAT ) || \ + ((REGISTER) == I2S_Register_SRR ) || \ + ((REGISTER) == I2S_Register_CID_CTRL ) || \ + ((REGISTER) == I2S_Register_TFIFO_STAT) || \ + ((REGISTER) == I2S_Register_RFIFO_STAT) || \ + ((REGISTER) == I2S_Register_TFIFO_CTRL) || \ + ((REGISTER) == I2S_Register_RFIFO_CTRL) || \ + ((REGISTER) == I2S_Register_DEV_CONF ) || \ + ((REGISTER) == I2S_Register_POLL_STAT )) +/** + * @} + */ + +/** @defgroup I2S_interrupts_definition + * @{ + */ +#define I2S_IT_TDATAUNDERR I2S_INTR_STAT_TDATAUNDERR +#define I2S_IT_RDATAOVRERR I2S_INTR_STAT_RDATAOVRERR +#define I2S_IT_TFIFOEMPTY I2S_INTR_STAT_TFIFOEMPTY +#define I2S_IT_TFIFOAEMPTY I2S_INTR_STAT_TFIFOAEMPTY +#define I2S_IT_TFIFOFULL I2S_INTR_STAT_TFIFOFULL +#define I2S_IT_TFIFOAFULL I2S_INTR_STAT_TFIFOAFULL +#define I2S_IT_RFIFOEMPTY I2S_INTR_STAT_RFIFOEMPTY +#define I2S_IT_RFIFOAEMPTY I2S_INTR_STAT_RFIFOAEMPTY +#define I2S_IT_RFIFOFULL I2S_INTR_STAT_RFIFOFULL +#define I2S_IT_RFIFOAFULL I2S_INTR_STAT_RFIFOAFULL + +#define IS_I2S_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFF00EE) == 0x00) && ((IT) != 0x00)) + +#define IS_I2S_GET_IT(IT) (((IT) == I2S_IT_TDATAUNDERR) || ((IT) == I2S_IT_RDATAOVRERR) || \ + ((IT) == I2S_IT_TFIFOEMPTY) || ((IT) == I2S_IT_TFIFOAEMPTY) || \ + ((IT) == I2S_IT_TFIFOFULL) || ((IT) == I2S_IT_TFIFOAFULL) || \ + ((IT) == I2S_IT_RFIFOEMPTY) || ((IT) == I2S_IT_RFIFOAEMPTY) || \ + ((IT) == I2S_IT_RFIFOFULL) || ((IT) == I2S_IT_RFIFOAFULL)) +/** + * @} + */ + +/** @defgroup I2S_FIFO_IT_MASK + * @{ + */ +#define I2S_TFIFOEMPTY_MASK I2S_CID_CTRL_TFIFOEMPTYMASK +#define I2S_TFIFOAEMPTY_MASK I2S_CID_CTRL_TFIFOAEMPTYMASK +#define I2S_TFIFOFULL_MASK I2S_CID_CTRL_TFIFOFULLMASK +#define I2S_TFIFOAFULL_MASK I2S_CID_CTRL_TFIFOAFULLMASK +#define I2S_RFIFOEMPTY_MASK I2S_CID_CTRL_RFIFOEMPTYMASK +#define I2S_RFIFOAEMPTY_MASK I2S_CID_CTRL_RFIFOAEMPTYMASK +#define I2S_RFIFOFULL_MASK I2S_CID_CTRL_RFIFOFULLMASK +#define I2S_RFIFOAFULL_MASK I2S_CID_CTRL_RFIFOAFULLMASK + +#define IS_I2S_FIFO_IT_MASK(IT_MASK) (((IT_MASK) == I2S_TFIFOEMPTY_MASK) || \ + ((IT_MASK) == I2S_TFIFOAEMPTY_MASK) || \ + ((IT_MASK) == I2S_TFIFOFULL_MASK) || \ + ((IT_MASK) == I2S_TFIFOAFULL_MASK) || \ + ((IT_MASK) == I2S_RFIFOEMPTY_MASK) || \ + ((IT_MASK) == I2S_RFIFOAEMPTY_MASK) || \ + ((IT_MASK) == I2S_RFIFOFULL_MASK) || \ + ((IT_MASK) == I2S_RFIFOAFULL_MASK)) +/** + * @} + */ + +/** @defgroup I2S_DATA_IT_MASK + * @{ + */ +#define I2S_0_MASK I2S_CID_CTRL_I2SMASK0 +#define I2S_1_MASK I2S_CID_CTRL_I2SMASK1 + +#define IS_I2S_DATA_IT_MASK(IT_MASK) (((IT_MASK) == I2S_0_MASK) || \ + ((IT_MASK) == I2S_1_MASK)) +/** + * @} + */ + +/** @defgroup I2S_POLL_STAT + * @{ + */ +#define I2S_STAT_TFIFOEMPTY I2S_POLL_STAT_TXEMPTY +#define I2S_STAT_TFIFOAEMPTY I2S_POLL_STAT_TXAEMPTY +#define I2S_STAT_TXUNDERRUN I2S_POLL_STAT_TXUNDERRUN +#define I2S_STAT_RFIFOFULL I2S_POLL_STAT_RXFULL +#define I2S_STAT_RFIFOAFULL I2S_POLL_STAT_RXAFULL +#define I2S_STAT_RXOVERRUN I2S_POLL_STAT_RXOVERRUN + +#define IS_I2S_GET_STAT(STAT) (((STAT) == I2S_STAT_TFIFOEMPTY) || \ + ((STAT) == I2S_STAT_TFIFOAEMPTY) || \ + ((STAT) == I2S_STAT_TXUNDERRUN) || \ + ((STAT) == I2S_STAT_RFIFOFULL) || \ + ((STAT) == I2S_STAT_RFIFOAFULL) || \ + ((STAT) == I2S_STAT_RXOVERRUN)) +/** + * @} + */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/* Initialization and Configuration functions *********************************/ +void I2S_DeInit(I2S_TypeDef* I2Sx); +void I2S_Init(I2S_TypeDef* I2Sx, I2S_InitTypeDef* I2S_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void I2S_ChannelConfig(I2S_TypeDef* I2Sx, uint32_t CHy, FunctionalState NewState); +void I2S_ChannelTranRecConfig(I2S_TypeDef* I2Sx, uint32_t CHy_TRANREC, uint32_t I2S_TranRec); +void I2S_LoopBackCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_SFRResetCmd(I2S_TypeDef* I2Sx); +void I2S_TranMasterSlaveConfig(I2S_TypeDef* I2Sx, uint32_t I2S_MS); +void I2S_RecMasterSlaveConfig(I2S_TypeDef* I2Sx, uint32_t I2S_MS); +void I2S_TranSyncResetCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_RecSyncResetCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_TranSyncLoopBackCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_RecSyncLoopBackCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_TranSampleRateConfig(I2S_TypeDef* I2Sx, uint16_t SAMPLE_RATE); +void I2S_TranSampleResolutionConfig(I2S_TypeDef* I2Sx, uint8_t RESOLUTION); +void I2S_RecSampleRateConfig(I2S_TypeDef* I2Sx, uint16_t SAMPLE_RATE); +void I2S_RecSampleResolutionConfig(I2S_TypeDef* I2Sx, uint8_t RESOLUTION); +void I2S_ChannelClockConfig(I2S_TypeDef* I2Sx, uint32_t CHy_CLOCK, FunctionalState NewState); +void I2S_TranSyncUnitCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_RecSyncUnitCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_StandardConfig(I2S_TypeDef* I2Sx, uint32_t Standard); +void I2S_TranSckPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_SCK_Polar); +void I2S_RecSckPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_SCK_Polar); +void I2S_TranWSPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Polar); +void I2S_RecWSPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Polar); +void I2S_TranAPBAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align); +void I2S_RecAPBAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align); +void I2S_TranI2SAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align); +void I2S_RecI2SAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align); +void I2S_TranDataWSDelConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Tran_Data_WS_Del); +void I2S_RecDataWSDelConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Rec_Data_WS_Del); +void I2S_TranWSFormatConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Format); +void I2S_RecWSFormatConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Format); + +/* TX/RX FIFO control functions ***********************************************/ +void I2S_TFIFOResetCmd(I2S_TypeDef* I2Sx); +void I2S_RFIFOResetCmd(I2S_TypeDef* I2Sx); +uint8_t I2S_GetTranFIFOLevel(I2S_TypeDef* I2Sx); +uint8_t I2S_GetRecFIFOLevel(I2S_TypeDef* I2Sx); +void I2S_TFIFOAEmptyThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold); +void I2S_TFIFOAFullThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold); +void I2S_RFIFOAEmptyThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold); +void I2S_RFIFOAFullThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold); + +/* I2S registers management functions *****************************************/ +uint32_t I2S_ReadRegister(I2S_TypeDef* I2Sx, uint8_t I2S_Register); + +/* Data transfers management functions ****************************************/ +void I2S_SendData(I2S_TypeDef* I2Sx, uint32_t Data); +uint32_t I2S_ReceiveData(I2S_TypeDef* I2Sx); + +/* Interrupts and flags management functions **********************************/ +void I2S_AllITMaskCmd(I2S_TypeDef* I2Sx, FunctionalState NewState); +void I2S_FIFOITConfig(I2S_TypeDef* I2Sx, uint32_t I2S_IT_Mask, FunctionalState NewState); +void I2S_DataITConfig(I2S_TypeDef* I2Sx, uint32_t I2S_IT_Mask, FunctionalState NewState); +ITStatus I2S_GetITStatus(I2S_TypeDef* I2Sx, uint32_t I2S_IT); +void I2S_ClearITPendingBit(I2S_TypeDef* I2Sx, uint32_t I2S_IT); +uint8_t I2S_GetUnderrunCode(I2S_TypeDef* I2Sx); +uint8_t I2S_GetOverrunCode(I2S_TypeDef* I2Sx); +FlagStatus I2S_GetPollStatus(I2S_TypeDef* I2Sx, uint32_t I2S_Stat); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_I2S_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE*******************/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_iwdg.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_iwdg.h new file mode 100644 index 00000000000..c40f08c9c3d --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_iwdg.h @@ -0,0 +1,121 @@ +/** + ****************************************************************************** + * @file ft32f4xx_iwdg.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the IWDG + * firmware library. + * @version V1.0.0 + * @data 2025-03-05 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F407XE_IWDG_H +#define __FT32F407XE_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup IWDG + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup IWDG_Exported_Constants + * @{ + */ + +/** @defgroup IWDG_WriteAccess + * @{ + */ + +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) +#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ + ((ACCESS) == IWDG_WriteAccess_Disable)) +/** + * @} + */ + +/** @defgroup IWDG_prescaler + * @{ + */ + +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) +#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ + ((PRESCALER) == IWDG_Prescaler_8) || \ + ((PRESCALER) == IWDG_Prescaler_16) || \ + ((PRESCALER) == IWDG_Prescaler_32) || \ + ((PRESCALER) == IWDG_Prescaler_64) || \ + ((PRESCALER) == IWDG_Prescaler_128)|| \ + ((PRESCALER) == IWDG_Prescaler_256)) +/** + * @} + */ + +/** @defgroup IWDG_Flag + * @{ + */ + +#define IWDG_FLAG_PVU IWDG_SR_PVU +#define IWDG_FLAG_RVU IWDG_SR_RVU +#define IWDG_FLAG_WVU IWDG_SR_WVU +#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ + ((FLAG) == IWDG_FLAG_WVU)) + +#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) + +#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Prescaler and Counter configuration functions ******************************/ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_SetWindowValue(uint16_t WindowValue); + +/* IWDG activation function ***************************************************/ +void IWDG_Enable(void); + +/* Flag management function ***************************************************/ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_IWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_lptim.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_lptim.h new file mode 100644 index 00000000000..2f847d93334 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_lptim.h @@ -0,0 +1,410 @@ +/** + ****************************************************************************** + * @file ft32f4xx_lptim.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the LPTIM + * firmware library. + * @version V1.0.0 + * @data 2025-03-31 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_LPTIM_H +#define __FT32F4XX_LPTIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup LPTIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief LPTIM Init structure definition + */ + +typedef struct +{ + uint32_t Source; /*!< Selects the clock source. + This parameter can be a value of @ref LPTIM_Clock_Source */ + + uint32_t Prescaler; /*!< Specifies the counter clock Prescaler. + This parameter can be a value of @ref LPTIM_Clock_Prescaler */ + + uint32_t Polarity; /*!< Selects the polarity of the active edge for the counter unit + if the ULPTIM input is selected. + Note: This parameter is used only when Ultra low power clock source is used. + Note: If the polarity is configured on 'both edges', an auxiliary clock + (one of the Low power oscillator) must be active. + This parameter can be a value of @ref LPTIM_Clock_Polarity */ + + uint32_t Clock_SampleTime; /*!< Selects the clock sampling time to configure the clock glitch filter. + Note: This parameter is used only when Ultra low power clock source is used. + This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ + + uint32_t Trigger_Source; /*!< Selects the Trigger source. + This parameter can be a value of @ref LPTIM_Trigger_Source */ + + uint32_t Trigegr_ActiveEdge; /*!< Selects the Trigger active edge. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */ + + uint32_t Trigg_SampleTime; /*!< Selects the trigger sampling time to configure the clock glitch filter. + Note: This parameter is used only when an external trigger is used. + This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ + + uint32_t OutputPolarity; /*!< Specifies the Output polarity. + This parameter can be a value of @ref LPTIM_Output_Polarity */ + + uint32_t UpdateMode; /*!< Specifies whether the update of the autoreload and the compare + values is done immediately or after the end of current period. + This parameter can be a value of @ref LPTIM_Updating_Mode */ + + uint32_t CounterSource; /*!< Specifies whether the counter is incremented each internal event + or each external event. + This parameter can be a value of @ref LPTIM_Counter_Source */ + + uint32_t Input1Source; /*!< Specifies source selected for input1 (GPIO or comparator output). + This parameter can be a value of @ref LPTIM_Input1_Source */ + + uint32_t Input2Source; /*!< Specifies source selected for input2 (GPIO or comparator output). + Note: This parameter is used only for encoder feature so is used only + for LPTIM1 instance. + This parameter can be a value of @ref LPTIM_Input2_Source */ +} LPTIM_InitTypeDef; + + + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPTIM_Exported_Constants + * @{ + */ + +/** @defgroup LPTIM_Clock_Source LPTIM Clock Source + * @{ + */ +#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC 0x00000000U +#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL +#define IS_LPTIM_CLOCK_SOURCE(SOURCE) (((SOURCE) == LPTIM_CLOCKSOURCE_ULPTIM) || \ + ((SOURCE) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler + * @{ + */ +#define LPTIM_PRESCALER_DIV1 0x00000000U +#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0 +#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1 +#define LPTIM_PRESCALER_DIV8 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1) +#define LPTIM_PRESCALER_DIV16 LPTIM_CFGR_PRESC_2 +#define LPTIM_PRESCALER_DIV32 (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV64 (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2) +#define LPTIM_PRESCALER_DIV128 LPTIM_CFGR_PRESC +#define IS_LPTIM_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LPTIM_PRESCALER_DIV1 ) || \ + ((PRESCALER) == LPTIM_PRESCALER_DIV2 ) || \ + ((PRESCALER) == LPTIM_PRESCALER_DIV4 ) || \ + ((PRESCALER) == LPTIM_PRESCALER_DIV8 ) || \ + ((PRESCALER) == LPTIM_PRESCALER_DIV16 ) || \ + ((PRESCALER) == LPTIM_PRESCALER_DIV32 ) || \ + ((PRESCALER) == LPTIM_PRESCALER_DIV64 ) || \ + ((PRESCALER) == LPTIM_PRESCALER_DIV128)) + +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity + * @{ + */ +#define LPTIM_CLOCKPOLARITY_RISING 0x00000000U +#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 +#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 +#define IS_LPTIM_CLOCK_POLARITY(POLARITY) (((POLARITY) == LPTIM_CLOCKPOLARITY_RISING) || \ + ((POLARITY) == LPTIM_CLOCKPOLARITY_FALLING) || \ + ((POLARITY) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) + +/** + * @} + */ + +/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time + * @{ + */ +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION 0x00000000U +#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 +#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 +#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT +#define IS_LPTIM_CLOCK_SAMPLE_TIME(SAMPLETIME) (((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ + ((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ + ((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ + ((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) + +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source + * @{ + */ +//#define LPTIM_TRIGSOURCE_SOFTWARE 0x0000FFFFU +#define LPTIM_TRIGSOURCE_0 0x00000000U +#define LPTIM_TRIGSOURCE_1 LPTIM_CFGR_TRIGSEL_0 +#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 +#define LPTIM_TRIGSOURCE_3 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 +#define LPTIM_TRIGSOURCE_5 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_6 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_7 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_8 LPTIM_CFGR_TRIGSEL_3 +#define LPTIM_TRIGSOURCE_9 (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_3) +#define LPTIM_TRIGSOURCE_10 (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3) +#define LPTIM_TRIGSOURCE_11 (LPTIM_CFGR_TRIGSEL_0 |LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_3) +#define LPTIM_TRIGSOURCE_12 (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_3) +#define IS_LPTIM_TRG_SOURCE(TRIG) (((TRIG) == LPTIM_TRIGSOURCE_0) || \ + ((TRIG) == LPTIM_TRIGSOURCE_1) || \ + ((TRIG) == LPTIM_TRIGSOURCE_2) || \ + ((TRIG) == LPTIM_TRIGSOURCE_3) || \ + ((TRIG) == LPTIM_TRIGSOURCE_4) || \ + ((TRIG) == LPTIM_TRIGSOURCE_5) || \ + ((TRIG) == LPTIM_TRIGSOURCE_6) || \ + ((TRIG) == LPTIM_TRIGSOURCE_7) || \ + ((TRIG) == LPTIM_TRIGSOURCE_8) || \ + ((TRIG) == LPTIM_TRIGSOURCE_9) || \ + ((TRIG) == LPTIM_TRIGSOURCE_10)|| \ + ((TRIG) == LPTIM_TRIGSOURCE_11)|| \ + ((TRIG) == LPTIM_TRIGSOURCE_12)) + +/** + * @} + */ + +/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity + * @{ + */ +#define LPTIM_SOFTWARE 0x00000000 +#define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 +#define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 +#define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN +#define IS_LPTIM_EXT_TRG_POLARITY(POLARITY) (((POLARITY) == LPTIM_SOFTWARE ) || \ + ((POLARITY) == LPTIM_ACTIVEEDGE_RISING ) || \ + ((POLARITY) == LPTIM_ACTIVEEDGE_FALLING ) || \ + ((POLARITY) == LPTIM_ACTIVEEDGE_RISING_FALLING )) + +/** + * @} + */ + +/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time + * @{ + */ +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION 0x00000000U +#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 +#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 +#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT +#define IS_LPTIM_TRIG_SAMPLE_TIME(SAMPLETIME) (((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \ + ((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ + ((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ + ((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) + + +/** + * @} + */ + +/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity + * @{ + */ + +#define LPTIM_OUTPUTPOLARITY_HIGH 0x00000000U +#define LPTIM_OUTPUTPOLARITY_LOW LPTIM_CFGR_WAVPOL +#define IS_LPTIM_OUTPUT_POLARITY(POLARITY) (((POLARITY) == LPTIM_OUTPUTPOLARITY_LOW ) || \ + ((POLARITY) == LPTIM_OUTPUTPOLARITY_HIGH)) + +/** + * @} + */ + +/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode + * @{ + */ + +#define LPTIM_UPDATE_IMMEDIATE 0x00000000U +#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD +#define IS_LPTIM_UPDATE_MODE(MODE) (((MODE) == LPTIM_UPDATE_IMMEDIATE) || \ + ((MODE) == LPTIM_UPDATE_ENDOFPERIOD)) +/** + * @} + */ + +/** @defgroup LPTIM_Counter_Source LPTIM Counter Source + * @{ + */ + +#define LPTIM_COUNTERSOURCE_INTERNAL 0x00000000U +#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE +#define IS_LPTIM_COUNTER_SOURCE(SOURCE) (((SOURCE) == LPTIM_COUNTERSOURCE_INTERNAL) || \ + ((SOURCE) == LPTIM_COUNTERSOURCE_EXTERNAL)) +/** + * @} + */ + +/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source + * @{ + */ + +#define LPTIM_INPUT1SOURCE_GPIO 0x00000000U +#define LPTIM_INPUT1SOURCE_COMP1 LPTIM_OR_IN1_0 +#define LPTIM_INPUT1SOURCE_COMP3 (LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0) +#define LPTIM_INPUT1SOURCE_COMP5 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_0) +#define LPTIM_INPUT1SOURCE_COMP5_1 (LPTIM_OR_IN1_2 | LPTIM_OR_IN1_1 | LPTIM_OR_IN1_0) +#define IS_LPTIM_INPUT1_SOURCE(SOURCE) (((SOURCE) == LPTIM_INPUT1SOURCE_GPIO) || \ + ((SOURCE) == LPTIM_INPUT1SOURCE_COMP1) || \ + ((SOURCE) == LPTIM_INPUT1SOURCE_COMP3) || \ + ((SOURCE) == LPTIM_INPUT1SOURCE_COMP5) || \ + ((SOURCE) == LPTIM_INPUT1SOURCE_COMP5_1)) + +/** + * @} + */ + +/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source + * @{ + */ + +#define LPTIM_INPUT2SOURCE_GPIO 0x00000000U +#define LPTIM_INPUT2SOURCE_COMP2 LPTIM_OR_IN2_0 +#define LPTIM_INPUT2SOURCE_COMP4 (LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0) +#define LPTIM_INPUT2SOURCE_COMP6 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_0) +#define LPTIM_INPUT2SOURCE_COMP6_1 (LPTIM_OR_IN2_2 | LPTIM_OR_IN2_1 | LPTIM_OR_IN2_0) +#define IS_LPTIM_INPUT2_SOURCE(SOURCE) (((SOURCE) == LPTIM_INPUT2SOURCE_GPIO) || \ + ((SOURCE) == LPTIM_INPUT2SOURCE_COMP2) || \ + ((SOURCE) == LPTIM_INPUT2SOURCE_COMP4) || \ + ((SOURCE) == LPTIM_INPUT2SOURCE_COMP6) || \ + ((SOURCE) == LPTIM_INPUT2SOURCE_COMP6_1)) +/** + * @} + */ + +/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition + * @{ + */ + +#define LPTIM_FLAG_DOWN ((uint32_t)0x00000040) +#define LPTIM_FLAG_UP ((uint32_t)0x00000020) +#define LPTIM_FLAG_ARROK ((uint32_t)0x00000010) +#define LPTIM_FLAG_CMPOK ((uint32_t)0x00000008) +#define LPTIM_FLAG_EXTTRIG ((uint32_t)0x00000004) +#define LPTIM_FLAG_ARRM ((uint32_t)0x00000002) +#define LPTIM_FLAG_CMPM ((uint32_t)0x00000001) +/** + * @} + */ + +/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition + * @{ + */ +#define LPTIM_IT_DOWNIE ((uint32_t)0x00000040) +#define LPTIM_IT_UPIE ((uint32_t)0x00000020) +#define LPTIM_IT_ARROKIE ((uint32_t)0x00000010) +#define LPTIM_IT_CMPOKIE ((uint32_t)0x00000008) +#define LPTIM_IT_EXTTRIGIE ((uint32_t)0x00000004) +#define LPTIM_IT_ARRMIE ((uint32_t)0x00000002) +#define LPTIM_IT_CMPMIE ((uint32_t)0x00000001) +/** + * @} + */ + +#define IS_LPTIM_AUTORELOAD(AUTORELOAD) ((AUTORELOAD) <= 0x0000FFFFUL) + +#define IS_LPTIM_COMPARE(COMPARE) ((COMPARE) <= 0x0000FFFFUL) + +#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFUL) + +#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFUL) + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Initialization and Configuration functions *********************************/ +void LPTIM_DeInit(void); +void LPTIM_Init(LPTIM_InitTypeDef *LPTIM_InitStruct); +void LPTIM_StructInit(LPTIM_InitTypeDef *LPTIM_InitStruct); + +/* Reading/Write operation functions ************************************************/ +uint32_t LPTIM_ReadCounter(void); +uint32_t LPTIM_ReadAutoReload(void); +uint32_t LPTIM_ReadCompare(void); +void LPTIM_Write_ARRRegister(uint32_t Period); +void LPTIM_Write_CMPRegister(uint32_t Pulse); +void LPTIM_Preload_Config(FunctionalState NewState); + +/* Start/Stop operation functions *********************************************/ +/* ################################# PWM Mode ################################*/ +/* Blocking mode: Polling */ +void LPTIM_PWM_Start(uint32_t Period, uint32_t Pulse); +void LPTIM_PWM_Stop(void); + +/* ############################# One Pulse Mode ##############################*/ +/* Blocking mode: Polling */ +void LPTIM_OnePulse_Start(uint32_t Period, uint32_t Pulse); +void LPTIM_OnePulse_Stop(void); + +/* ############################## Set once Mode ##############################*/ +/* Blocking mode: Polling */ +void LPTIM_SetOnce_Start(uint32_t Period, uint32_t Pulse); +void LPTIM_SetOnce_Stop(void); + +/* ############################### Encoder Mode ##############################*/ +/* Blocking mode: Polling */ +void LPTIM_Encoder_Start(uint32_t Period); +void LPTIM_Encoder_Stop(void); + +/* ############################# Time out Mode ##############################*/ +/* Blocking mode: Polling */ +void LPTIM_TimeOut_Start(uint32_t Period, uint32_t Timeout); +void LPTIM_TimeOut_Stop(void); + +/* ############################## Counter Mode ###############################*/ +/* Blocking mode: Polling */ +void LPTIM_Counter_Start(uint32_t Period); +void LPTIM_Counter_Stop(void); + +/* LPTIM Reset ****************************************************************/ +void LPTIM_RSTARE(FunctionalState NewState); +void LPTIM_COUNTRST(void); + +/* LPTIM IRQ functions *******************************************************/ +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState); +uint32_t LPTIM_GetStatus(uint32_t LPTIM_ISR_FLAG); +void LPTIM_ClearFlag(uint32_t flag); +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_LPTIM_H */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_misc.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_misc.h new file mode 100644 index 00000000000..526f78b2959 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_misc.h @@ -0,0 +1,177 @@ +/** + ****************************************************************************** + * @file ft32f4xx_misc.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the miscellaneous + * firmware library functions (add-on to CMSIS functions). + * @version V1.0.0 + * @data 2025-07-01 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_MISC_H +#define __FT32F4XX_MISC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup STM32F4xx_StdPeriph_Driver + * @{ + */ + +/** @addtogroup MISC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief NVIC Init Structure definition + */ + +typedef struct +{ + uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be an enumerator of @ref IRQn_Type + enumeration (For the complete STM32 Devices IRQ Channels + list, please refer to stm32f4xx.h file) */ + + uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified + in NVIC_IRQChannel. This parameter can be a value + between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table + A lower priority value indicates a higher priority */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup MISC_Exported_Constants + * @{ + */ + +/** @defgroup MISC_Vector_Table_Base + * @{ + */ + +#define NVIC_VectTab_RAM ((uint32_t)0x20000000) +#define NVIC_VectTab_FLASH ((uint32_t)0x08000000) +#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ + ((VECTTAB) == NVIC_VectTab_FLASH)) +/** + * @} + */ + +/** @defgroup MISC_System_Low_Power + * @{ + */ + +#define NVIC_LP_SEVONPEND ((uint8_t)0x10) +#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) +#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) +#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ + ((LP) == NVIC_LP_SLEEPDEEP) || \ + ((LP) == NVIC_LP_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup MISC_Preemption_Priority_Group + * @{ + */ + +#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ + ((GROUP) == NVIC_PriorityGroup_1) || \ + ((GROUP) == NVIC_PriorityGroup_2) || \ + ((GROUP) == NVIC_PriorityGroup_3) || \ + ((GROUP) == NVIC_PriorityGroup_4)) + +#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) + +#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) + +/** + * @} + */ + +/** @defgroup MISC_SysTick_clock_source + * @{ + */ + +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) +#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ + ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup TICK_FREQ Tick Frequency + * @{ + */ +typedef enum +{ + TICK_FREQ_10HZ = 100U, + TICK_FREQ_100HZ = 10U, + TICK_FREQ_1KHZ = 1U, + TICK_FREQ_DEFAULT = TICK_FREQ_1KHZ +} TickFreqTypeDef; +/** + * @} + */ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); +void InitTick(uint32_t TickPriority, uint32_t SubPriority); +void IncTick(void); +uint32_t GetTick(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_MISC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_opamp.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_opamp.h new file mode 100644 index 00000000000..3756b5bd4d9 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_opamp.h @@ -0,0 +1,363 @@ +/** + ****************************************************************************** + * @file ft32f4xx_opamp.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the comparators (OPA1 and OPA2) peripheral + * applicable only on FT32F030 devices: + * + Comparators configuration + * + Window mode control + * @version V1.0.0 + * @data 2025-03-31 + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_OPAMP_H +#define __FT32F4XX_OPAMP_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +/* Exported types ------------------------------------------------------------*/ +/** @defgroup opamp Exported_Types opamp Exported Types + * @{ + */ +/** + * @brief opamp Init structure definition + */ +typedef struct +{ + + uint32_t OPA_VPSEL; /*!< Select the 1 level positive input of the OPA. + This parameter can be a value of @ref OPA_VPSEL */ + + uint32_t OPA_VMSEL; /*!< Select the 1 level negative input of the OPA. + This parameter can be a value of @ref OPA_VMSEL */ + + uint32_t OPA_VPSSEL; /*!< Select the 2 level positive input of the OPA. + This parameter can be a value of @ref OPA_VPSSEL */ + + uint32_t OPA_VMSSEL; /*!< Select the 2 level negative input of the OPA. + This parameter can be a value of @ref OPA_VMSSEL */ + + uint32_t T8_CM; /*!< Select the VM SEL of 1 or 2 level input by time8. + This parameter can be a value of @ref T8_CM*/ + + uint32_t T1_CM; /*!< Select the VM SEL of 1 or 2 level input by time1. + This parameter can be a value of @ref T1_CM */ + + uint32_t OPAHSM; /*!< Select the high or low speed of the OPA. + This parameter can be a value of @ref OPAHSM*/ + + uint32_t OPINTOEN; /*!< Select the output to pad or ADC inside. + This parameter can be a value of @ref OPINTOEN */ + + uint32_t O2PADSEL; /*!< Select the output pad of the OPA1 or OPA2. + This parameter can be a value of @ref O2PADSEL*/ + + uint32_t OPA_PGAGAIN; /*!< Select the amplification value. + This parameter can be a value of @ref OPA_PGAGAIN */ + +} OPA_InitTypeDef; + + +/** @defgroup OPAMP_Selection + * @{ + */ +#define OPAMP_1 ((uint32_t)0x00000001) /*!< OPAMP1 Selection */ +#define OPAMP_2 ((uint32_t)0x00000010) /*!< OPAMP2 Selection */ +#define OPAMP_3 ((uint32_t)0x00000100) /*!< OPAMP3 Selection */ + +#define IS_OPAX_PERIPH(PERIPH) (((PERIPH) == OPAMP_1) || \ + ((PERIPH) == OPAMP_2) || \ + ((PERIPH) == OPAMP_3)) + + +/** @defgroup OPA_VPSEL + * @{ + */ +#define OPA1_VIP_SEL_PA0 ((uint32_t)0x00000000) /*opamp1*/ +#define OPA1_VIP_SEL_PC3 ((uint32_t)0x00000002) +#define OPA1_VIP_SEL_PA6 ((uint32_t)0x00000004) +#define OPA1_VIP_SEL_PA2 ((uint32_t)0x00000006) +#define OPA1_VIP_SEL_DAC1 ((uint32_t)0x00000008) +#define OPA1_VIP_SEL_TRIM ((uint32_t)0x0000000a) +#define OPA1_VIP_SEL_VSSA ((uint32_t)0x0000000c) + +#define OPA2_VIP_SEL_PA6 ((uint32_t)0x00000000) /*opamp2*/ +#define OPA2_VIP_SEL_PB1 ((uint32_t)0x00000002) +#define OPA2_VIP_SEL_TRIM ((uint32_t)0x0000000a) +#define OPA2_VIP_SEL_VSSA ((uint32_t)0x0000000c) + +#define OPA3_VIP_SEL_PB11 ((uint32_t)0x00000000) /*opamp3*/ +#define OPA3_VIP_SEL_PB2 ((uint32_t)0x00000002) +#define OPA3_VIP_SEL_PC5 ((uint32_t)0x00000004) +#define OPA3_VIP_SEL_DAC2 ((uint32_t)0x00000008) +#define OPA3_VIP_SEL_TRIM ((uint32_t)0x0000000a) +#define OPA3_VIP_SEL_VSSA ((uint32_t)0x0000000c) + +#define IS_OPA_VIP_SEL(INPUT) (((INPUT) ==OPA1_VIP_SEL_PA0 ) || \ + ((INPUT) ==OPA1_VIP_SEL_PC3 ) || \ + ((INPUT) ==OPA1_VIP_SEL_PA6 ) || \ + ((INPUT) ==OPA1_VIP_SEL_PA2 ) || \ + ((INPUT) ==OPA1_VIP_SEL_DAC1 ) || \ + ((INPUT) ==OPA1_VIP_SEL_TRIM ) || \ + ((INPUT) ==OPA1_VIP_SEL_VSSA ) || \ + ((INPUT) ==OPA2_VIP_SEL_PA6 ) || \ + ((INPUT) ==OPA2_VIP_SEL_PB1 ) || \ + ((INPUT) ==OPA2_VIP_SEL_TRIM ) || \ + ((INPUT) ==OPA2_VIP_SEL_VSSA ) || \ + ((INPUT) ==OPA3_VIP_SEL_PB11 ) || \ + ((INPUT) ==OPA3_VIP_SEL_PB2 ) || \ + ((INPUT) ==OPA3_VIP_SEL_PC5 ) || \ + ((INPUT) ==OPA3_VIP_SEL_DAC2 ) || \ + ((INPUT) ==OPA3_VIP_SEL_TRIM ) || \ + ((INPUT) ==OPA3_VIP_SEL_VSSA ) ) + +/** @defgroup OPA_VMSEL + * @{ + */ +#define OPA1_VIM_SEL_PA1 ((uint32_t)0x00000000) /*opamp1*/ +#define OPA1_VIM_SEL_PC2 ((uint32_t)0x00000010) +#define OPA1_VIM_SEL_PA2 ((uint32_t)0x00000020) +#define OPA1_VIM_SEL_PA4 ((uint32_t)0x00000030) +#define OPA1_VIM_SEL_FOLLOW ((uint32_t)0x00000040) +#define OPA1_VIM_SEL_PGA ((uint32_t)0x00000050) + +#define OPA2_VIM_SEL_PA7 ((uint32_t)0x00000000) /*opamp2*/ +#define OPA2_VIM_SEL_PA4 ((uint32_t)0x00000010) +#define OPA2_VIM_SEL_FOLLOW ((uint32_t)0x00000040) +#define OPA2_VIM_SEL_PGA ((uint32_t)0x00000050) + +#define OPA3_VIM_SEL_PB11 ((uint32_t)0x00000000) /*opamp3*/ +#define OPA3_VIM_SEL_PB2 ((uint32_t)0x00000010) +#define OPA3_VIM_SEL_PC5 ((uint32_t)0x00000020) +#define OPA3_VIM_SEL_FOLLOW ((uint32_t)0x00000040) +#define OPA3_VIM_SEL_PGA ((uint32_t)0x00000050) + +#define IS_OPA_VIM_SEL(INPUT) (((INPUT)== OPA1_VIM_SEL_PA1 ) || \ + ((INPUT) == OPA1_VIM_SEL_PC2 ) || \ + ((INPUT) == OPA1_VIM_SEL_PA2 ) || \ + ((INPUT) == OPA1_VIM_SEL_PA4 ) || \ + ((INPUT) == OPA1_VIM_SEL_FOLLOW ) || \ + ((INPUT) == OPA1_VIM_SEL_PGA ) || \ + ((INPUT) == OPA2_VIM_SEL_PA7 ) || \ + ((INPUT) == OPA2_VIM_SEL_PA4 ) || \ + ((INPUT) == OPA2_VIM_SEL_FOLLOW ) || \ + ((INPUT) == OPA2_VIM_SEL_PGA ) || \ + ((INPUT) == OPA3_VIM_SEL_PB11 ) || \ + ((INPUT) == OPA3_VIM_SEL_PB2 ) || \ + ((INPUT) == OPA3_VIM_SEL_PC5 ) || \ + ((INPUT) == OPA3_VIM_SEL_FOLLOW ) || \ + ((INPUT) == OPA3_VIM_SEL_PGA )) + + +/** @defgroup OPA_VPSSEL + * @{ + */ +#define OPA1_VIPS_SEL_PA0 ((uint32_t)0x00000000) /*opamp1*/ +#define OPA1_VIPS_SEL_PC3 ((uint32_t)0x00000004) +#define OPA1_VIPS_SEL_PA6 ((uint32_t)0x00000008) +#define OPA1_VIPS_SEL_PA2 ((uint32_t)0x0000000c) +#define OPA1_VIPS_SEL_DAC1 ((uint32_t)0x00000010) +#define OPA1_VIPS_SEL_VSSA ((uint32_t)0x0000001c) + +#define OPA2_VIPS_SEL_PA6 ((uint32_t)0x00000000) /*opamp2*/ +#define OPA2_VIPS_SEL_PB1 ((uint32_t)0x00000002) +#define OPA2_VIPS_SEL_VSSA ((uint32_t)0x0000001c) + +#define OPA3_VIPS_SEL_PB11 ((uint32_t)0x00000000) /*opamp3*/ +#define OPA3_VIPS_SEL_PB2 ((uint32_t)0x00000002) +#define OPA3_VIPS_SEL_PC5 ((uint32_t)0x00000004) +#define OPA3_VIPS_SEL_DAC2 ((uint32_t)0x00000008) +#define OPA3_VIPS_SEL_VSSA ((uint32_t)0x0000000c) + +#define IS_OPA_VIPS_SEL(INPUT) (((INPUT) ==OPA1_VIPS_SEL_PA0 ) || \ + ((INPUT) ==OPA1_VIPS_SEL_PC3 ) || \ + ((INPUT) ==OPA1_VIPS_SEL_PA6 ) || \ + ((INPUT) ==OPA1_VIPS_SEL_PA2 ) || \ + ((INPUT) ==OPA1_VIPS_SEL_DAC1) || \ + ((INPUT) ==OPA1_VIPS_SEL_VSSA) || \ + ((INPUT) ==OPA2_VIPS_SEL_PA6) || \ + ((INPUT) ==OPA2_VIPS_SEL_PB1) || \ + ((INPUT) ==OPA2_VIPS_SEL_VSSA) || \ + ((INPUT) ==OPA3_VIPS_SEL_PB11) || \ + ((INPUT) ==OPA3_VIPS_SEL_PB2) || \ + ((INPUT) ==OPA3_VIPS_SEL_PC5) || \ + ((INPUT) ==OPA3_VIPS_SEL_DAC2) || \ + ((INPUT) ==OPA3_VIPS_SEL_VSSA)) + +/** @defgroup OPA_VMSSEL + * @{ + */ +#define OPA1_VIMS_SEL_00 ((uint32_t)0x00000000) /*opamp1*/ +#define OPA1_VIMS_SEL_01 ((uint32_t)0x00000001) +#define OPA1_VIMS_SEL_10 ((uint32_t)0x00000002) +#define OPA1_VIMS_SEL_11 ((uint32_t)0x00000003) + +#define OPA2_VIMS_SEL_00 ((uint32_t)0x00000000) /*opamp2*/ +#define OPA2_VIMS_SEL_01 ((uint32_t)0x00000001) +#define OPA2_VIMS_SEL_10 ((uint32_t)0x00000002) +#define OPA2_VIMS_SEL_11 ((uint32_t)0x00000003) + +#define OPA3_VIMS_SEL_00 ((uint32_t)0x00000000) /*opamp3*/ +#define OPA3_VIMS_SEL_01 ((uint32_t)0x00000001) +#define OPA3_VIMS_SEL_10 ((uint32_t)0x00000002) +#define OPA3_VIMS_SEL_11 ((uint32_t)0x00000003) + +#define IS_OPA_VIMS_SEL(INPUT) (((INPUT)==OPA1_VIMS_SEL_00) || \ + ((INPUT) ==OPA1_VIMS_SEL_01) || \ + ((INPUT) ==OPA1_VIMS_SEL_10) || \ + ((INPUT) ==OPA1_VIMS_SEL_11) || \ + ((INPUT) ==OPA2_VIMS_SEL_00) || \ + ((INPUT) ==OPA2_VIMS_SEL_01) || \ + ((INPUT) ==OPA2_VIMS_SEL_10) || \ + ((INPUT) ==OPA2_VIMS_SEL_11) || \ + ((INPUT) ==OPA3_VIMS_SEL_00) || \ + ((INPUT) ==OPA3_VIMS_SEL_01) || \ + ((INPUT) ==OPA3_VIMS_SEL_10) || \ + ((INPUT) ==OPA3_VIMS_SEL_11)) + + +/** @defgroup T8_CM + * @{ + */ +#define OPAMP_TIM8_EN ((uint32_t)0x00000000) /*!< DISABLE tim8 */ +#define OPAMP_TIM8_DIS ((uint32_t)0x00000040) /*!< ENABLE tim8 to AUTOchange */ + +#define IS_OPAX_TIM8_EN(SEL) (((SEL) == OPAMP_TIM8_EN) || \ + ((SEL) == OPAMP_TIM8_DIS)) + +/** @defgroup T1_CM + * @{ + */ +#define OPAMP_TIM1_EN ((uint32_t)0x00000000) /*!< DISABLE tim1 */ +#define OPAMP_TIM1_DIS ((uint32_t)0x00000020) /*!< ENABLE tim1 to AUTOchange */ + +#define IS_OPAX_TIM1_EN(SEL) (((SEL) == OPAMP_TIM1_EN) || \ + ((SEL) == OPAMP_TIM1_DIS)) + + + +/** @defgroup OPAHSM + * @{ + */ +#define OPAHSM_ENABLE ((uint32_t)0x00000080) +#define OPAHSM_DISABLE ((uint32_t)0x00000000) +#define IS_OPAX_OPAHSM(OPAHSM) (((OPAHSM) == OPAHSM_ENABLE ) || \ + ((OPAHSM) == OPAHSM_DISABLE)) + +/** @defgroup OPINTOEN + * @{ + */ +#define OPINTOEN_ENABLE ((uint32_t)0x00000100)//to ADC +#define OPINTOEN_DISABLE ((uint32_t)0x00000000)//to output pad and need O2PADSEL to select +#define IS_OPAX_OPINTOEN(OPINTOEN) (((OPINTOEN) == OPAHSM_ENABLE ) || \ + ((OPINTOEN) == OPAHSM_DISABLE)) + +/** @defgroup O2PADSEL + * @{ + */ +#define O2PADSEL_SEL_PAD1 ((uint32_t)0x00000200)//select pad1 +#define O2PADSEL_SEL_PAD2 ((uint32_t)0x00000000)//select pad2 +#define IS_OPAX_O2PADSEL(O2PADSEL) (((O2PADSEL) == O2PADSEL_SEL_PAD1 ) || \ + ((O2PADSEL) == O2PADSEL_SEL_PAD2)) + +/** @defgroup OPA_PGAGAIN + * @{ + */ +#define OPA_PGAGAIN_GAIN_P2 ((uint32_t)0x00000000) +#define OPA_PGAGAIN_GAIN_P4 ((uint32_t)0x00004000) +#define OPA_PGAGAIN_GAIN_P8 ((uint32_t)0x00008000) +#define OPA_PGAGAIN_GAIN_P16 ((uint32_t)0x0000C000) +#define OPA_PGAGAIN_GAIN_P32 ((uint32_t)0x00010000) +#define OPA_PGAGAIN_GAIN_P64 ((uint32_t)0x00014000) + +#define OPA_PGAGAIN_GAIN_M2_VINM0 ((uint32_t)0x00020000) +#define OPA_PGAGAIN_GAIN_M4_VINM0 ((uint32_t)0x00024000) +#define OPA_PGAGAIN_GAIN_M8_VINM0 ((uint32_t)0x00028000) +#define OPA_PGAGAIN_GAIN_M16_VINM0 ((uint32_t)0x0002c000) +#define OPA_PGAGAIN_GAIN_M32_VINM0 ((uint32_t)0x00030000) +#define OPA_PGAGAIN_GAIN_M64_VINM0 ((uint32_t)0x00034000) + +#define OPA_PGAGAIN_GAIN_FILTER_P2 ((uint32_t)0x00040000) +#define OPA_PGAGAIN_GAIN_FILTER_P4 ((uint32_t)0x00044000) +#define OPA_PGAGAIN_GAIN_FILTER_P8 ((uint32_t)0x00048000) +#define OPA_PGAGAIN_GAIN_FILTER_P16 ((uint32_t)0x0004c000) +#define OPA_PGAGAIN_GAIN_FILTER_P32 ((uint32_t)0x00050000) +#define OPA_PGAGAIN_GAIN_FILTER_P64 ((uint32_t)0x00054000) + +#define OPA_PGAGAIN_GAIN_M2_VINM0_VINM1FIL ((uint32_t)0x00060000) +#define OPA_PGAGAIN_GAIN_M4_VINM0_VINM1FIL ((uint32_t)0x00064000) +#define OPA_PGAGAIN_GAIN_M8_VINM0_VINM1FIL ((uint32_t)0x00068000) +#define OPA_PGAGAIN_GAIN_M16_VINM0_VINM1FIL ((uint32_t)0x0006c000) +#define OPA_PGAGAIN_GAIN_M32_VINM0_VINM1FIL ((uint32_t)0x00070000) +#define OPA_PGAGAIN_GAIN_M64_VINM0_VINM1FIL ((uint32_t)0x00074000) + +#define IS_OPA_PGAGAIN(INPUT) (((INPUT)==OPA_PGAGAIN_GAIN_P2 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_P4 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_P8 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_P16 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_P32 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_P64 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M2_VINM0 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M4_VINM0 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M8_VINM0 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M16_VINM0 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M32_VINM0 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M64_VINM0 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_FILTER_P2 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_FILTER_P4 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_FILTER_P8 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_FILTER_P16 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_FILTER_P32 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_FILTER_P64 ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M2_VINM0_VINM1FIL ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M4_VINM0_VINM1FIL ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M8_VINM0_VINM1FIL ) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M16_VINM0_VINM1FIL) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M32_VINM0_VINM1FIL) || \ + ((INPUT)==OPA_PGAGAIN_GAIN_M64_VINM0_VINM1FIL)) + + + +/** @defgroup OPAMP_CALSEL_SEL + * @{ + */ +#define OPAMP_VDDA003_CAL ((uint32_t)0x00000000) /*!< Selection:0.03VDDA */ +#define OPAMP_PMOS_CAL ((uint32_t)0x00001000) /*!< PMOS Selection:0.1VDDA */ +#define OPAMP_VDDA05_CAL ((uint32_t)0x00002000) /*!< Selection:0.5VDDA */ +#define OPAMP_NMOS_CAL ((uint32_t)0x00003000) /*!< NMOS Selection:0.9VDDA */ + +#define IS_OPAX_NPMOS(VOL) (((VOL) ==OPAMP_VDDA003_CAL ) || \ + ((VOL) ==OPAMP_PMOS_CAL ) || \ + ((VOL) ==OPAMP_VDDA05_CAL) || \ + ((VOL) ==OPAMP_NMOS_CAL )) + + +/* Initialization and Configuration functions *********************************/ +void OPA_Init(OPA_InitTypeDef* OPA_InitStruct, uint32_t OPAMP_Selection); +void OPA_DeInit(uint32_t OPAMP_Selection); +void OPA_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState); +/* Function used to set the COMP configuration to the default reset state ****/ +void OPAMP_Calibration(uint32_t OPAMP_Selection); + + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F0XX_OPAMP_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_ex_hs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_ex_hs.h new file mode 100644 index 00000000000..babff4e00f4 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_ex_hs.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pcd_ex_hs.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the + * >>->-USB_OTG_HS firmware library. + * @version V1.0.0 + * @data 2025-03-31 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_PCD_EX_HS_H +#define __FT32F4XX_PCD_EX_HS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_usb_hs.h" + +#if defined (USB_OTG_HS) +/** @addtogroup ft32f4xx Drive + * @ + */ + +/** @addtogroup PCD_HS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_HS_Exported_Types PCD Exported Types + * @{ + */ + +/** @defgroup PCD_HS_Exported_Types_Group1 PCD State Structure definition + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions + * @{ + */ +/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions + * @{ + */ + +#if defined (USB_OTG_HS) +void PCDEx_HS_SetTxFiFo(uint8_t fifo, uint16_t size); +void PCDEx_HS_SetRxFiFo(uint16_t size); +#endif /* defined (USB_OTG_HS) */ + + + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* FT32F4XX_PCD_HS_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_fs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_fs.h new file mode 100644 index 00000000000..abe78f1f5ed --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_fs.h @@ -0,0 +1,186 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pcd_fs.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the + * >>->-USB_OTG_FS firmware library. + * @version V1.0.0 + * @data 2025-06-04 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_PCD_FS_H +#define __FT32F4XX_PCD_FS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_usb_fs.h" + +#if defined (USB_OTG_FS) + + +/* Exported types ------------------------------------------------------------*/ + +#if defined (USB_OTG_FS) +void PCD_FS_SetTxFiFo(uint8_t fifo, uint16_t size, uint8_t dpb); +void PCD_FS_SetRxFiFo(uint8_t fifo, uint16_t size, uint8_t dpb); +#endif /* defined (USB_OTG_FS) */ + + +/** + * @brief PCD state structure definition + */ + +typedef enum +{ + PCD_FS_STATE_RESET = 0x00, + PCD_FS_STATE_READY = 0x01, + PCD_FS_STATE_ERROR = 0x02, + PCD_FS_STATE_BUSY = 0x03, + PCD_FS_STATE_TIMEOUT = 0x04 +} PCD_FS_StateTypeDef; + + + +#if defined (USB_OTG_FS) +typedef USB_OTG_FS_CfgTypeDef PCD_FS_InitTypeDef; +typedef USB_OTG_FS_DEPTypeDef PCD_FS_EPTypeDef; +typedef USB_FS_LockTypeDef PCD_FS_LockTypeDef; +typedef USB_OTG_FS_CtlStateTypeDef PCD_FS_CtlStateTypeDef; +#endif /* defined (USB_OTG_FS) */ + +/** + * @} + */ + +/** @brief PCD Handle Structure definition + * @{ + */ +typedef struct +{ + PCD_FS_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address;/*!< USB Address */ + PCD_FS_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_FS_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + PCD_FS_CtlStateTypeDef ctrl_state; + PCD_FS_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_FS_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[2]; /*!< Setup packet buffer */ + uint32_t FrameNumber;/*!< Store Current Frame number*/ + void *pData; /*!< Pointer Stack Handler */ +} PCD_FS_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ + +#define PCD_SPEED_FULL USB_FS_SPEED + +/* Exported macro ------------------------------------------------------------*/ + +#define __USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_FS_WAKEUP_EXTI_LINE +#define __USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE) +#define __USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE + +#define __USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE; \ + } while(0U) + + +/* Exported functions --------------------------------------------------------*/ + +USB_FS_StatusTypeDef PCD_FS_Init(PCD_FS_HandleTypeDef *hpcd); +USB_FS_StatusTypeDef PCD_FS_DeInit(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_SetISO(uint8_t ep_num, uint8_t state); +void PCD_FS_SetMaxPkt(uint8_t ep_num, uint16_t size); + +void PCD_FS_MspInit(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_MspDeInit(PCD_FS_HandleTypeDef *hpcd); + + +/* I/O operation functions ***************************************************/ + +USB_FS_StatusTypeDef PCD_FS_Start(PCD_FS_HandleTypeDef *hpcd); +USB_FS_StatusTypeDef PCD_FS_Stop(PCD_FS_HandleTypeDef *hpcd); + +/* Non-Blocking mode: Interrupt */ +void PCD_FS_IRQHandler(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_EP0_IRQHandler(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_TXEP_IRQHandler(PCD_FS_HandleTypeDef *hpcd, uint32_t epnum); +void PCD_FS_RXEP_IRQHandler(PCD_FS_HandleTypeDef *hpcd, uint32_t epnum); +void PCD_FS_WKUP_IRQHandler(void); + +void PCD_FS_SOFCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_SetupStageCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_ResetCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_SuspendCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_ResumeCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_ConnectCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_DisconnectCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_SessionCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_VBusErrCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_OVERRUNCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_UNDERRUNCallback(PCD_FS_HandleTypeDef *hpcd); +void PCD_FS_DERRCallback(PCD_FS_HandleTypeDef *hpcd); + +void PCD_FS_DataOutStageCallback(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum); +void PCD_FS_DataInStageCallback(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum); + +/* Peripheral Control functions **********************************************/ + +USB_FS_StatusTypeDef PCD_FS_DevDisconnect(PCD_FS_HandleTypeDef *hpcd); +USB_FS_StatusTypeDef PCD_FS_SetAddress(PCD_FS_HandleTypeDef *hpcd, uint8_t address); +USB_FS_StatusTypeDef PCD_FS_EP_Open(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +USB_FS_StatusTypeDef PCD_FS_Ep_Close(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr); +void PCD_FS_Ep_Receive(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +void PCD_FS_Ep_Transmit(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +USB_FS_StatusTypeDef PCD_FS_EP_SetStall(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr); +USB_FS_StatusTypeDef PCD_FS_EP_ClrStall(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr); +USB_FS_StatusTypeDef PCD_FS_EP_Flush(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr); +USB_FS_StatusTypeDef PCD_FS_EP_Abort(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr); +void PCD_FS_ActivateRemoteWakeup(void); +void PCD_FS_DeActivateRemoteWakeup(void); + +uint32_t PCD_FS_EP_GetRxCount(const PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr); +USB_FS_StatusTypeDef PCD_FS_EP_Close(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr); +void PCD_FS_EP_Receive(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +void PCD_FS_EP_Transmit(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +/* Peripheral State functions ************************************************/ + +PCD_FS_StateTypeDef PCD_FS_GetState(PCD_FS_HandleTypeDef const *hpcd); + + +/* Private constants ---------------------------------------------------------*/ + + +#if defined (USB_OTG_FS) +#define USB_OTG_FS_WAKEUP_EXTI_LINE (0x1U << 18) /*!< USB FS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_FS) */ + + + +/* Private constants ---------------------------------------------------------*/ + + +#endif /* defined (USB_OTG_FS) */ + +#ifdef __cplusplus +} +#endif + +#endif /* FT32F4XX_PCD_FS_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_hs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_hs.h new file mode 100644 index 00000000000..520a5c73280 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pcd_hs.h @@ -0,0 +1,304 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pcd_hs.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the + * >>->-USB_OTG_HS firmware library. + * @version V1.0.0 + * @data 2025-03-31 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_PCD_HS_H +#define __FT32F4XX_PCD_HS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_usb_hs.h" + +#if defined (USB_OTG_HS) +/** @addtogroup ft32f4xx Drive + * @ + */ + +/** @addtogroup PCD_HS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup PCD_HS_Exported_Types PCD Exported Types + * @{ + */ + +/** @defgroup PCD_HS_Exported_Types_Group1 PCD State Structure definition + * @{ + */ + +/** + * @brief PCD state structure definition + */ + +typedef enum +{ + PCD_HS_STATE_RESET = 0x00, + PCD_HS_STATE_READY = 0x01, + PCD_HS_STATE_ERROR = 0x02, + PCD_HS_STATE_BUSY = 0x03, + PCD_HS_STATE_TIMEOUT = 0x04 +} PCD_HS_StateTypeDef; + + + +#if defined (USB_OTG_HS) +typedef USB_OTG_HS_GlobalTypeDef PCD_HS_TypeDef; +typedef USB_OTG_HS_CfgTypeDef PCD_HS_InitTypeDef; +typedef USB_OTG_HS_EPTypeDef PCD_HS_EPTypeDef; +typedef USB_HS_LockTypeDef PCD_HS_LockTypeDef; +#endif /* defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** @brief PCD Handle Structure definition + * @{ + */ +typedef struct +{ + PCD_HS_InitTypeDef Init; /*!< PCD required parameters */ + __IO uint8_t USB_Address;/*!< USB Address */ + PCD_HS_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ + PCD_HS_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ + PCD_HS_LockTypeDef Lock; /*!< PCD peripheral status */ + __IO PCD_HS_StateTypeDef State; /*!< PCD communication state */ + __IO uint32_t ErrorCode; /*!< PCD Error code */ + uint32_t Setup[2]; /*!< Setup packet buffer */ + uint32_t FrameNumber;/*!< Store Current Frame number*/ + void *pData; /*!< Pointer Stack Handler */ +} PCD_HS_HandleTypeDef; +/** + * @} + */ + +/* Include PCD Extended module */ +#include "ft32f4xx_pcd_ex_hs.h" + + + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup PCD_HS_Exported_Constants PCD Exported Constants + * @{ + */ + +/** @defgroup PCD_Speed PCD Speed + * @{ + */ +#define PCD_SPEED_HIGH USBD_HS_SPEED +#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED +#define PCD_SPEED_FULL USBD_FS_SPEED +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup PCD_HS_Exported_Macros PCD Exported Macros + * @brief macros to handle interrupts and specific clock configurations + * @{ + */ +#define __PCD_HS_ENABLE() (void)USB_HS_EnableGlobalInt () +#define __PCD_HS_DISABLE() (void)USB_HS_DisableGlobalInt () + +#define __PCD_HS_GET_FLAG(__INTERRUPT__) ((USB_HS_ReadInterrupts()\ + & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __PCD_HS_GET_CH_FLAG(__chnum__, __INTERRUPT__) \ + ((USB_HS_ReadChInterrupts((__chnum__))\ + & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __PCD_HS_CLEAR_FLAG(__INTERRUPT__) ((USB_HS->GINTSTS) = (__INTERRUPT__)) +#define __PCD_HS_IS_INVALID_INTERRUPT() (USB_HS_ReadInterrupts() == 0U) + +#define __PCD_HS_UNGATE_PHYCLOCK() \ + *(__IO uint32_t *)((uint32_t)OTG_HS_BASE + USB_OTG_HS_PCGCCTL_BASE) &= ~(OTG_HS_PCGCCTL_STOPCLK) + +#define __PCD_HS_GATE_PHYCLOCK() \ + *(__IO uint32_t *)((uint32_t)OTG_HS_BASE + USB_OTG_HS_PCGCCTL_BASE) |= OTG_HS_PCGCCTL_STOPCLK + +#define __PCD_HS_IS_PHY_SUSPENDED() \ + ((*(__IO uint32_t *)((uint32_t)OTG_HS_BASE + USB_OTG_HS_PCGCCTL_BASE)) & 0x10U) + +#define __USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_OTG_HS_WAKEUP_EXTI_LINE +#define __USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE) +#define __USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() \ + do { \ + EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE); \ + EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE; \ + } while(0U) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup PCD_HS_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_HS_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +USB_HS_StatusTypeDef PCD_HS_Init(PCD_HS_HandleTypeDef *hpcd); +USB_HS_StatusTypeDef PCD_HS_DeInit(PCD_HS_HandleTypeDef *hpcd); + +void PCD_HS_MspInit(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_MspDeInit(PCD_HS_HandleTypeDef *hpcd); + +/** + * @} + */ + +/* I/O operation functions ***************************************************/ +/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +USB_HS_StatusTypeDef PCD_HS_Start(PCD_HS_HandleTypeDef *hpcd); +USB_HS_StatusTypeDef PCD_HS_Stop(PCD_HS_HandleTypeDef *hpcd); + +/* Non-Blocking mode: Interrupt */ +void PCD_HS_IRQHandler(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_WKUP_IRQHandler(void); + +void PCD_HS_SOFCallback(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_SetupStageCallback(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_ResetCallback(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_SuspendCallback(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_ResumeCallback(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_ConnectCallback(PCD_HS_HandleTypeDef *hpcd); +void PCD_HS_DisconnectCallback(PCD_HS_HandleTypeDef *hpcd); + +void PCD_HS_DataOutStageCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum); +void PCD_HS_DataInStageCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum); +void PCD_HS_ISOOUTIncompleteCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum); +void PCD_HS_ISOINIncompleteCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum); +void USBD_SET_ADDR_Callback(PCD_HS_HandleTypeDef *hpcd); + +/** + * @} + */ + +/* Peripheral Control functions **********************************************/ +/** @addtogroup PCD_HS_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ +USB_HS_StatusTypeDef PCD_HS_DevConnect(PCD_HS_HandleTypeDef *hpcd); +USB_HS_StatusTypeDef PCD_HS_DevDisconnect(PCD_HS_HandleTypeDef *hpcd); +USB_HS_StatusTypeDef PCD_HS_SetAddress(PCD_HS_HandleTypeDef *hpcd, uint8_t address); +USB_HS_StatusTypeDef PCD_HS_EP_Open(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); +USB_HS_StatusTypeDef PCD_HS_Ep_Close(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr); +void PCD_HS_Ep_Receive(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +void PCD_HS_Ep_Transmit(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +USB_HS_StatusTypeDef PCD_HS_EP_SetStall(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr); +USB_HS_StatusTypeDef PCD_HS_EP_ClrStall(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr); +USB_HS_StatusTypeDef PCD_HS_EP_Flush(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr); +USB_HS_StatusTypeDef PCD_HS_EP_Abort(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr); +void PCD_HS_ActivateRemoteWakeup(void); +void PCD_HS_DeActivateRemoteWakeup(void); + +void PCD_HS_SetTestMode(uint8_t testmode); + +uint32_t PCD_HS_EP_GetRxCount(PCD_HS_HandleTypeDef const *hpcd, uint8_t ep_addr); +USB_HS_StatusTypeDef PCD_HS_EP_Close(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr); +void PCD_HS_EP_Transmit(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +void PCD_HS_EP_Receive(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); +/** + * @} + */ + +/* Peripheral State functions ************************************************/ +/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions + * @{ + */ +PCD_HS_StateTypeDef PCD_HS_GetState(PCD_HS_HandleTypeDef const *hpcd); + +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Constants PCD Private Constants + * @{ + */ +/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt + * @{ + */ +#if defined (USB_OTG_HS) +#define USB_OTG_HS_WAKEUP_EXTI_LINE (0x1U << 20) /*!< USB HS EXTI Line WakeUp Interrupt */ +#endif /* defined (USB_OTG_HS) */ + + +/** + * @} + */ + + +#if defined (USB_OTG_HS) +#ifndef USB_OTG_DOEPINT_OTEPSPR +#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ + +#ifndef USB_OTG_DOEPMSK_OTEPSPRM +#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ + +#ifndef USB_OTG_DOEPINT_NAK +#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ +#endif /* defined USB_OTG_DOEPINT_NAK */ + +#ifndef USB_OTG_DOEPMSK_NAKM +#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NAKM */ + +#ifndef USB_OTG_DOEPINT_STPKTRX +#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ +#endif /* defined USB_OTG_DOEPINT_STPKTRX */ + +#ifndef USB_OTG_DOEPMSK_NYETM +#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ +#endif /* defined USB_OTG_DOEPMSK_NYETM */ +#endif /* defined (USB_OTG_HS) */ + + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup PCD_Private_Macros PCD Private Constants + * @{ + */ +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* FT32F4XX_PCD_HS_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pwr.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pwr.h new file mode 100644 index 00000000000..29acde4f759 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_pwr.h @@ -0,0 +1,251 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pwr.h + * @author Rwang + * @brief This file contains all the functions prototypes for the PWR firmware + * library. + * @version V1.0.0 + * @data 2025-03-24 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_PWR_H +#define __FT32F4XX_PWR_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + + +/** @addtogroup PWR + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PWR_Exported_Constants + * @{ + */ + +/** @defgroup PWR_Vbat_charge_Resistance_Choose + * @{ + */ + +#define PWR_Vbat_Charge_5k ((uint32_t)0x00000000) +#define PWR_Vbat_Charge_1point5k ((uint32_t)0x00000001) + +#define IS_PWR_VBAT_RES(RES) (((RES) == PWR_Vbat_Charge_5k) || \ + ((RES) == PWR_Vbat_Charge_1point5k) ) +/** + * @} + */ + +/** @defgroup PWR_Vos_Level_Choose + * @{ + */ + +#define PWR_VosLevel_0 PWR_CR_VOS_0 +#define PWR_VosLevel_1 PWR_CR_VOS_1 +#define PWR_VosLevel_2 PWR_CR_VOS_2 +#define PWR_VosLevel_3 PWR_CR_VOS_3 +#define IS_PWR_VOS_LEVEL(LEVEL) (((LEVEL) == PWR_VosLevel_0) || \ + ((LEVEL) == PWR_VosLevel_1) || \ + ((LEVEL) == PWR_VosLevel_2) || \ + ((LEVEL) == PWR_VosLevel_3) ) +/** + * @} + */ + +/** @defgroup PWR_PVDR_detection_level + * @brief + * @{ + */ +#define PWR_PVDRLevel_0 PWR_CR_PLSR_0 +#define PWR_PVDRLevel_1 PWR_CR_PLSR_1 +#define PWR_PVDRLevel_2 PWR_CR_PLSR_2 +#define PWR_PVDRLevel_3 PWR_CR_PLSR_3 +#define PWR_PVDRLevel_4 PWR_CR_PLSR_4 +#define PWR_PVDRLevel_5 PWR_CR_PLSR_5 +#define PWR_PVDRLevel_6 PWR_CR_PLSR_6 +#define PWR_PVDRLevel_7 PWR_CR_PLSR_7 + +#define IS_PWR_PVDR_LEVEL(LEVEL) (((LEVEL) == PWR_PVDRLevel_0) || ((LEVEL) == PWR_PVDRLevel_1)|| \ + ((LEVEL) == PWR_PVDRLevel_2) || ((LEVEL) == PWR_PVDRLevel_3)|| \ + ((LEVEL) == PWR_PVDRLevel_4) || ((LEVEL) == PWR_PVDRLevel_5)|| \ + ((LEVEL) == PWR_PVDRLevel_6) || ((LEVEL) == PWR_PVDRLevel_7) ) +/** + * @} + */ + +/** @defgroup PWR_PVDF_detection_level + * @brief + * @{ + */ +#define PWR_PVDFLevel_0 PWR_CR_PLSF_0 +#define PWR_PVDFLevel_1 PWR_CR_PLSF_1 +#define PWR_PVDFLevel_2 PWR_CR_PLSF_2 +#define PWR_PVDFLevel_3 PWR_CR_PLSF_3 +#define PWR_PVDFLevel_4 PWR_CR_PLSF_4 +#define PWR_PVDFLevel_5 PWR_CR_PLSF_5 +#define PWR_PVDFLevel_6 PWR_CR_PLSF_6 +#define PWR_PVDFLevel_7 PWR_CR_PLSF_7 + +#define IS_PWR_PVDF_LEVEL(LEVEL) (((LEVEL) == PWR_PVDFLevel_0) || ((LEVEL) == PWR_PVDFLevel_1)|| \ + ((LEVEL) == PWR_PVDFLevel_2) || ((LEVEL) == PWR_PVDFLevel_3)|| \ + ((LEVEL) == PWR_PVDFLevel_4) || ((LEVEL) == PWR_PVDFLevel_5)|| \ + ((LEVEL) == PWR_PVDFLevel_6) || ((LEVEL) == PWR_PVDFLevel_7) ) +/** + * @} + */ + +/** @defgroup PWR_WakeUp_Pins + * @{ + */ + +#define PWR_WakeUpPin_1 PWR_CSR_EWUP_PA0 +#define PWR_WakeUpPin_2 PWR_CSR_EWUP_PC13 +#define PWR_WakeUpPin_3 PWR_CSR_EWUP_PA2 +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \ + ((PIN) == PWR_WakeUpPin_3)) +/** + * @} + */ + +/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode + * @{ + */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower PWR_CR_LPDS +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ + ((REGULATOR) == PWR_Regulator_LowPower)) +/** + * @} + */ + + +/** @defgroup PWR_Sleep_mode_entry + * @{ + */ +#define PWR_SleepEntry_WFI ((uint8_t)0x01) +#define PWR_SleepEntry_WFE ((uint8_t)0x02) +#define PWR_SleepEntry_SLEEPONEXIT ((uint8_t)0x03) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SleepEntry_WFI) || ((ENTRY) == PWR_SleepEntry_WFE) || \ + ((ENTRY) == PWR_SleepEntry_SLEEPONEXIT)) +/** + * @} + */ + +/** @defgroup PWR_Stop_mode_entry + * @{ + */ +#define PWR_StopEntry_WFI ((uint8_t)0x01) +#define PWR_StopEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_StopEntry_WFI) || ((ENTRY) == PWR_StopEntry_WFE)) +/** + * @} + */ + +/** @defgroup PWR_Standby_mode_entry + * @{ + */ +#define PWR_StandbyEntry_WFI ((uint8_t)0x01) +#define PWR_StandbyEntry_WFE ((uint8_t)0x02) +#define IS_PWR_STANDBY_ENTRY(ENTRY) (((ENTRY) == PWR_StandbyEntry_WFI) || ((ENTRY) == PWR_StandbyEntry_WFE)) +/** + * @} + */ + + + +/** @defgroup PWR_Flag + * @{ + */ +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_BRR PWR_CSR_BRR +#define PWR_FLAG_VREFINTRDY PWR_CSR_VOSRDY +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \ + ((FLAG) == PWR_FLAG_VREFINTRDY)) +/** + * @} + */ + +/** @defgroup PWR_Flag_Clear + * @{ + */ +#define PWR_FLAG_CWU PWR_CR_CWUF +#define PWR_FLAG_CSB PWR_CR_CSBF +#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_CWU) || \ + ((FLAG) == PWR_FLAG_CSB)) +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the PWR configuration to the default reset state ******/ +void PWR_DeInit(void); + +/* Vbat charge and charge resistance choose function ******/ +void PWR_VbatCharge(FunctionalState NewState); +void PWR_VbatResConfig(uint32_t PWR_VbatRes); + +/* Main Voltage Regulator choose function ******/ +void PWR_VosLevelConfig(uint32_t PWR_VosLevel); + +/* Backup Domain Access function **********************************************/ +void PWR_BackupAccessCmd(FunctionalState NewState); + +/* PVD configuration functions ************************************************/ +void PWR_PVDEnable(FunctionalState NewState); +void PWR_PVDRLevelConfig(uint32_t PWR_PVDRLevel); +void PWR_PVDFLevelConfig(uint32_t PWR_PVDFLevel); + +/* PDROFF enable functions ************************************************/ +void PWR_PdroffEnable(FunctionalState NewState); + +/* WakeUp pins configuration functions ****************************************/ +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); + +/* Backup Regulator Enable ************************************************/ +void PWR_BreEnable(FunctionalState NewState); + +/* Low Power modes configuration functions ************************************/ +void PWR_EnterSleepMode(uint8_t PWR_SleepEntry); +void PWR_EnterStopMode(uint32_t PWR_Regulator, uint8_t PWR_StopEntry); +void PWR_EnterStandbyMode(uint8_t PWR_StandbyEntry); + +/* Flags management functions *************************************************/ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F0XX_PWR_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_qspi.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_qspi.h new file mode 100644 index 00000000000..b5935e6854b --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_qspi.h @@ -0,0 +1,732 @@ +/** + ****************************************************************************** + * @file ft32f4xx_qspi.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the QSPI + * firmware library. + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_QSPI_H +#define __FT32F4XX_QSPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup QSPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief QSPI Init structure definition + */ + +typedef struct +{ + + uint32_t QSPI_Protocol; /*!< Specifies which QSPI serial proptocol is selected. + This parameter can be a value of @ref QSPI_Protocol_Sel . */ + + uint32_t QSPI_Direction; /*!< Specifies the QSPI transfer mode. + This parameter can be a value of @ref QSPI_data_direction. */ + + uint32_t QSPI_SSTE; /*!< Specifies the QSPI NCSX Toggle Enable. + This parameter can be a value of @ref QSPI_SSTE_Enable . */ + + uint32_t QSPI_DataSize; /*!< Specifies the QSPI data size. + This parameter can be a value of @ref QSPI_data_size. */ + + uint32_t QSPI_SCPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref QSPI_Clock_Polarity. */ + + uint32_t QSPI_SCPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref QSPI_Clock_Phase */ + + uint32_t QSPI_SER; /*!< Specifies which NCSx line is selected. + This parameter can be a value of @ref QSPI_SER_SEL. */ + + uint32_t QSPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value (15-bits) between 0x0 and 0xEFFF. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint32_t QSPI_CS_MIN_HIGH; /*!< Specifies the CS mini high time + This parameter can be a value (8 bits) between 0x0 and 0xF. */ + + uint32_t QSPI_DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) + This parameter can be a value of @ref QSPI_DataMode */ + +} QSPI_InitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_Exported_Constants + * @{ + */ + + +/** @defgroup + * @{ + */ + +#define QSPI_STANDARD ((uint32_t)0x00000000) +#define QSPI_DUAL ((uint32_t)0x00400000) +#define QSPI_QUAD ((uint32_t)0x00800000) +#define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_STANDARD) || \ + ((MODE) == QSPI_DUAL) || \ + ((MODE) == QSPI_QUAD)) +/** + * @} + */ + +/** @defgroup QSPI_SER_SEL + * @{ + */ + +#define QSPI_NCS0 ((uint32_t)0x00000001) +#define QSPI_NCS1 ((uint32_t)0x00000002) +#define IS_QSPI_SER_SEL(MODE) (((MODE) == QSPI_NCS0) || \ + ((MODE) == QSPI_NCS1)) +/** + * @} + */ + +/** @defgroup QSPI_data_direction + * @{ + */ + +#define QSPI_DIRECTION_Tx_AND_Rx ((uint32_t)0x00000000) +#define QSPI_DIRECTION_Tx_ONLY ((uint32_t)0x00000400) +#define QSPI_DIRECTION_Rx_ONLY ((uint32_t)0x00000800) +#define QSPI_DIRECTION_EEPROM_READ ((uint32_t)0x00000C00) +#define IS_QSPI_DIRECTION_MODE(MODE) (((MODE) == QSPI_DIRECTION_Tx_AND_Rx) || \ + ((MODE) == QSPI_DIRECTION_Tx_ONLY) || \ + ((MODE) == QSPI_DIRECTION_Rx_ONLY) || \ + ((MODE) == QSPI_DIRECTION_EEPROM_READ)) +/** + * @} + */ + +/** @defgroup QSPI_SSTE_Enable + * @{ + */ + +#define QSPI_SSTE_TOGGLE_DIS ((uint32_t)0x00000000) +#define QSPI_SSTE_TOGGLE_EN ((uint32_t)0x00004000) +#define IS_QSPI_SSTE(MODE) (((MODE) == QSPI_TOGGLE_DIS) || \ + ((MODE) == QSPI_TOGGLE_EN)) +/** + * @} + */ + + + +/** @defgroup QSPI_data_size + * @{ + */ + +#define QSPI_DATASIZE_4B ((uint32_t)0x00000003) +#define QSPI_DATASIZE_5B ((uint32_t)0x00000004) +#define QSPI_DATASIZE_6B ((uint32_t)0x00000005) +#define QSPI_DATASIZE_7B ((uint32_t)0x00000006) +#define QSPI_DATASIZE_8B ((uint32_t)0x00000007) +#define QSPI_DATASIZE_9B ((uint32_t)0x00000008) +#define QSPI_DATASIZE_10B ((uint32_t)0x00000009) +#define QSPI_DATASIZE_11B ((uint32_t)0x0000000a) +#define QSPI_DATASIZE_12B ((uint32_t)0x0000000b) +#define QSPI_DATASIZE_13B ((uint32_t)0x0000000c) +#define QSPI_DATASIZE_14B ((uint32_t)0x0000000d) +#define QSPI_DATASIZE_15B ((uint32_t)0x0000000e) +#define QSPI_DATASIZE_16B ((uint32_t)0x0000000f) +#define QSPI_DATASIZE_17B ((uint32_t)0x00000010) +#define QSPI_DATASIZE_18B ((uint32_t)0x00000011) +#define QSPI_DATASIZE_19B ((uint32_t)0x00000012) +#define QSPI_DATASIZE_20B ((uint32_t)0x00000013) +#define QSPI_DATASIZE_21B ((uint32_t)0x00000014) +#define QSPI_DATASIZE_22B ((uint32_t)0x00000015) +#define QSPI_DATASIZE_23B ((uint32_t)0x00000016) +#define QSPI_DATASIZE_24B ((uint32_t)0x00000017) +#define QSPI_DATASIZE_25B ((uint32_t)0x00000018) +#define QSPI_DATASIZE_26B ((uint32_t)0x00000019) +#define QSPI_DATASIZE_27B ((uint32_t)0x0000001a) +#define QSPI_DATASIZE_28B ((uint32_t)0x0000001b) +#define QSPI_DATASIZE_29B ((uint32_t)0x0000001c) +#define QSPI_DATASIZE_30B ((uint32_t)0x0000001d) +#define QSPI_DATASIZE_31B ((uint32_t)0x0000001e) +#define QSPI_DATASIZE_32B ((uint32_t)0x0000001f) +#define IS_QSPI_DATA_SIZE(SIZE) (((SIZE) == QSPI_DATASIZE_4B) || \ + ((SIZE) == QSPI_DATASIZE_5B) || \ + ((SIZE) == QSPI_DATASIZE_6B) || \ + ((SIZE) == QSPI_DATASIZE_7B) || \ + ((SIZE) == QSPI_DATASIZE_8B) || \ + ((SIZE) == QSPI_DATASIZE_9B) || \ + ((SIZE) == QSPI_DATASIZE_10B) || \ + ((SIZE) == QSPI_DATASIZE_11B) || \ + ((SIZE) == QSPI_DATASIZE_12B) || \ + ((SIZE) == QSPI_DATASIZE_13B) || \ + ((SIZE) == QSPI_DATASIZE_14B) || \ + ((SIZE) == QSPI_DATASIZE_15B) || \ + ((SIZE) == QSPI_DATASIZE_16B) || \ + ((SIZE) == QSPI_DATASIZE_17B) || \ + ((SIZE) == QSPI_DATASIZE_18B) || \ + ((SIZE) == QSPI_DATASIZE_19B) || \ + ((SIZE) == QSPI_DATASIZE_20B) || \ + ((SIZE) == QSPI_DATASIZE_21B) || \ + ((SIZE) == QSPI_DATASIZE_22B) || \ + ((SIZE) == QSPI_DATASIZE_23B) || \ + ((SIZE) == QSPI_DATASIZE_24B) || \ + ((SIZE) == QSPI_DATASIZE_25B) || \ + ((SIZE) == QSPI_DATASIZE_26B) || \ + ((SIZE) == QSPI_DATASIZE_27B) || \ + ((SIZE) == QSPI_DATASIZE_28B) || \ + ((SIZE) == QSPI_DATASIZE_29B) || \ + ((SIZE) == QSPI_DATASIZE_30B) || \ + ((SIZE) == QSPI_DATASIZE_31B) || \ + ((SIZE) == QSPI_DATASIZE_32B)) +/** + * @} + */ + +/** @defgroup QSPI_Microwire_CFS + * @{ + */ +#define QSPI_CFS_1B ((uint32_t)0x00000000) +#define QSPI_CFS_2B ((uint32_t)0x00010000) +#define QSPI_CFS_3B ((uint32_t)0x00020000) +#define QSPI_CFS_4B ((uint32_t)0x00030000) +#define QSPI_CFS_5B ((uint32_t)0x00040000) +#define QSPI_CFS_6B ((uint32_t)0x00050000) +#define QSPI_CFS_7B ((uint32_t)0x00060000) +#define QSPI_CFS_8B ((uint32_t)0x00070000) +#define QSPI_CFS_9B ((uint32_t)0x00080000) +#define QSPI_CFS_10B ((uint32_t)0x00090000) +#define QSPI_CFS_11B ((uint32_t)0x000a0000) +#define QSPI_CFS_12B ((uint32_t)0x000b0000) +#define QSPI_CFS_13B ((uint32_t)0x000c0000) +#define QSPI_CFS_14B ((uint32_t)0x000d0000) +#define QSPI_CFS_15B ((uint32_t)0x000e0000) +#define QSPI_CFS_16B ((uint32_t)0x000f0000) +#define IS_QSPI_CFS_SIZE(SIZE) (((SIZE) == QSPI_CFS_1B) || \ + ((SIZE) == QSPI_CFS_2B) || \ + ((SIZE) == QSPI_CFS_3B) || \ + ((SIZE) == QSPI_CFS_4B) || \ + ((SIZE) == QSPI_CFS_5B) || \ + ((SIZE) == QSPI_CFS_6B) || \ + ((SIZE) == QSPI_CFS_7B) || \ + ((SIZE) == QSPI_CFS_8B) || \ + ((SIZE) == QSPI_CFS_9B) || \ + ((SIZE) == QSPI_CFS_10B) || \ + ((SIZE) == QSPI_CFS_11B) || \ + ((SIZE) == QSPI_CFS_12B) || \ + ((SIZE) == QSPI_CFS_13B) || \ + ((SIZE) == QSPI_CFS_14B) || \ + ((SIZE) == QSPI_CFS_15B) || \ + ((SIZE) == QSPI_CFS_16B)) + +/** + * @} + */ + + +/** @defgroup QSPI_Clock_Polarity + * @{ + */ + +#define QSPI_SCPOL_LOW ((uint32_t)0x00000000) +#define QSPI_SCPOL_HIGH ((uint32_t)0x00000200) +#define IS_QSPI_SCPOL(SCPOL) (((SCPOL) == QSPI_CPOL_LOW) || \ + ((SCPOL) == QSPI_CPOL_HIGH)) +/** + * @} + */ + +/** @defgroup QSPI_Clock_Phase + * @{ + */ + +#define QSPI_SCPHA_1EDGE ((uint32_t)0x00000000) +#define QSPI_SCPHA_2EDGE ((uint32_t)0x00000100) +#define IS_QSPI_SCPHA(SCPHA) (((SCPHA) == QSPI_CPHA_1EDGE) || \ + ((SCPHA) == QSPI_CPHA_2EDGE)) +/** + * @} + */ + +/** @defgroup QSPI_Protocol_Sel + * @{ + */ + +#define QSPI_PROTOCOL_SPI ((uint32_t)0x00000000) +#define QSPI_PROTOCOL_SSP ((uint32_t)0x00000040) +#define QSPI_PROTOCOL_MICROWIRE ((uint32_t)0x00000080) +#define IS_QSPI_PROPTOCOL(PROTOCOL) (((PROTOCOL) == QSPI_PROTOCOL_QSPI) || \ + ((PROTOCOL) == QSPI_PROTOCOL_SSP) || \ + ((PROTOCOL) == QSPI_Protocol_MICROWIRE)) +/** + * @} + */ + +/** @defgroup QSPI_Opration_Mode + * @{ + */ + +#define QSPI_NORMAL_MODE ((uint32_t)0x00000000) +#define QSPI_TESTING_MODE ((uint32_t)0x00002000) +#define IS_QSPI_OPERATION_MODE(MODE) (((MODE) == QSPI_NORMAL_MODE) || \ + ((MODE) == QSPI_TESTING_MODE)) +/** + * @} + */ + +/** @defgroup QSPI_TDMA_EN + * @{ + */ + +#define QSPI_TDMA_DIS ((uint32_t)0x00000000) +#define QSPI_TDMA_EN ((uint32_t)0x00000002) +#define IS_QSPI_TDMA_MODE(MODE) (((MODE) == QSPI_TDMA_DIS) || \ + ((MODE) == QSPI_TDMA_EN)) +/** + * @} + */ + +/** @defgroup QSPI_RDMA_EN + * @{ + */ + +#define QSPI_RDMA_DIS ((uint32_t)0x00000000) +#define QSPI_RDMA_EN ((uint32_t)0x00000001) +#define IS_QSPI_RDMA_MODE(MODE) (((MODE) == QSPI_RDMA_DIS) || \ + ((MODE) == QSPI_RDMA_EN)) +/** + * @} + */ + +/** @defgroup QSPI_Clk_Loop_EN + * @{ + */ + +#define QSPI_CLK_LOOP_DIS ((uint32_t)0x00000000) +#define QSPI_CLK_LOOP_EN ((uint32_t)0x04000000) +#define IS_QSPI_CLK_LOOP_EN(MODE) (((MODE) == QSPI_CLK_LOOP_DIS) || \ + ((MODE) == QSPI_CLK_LOOP_EN)) +/** + * @} + */ + +/** @defgroup QSPI_Read_strobe_En. + * @{ + */ +#define QSPI_READ_STROBE_DIS ((uint32_t)0x00000000) +#define QSPI_READ_STROBE_EN ((uint32_t)0x00040000) +#define IS_QSPI_RXDS_EN(MODE) (((MODE) == QSPI_READ_STROBE_DIS) || \ + ((MODE) == QSPI_READ_STROBE_EN)) + +/** + * @} + */ + +/** @defgroup QSPI_Variable_Laten + * @{ + */ +#define QSPI_VARIABLE_LATEN_DIS ((uint32_t)0x00000000) +#define QSPI_VARIABLE_LATEN_EN ((uint32_t)0x00800000) +#define IS_QSPI_VL_EN(MODE) (((MODE) == QSPI_VARIABLE_LATEN_DIS) || \ + ((MODE) == QSPI_VARIABLE_LATEN_EN)) + +/** + * @} + */ + +/** @defgroup QSPI_Sample_Edge. + * @{ + */ +#define QSPI_SAMPLE_POSEDGE ((uint32_t)0x00000000) +#define QSPI_SAMPLE_NEGEDGE ((uint32_t)0x00010000) +#define IS_QSPI_SAMPLE_DLY_EDGE(MODE) (((MODE) == QSPI_SAMPLE_POSEDGE) || \ + ((MODE) == QSPI_SAMPLE_NEGEDGE)) +/** + * @} + */ + +/** @defgroup QSPI_InstructionSize + * @{ + */ +#define QSPI_INSTRUCTION_0B ((uint32_t)0x00000000) +#define QSPI_INSTRUCTION_4B ((uint32_t)0x00000100) +#define QSPI_INSTRUCTION_8B ((uint32_t)0x00000200) +#define QSPI_INSTRUCTION_16B ((uint32_t)0x00000300) +#define IS_QSPI_INSTRUCTIONSIZE(SIZE) (((SIZE) == QSPI_INSTRUCTION_0B) || \ + ((SIZE) == QSPI_INSTRUCTION_4B) || \ + ((SIZE) == QSPI_INSTRUCTION_8B) || \ + ((SIZE) == QSPI_INSTRUCTION_16B)) +/** + * @} + */ + +/** @defgroup QSPI_AddressSize + * @{ + */ +#define QSPI_ADDRESS_0B ((uint32_t)0x00000000) +#define QSPI_ADDRESS_4B ((uint32_t)0x00000004) +#define QSPI_ADDRESS_8B ((uint32_t)0x00000008) +#define QSPI_ADDRESS_12B ((uint32_t)0x0000000c) +#define QSPI_ADDRESS_16B ((uint32_t)0x00000010) +#define QSPI_ADDRESS_20B ((uint32_t)0x00000014) +#define QSPI_ADDRESS_24B ((uint32_t)0x00000018) +#define QSPI_ADDRESS_28B ((uint32_t)0x0000001c) +#define QSPI_ADDRESS_32B ((uint32_t)0x00000020) +#define QSPI_ADDRESS_36B ((uint32_t)0x00000024) +#define QSPI_ADDRESS_40B ((uint32_t)0x00000028) +#define QSPI_ADDRESS_44B ((uint32_t)0x0000002c) +#define QSPI_ADDRESS_48B ((uint32_t)0x00000030) +#define QSPI_ADDRESS_52B ((uint32_t)0x00000034) +#define QSPI_ADDRESS_56B ((uint32_t)0x00000038) +#define QSPI_ADDRESS_60B ((uint32_t)0x0000003c) +#define IS_QSPI_ADDRESSSIZE(SIZE) (((SIZE) == QSPI_ADDRESS_0B) || \ + ((SIZE) == QSPI_ADDRESS_4B) || \ + ((SIZE) == QSPI_ADDRESS_8B) || \ + ((SIZE) == QSPI_ADDRESS_12B) || \ + ((SIZE) == QSPI_ADDRESS_16B) || \ + ((SIZE) == QSPI_ADDRESS_20B) || \ + ((SIZE) == QSPI_ADDRESS_24B) || \ + ((SIZE) == QSPI_ADDRESS_28B) || \ + ((SIZE) == QSPI_ADDRESS_32B) || \ + ((SIZE) == QSPI_ADDRESS_36B) || \ + ((SIZE) == QSPI_ADDRESS_40B) || \ + ((SIZE) == QSPI_ADDRESS_44B) || \ + ((SIZE) == QSPI_ADDRESS_48B) || \ + ((SIZE) == QSPI_ADDRESS_52B) || \ + ((SIZE) == QSPI_ADDRESS_56B) || \ + ((SIZE) == QSPI_ADDRESS_60B)) +/** + * @} + */ + +/** @defgroup QSPI_ModeBitsSize + * @{ + */ +#define QSPI_MODEBITS_2B ((uint32_t)0x00000000) +#define QSPI_MODEBITS_4B ((uint32_t)0x04000000) +#define QSPI_MODEBITS_8B ((uint32_t)0x08000000) +#define QSPI_MODEBITS_16B ((uint32_t)0x0c000000) +#define IS_QSPI_MODEBITSSIZE(SIZE) (((SIZE) == QSPI_MODEBITS_2B) || \ + ((SIZE) == QSPI_MODEBITS_4B) || \ + ((SIZE) == QSPI_MODEBITS_8B) || \ + ((SIZE) == QSPI_MODEBITS_16B)) +/** + * @} + */ +/** @defgroup QSPI_XIPInstructionEn + * @{ + */ +#define QSPI_INSTRUCTION_DIS ((uint32_t)0x00000000) +#define QSPI_INSTRUCTION_EN ((uint32_t)0x00100000) +#define IS_QSPI_INSTRUCTION(MODE) (((MODE) == QSPI_INSTRUCTION_DIS) || \ + ((MODE) == QSPI_INSTRUCTION_EN)) +/** + * @} + */ + +/** @defgroup QSPI_ModeBitsEn + * @{ + */ +#define QSPI_MODEBITS_DIS ((uint32_t)0x00000000) +#define QSPI_MODEBITS_EN ((uint32_t)0x00000080) +#define IS_QSPI_MODEBITS(MODE) (((MODE) == QSPI_MODEBITS_DIS) || \ + ((MODE) == QSPI_MODEBITS_EN)) +/** + * @} + */ + +/** @defgroup QSPI_transType + * @{ + */ +#define QSPI_TRANSTYPE_STAND ((uint32_t)0x00000000) +#define QSPI_TRANSTYPE_MIX ((uint32_t)0x00000001) +#define QSPI_TRANSTYPE_FRF ((uint32_t)0x00000002) +#define IS_QSPI_TRANSTYPE(MODE) (((MODE) == QSPI_TRANSTYPE_STAND) || \ + ((MODE) == QSPI_TRANSTYPE_MIX) || \ + ((MODE) == QSPI_TRANSTYPE_FRF)) +/** + * @} + */ + +/** @defgroup QSPI_ClkstretchEn + * @{ + */ +#define QSPI_CLKSTRETCH_DIS ((uint32_t)0x00000000) +#define QSPI_CLKSTRETCH_EN ((uint32_t)0x40000000) +#define IS_QSPI_CLKSTRETCH(MODE) (((MODE) == QSPI_CLKSTRETCH_DIS) || \ + ((MODE) == QSPI_CLKSTRETCH_EN)) +/** + * @} + */ + +/** @defgroup QSPI_DdrMode + * @{ + */ +#define QSPI_DDRMODE_DIS ((uint32_t)0x00000000) +#define QSPI_DDRMODE_EN ((uint32_t)0x00010000) +#define IS_QSPI_DDRMODE(MODE) (((MODE) == QSPI_DDRMODE_DIS) || \ + ((MODE) == QSPI_DDRMODE_EN)) +/** + * @} + */ + +/** @defgroup QSPI_InstDdrMode + * @{ + */ +#define QSPI_INSTDDRMODE_DIS ((uint32_t)0x00000000) +#define QSPI_INSTDDRMODE_EN ((uint32_t)0x00020000) +#define IS_QSPI_INSTDDRMODE(MODE) (((MODE) == QSPI_INSTDDRMODE_DIS) || \ + ((MODE) == QSPI_INSTDDRMODE_EN)) +/** + * @} + */ + +/** @defgroup QSPI_XIP_DFS + * @{ + */ +#define QSPI_XIP_DFS_DIS ((uint32_t)0x00000000) +#define QSPI_XIP_DFS_EN ((uint32_t)0x00080000) +#define IS_QSPI_XIP_DFS(MODE) (((MODE) == QSPI_XIP_DFS_DIS) || \ + ((MODE) == QSPI_XIP_DFS_EN)) +/** + * @} + */ + +/** @defgroup QSPI_XIP_Cont + * @{ + */ +#define QSPI_XIP_CONT_DIS ((uint32_t)0x00000000) +#define QSPI_XIP_CONT_EN ((uint32_t)0x00200000) +#define IS_QSPI_XIP_CONT(MODE) (((MODE) == QSPI_XIP_CONT_DIS) || \ + ((MODE) == QSPI_XIP_CONT_EN)) +/** + * @} + */ + +/** @defgroup QSPI_MicroHand + * @{ + */ +#define QSPI_MICROHAND_DIS ((uint32_t)0x00000000) +#define QSPI_MICROHAND_EN ((uint32_t)0x00000004) +#define IS_QSPI_MICROHAND(MODE) (((MODE) == QSPI_MICROHAND_DIS) || \ + ((MODE) == QSPI_MICROHAND_EN)) +/** + * @} + */ + +/** @defgroup QSPI_MicroDir + * @{ + */ +#define QSPI_MICRODIR_Rx ((uint32_t)0x00000000) +#define QSPI_MICRODIR_Tx ((uint32_t)0x00000002) +#define IS_QSPI_MICRODIR(MODE) (((MODE) == QSPI_MICRODIR_Rx) || \ + ((MODE) == QSPI_MICRODIR_Tx)) +/** + * @} + */ + +/** @defgroup QSPI_MicroTrans + * @{ + */ +#define QSPI_MICROTRANS_NSEQ ((uint32_t)0x00000000) +#define QSPI_MICROTRANS_SEQ ((uint32_t)0x00000001) +#define IS_QSPI_MICROTRANS(MODE) (((MODE) == QSPI_MICROTRANS_NSE) || \ + ((MODE) == QSPI_MICROTRANS_SEQ)) +/** + * @} + */ + +/** @defgroup QSPI_DMAReq + * @{ + */ +#define QSPI_DMAReq_Tx ((uint32_t)0x00000002) +#define QSPI_DMAReq_Rx ((uint32_t)0x00000001) +#define IS_QSPI_DMA_REQ(MODE) (((MODE) == QSPI_DMAReq_Tx) || \ + ((MODE) == QSPI_DMAReq_Rx)) +/** + * @} + */ + + +#define IS_QSPI_DATANUMBER(SIZE) ((SIZE) <= 0xFFFFFFFF) +#define IS_QSPI_BR(BR) ((BR) <= 0x7FFF) + + +#define IS_QSPI_RX_FIFO_THRESHOLD(RFT) ((RFT) <= 0xFU) +#define IS_QSPI_TX_FIFO_THRESHOLD(TFT) ((TFT) <= 0xFU) +#define IS_QSPI_TX_FIFO_STARTLEVEL(TST) ((TST) <= 0xFU) + +#define IS_QSPI_DMA_RX_DATA_LEVEL(LEVEL) ((LEVEL) <= 0xFU) +#define IS_QSPI_DMA_TX_DATA_LEVEL(LEVEL) ((LEVEL) <= 0xFU) + +#define IS_QSPI_WAITCYCLES(NUM) ((NUM) <= 0x1FU) + +#define IS_QSPI_XIP_INST(INST) ((INST) <= 0xFFFF) +#define IS_QSPI_XIP_MODEBITS(MODE) ((MODE) <= 0xFFFF) +#define IS_QSPI_XIP_TIMOUT(TIME) ((TIME) <= 0xFFU) +#define IS_QSPI_DDR_DRIVE_EDGE(TDE) ((TDE) <= 0xFFU) +#define IS_QSPI_SAMPLE_DLY(DLY) ((DLY) <= 0xFFU) +/** @defgroup QSPI_interrupts_definition + * @{ + */ + +#define QSPI_IT_TXEIM ((uint8_t)0x01) +#define QSPI_IT_TXOIM ((uint8_t)0x02) +#define QSPI_IT_RXUIM ((uint8_t)0x04) +#define QSPI_IT_RXOIM ((uint8_t)0x08) +#define QSPI_IT_RXFIM ((uint8_t)0x10) +#define QSPI_IT_TXUIM ((uint8_t)0x80) + +#define IS_QSPI_CONFIG_IT(IT) (((IT) == QSPI_IT_TXEIM) || \ + ((IT) == QSPI_IT_TXOIM) || \ + ((IT) == QSPI_IT_RXUIM) || \ + ((IT) == QSPI_IT_RXOIM) || \ + ((IT) == QSPI_IT_RXFIM) || \ + ((IT) == QSPI_IT_TXUIM)) + +/** + * @} + */ + + +/** @defgroup QSPI_flags_definition + * @{ + */ +#define QSPI_STATE_BUSY ((uint8_t) 0x01) +#define QSPI_STATE_TFNF ((uint8_t) 0x02) +#define QSPI_STATE_TFE ((uint8_t) 0x04) +#define QSPI_STATE_RFNE ((uint8_t) 0x08) +#define QSPI_STATE_RFF ((uint8_t) 0x10) + +#define QSPI_FLAG_TXEIS ((uint8_t)0x01) +#define QSPI_FLAG_TXOIS ((uint8_t)0x02) +#define QSPI_FLAG_RXUIS ((uint8_t)0x04) +#define QSPI_FLAG_RXOIS ((uint8_t)0x08) +#define QSPI_FLAG_RXFIS ((uint8_t)0x10) +#define QSPI_FLAG_TXUIS ((uint8_t)0x80) + +#define QSPI_FLAG_TXEIR ((uint8_t)0x01) +#define QSPI_FLAG_TXOIR ((uint8_t)0x02) +#define QSPI_FLAG_RXUIR ((uint8_t)0x04) +#define QSPI_FLAG_RXOIR ((uint8_t)0x08) +#define QSPI_FLAG_RXFIR ((uint8_t)0x10) +#define QSPI_FLAG_TXUIR ((uint8_t)0x80) + +#define QSPI_FLAG_TXEICR ((uint8_t)0x01) +#define QSPI_FLAG_RXOICR ((uint8_t)0x01) +#define QSPI_FLAG_RXUICR ((uint8_t)0x01) +#define QSPI_FLAG_ICR ((uint8_t)0x01) + + +#define IS_QSPI_TXE_CLEAR_FLAG(FLAG) (((FLAG) == QSPI_FLAG_TXEICR)) +#define IS_QSPI_RXO_CLEAR_FLAG(FLAG) (((FLAG) == QSPI_FLAG_RXOICR)) +#define IS_QSPI_RXU_CLEAR_FLAG(FLAG) (((FLAG) == QSPI_FLAG_RXUICR)) +#define IS_QSPI_CLEAR_FLAG(FLAG) (((FLAG) == QSPI_FLAG_ICR)) + +#define IS_QSPI_BeforMaskInterruptStatus(ST) (((ST) == QSPI_FLAG_TXEIR) || ((ST) == QSPI_FLAG_TXOIR) || \ + ((ST) == QSPI_FLAG_RXUIR) || ((ST) == QSPI_FLAG_RXOIR) || \ + ((ST) == QSPI_FLAG_RXFIR) || ((ST) == QSPI_FLAG_TXUIR)) + +#define IS_QSPI_AfterMaskInterruptStatus(ST) (((ST) == QSPI_FLAG_TXEIS) || ((ST) == QSPI_FLAG_TXEIS) || \ + ((ST) == QSPI_FLAG_RXUIS) || ((ST) == QSPI_FLAG_RXOIS) || \ + ((ST) == QSPI_FLAG_RXFIS) || ((ST) == QSPI_FLAG_TXUIS)) + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Initialization and Configuration functions *********************************/ +void QSPI_DeInit(void); +void QSPI_Init(QSPI_InitTypeDef *QSPI_InitStruct, uint16_t Br); +void QSPI_StructInit(QSPI_InitTypeDef *QSPI_InitStruct); + +/* QSPI Mode Configuration functions ******************************************/ +void QSPI_TestMode_Enable(FunctionalState NewState); +void QSPI_MicroWireMode_Config(uint32_t MHS, uint32_t MDD, uint32_t MWMOD, uint32_t FrameSize, FunctionalState NewState); +void QSPI_EnCmd(FunctionalState NewState); +void QSPI_TIModeCmd(FunctionalState NewState); +void QSPI_SSTEModeCmd(FunctionalState NewState); +void QSPI_LineCfg(uint32_t LINE); +void QSPI_TransMode(uint32_t TRANS); +void QSPI_WaitCyclesConfig(uint32_t NUMBER); +void QSPI_TransTypeConfig(uint32_t TRANSTYPE); + +/* Data transfers functions ***************************************************/ +void QSPI_SendData(uint32_t Data); +uint32_t QSPI_ReceiveData(void); +void QSPI_DataSizeConfig(uint16_t QSPI_DataSize); +void QSPI_DataNumberConfig(uint32_t QSPI_NDF); + +void QSPI_RxFIFOThresholdConfig(uint16_t QSPI_RxFIFOThreshold); +void QSPI_TxFIFOThresholdConfig(uint16_t QSPI_TxFIFOStart, uint16_t QSPI_TxFIFOThreshold); + +/* DMA transfers management functions *****************************************/ +void QSPI_DMACmd(uint32_t QSPI_DMAReq, FunctionalState NewState); +void QSPI_DMA_Tx_DATALEVELCmd(uint32_t QSPI_DMATxDLevel); +void QSPI_DMA_Rx_DATALEVELCmd(uint32_t QSPI_DMARxDLevel); + +/* XIP transfers functions ****************************************************/ +void QSPI_XIP_INSTCmd(uint32_t INSTRUCTION_L, FunctionalState NewState); +void QSPI_XIP_INST_Config(uint32_t QSPI_XIP_INSTCfg); +void QSPI_ADDRCfg(uint32_t ADDR_L); +void QSPI_XIP_ModeBitsCmd(uint32_t MODEBITS, uint32_t MD_SIZE, FunctionalState NewState); +void QSPI_Ddrcmd(uint32_t Ddr_TXD, FunctionalState NewState); +void QSPI_InstDdrcmd(FunctionalState NewState); +void QSPI_XIP_ContinuousCmd(uint32_t TIMOUT, FunctionalState NewState); +void QSPI_XIP_DFSHCCmd(FunctionalState NewState); + +/* other receive data fonfigure function **************************************/ +void QSPI_CLK_LOOPCmd(FunctionalState NewState); +void QSPI_RX_SAMPLEDLYConfig(uint32_t SE, uint32_t RSD); +void QSPI_RXDSConfig(uint32_t RXDS_VL_EN, FunctionalState NewState); +void QSPI_CLK_StretchCmd(FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState); +uint32_t QSPI_GetStatus(uint16_t QSPI_SR_FLAG); +uint32_t QSPI_GetAfterMaskInterruptStatus(uint16_t QSPI_ISR_FLAG); +uint32_t QSPI_GetBeforeMaskInterruptStatus(uint16_t QSPI_RISR_FLAG); +void QSPI_ClearTxFIFOErrorInterrupt(void); +void QSPI_ClearRxFIFOOverflowInterrupt(void); +void QSPI_ClearRxFIFOUnderflowInterrupt(void); +void QSPI_ClearFIFOFlowInterrupt(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_QSPI_H */ + +/** + * @} + */ + +/** + * @} + */ + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rcc.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rcc.h new file mode 100644 index 00000000000..2421ed8889a --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rcc.h @@ -0,0 +1,1096 @@ +/** + ****************************************************************************** + * @file ft32f4xx_rcc.h + * @author Rwang + * @brief This file contains all the functions prototypes for the RCC + * firmware library. + * @version V1.0.0 + * @data 2025-03-03 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F0XX_RCC_H +#define __FT32F0XX_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup RCC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +typedef struct +{ + uint32_t SYSCLK_Frequency; + uint32_t HCLK_Frequency; + uint32_t PCLK_Frequency; + uint32_t PLLQ_Frequency; + uint32_t PLLR_Frequency; + uint32_t P2CLK_Frequency; + uint32_t PLL2Q_Frequency; + uint32_t PLL2R_Frequency; + uint32_t QSPICLK_Frequency; + uint32_t ADCCLK_Frequency; + uint32_t CANCLK_Frequency; + uint32_t LPTIMCLK_Frequency; + uint32_t I2C3CLK_Frequency; + uint32_t I2C2CLK_Frequency; + uint32_t I2C1CLK_Frequency; + uint32_t LPUARTCLK_Frequency; + uint32_t PWMCLK_Frequency; + uint32_t EQEPCLK_Frequency; + uint32_t ECAPCLK_Frequency; + uint32_t I2SCLK_Frequency; +} RCC_ClocksTypeDef; + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RCC_Exported_Constants + * @{ + */ +#define RCC_FLAG_PLL2RDY ((uint32_t)0x08000000) +#define RCC_FLAG_PLLRDY ((uint32_t)0x02000000) +#define RCC_FLAG_HSERDY ((uint32_t)0x00020000) +#define RCC_FLAG_HSIRDY ((uint32_t)0x00000002) +#define RCC_FLAG_HSI48RDY ((uint32_t)0x00020000) +#define RCC_FLAG_LSERDY ((uint32_t)0x00000002) +#define RCC_FLAG_LPWRRSTF ((uint32_t)0x80000000) +#define RCC_FLAG_WWDGRSTF ((uint32_t)0x40000000) +#define RCC_FLAG_IWDGRSTF ((uint32_t)0x20000000) +#define RCC_FLAG_SFTRSTF ((uint32_t)0x10000000) +#define RCC_FLAG_PORRSTF ((uint32_t)0x08000000) +#define RCC_FLAG_PINRSTF ((uint32_t)0x04000000) +#define RCC_FLAG_RMVF ((uint32_t)0x01000000) +#define RCC_FLAG_LSIRDY ((uint32_t)0x00000002) +#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \ + ((FLAG) == RCC_FLAG_HSERDY) || ((FLAG) == RCC_FLAG_HSIRDY) || \ + ((FLAG) == RCC_FLAG_HSI48RDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ + ((FLAG) == RCC_FLAG_LPWRRSTF) || ((FLAG) == RCC_FLAG_WWDGRSTF) || \ + ((FLAG) == RCC_FLAG_IWDGRSTF) || ((FLAG) == RCC_FLAG_SFTRSTF) || \ + ((FLAG) == RCC_FLAG_PORRSTF) || ((FLAG) == RCC_FLAG_PINRSTF) || \ + ((FLAG) == RCC_FLAG_RMVF) || ((FLAG) == RCC_FLAG_LSIRDY)) + +#define RCC_FLAG_REG_CR ((uint8_t)0x00) +#define RCC_FLAG_REG_CR2 ((uint8_t)0x01) +#define RCC_FLAG_REG_BDCR ((uint8_t)0x02) +#define RCC_FLAG_REG_CSR ((uint8_t)0x03) +#define IS_RCC_FLAG_REG(REG) (((REG) == RCC_FLAG_REG_CR) || ((REG) == RCC_FLAG_REG_CR2) || \ + ((REG) == RCC_FLAG_REG_BDCR) || ((REG) == RCC_FLAG_REG_CSR)) + +#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x0000001F) + + +#define IS_RCC_HSI48_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x000001FF) + + + +//RCC_CR_REG +#define RCC_SEL_PLL ((uint32_t)0x00000000) +#define RCC_SEL_PLL2 ((uint32_t)0x00000001) +#define IS_RCC_SEL(SEL) (((SEL) == RCC_SEL_PLL) || \ + ((SEL) == RCC_SEL_PLL2)) + + + +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00050000) +#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || \ + ((HSE) == RCC_HSE_ON) || \ + ((HSE) == RCC_HSE_Bypass) ) + +#define RCC_HSI_OFF ((uint8_t)0x00) +#define RCC_HSI_ON ((uint8_t)0x01) +#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || \ + ((HSI) == RCC_HSI_ON) ) + +//RCC_PLLCFGR_REG +//PLLRCLK=((VCO/(PLLR+1)) +#define IS_RCC_PLLR_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00000007) + +#define RCC_PLLR_OFF ((uint32_t)0x00000000) +#define RCC_PLLR_ON ((uint32_t)0x00000001) +#define IS_RCC_PLLR(PLLR) (((PLLR) == RCC_PLLR_OFF) || \ + ((PLLR) == RCC_PLLR_ON) ) + +//PLLQCLK=((VCO/(PLLQ+1)) +#define IS_RCC_PLLQ_VALUE(VALUE) ((VALUE) <= (uint32_t)0x0000000F) + +#define RCC_PLLQ_OFF ((uint32_t)0x00000000) +#define RCC_PLLQ_ON ((uint32_t)0x00000001) +#define IS_RCC_PLLQ(PLLQ) (((PLLQ) == RCC_PLLQ_OFF) || \ + ((PLLQ) == RCC_PLLQ_ON) ) + +//PLLPCLK=((VCO/(PLLP+1)) +#define IS_RCC_PLLP_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00000007) + +#define RCC_PLLP_OFF ((uint32_t)0x00000000) +#define RCC_PLLP_ON ((uint32_t)0x00000001) +#define IS_RCC_PLLP(PLLP) (((PLLP) == RCC_PLLP_OFF) || \ + ((PLLP) == RCC_PLLP_ON) ) + +//RCC_PLL_Clock_Source PLLCLK_INPUT=HSE/HSI +#define RCC_PLLSource_HSI ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE ((uint32_t)0x00000001) +#define IS_RCC_PLLSRC(SRC) (((SRC) == RCC_PLLSource_HSI) || \ + ((SRC) == RCC_PLLSource_HSE)) + +// RCC_PLLN_Factor VCO_OUTCLK=VCO_IN*PLLN +#define IS_RCC_PLLN_VALUE(VALUE) ((VALUE) <= (uint32_t)0x000000FF) + +//VCO_OUT=PLL_IN*(PLLN/PLLM) +#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= (uint32_t)0x0000001F) + +/** + * @} + */ + +//RCC_PLL2CFGR_REG +//PLL2RCLK=((VCO/(PLL2R+1)) +#define IS_RCC_PLL2R_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00000007) + +#define RCC_PLL2R_OFF ((uint32_t)0x00000000) +#define RCC_PLL2R_ON ((uint32_t)0x00000001) +#define IS_RCC_PLL2R(PLL2R) (((PLL2R) == RCC_PLL2R_OFF) || \ + ((PLL2R) == RCC_PLL2R_ON) ) + +//PLL2QCLK=((VCO/(PLL2Q+1)) +#define IS_RCC_PLL2Q_VALUE(VALUE) ((VALUE) <= (uint32_t)0x0000000F) + +#define RCC_PLL2Q_OFF ((uint32_t)0x00000000) +#define RCC_PLL2Q_ON ((uint32_t)0x00000001) +#define IS_RCC_PLL2Q(PLL2Q) (((PLL2Q) == RCC_PLL2Q_OFF) || \ + ((PLL2Q) == RCC_PLL2Q_ON) ) + +//RCC_PLL2_Clock_Source PLL2CLK_INPUT=HSE/HSI +#define RCC_PLL2Source_HSI ((uint32_t)0x00000000) +#define RCC_PLL2Source_HSE ((uint32_t)0x00000001) +#define IS_RCC_PLL2SRC(SRC) (((SRC) == RCC_PLL2Source_HSI) || \ + ((SRC) == RCC_PLL2Source_HSE) ) + +// RCC_PLL2N_Factor VCO_OUTCLK=VCO_IN*PLL2N +#define IS_RCC_PLL2N_VALUE(VALUE) ((VALUE) <= (uint32_t)0x000000FF) + +//VCO_OUT=PLL_IN*(PLL2N/PLL2M) +#define IS_RCC_PLL2M_VALUE(VALUE) ((VALUE) <= (uint32_t)0x0000001F) +/** + * @} + */ + +/** @defgroup RCC_MCOSource_Select + * @{ + */ +#define RCC_MCOSource_NoClock ((uint32_t)0x00000000) +#define RCC_MCOSource_SYSCLK ((uint32_t)0x01000000) +#define RCC_MCOSource_PLL2R ((uint32_t)0x02000000) +#define RCC_MCOSource_HSI16 ((uint32_t)0x03000000) +#define RCC_MCOSource_HSE ((uint32_t)0x04000000) +#define RCC_MCOSource_PLLP ((uint32_t)0x05000000) +#define RCC_MCOSource_LSI ((uint32_t)0x06000000) +#define RCC_MCOSource_LSE ((uint32_t)0x07000000) +#define RCC_MCOSource_HSI48 ((uint32_t)0x08000000) +#define IS_RCC_MCO_SOURCE(SRC) (((SRC) == RCC_MCOSource_NoClock) || ((SRC) == RCC_MCOSource_SYSCLK) || \ + ((SRC) == RCC_MCOSource_PLL2R) || ((SRC) == RCC_MCOSource_HSI16) || \ + ((SRC) == RCC_MCOSource_HSE) || ((SRC) == RCC_MCOSource_PLLP) || \ + ((SRC) == RCC_MCOSource_LSI) || ((SRC) == RCC_MCOSource_LSE) || \ + ((SRC) == RCC_MCOSource_HSI48)) +/** + * @} + */ + +/** @defgroup RCC_MCOPrescaler_Select + * @{ + */ +#define RCC_MCOPrescaler_1 ((uint32_t)0x00000000) +#define RCC_MCOPrescaler_2 ((uint32_t)0x10000000) +#define RCC_MCOPrescaler_4 ((uint32_t)0x20000000) +#define RCC_MCOPrescaler_8 ((uint32_t)0x30000000) +#define RCC_MCOPrescaler_16 ((uint32_t)0x40000000) +#define RCC_MCOPrescaler_32 ((uint32_t)0x50000000) +#define RCC_MCOPrescaler_64 ((uint32_t)0x60000000) +#define RCC_MCOPrescaler_128 ((uint32_t)0x70000000) +#define IS_RCC_MCO_PRESCALER(PRE) (((PRE) == RCC_MCOPrescaler_1) || ((PRE) == RCC_MCOPrescaler_2) || \ + ((PRE) == RCC_MCOPrescaler_4) || ((PRE) == RCC_MCOPrescaler_8) || \ + ((PRE) == RCC_MCOPrescaler_16) || ((PRE) == RCC_MCOPrescaler_32) || \ + ((PRE) == RCC_MCOPrescaler_64) || ((PRE) == RCC_MCOPrescaler_128)) +/** + * @} + */ + +/** @defgroup RCC_apbclk_division_factor(APBCLK=HCLK/DIV) + * @{ + */ +#define RCC_HCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_HCLK_DIV2 ((uint32_t)0x00000004) +#define RCC_HCLK_DIV4 ((uint32_t)0x00000005) +#define RCC_HCLK_DIV8 ((uint32_t)0x00000006) +#define RCC_HCLK_DIV16 ((uint32_t)0x00000007) +#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ + ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ + ((PCLK) == RCC_HCLK_DIV16)) +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source(HCLK=SYSCLK/HPREDIV) + * @{ + */ + +#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 +#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 +#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 +#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 +#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 +#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 +#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 +#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 +#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 +#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ + ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ + ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ + ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ + ((HCLK) == RCC_SYSCLK_DIV512)) +/** + * @} + */ + +/** @defgroup RCC_SYSCLK_SOURCE + * @{ + */ + +#define RCC_SYSCLKSource_HSI16 RCC_CFGR_SW_HSI +#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE +#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL +#define IS_RCC_SYSCLK_SOURCE(SRC) (((SRC) == RCC_SYSCLKSource_HSI16) || \ + ((SRC) == RCC_SYSCLKSource_HSE) || \ + ((SRC) == RCC_SYSCLKSource_PLLCLK)) +/** + * @} + */ + +//RCC_CIR_REG +/** @defgroup RCC_Interrupt_Source + * @{ + */ +#define RCC_ITCLR_CSS RCC_CIR_CSSC +#define RCC_ITCLR_PLL2RDY RCC_CIR_PLL2RDYC +#define RCC_ITCLR_PLLRDY RCC_CIR_PLLRDYC +#define RCC_ITCLR_HSERDY RCC_CIR_HSERDYC +#define RCC_ITCLR_HSI48RDY RCC_CIR_HSI48RDYC +#define RCC_ITCLR_HSIRDY RCC_CIR_HSIRDYC +#define RCC_ITCLR_LSERDY RCC_CIR_LSERDYC +#define RCC_ITCLR_LSIRDY RCC_CIR_LSIRDYC +#define IS_RCC_ITCLR(ITCLR) (((ITCLR) == RCC_ITCLR_LSIRDY) || ((ITCLR) == RCC_ITCLR_LSERDY) || \ + ((ITCLR) == RCC_ITCLR_HSIRDY) || ((ITCLR) == RCC_ITCLR_HSI48RDY) || \ + ((ITCLR) == RCC_ITCLR_HSERDY) || ((ITCLR) == RCC_ITCLR_PLLRDY) || \ + ((ITCLR) == RCC_ITCLR_PLL2RDY) || ((ITCLR) == RCC_ITCLR_CSS)) + +#define RCC_ITEN_PLL2RDY RCC_CIR_PLL2RDYIE +#define RCC_ITEN_PLLRDY RCC_CIR_PLLRDYIE +#define RCC_ITEN_HSERDY RCC_CIR_HSERDYIE +#define RCC_ITEN_HSI48RDY RCC_CIR_HSI48RDYIE +#define RCC_ITEN_HSIRDY RCC_CIR_HSIRDYIE +#define RCC_ITEN_LSERDY RCC_CIR_LSERDYIE +#define RCC_ITEN_LSIRDY RCC_CIR_LSIRDYIE +#define IS_RCC_ITEN(ITEN) (((ITEN) == RCC_ITEN_LSIRDY) || ((ITEN) == RCC_ITEN_LSERDY) || \ + ((ITEN) == RCC_ITEN_HSIRDY) || ((ITEN) == RCC_ITEN_HSI48RDY) || \ + ((ITEN) == RCC_ITEN_HSERDY) || ((ITEN) == RCC_ITEN_PLLRDY) || \ + ((ITEN) == RCC_ITEN_PLL2RDY)) + +#define RCC_ITFLAG_CSS RCC_CIR_CSSF +#define RCC_ITFLAG_PLL2RDY RCC_CIR_PLL2RDYF +#define RCC_ITFLAG_PLLRDY RCC_CIR_PLLRDYF +#define RCC_ITFLAG_HSERDY RCC_CIR_HSERDYF +#define RCC_ITFLAG_HSI48RDY RCC_CIR_HSI48RDYF +#define RCC_ITFLAG_HSIRDY RCC_CIR_HSIRDYF +#define RCC_ITFLAG_LSERDY RCC_CIR_LSERDYF +#define RCC_ITFLAG_LSIRDY RCC_CIR_LSIRDYF +#define IS_RCC_ITFLAG(ITFLAG) (((ITFLAG) == RCC_ITFLAG_LSIRDY) || ((ITFLAG) == RCC_ITFLAG_LSERDY) || \ + ((ITFLAG) == RCC_ITFLAG_HSIRDY) || ((ITFLAG) == RCC_ITFLAG_HSI48RDY) || \ + ((ITFLAG) == RCC_ITFLAG_HSERDY) || ((ITFLAG) == RCC_ITFLAG_PLLRDY) || \ + ((ITFLAG) == RCC_ITFLAG_PLL2RDY) || ((ITFLAG) == RCC_ITFLAG_CSS)) +/** + * @} + */ + +//RCC_AHB1/2/3_PERIPH_RSTR_REG +/** @defgroup RCC_AHB1/2/3_Peripherals_Reset + * @{ + */ +#define RCC_AHB1PeriphRst_USBOTGHS RCC_AHB1RSTR_OTGHSRST +#define RCC_AHB1PeriphRst_ETHMAC RCC_AHB1RSTR_ETHMACRST +#define RCC_AHB1PeriphRst_DMA2 RCC_AHB1RSTR_DMA2RST +#define RCC_AHB1PeriphRst_DMA1 RCC_AHB1RSTR_DMA1RST +#define RCC_AHB1PeriphRst_CRC RCC_AHB1RSTR_CRCRST +#define RCC_AHB1PeriphRst_GPIOH RCC_AHB1RSTR_GPIOHRST +#define RCC_AHB1PeriphRst_GPIOE RCC_AHB1RSTR_GPIOERST +#define RCC_AHB1PeriphRst_GPIOD RCC_AHB1RSTR_GPIODRST +#define RCC_AHB1PeriphRst_GPIOC RCC_AHB1RSTR_GPIOCRST +#define RCC_AHB1PeriphRst_GPIOB RCC_AHB1RSTR_GPIOBRST +#define RCC_AHB1PeriphRst_GPIOA RCC_AHB1RSTR_GPIOARST +#define IS_RCC_AHB1RST_PERIPH(PERIPH) (((PERIPH) == RCC_AHB1PeriphRst_USBOTGHS) || ((PERIPH) == RCC_AHB1PeriphRst_ETHMAC) || \ + ((PERIPH) == RCC_AHB1PeriphRst_DMA2) || ((PERIPH) == RCC_AHB1PeriphRst_DMA1) || \ + ((PERIPH) == RCC_AHB1PeriphRst_CRC) || ((PERIPH) == RCC_AHB1PeriphRst_GPIOH) || \ + ((PERIPH) == RCC_AHB1PeriphRst_GPIOE) || ((PERIPH) == RCC_AHB1PeriphRst_GPIOD) || \ + ((PERIPH) == RCC_AHB1PeriphRst_GPIOC) || ((PERIPH) == RCC_AHB1PeriphRst_GPIOB) || \ + ((PERIPH) == RCC_AHB1PeriphRst_GPIOA)) + +#define RCC_AHB2PeriphRst_USBOTGFS RCC_AHB2RSTR_OTGFSRST +#define RCC_AHB2PeriphRst_RNG RCC_AHB2RSTR_RNGRST +#define IS_RCC_AHB2RST_PERIPH(PERIPH) (((PERIPH) == RCC_AHB2PeriphRst_USBOTGFS) || ((PERIPH) == RCC_AHB2PeriphRst_RNG)) + +#define RCC_AHB3PeriphRst_QSPI RCC_AHB3RSTR_QSPIRST +#define RCC_AHB3PeriphRst_FMC RCC_AHB3RSTR_FMCRST +#define IS_RCC_AHB3RST_PERIPH(PERIPH) (((PERIPH) == RCC_AHB3PeriphRst_QSPI) || ((PERIPH) == RCC_AHB3PeriphRst_FMC)) +/** + * @} + */ + +//RCC_APB1/2_PERIPH_RSTR_REG +/** @defgroup RCC_APB1/2_Peripherals_Reset + * @{ + */ +#define RCC_APB1PeriphRst_UART7 RCC_APB1RSTR_UART7RST +#define RCC_APB1PeriphRst_DAC RCC_APB1RSTR_DACRST +#define RCC_APB1PeriphRst_PWR RCC_APB1RSTR_PWRRST +#define RCC_APB1PeriphRst_CAN4 RCC_APB1RSTR_CAN4RST +#define RCC_APB1PeriphRst_CAN3 RCC_APB1RSTR_CAN3RST +#define RCC_APB1PeriphRst_CAN2 RCC_APB1RSTR_CAN2RST +#define RCC_APB1PeriphRst_CAN1 RCC_APB1RSTR_CAN1RST +#define RCC_APB1PeriphRst_I2C3 RCC_APB1RSTR_I2C3RST +#define RCC_APB1PeriphRst_I2C2 RCC_APB1RSTR_I2C2RST +#define RCC_APB1PeriphRst_I2C1 RCC_APB1RSTR_I2C1RST +#define RCC_APB1PeriphRst_UART5 RCC_APB1RSTR_UART5RST +#define RCC_APB1PeriphRst_UART4 RCC_APB1RSTR_UART4RST +#define RCC_APB1PeriphRst_UART3 RCC_APB1RSTR_UART3RST +#define RCC_APB1PeriphRst_UART2 RCC_APB1RSTR_UART2RST +#define RCC_APB1PeriphRst_LPUART RCC_APB1RSTR_LPUARTRST +#define RCC_APB1PeriphRst_SPI3 RCC_APB1RSTR_SPI3RST +#define RCC_APB1PeriphRst_SPI2 RCC_APB1RSTR_SPI2RST +#define RCC_APB1PeriphRst_I2S3 RCC_APB1RSTR_I2S3RST +#define RCC_APB1PeriphRst_I2S2 RCC_APB1RSTR_I2S2RST +#define RCC_APB1PeriphRst_WWDG RCC_APB1RSTR_WWDGRST +#define RCC_APB1PeriphRst_AC97 RCC_APB1RSTR_AC97RST +#define RCC_APB1PeriphRst_CRS RCC_APB1RSTR_CRSRST +#define RCC_APB1PeriphRst_TIM14 RCC_APB1RSTR_TIM14RST +#define RCC_APB1PeriphRst_TIM13 RCC_APB1RSTR_TIM13RST +#define RCC_APB1PeriphRst_TIM12 RCC_APB1RSTR_TIM12RST +#define RCC_APB1PeriphRst_TIM7 RCC_APB1RSTR_TIM7RST +#define RCC_APB1PeriphRst_TIM6 RCC_APB1RSTR_TIM6RST +#define RCC_APB1PeriphRst_TIM5 RCC_APB1RSTR_TIM5RST +#define RCC_APB1PeriphRst_TIM4 RCC_APB1RSTR_TIM4RST +#define RCC_APB1PeriphRst_TIM3 RCC_APB1RSTR_TIM3RST +#define RCC_APB1PeriphRst_TIM2 RCC_APB1RSTR_TIM2RST +#define IS_RCC_APB1RST_PERIPH(PERIPH) (((PERIPH) == RCC_APB1PeriphRst_UART7) || ((PERIPH) == RCC_APB1PeriphRst_DAC) || \ + ((PERIPH) == RCC_APB1PeriphRst_PWR) || ((PERIPH) == RCC_APB1PeriphRst_CAN4) || \ + ((PERIPH) == RCC_APB1PeriphRst_CAN3) || ((PERIPH) == RCC_APB1PeriphRst_CAN2) || \ + ((PERIPH) == RCC_APB1PeriphRst_CAN1) || ((PERIPH) == RCC_APB1PeriphRst_I2C3) || \ + ((PERIPH) == RCC_APB1PeriphRst_I2C2) || ((PERIPH) == RCC_APB1PeriphRst_I2C1) || \ + ((PERIPH) == RCC_APB1PeriphRst_UART5) || ((PERIPH) == RCC_APB1PeriphRst_UART4) || \ + ((PERIPH) == RCC_APB1PeriphRst_UART3) || ((PERIPH) == RCC_APB1PeriphRst_UART2) || \ + ((PERIPH) == RCC_APB1PeriphRst_LPUART) || ((PERIPH) == RCC_APB1PeriphRst_SPI3) || \ + ((PERIPH) == RCC_APB1PeriphRst_SPI2) || ((PERIPH) == RCC_APB1PeriphRst_I2S3) || \ + ((PERIPH) == RCC_APB1PeriphRst_I2S2) || ((PERIPH) == RCC_APB1PeriphRst_WWDG) || \ + ((PERIPH) == RCC_APB1PeriphRst_AC97) || ((PERIPH) == RCC_APB1PeriphRst_CRS) || \ + ((PERIPH) == RCC_APB1PeriphRst_TIM14) || ((PERIPH) == RCC_APB1PeriphRst_TIM13) || \ + ((PERIPH) == RCC_APB1PeriphRst_TIM12) || ((PERIPH) == RCC_APB1PeriphRst_TIM7) || \ + ((PERIPH) == RCC_APB1PeriphRst_TIM6) || ((PERIPH) == RCC_APB1PeriphRst_TIM5) || \ + ((PERIPH) == RCC_APB1PeriphRst_TIM4) || ((PERIPH) == RCC_APB1PeriphRst_TIM3) || \ + ((PERIPH) == RCC_APB1PeriphRst_TIM2)) + +#define RCC_APB2PeriphRst_EQEP RCC_APB2RSTR_EQEPRST +#define RCC_APB2PeriphRst_ECAP RCC_APB2RSTR_ECAPRST +#define RCC_APB2PeriphRst_EPWM4 RCC_APB2RSTR_EPWM4RST +#define RCC_APB2PeriphRst_EPWM3 RCC_APB2RSTR_EPWM3RST +#define RCC_APB2PeriphRst_EPWM2 RCC_APB2RSTR_EPWM2RST +#define RCC_APB2PeriphRst_EPWM1 RCC_APB2RSTR_EPWM1RST +#define RCC_APB2PeriphRst_TIM11 RCC_APB2RSTR_TIM11RST +#define RCC_APB2PeriphRst_TIM10 RCC_APB2RSTR_TIM10RST +#define RCC_APB2PeriphRst_TIM9 RCC_APB2RSTR_TIM9RST +#define RCC_APB2PeriphRst_LPTIM RCC_APB2RSTR_LPTIMRST +#define RCC_APB2PeriphRst_SYSCFG RCC_APB2RSTR_SYSCFGRST +#define RCC_APB2PeriphRst_SPI1 RCC_APB2RSTR_SPI1RST +#define RCC_APB2PeriphRst_SDIO RCC_APB2RSTR_SDIORST +#define RCC_APB2PeriphRst_SPD RCC_APB2RSTR_SPDRST +#define RCC_APB2PeriphRst_ADC RCC_APB2RSTR_ADCRST +#define RCC_APB2PeriphRst_USART6 RCC_APB2RSTR_USART6RST +#define RCC_APB2PeriphRst_USART1 RCC_APB2RSTR_USART1RST +#define RCC_APB2PeriphRst_TIM8 RCC_APB2RSTR_TIM8RST +#define RCC_APB2PeriphRst_TIM1 RCC_APB2RSTR_TIM1RST +#define IS_RCC_APB2RST_PERIPH(PERIPH) (((PERIPH) == RCC_APB2PeriphRst_EQEP) || ((PERIPH) == RCC_APB2PeriphRst_ECAP) || \ + ((PERIPH) == RCC_APB2PeriphRst_EPWM4) || ((PERIPH) == RCC_APB2PeriphRst_EPWM3) || \ + ((PERIPH) == RCC_APB2PeriphRst_EPWM2) || ((PERIPH) == RCC_APB2PeriphRst_EPWM1) || \ + ((PERIPH) == RCC_APB2PeriphRst_TIM11) || ((PERIPH) == RCC_APB2PeriphRst_TIM10) || \ + ((PERIPH) == RCC_APB2PeriphRst_TIM9) || ((PERIPH) == RCC_APB2PeriphRst_LPTIM) || \ + ((PERIPH) == RCC_APB2PeriphRst_SYSCFG) || ((PERIPH) == RCC_APB2PeriphRst_SPI1) || \ + ((PERIPH) == RCC_APB2PeriphRst_SDIO) || ((PERIPH) == RCC_APB2PeriphRst_SPD) || \ + ((PERIPH) == RCC_APB2PeriphRst_ADC) || ((PERIPH) == RCC_APB2PeriphRst_USART6) || \ + ((PERIPH) == RCC_APB2PeriphRst_USART1) || ((PERIPH) == RCC_APB2PeriphRst_TIM8) || \ + ((PERIPH) == RCC_APB2PeriphRst_TIM1)) +/** + * @} + */ + +//RCC_AHB1/2/3_PERIPH_CLKEN_REG +/** @defgroup RCC_AHB1/2/3_Peripherals_Clken + * @{ + */ +#define RCC_AHB1Periph_USBOTGHS RCC_AHB1ENR_OTGHSEN +#define RCC_AHB1Periph_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN +#define RCC_AHB1Periph_ETHMACRX RCC_AHB1ENR_ETHMACRXEN +#define RCC_AHB1Periph_ETHMACTX RCC_AHB1ENR_ETHMACTXEN +#define RCC_AHB1Periph_ETHMAC RCC_AHB1ENR_ETHMACEN +#define RCC_AHB1Periph_DMA2 RCC_AHB1ENR_DMA2EN +#define RCC_AHB1Periph_DMA1 RCC_AHB1ENR_DMA1EN +#define RCC_AHB1Periph_CCMDATARAM RCC_AHB1ENR_CCMDATARAMEN +#define RCC_AHB1Periph_BKPSRAM RCC_AHB1ENR_BKPSRAMEN +#define RCC_AHB1Periph_CRC RCC_AHB1ENR_CRCEN +#define RCC_AHB1Periph_GPIOH RCC_AHB1ENR_GPIOHEN +#define RCC_AHB1Periph_GPIOE RCC_AHB1ENR_GPIOEEN +#define RCC_AHB1Periph_GPIOD RCC_AHB1ENR_GPIODEN +#define RCC_AHB1Periph_GPIOC RCC_AHB1ENR_GPIOCEN +#define RCC_AHB1Periph_GPIOB RCC_AHB1ENR_GPIOBEN +#define RCC_AHB1Periph_GPIOA RCC_AHB1ENR_GPIOAEN +#define IS_RCC_AHB1_PERIPH(PERIPH) (((PERIPH) == RCC_AHB1Periph_USBOTGHS) || ((PERIPH) == RCC_AHB1Periph_ETHMACPTP) || \ + ((PERIPH) == RCC_AHB1Periph_ETHMACRX) || ((PERIPH) == RCC_AHB1Periph_ETHMACTX) || \ + ((PERIPH) == RCC_AHB1Periph_ETHMAC) || ((PERIPH) == RCC_AHB1Periph_DMA2) || \ + ((PERIPH) == RCC_AHB1Periph_DMA1) || ((PERIPH) == RCC_AHB1Periph_CCMDATARAM) || \ + ((PERIPH) == RCC_AHB1Periph_BKPSRAM) || ((PERIPH) == RCC_AHB1Periph_CRC) || \ + ((PERIPH) == RCC_AHB1Periph_GPIOH) || ((PERIPH) == RCC_AHB1Periph_GPIOE) || \ + ((PERIPH) == RCC_AHB1Periph_GPIOD) || ((PERIPH) == RCC_AHB1Periph_GPIOC) || \ + ((PERIPH) == RCC_AHB1Periph_GPIOB) || ((PERIPH) == RCC_AHB1Periph_GPIOA)) + +#define RCC_AHB2Periph_USBOTGFS RCC_AHB2ENR_OTGFSEN +#define RCC_AHB2periph_RNG RCC_AHB2ENR_RNGEN +#define IS_RCC_AHB2_PERIPH(PERIPH) (((PERIPH) == RCC_AHB2Periph_USBOTGFS) || ((PERIPH) == RCC_AHB2periph_RNG)) + +#define RCC_AHB3Periph_QSPI RCC_AHB3ENR_QSPIEN +#define RCC_AHB3Periph_FMC RCC_AHB3ENR_FMCEN +#define IS_RCC_AHB3_PERIPH(PERIPH) (((PERIPH) == RCC_AHB3Periph_QSPI) || ((PERIPH) == RCC_AHB3Periph_FMC)) +/** + * @} + */ + +//RCC_APB1/2_PERIPH_CLKEN_REG +/** @defgroup RCC_APB1/2_Peripherals_Clken + * @{ + */ +#define RCC_APB1Periph_UART7 RCC_APB1ENR_UART7EN +#define RCC_APB1Periph_RAMP RCC_APB1ENR_RAMPEN +#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN +#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN +#define RCC_APB1Periph_CAN4 RCC_APB1ENR_CAN4EN +#define RCC_APB1Periph_CAN3 RCC_APB1ENR_CAN3EN +#define RCC_APB1Periph_CAN2 RCC_APB1ENR_CAN2EN +#define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN +#define RCC_APB1Periph_I2C3 RCC_APB1ENR_I2C3EN +#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN +#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN +#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN +#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN +#define RCC_APB1Periph_UART3 RCC_APB1ENR_UART3EN +#define RCC_APB1Periph_UART2 RCC_APB1ENR_UART2EN +#define RCC_APB1Periph_LPUART RCC_APB1ENR_LPUARTEN +#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN +#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN +#define RCC_APB1Periph_I2S3 RCC_APB1ENR_I2S3EN +#define RCC_APB1Periph_I2S2 RCC_APB1ENR_I2S2EN +#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN +#define RCC_APB1Periph_AC97 RCC_APB1ENR_AC97EN +#define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN +#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN +#define RCC_APB1Periph_TIM13 RCC_APB1ENR_TIM13EN +#define RCC_APB1Periph_TIM12 RCC_APB1ENR_TIM12EN +#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN +#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN +#define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN +#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN +#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN +#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN +#define IS_RCC_APB1_PERIPH(PERIPH) (((PERIPH) == RCC_APB1Periph_UART7) || ((PERIPH) == RCC_APB1Periph_RAMP) || \ + ((PERIPH) == RCC_APB1Periph_DAC) || ((PERIPH) == RCC_APB1Periph_PWR) || \ + ((PERIPH) == RCC_APB1Periph_CAN4) || ((PERIPH) == RCC_APB1Periph_CAN3) || \ + ((PERIPH) == RCC_APB1Periph_CAN2) || ((PERIPH) == RCC_APB1Periph_CAN1) || \ + ((PERIPH) == RCC_APB1Periph_I2C3) || ((PERIPH) == RCC_APB1Periph_I2C2) || \ + ((PERIPH) == RCC_APB1Periph_I2C1) || ((PERIPH) == RCC_APB1Periph_UART5) || \ + ((PERIPH) == RCC_APB1Periph_UART4) || ((PERIPH) == RCC_APB1Periph_UART3) || \ + ((PERIPH) == RCC_APB1Periph_UART2) || ((PERIPH) == RCC_APB1Periph_LPUART)|| \ + ((PERIPH) == RCC_APB1Periph_SPI3) || ((PERIPH) == RCC_APB1Periph_SPI2) || \ + ((PERIPH) == RCC_APB1Periph_I2S3) || ((PERIPH) == RCC_APB1Periph_I2S2) || \ + ((PERIPH) == RCC_APB1Periph_WWDG) || ((PERIPH) == RCC_APB1Periph_AC97) || \ + ((PERIPH) == RCC_APB1Periph_CRS) || ((PERIPH) == RCC_APB1Periph_TIM14) || \ + ((PERIPH) == RCC_APB1Periph_TIM13) || ((PERIPH) == RCC_APB1Periph_TIM12) || \ + ((PERIPH) == RCC_APB1Periph_TIM7) || ((PERIPH) == RCC_APB1Periph_TIM6) || \ + ((PERIPH) == RCC_APB1Periph_TIM5) || ((PERIPH) == RCC_APB1Periph_TIM4) || \ + ((PERIPH) == RCC_APB1Periph_TIM3) || ((PERIPH) == RCC_APB1Periph_TIM2)) + +#define RCC_APB2Periph_TBCLK RCC_APB2ENR_TBCLKSYNC +#define RCC_APB2Periph_EQEP RCC_APB2ENR_EQEPEN +#define RCC_APB2Periph_ECAP RCC_APB2ENR_ECAPEN +#define RCC_APB2Periph_EPWM4 RCC_APB2ENR_EPWM4EN +#define RCC_APB2Periph_EPWM3 RCC_APB2ENR_EPWM3EN +#define RCC_APB2Periph_EPWM2 RCC_APB2ENR_EPWM2EN +#define RCC_APB2Periph_EPWM1 RCC_APB2ENR_EPWM1EN +#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN +#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN +#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN +#define RCC_APB2Periph_LPTIM RCC_APB2ENR_LPTIMEN +#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN +#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN +#define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN +#define RCC_APB2Periph_SPD RCC_APB2ENR_SPDEN +#define RCC_APB2Periph_ADC RCC_APB2ENR_ADCEN +#define RCC_APB2Periph_USART6 RCC_APB2ENR_USART6EN +#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN +#define RCC_APB2Periph_TIM8 RCC_APB2ENR_TIM8EN +#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN +#define IS_RCC_APB2_PERIPH(PERIPH) (((PERIPH) == RCC_APB2Periph_TBCLK) || ((PERIPH) == RCC_APB2Periph_EQEP) || \ + ((PERIPH) == RCC_APB2Periph_ECAP) || ((PERIPH) == RCC_APB2Periph_EPWM4) || \ + ((PERIPH) == RCC_APB2Periph_EPWM3) || ((PERIPH) == RCC_APB2Periph_EPWM2) || \ + ((PERIPH) == RCC_APB2Periph_EPWM1) || ((PERIPH) == RCC_APB2Periph_TIM11) || \ + ((PERIPH) == RCC_APB2Periph_TIM10) || ((PERIPH) == RCC_APB2Periph_TIM9) || \ + ((PERIPH) == RCC_APB2Periph_LPTIM) || ((PERIPH) == RCC_APB2Periph_SYSCFG) || \ + ((PERIPH) == RCC_APB2Periph_SPI1) || ((PERIPH) == RCC_APB2Periph_SDIO) || \ + ((PERIPH) == RCC_APB2Periph_SPD) || ((PERIPH) == RCC_APB2Periph_ADC) || \ + ((PERIPH) == RCC_APB2Periph_USART6) || ((PERIPH) == RCC_APB2Periph_USART1) || \ + ((PERIPH) == RCC_APB2Periph_TIM8) || ((PERIPH) == RCC_APB2Periph_TIM1)) +/** + * @} + */ + +//RCC_AHB1/2/3_PERIPH_LPCLKEN_REG +/** @defgroup RCC_AHB1/2/3_Peripherals_Lpclken + * @{ + */ +#define RCC_AHB1PeriphLpen_USBOTGHS RCC_AHB1LPENR_OTGHSLPEN +#define RCC_AHB1PeriphLpen_ETHMACPTP RCC_AHB1LPENR_ETHMACPTPLPEN +#define RCC_AHB1PeriphLpen_ETHMACRX RCC_AHB1LPENR_ETHMACRXLPEN +#define RCC_AHB1PeriphLpen_ETHMACTX RCC_AHB1LPENR_ETHMACTXLPEN +#define RCC_AHB1PeriphLpen_ETHMAC RCC_AHB1LPENR_ETHMACLPEN +#define RCC_AHB1PeriphLpen_DMA2 RCC_AHB1LPENR_DMA2LPEN +#define RCC_AHB1PeriphLpen_DMA1 RCC_AHB1LPENR_DMA1LPEN +#define RCC_AHB1PeriphLpen_BKPSRAM RCC_AHB1LPENR_BKPSRAMLPEN +#define RCC_AHB1PeriphLpen_SRAM2 RCC_AHB1LPENR_SRAM2LPEN +#define RCC_AHB1PeriphLpen_SRAM1 RCC_AHB1LPENR_SRAM1LPEN +#define RCC_AHB1PeriphLpen_CRC RCC_AHB1LPENR_CRCLPEN +#define RCC_AHB1PeriphLpen_GPIOH RCC_AHB1LPENR_GPIOHLPEN +#define RCC_AHB1PeriphLpen_GPIOE RCC_AHB1LPENR_GPIOELPEN +#define RCC_AHB1PeriphLpen_GPIOD RCC_AHB1LPENR_GPIODLPEN +#define RCC_AHB1PeriphLpen_GPIOC RCC_AHB1LPENR_GPIOCLPEN +#define RCC_AHB1PeriphLpen_GPIOB RCC_AHB1LPENR_GPIOBLPEN +#define RCC_AHB1PeriphLpen_GPIOA RCC_AHB1LPENR_GPIOALPEN +#define IS_RCC_AHB1LP_PERIPH(PERIPH) (((PERIPH) == RCC_AHB1PeriphLpen_USBOTGHS) || ((PERIPH) == RCC_AHB1PeriphLpen_ETHMACPTP) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_ETHMACRX) || ((PERIPH) == RCC_AHB1PeriphLpen_ETHMACTX) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_ETHMAC) || ((PERIPH) == RCC_AHB1PeriphLpen_DMA2) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_DMA1) || ((PERIPH) == RCC_AHB1PeriphLpen_BKPSRAM) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_SRAM2) || ((PERIPH) == RCC_AHB1PeriphLpen_SRAM1) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_CRC) || ((PERIPH) == RCC_AHB1PeriphLpen_GPIOH) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_GPIOE) || ((PERIPH) == RCC_AHB1PeriphLpen_GPIOD) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_GPIOC) || ((PERIPH) == RCC_AHB1PeriphLpen_GPIOB) || \ + ((PERIPH) == RCC_AHB1PeriphLpen_GPIOA)) + +#define RCC_AHB2PeriphLpen_USBOTGFS RCC_AHB2LPENR_OTGFSLPEN +#define RCC_AHB2PeriphLpen_RNG RCC_AHB2LPENR_RNGLPEN +#define IS_RCC_AHB2LP_PERIPH(PERIPH) (((PERIPH) == RCC_AHB2PeriphLpen_USBOTGFS) || ((PERIPH) == RCC_AHB2PeriphLpen_RNG)) + +#define RCC_AHB3PeriphLpen_QSPI RCC_AHB3LPENR_QSPILPEN +#define RCC_AHB3PeriphLpen_FMC RCC_AHB3LPENR_FMCLPEN +#define IS_RCC_AHB3LP_PERIPH(PERIPH) (((PERIPH) == RCC_AHB3PeriphLpen_QSPI) || ((PERIPH) == RCC_AHB3PeriphLpen_FMC)) +/** + * @} + */ + +//RCC_APB1/2_PERIPH_LPCLKEN_REG +/** @defgroup RCC_APB1/2_Peripherals_Lpclken + * @{ + */ +#define RCC_APB1PeriphLpen_UART7 RCC_APB1LPENR_UART7LPEN +#define RCC_APB1PeriphLpen_RAMP RCC_APB1LPENR_RAMPLPEN +#define RCC_APB1PeriphLpen_DAC RCC_APB1LPENR_DACLPEN +#define RCC_APB1PeriphLpen_PWR RCC_APB1LPENR_PWRLPEN +#define RCC_APB1PeriphLpen_CAN4 RCC_APB1LPENR_CAN4LPEN +#define RCC_APB1PeriphLpen_CAN3 RCC_APB1LPENR_CAN3LPEN +#define RCC_APB1PeriphLpen_CAN2 RCC_APB1LPENR_CAN2LPEN +#define RCC_APB1PeriphLpen_CAN1 RCC_APB1LPENR_CAN1LPEN +#define RCC_APB1PeriphLpen_I2C3 RCC_APB1LPENR_I2C3LPEN +#define RCC_APB1PeriphLpen_I2C2 RCC_APB1LPENR_I2C2LPEN +#define RCC_APB1PeriphLpen_I2C1 RCC_APB1LPENR_I2C1LPEN +#define RCC_APB1PeriphLpen_UART5 RCC_APB1LPENR_UART5LPEN +#define RCC_APB1PeriphLpen_UART4 RCC_APB1LPENR_UART4LPEN +#define RCC_APB1PeriphLpen_UART3 RCC_APB1LPENR_UART3LPEN +#define RCC_APB1PeriphLpen_UART2 RCC_APB1LPENR_UART2LPEN +#define RCC_APB1PeriphLpen_LPUART RCC_APB1LPENR_LPUARTLPEN +#define RCC_APB1PeriphLpen_SPI3 RCC_APB1LPENR_SPI3LPEN +#define RCC_APB1PeriphLpen_SPI2 RCC_APB1LPENR_SPI2LPEN +#define RCC_APB1PeriphLpen_I2S3 RCC_APB1LPENR_I2S3LPEN +#define RCC_APB1PeriphLpen_I2S2 RCC_APB1LPENR_I2S2LPEN +#define RCC_APB1PeriphLpen_WWDG RCC_APB1LPENR_WWDGLPEN +#define RCC_APB1PeriphLpen_AC97 RCC_APB1LPENR_AC97LPEN +#define RCC_APB1PeriphLpen_CRS RCC_APB1LPENR_CRSLPEN +#define RCC_APB1PeriphLpen_TIM14 RCC_APB1LPENR_TIM14LPEN +#define RCC_APB1PeriphLpen_TIM13 RCC_APB1LPENR_TIM13LPEN +#define RCC_APB1PeriphLpen_TIM12 RCC_APB1LPENR_TIM12LPEN +#define RCC_APB1PeriphLpen_TIM7 RCC_APB1LPENR_TIM7LPEN +#define RCC_APB1PeriphLpen_TIM6 RCC_APB1LPENR_TIM6LPEN +#define RCC_APB1PeriphLpen_TIM5 RCC_APB1LPENR_TIM5LPEN +#define RCC_APB1PeriphLpen_TIM4 RCC_APB1LPENR_TIM4LPEN +#define RCC_APB1PeriphLpen_TIM3 RCC_APB1LPENR_TIM3LPEN +#define RCC_APB1PeriphLpen_TIM2 RCC_APB1LPENR_TIM2LPEN +#define IS_RCC_APB1LP_PERIPH(PERIPH) (((PERIPH) == RCC_APB1PeriphLpen_UART7) || ((PERIPH) == RCC_APB1PeriphLpen_RAMP) || \ + ((PERIPH) == RCC_APB1PeriphLpen_DAC) || ((PERIPH) == RCC_APB1PeriphLpen_PWR) || \ + ((PERIPH) == RCC_APB1PeriphLpen_CAN4) || ((PERIPH) == RCC_APB1PeriphLpen_CAN3) || \ + ((PERIPH) == RCC_APB1PeriphLpen_CAN2) || ((PERIPH) == RCC_APB1PeriphLpen_CAN1) || \ + ((PERIPH) == RCC_APB1PeriphLpen_I2C3) || ((PERIPH) == RCC_APB1PeriphLpen_I2C2) || \ + ((PERIPH) == RCC_APB1PeriphLpen_I2C1) || ((PERIPH) == RCC_APB1PeriphLpen_UART5) || \ + ((PERIPH) == RCC_APB1PeriphLpen_UART4) || ((PERIPH) == RCC_APB1PeriphLpen_UART3) || \ + ((PERIPH) == RCC_APB1PeriphLpen_UART2) || ((PERIPH) == RCC_APB1PeriphLpen_LPUART)|| \ + ((PERIPH) == RCC_APB1PeriphLpen_SPI3) || ((PERIPH) == RCC_APB1PeriphLpen_SPI2) || \ + ((PERIPH) == RCC_APB1PeriphLpen_I2S3) || ((PERIPH) == RCC_APB1PeriphLpen_I2S2) || \ + ((PERIPH) == RCC_APB1PeriphLpen_WWDG) || ((PERIPH) == RCC_APB1PeriphLpen_AC97) || \ + ((PERIPH) == RCC_APB1PeriphLpen_CRS) || ((PERIPH) == RCC_APB1PeriphLpen_TIM14) || \ + ((PERIPH) == RCC_APB1PeriphLpen_TIM13) || ((PERIPH) == RCC_APB1PeriphLpen_TIM12) || \ + ((PERIPH) == RCC_APB1PeriphLpen_TIM7) || ((PERIPH) == RCC_APB1PeriphLpen_TIM6) || \ + ((PERIPH) == RCC_APB1PeriphLpen_TIM5) || ((PERIPH) == RCC_APB1PeriphLpen_TIM4) || \ + ((PERIPH) == RCC_APB1PeriphLpen_TIM3) || ((PERIPH) == RCC_APB1PeriphLpen_TIM2)) + +#define RCC_APB2PeriphLpen_EQEP RCC_APB2LPENR_EQEPLPEN +#define RCC_APB2PeriphLpen_ECAP RCC_APB2LPENR_ECAPLPEN +#define RCC_APB2PeriphLpen_EPWM4 RCC_APB2LPENR_EPWM4LPEN +#define RCC_APB2PeriphLpen_EPWM3 RCC_APB2LPENR_EPWM3LPEN +#define RCC_APB2PeriphLpen_EPWM2 RCC_APB2LPENR_EPWM2LPEN +#define RCC_APB2PeriphLpen_EPWM1 RCC_APB2LPENR_EPWM1LPEN +#define RCC_APB2PeriphLpen_TIM11 RCC_APB2LPENR_TIM11LPEN +#define RCC_APB2PeriphLpen_TIM10 RCC_APB2LPENR_TIM10LPEN +#define RCC_APB2PeriphLpen_TIM9 RCC_APB2LPENR_TIM9LPEN +#define RCC_APB2PeriphLpen_LPTIM RCC_APB2LPENR_LPTIMLPEN +#define RCC_APB2PeriphLpen_SYSCFG RCC_APB2LPENR_SYSCFGLPEN +#define RCC_APB2PeriphLpen_SPI1 RCC_APB2LPENR_SPI1LPEN +#define RCC_APB2PeriphLpen_SDIO RCC_APB2LPENR_SDIOLPEN +#define RCC_APB2PeriphLpen_SPD RCC_APB2LPENR_SPDLPEN +#define RCC_APB2PeriphLpen_ADC RCC_APB2LPENR_ADCLPEN +#define RCC_APB2PeriphLpen_USART6 RCC_APB2LPENR_USART6LPEN +#define RCC_APB2PeriphLpen_USART1 RCC_APB2LPENR_USART1LPEN +#define RCC_APB2PeriphLpen_TIM8 RCC_APB2LPENR_TIM8LPEN +#define RCC_APB2PeriphLpen_TIM1 RCC_APB2LPENR_TIM1LPEN +#define IS_RCC_APB2LP_PERIPH(PERIPH) (((PERIPH) == RCC_APB2PeriphLpen_EQEP) || ((PERIPH) == RCC_APB2PeriphLpen_ECAP) || \ + ((PERIPH) == RCC_APB2PeriphLpen_EPWM4) || ((PERIPH) == RCC_APB2PeriphLpen_EPWM3) || \ + ((PERIPH) == RCC_APB2PeriphLpen_EPWM2) || ((PERIPH) == RCC_APB2PeriphLpen_EPWM1) || \ + ((PERIPH) == RCC_APB2PeriphLpen_TIM11) || ((PERIPH) == RCC_APB2PeriphLpen_TIM10) || \ + ((PERIPH) == RCC_APB2PeriphLpen_TIM9) || ((PERIPH) == RCC_APB2PeriphLpen_LPTIM) || \ + ((PERIPH) == RCC_APB2PeriphLpen_SYSCFG) || ((PERIPH) == RCC_APB2PeriphLpen_SPI1) || \ + ((PERIPH) == RCC_APB2PeriphLpen_SDIO) || ((PERIPH) == RCC_APB2PeriphLpen_SPD) || \ + ((PERIPH) == RCC_APB2PeriphLpen_ADC) || ((PERIPH) == RCC_APB2PeriphLpen_USART6) || \ + ((PERIPH) == RCC_APB2PeriphLpen_USART1) || ((PERIPH) == RCC_APB2PeriphLpen_TIM8) || \ + ((PERIPH) == RCC_APB2PeriphLpen_TIM1)) +/** + * @} + */ + +/** @defgroup RCC_QSPI_clock_source + * @{ + */ +#define RCC_QSPICLK_SYSCLK ((uint32_t)0x00000000) +#define RCC_QSPICLK_HSI16 ((uint32_t)0x40000000) +#define RCC_QSPICLK_PLL1Q ((uint32_t)0x80000000) +#define IS_RCC_QSPICLK(QSPICLK) (((QSPICLK) == RCC_QSPICLK_SYSCLK) || ((QSPICLK) == RCC_QSPICLK_HSI16) || \ + ((QSPICLK) == RCC_QSPICLK_PLL1Q)) +/** + * @} + */ + +/** @defgroup RCC_ADC_clock_source + * @{ + */ +/* These defines are obsolete and kept for legacy purpose only. +Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */ +#define RCC_ADCCLK_NOCLK ((uint32_t)0x00000000) +#define RCC_ADCCLK_PLL1R ((uint32_t)0x10000000) +#define RCC_ADCCLK_SYSCLK ((uint32_t)0x20000000) +#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_NOCLK) || ((ADCCLK) == RCC_ADCCLK_PLL1R) || \ + ((ADCCLK) == RCC_ADCCLK_SYSCLK)) +/** + * @} + */ + +/** @defgroup RCC_CAN_clock_source + * @{ + */ +#define RCC_CANCLK_HCLK ((uint32_t)0x00000000) +#define RCC_CANCLK_HCLK_DIV2 ((uint32_t)0x08000000) +#define RCC_CANCLK_HCLK_DIV4 ((uint32_t)0x09000000) +#define RCC_CANCLK_HCLK_DIV8 ((uint32_t)0x0A000000) +#define RCC_CANCLK_HCLK_DIV16 ((uint32_t)0x0B000000) +#define RCC_CANCLK_HCLK_DIV32 ((uint32_t)0x0C000000) +#define IS_RCC_CANCLK(CANCLK) (((CANCLK) == RCC_CANCLK_HCLK) || ((CANCLK) == RCC_CANCLK_HCLK_DIV2) || \ + ((CANCLK) == RCC_CANCLK_HCLK_DIV4) || ((CANCLK) == RCC_CANCLK_HCLK_DIV8) || \ + ((CANCLK) == RCC_CANCLK_HCLK_DIV16) || ((CANCLK) == RCC_CANCLK_HCLK_DIV32)) +/** + * @} + */ + +/** @defgroup RCC_LPTIM_clock_source + * @{ + */ +#define RCC_LPTIMCLK_PCLK ((uint32_t)0x00000000) +#define RCC_LPTIMCLK_LSI ((uint32_t)0x00040000) +#define RCC_LPTIMCLK_HSI16 ((uint32_t)0x00080000) +#define RCC_LPTIMCLK_LSE ((uint32_t)0x000C0000) +#define IS_RCC_LPTIMCLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIMCLK_PCLK) || ((LPTIMCLK) == RCC_LPTIMCLK_LSI) || \ + ((LPTIMCLK) == RCC_LPTIMCLK_HSI16) || ((LPTIMCLK) == RCC_LPTIMCLK_LSE)) +/** + * @} + */ + +/** @defgroup RCC_I2C3_clock_source + * @{ + */ +#define RCC_I2C3CLK_PCLK ((uint32_t)0x00000000) +#define RCC_I2C3CLK_SYSCLK ((uint32_t)0x00010000) +#define RCC_I2C3CLK_HSI16 ((uint32_t)0x00020000) +#define IS_RCC_I2C3CLK(I2C3CLK) (((I2C3CLK) == RCC_I2C3CLK_PCLK) || ((I2C3CLK) == RCC_I2C3CLK_SYSCLK) || \ + ((I2C3CLK) == RCC_I2C3CLK_HSI16)) +/** + * @} + */ + +/** @defgroup RCC_I2C2_clock_source + * @{ + */ +#define RCC_I2C2CLK_PCLK ((uint32_t)0x00000000) +#define RCC_I2C2CLK_SYSCLK ((uint32_t)0x00004000) +#define RCC_I2C2CLK_HSI16 ((uint32_t)0x00008000) +#define IS_RCC_I2C2CLK(I2C2CLK) (((I2C2CLK) == RCC_I2C2CLK_PCLK) || ((I2C2CLK) == RCC_I2C2CLK_SYSCLK) || \ + ((I2C2CLK) == RCC_I2C2CLK_HSI16)) +/** + * @} + */ + +/** @defgroup RCC_I2C1_clock_source + * @{ + */ +#define RCC_I2C1CLK_PCLK ((uint32_t)0x00000000) +#define RCC_I2C1CLK_SYSCLK ((uint32_t)0x00001000) +#define RCC_I2C1CLK_HSI16 ((uint32_t)0x00002000) +#define IS_RCC_I2C1CLK(I2C1CLK) (((I2C1CLK) == RCC_I2C1CLK_PCLK) || ((I2C1CLK) == RCC_I2C1CLK_SYSCLK) || \ + ((I2C1CLK) == RCC_I2C1CLK_HSI16)) +/** + * @} + */ + +/** @defgroup RCC_LPUART_clock_source + * @{ + */ +#define RCC_LPUARTCLK_PCLK ((uint32_t)0x00000000) +#define RCC_LPUARTCLK_LSE ((uint32_t)0x00000800) +#define IS_RCC_LPUARTCLK(LPUARTCLK) (((LPUARTCLK) == RCC_LPUARTCLK_PCLK) || ((LPUARTCLK) == RCC_LPUARTCLK_LSE)) +/** + * @} + */ + +/** @defgroup RCC_RNG_clock_div_factors + * @{ + */ +#define RCC_RNGCLK_DIV1 ((uint32_t)0x00000000) +#define RCC_RNGCLK_DIV2 ((uint32_t)0x00000100) +#define RCC_RNGCLK_DIV4 ((uint32_t)0x00000200) +#define RCC_RNGCLK_DIV8 ((uint32_t)0x00000300) +#define IS_RCC_RNGCLK_DIV(DIV) (((DIV) == RCC_RNGCLK_DIV1) || ((DIV) == RCC_RNGCLK_DIV2) || \ + ((DIV) == RCC_RNGCLK_DIV4) || ((DIV) == RCC_RNGCLK_DIV8)) +/** + * @} + */ + +/** @defgroup RCC_48M_clock_source + * @{ + */ +#define RCC_48MCLK_HSI48 ((uint32_t)0x00000000) +#define RCC_48MCLK_PLLQ ((uint32_t)0x00000080) +#define IS_RCC_48MCLK(RCC48MCLK) (((RCC48MCLK) == RCC_48MCLK_HSI48) || ((RCC48MCLK) == RCC_48MCLK_PLLQ)) +/** + * @} + */ + +/** @defgroup RCC_EPWM_clock_source + * @{ + */ +#define RCC_EPWMCLK_SYSCLK ((uint32_t)0x00000000) +#define RCC_EPWMCLK_SYSCLK_DIV2 ((uint32_t)0x00000020) +#define RCC_EPWMCLK_SYSCLK_DIV4 ((uint32_t)0x00000040) +#define IS_RCC_EPWMCLK(EPWMCLK) (((EPWMCLK) == RCC_EPWMCLK_SYSCLK) || ((EPWMCLK) == RCC_EPWMCLK_SYSCLK_DIV2) || \ + ((EPWMCLK) == RCC_EPWMCLK_SYSCLK_DIV4)) +/** + * @} + */ + +/** @defgroup RCC_EQEP_clock_source + * @{ + */ +#define RCC_EQEPCLK_SYSCLK ((uint32_t)0x00000000) +#define RCC_EQEPCLK_SYSCLK_DIV2 ((uint32_t)0x00000008) +#define RCC_EQEPCLK_SYSCLK_DIV4 ((uint32_t)0x00000010) +#define IS_RCC_EQEPCLK(EQEPCLK) (((EQEPCLK) == RCC_EQEPCLK_SYSCLK) || ((EQEPCLK) == RCC_EQEPCLK_SYSCLK_DIV2) || \ + ((EQEPCLK) == RCC_EQEPCLK_SYSCLK_DIV4)) +/** + * @} + */ + +/** @defgroup RCC_ECAP_clock_source + * @{ + */ +#define RCC_ECAPCLK_SYSCLK ((uint32_t)0x00000000) +#define RCC_ECAPCLK_SYSCLK_DIV2 ((uint32_t)0x00000002) +#define RCC_ECAPCLK_SYSCLK_DIV4 ((uint32_t)0x00000004) +#define IS_RCC_ECAPCLK(ECAPCLK) (((ECAPCLK) == RCC_ECAPCLK_SYSCLK) || ((ECAPCLK) == RCC_ECAPCLK_SYSCLK_DIV2) || \ + ((ECAPCLK) == RCC_ECAPCLK_SYSCLK_DIV4)) +/** + * @} + */ + +/** @defgroup RCC_I2S_clock_source + * @{ + */ +#define RCC_I2SCLK_PLL2Q ((uint32_t)0x00000000) +#define RCC_I2SCLK_I2S_CLKIN ((uint32_t)0x00000001) +#define IS_RCC_I2SCLK(I2SCLK) (((I2SCLK) == RCC_I2SCLK_PLL2Q) || ((I2SCLK) == RCC_I2SCLK_I2S_CLKIN)) +/** + * @} + */ + + +//RCC_BDCR_REG +/** @defgroup RCC_LSCO_clock_source + * @brief + * @{ + */ +#define RCC_LSCOCLK_LSE RCC_BDCR_LSCOSEL_LSE +#define RCC_LSCOCLK_LSI RCC_BDCR_LSCOSEL_LSI +#define IS_RCC_LSCOCLK_SRC(SRC) (((SRC) == RCC_LSCOCLK_LSE) || ((SRC) == RCC_LSCOCLK_LSI)) +/** + * @} + */ + +/** @defgroup RCC_LSCO_clock_enable + * @brief + * @{ + */ +#define RCC_LSCOCLK_OFF ((uint32_t)0x00000000) +#define RCC_LSCOCLK_ON ((uint32_t)0x01000000) +#define IS_RCC_LSCOCLK_STATUS(STATUS) (((STATUS) == RCC_LSCOCLK_OFF) || ((STATUS) == RCC_LSCOCLK_ON)) +/** + * @} + */ + +/** @defgroup RCC_RTC_soft_reset + * @brief + * @{ + */ +#define RCC_RTC_BDRST_OFF ((uint32_t)0x00000000) +#define RCC_RTC_BDRST_ON ((uint32_t)0x00010000) +#define IS_RCC_RTC_BDRST(BDRST) (((BDRST) == RCC_RTC_BDRST_OFF) || ((BDRST) == RCC_RTC_BDRST_ON)) +/** + * @} + */ + +/** @defgroup RCC_RTC_clock_enable + * @brief + * @{ + */ +#define RCC_RTCCLK_OFF ((uint32_t)0x00000000) +#define RCC_RTCCLK_ON ((uint32_t)0x00008000) +#define IS_RCC_RTCCLK_ENABLE(RTCCLK) (((RTCCLK) == RCC_RTCCLK_OFF) || ((RTCCLK) == RCC_RTCCLK_ON)) +/** + * @} + */ + +/** @defgroup RCC_RTC_clock_source + * @brief + * @{ + */ +#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSEDIV32 +#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI +#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE +#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_HSE_Div32) || ((SOURCE) == RCC_RTCCLKSource_LSI) || \ + ((SOURCE) == RCC_RTCCLKSource_LSE)) +/** + * @} + */ + +/** @defgroup RCC_LSE_drv + * @brief + * @{ + */ +#define RCC_LSEDrive_Low ((uint32_t)0x00000000) +#define RCC_LSEDrive_MediumLow ((uint32_t)0x00000008) +#define RCC_LSEDrive_MediumHigh ((uint32_t)0x00000010) +#define RCC_LSEDrive_High ((uint32_t)0x00000018) +#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \ + ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High)) +/** + * @} + */ + +/** @defgroup RCC_LSE_config + * @brief + * @{ + */ +#define RCC_LSE_OFF ((uint32_t)0x00000000) +#define RCC_LSE_ON ((uint32_t)0x00000001) +#define RCC_LSE_BYP ((uint32_t)0x00000005) +#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ + ((LSE) == RCC_LSE_BYP)) +/** + * @} + */ + + +/** @defgroup RCC_LSI_clock_enable + * @brief + * @{ + */ +#define RCC_LSI_OFF ((uint32_t)0x00000000) +#define RCC_LSI_ON ((uint32_t)0x00000001) +#define RCC_LSI_RDY ((uint32_t)0x00000002) +#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON) || \ + ((LSI) == RCC_LSI_RDY)) +/** + * @} + */ + +//RCC_RAMCTL_REG +/** @defgroup RCC_RAMCTL_config + * @brief + * @{ + */ +#define RCC_DCACHE_CTL RCC_RAMCTL_DCHRAMSEL +#define RCC_ICACHE_CTL RCC_RAMCTL_ICHRAMSEL +#define RCC_ETHMAC_CTL RCC_RAMCTL_ETHRAMSEL +#define RCC_CAN_CTL RCC_RAMCTL_CANRAMSEL +#define RCC_USBHS_CTL RCC_RAMCTL_UHSRAMSEL +#define RCC_USBFS_CTL RCC_RAMCTL_UFSRAMSEL +#define IS_RCC_RAMCTL(CTL) (((CTL) == RCC_DCACHE_CTL) || ((CTL) == RCC_ICACHE_CTL) || \ + ((CTL) == RCC_ETHMAC_CTL) || ((CTL) == RCC_CAN_CTL) || \ + ((CTL) == RCC_USBHS_CTL) || ((CTL) == RCC_USBFS_CTL)) + +#define RCC_RAM_CTL_SELF ((uint32_t)0x00000000) +#define RCC_RAM_CTL_AHB ((uint32_t)0x00000001) +#define IS_RCC_RAMCTL_SEL(SEL) (((SEL) == RCC_RAM_CTL_SELF) || ((SEL) == RCC_RAM_CTL_AHB)) + +/** + * @} + */ + + + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the RCC clock configuration to the default reset state */ +void RCC_DeInit(void); + +/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/ +void RCC_HSEConfig(uint32_t RCC_HSE);/* Function used config hse */ +ErrorStatus RCC_WaitForHSEStartUp(void);/* Function used wait hserdy */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);/* Function usde hsi calibration value */ +void RCC_HSICmd(FunctionalState NewState);/* Function usde enable hsi */ +ErrorStatus RCC_WaitForHSIStartUp(void);/* Function used wait hsirdy */ +void RCC_AdjustHSI48CalibrationValue(uint32_t HSI48CalibrationValue);/* Function used hsi48 calibration value */ +void RCC_HSI48Cmd(FunctionalState NewState);/* Function used enable hsi48 */ +ErrorStatus RCC_WaitForHSI48StartUp(void);/* Function used wait hsi48rdy */ +void RCC_LSEConfig(uint32_t RCC_LSE);/* Function used config lse */ +ErrorStatus RCC_WaitForLSEStartUp(void);/* Function used wait lserdy */ +void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);/* Functoion usde config lse drive */ +void RCC_LSICmd(FunctionalState NewState);/* Function used enable lsi */ +ErrorStatus RCC_WaitForLSIStartUp(void);/* Function used wait lsirdy */ +/* Function used config pllsource, pllm and plln */ +void RCC_PLLVcoOutputConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLNul, uint32_t RCC_PLLMul); +void RCC_PLLROutputConfig(uint32_t RCC_PLLRStatus, uint32_t RCC_PLLR);/* Function used config pllren and pllr division value */ +void RCC_PLLQOutputConfig(uint32_t RCC_PLLQStatus, uint32_t RCC_PLLQ);/* Function used config pllqen and pllq division value */ +void RCC_PLLPOutputConfig(uint32_t RCC_PLLPStatus, uint32_t RCC_PLLP);/* Function used config pllpen and pllp division value */ +/* Function used config pll2source, pll2m and pll2n */ +void RCC_PLL2VcoOutputConfig(uint32_t RCC_PLL2Source, uint32_t RCC_PLL2Nul, uint32_t RCC_PLL2Mul); +void RCC_PLL2ROutputConfig(uint32_t RCC_PLL2RStatus, uint32_t RCC_PLL2R);/* Function used config pll2ren and pll2r division value */ +void RCC_PLL2QOutputConfig(uint32_t RCC_PLL2QStatus, uint32_t RCC_PLL2Q);/* Function used config pll2qen and pll2q division value */ +void RCC_PLLCmd(uint32_t RCC_PLLSelect, FunctionalState NewState);/* Function used enable pll and pll2 */ +ErrorStatus RCC_WaitForPLLStartUp(void);/* Function used wait pllrdy */ +ErrorStatus RCC_WaitForPLL2StartUp(void);/* Function used wait pll2rdy */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState);/* Function used enable css */ +void RCC_MCOConfig(uint32_t RCC_MCOSource, uint32_t RCC_MCOPrescaler); /* Function used config MCO source and prescaler */ + +/* System, AHB and APB busses clocks configuration functions ******************/ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);/* Function used config sysclk's source */ +uint32_t RCC_GetSYSCLKSource(void);/* Function usde get sysclk's source */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK);/* Function used config hclk's frequence */ +void RCC_PCLK1Config(uint32_t RCC_HCLK1);/* Function used config pclk1's frequence */ +void RCC_PCLK2Config(uint32_t RCC_HCLK2);/* Function used config pclk2's frequence */ +void RCC_QSPICLKConfig(uint32_t RCC_QSPICLK); /* Function used config qspi clk */ +void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* Function used config adc123 clk */ +void RCC_CANCLKConfig(uint32_t RCC_CANCLK); /* Function used config can clk */ +void RCC_LPTIMCLKConfig(uint32_t RCC_LPTIMCLK); /* Function used config lptim clk */ +void RCC_I2C3CLKConfig(uint32_t RCC_I2C3CLK); /* Function used config i2c3 clk */ +void RCC_I2C2CLKConfig(uint32_t RCC_I2C2CLK); /* Function used config i2c2 clk */ +void RCC_I2C1CLKConfig(uint32_t RCC_I2C1CLK); /* Function used config i2c1 clk */ +void RCC_LPUARTCLKConfig(uint32_t RCC_LPUARTCLK);/* Function used config lpuart clk */ +void RCC_RNGCLKDIVConfig(uint32_t RCC_RNGCLKDIV);/* Function used config rng division */ +void RCC_48MCLKConfig(uint32_t RCC_48MCLK);/* Function used config 48MCLK's source */ +void RCC_EPWMCLKConfig(uint32_t RCC_EPWMCLK);/* Function used config EPWM source */ +void RCC_EQEPCLKConfig(uint32_t RCC_EQEPCLK);/* Function used config EQEP source */ +void RCC_ECAPCLKConfig(uint32_t RCC_ECAPCLK);/* Function used config ECAP source */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLK);/* Function used config I2S source */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); + +/* Peripheral clocks configuration functions **********************************/ +void RCC_LSCOCLKConfig(uint32_t RCC_LSCOCLKSource); +void RCC_LSCOCLKCmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState); +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState); +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_AHB1PeriphLpenCmd(uint32_t RCC_AHB1PeriphLpen, FunctionalState NewState); +void RCC_AHB2PeriphLpenCmd(uint32_t RCC_AHB2PeriphLpen, FunctionalState NewState); +void RCC_AHB3PeriphLpenCmd(uint32_t RCC_AHB3PeriphLpen, FunctionalState NewState); +void RCC_APB1PeriphLpenCmd(uint32_t RCC_APB1PeriphLpen, FunctionalState NewState); +void RCC_APB2PeriphLpenCmd(uint32_t RCC_APB2PeriphLpen, FunctionalState NewState); +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1PeriphRst, FunctionalState NewState); +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2PeriphRst, FunctionalState NewState); +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3PeriphRst, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1PeriphRst, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2PeriphRst, FunctionalState NewState); + + + +/* Interrupts and flags management functions **********************************/ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG_REG, uint32_t RCC_FLAG); +void RCC_ClrRstFlag(void); +void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState); +ITStatus RCC_GetITStatus(uint32_t RCC_IT_FLAG); +void RCC_ClearITPendingBit(uint32_t RCC_IT_CLR); +void RCC_RamCtrlSel(uint32_t RCC_RAM_CTL, uint32_t RCC_RAM_CTL_SEL); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F0XX_RCC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rng.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rng.h new file mode 100644 index 00000000000..6f577639d8e --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rng.h @@ -0,0 +1,47 @@ +/** + ****************************************************************************** + * @file ft32f4xx_rng.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the rng + * firmware library. + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_RNG_H +#define __FT32F4XX_RNG_H + +#ifdef __cplusplus +extern "C" { +#endif + + +#include "ft32f4xx.h" + +void RNG_Init(); +void RNG_DeInit(FunctionalState NewState); + +uint32_t RNG_GenerateRandomNumber(); +void RNG_IT(FunctionalState NewState); +uint8_t RNG_get_error_status(); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F0XX_RNG_H */ + +/** + * @} + */ +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ + + + + + + + + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rtc.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rtc.h new file mode 100644 index 00000000000..f99a7d21f63 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_rtc.h @@ -0,0 +1,911 @@ +/** + ****************************************************************************** + * @file ft32f4xx_rtc.h + * @author Rwang + * @brief This file contains all the functions prototypes for the RTC firmware + * library. + * @version V1.0.0 + * @data 2025-03-24 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_RTC_H +#define __FT32F4XX_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "ft32f407xe.h" + + + +/** @addtogroup RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format. + This parameter can be a value of @ref RTC_Hour_Formats */ + + uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be set to a value lower than 0x7F */ + + uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value. + This parameter must be set to a value lower than 0x1FFF */ +} RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour. + This parameter must be set to a value in the 0-12 range + if the RTC_HourFormat_12 is selected or 0-23 range if + the RTC_HourFormat_24 is selected. */ + + uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be set to a value in the 0-59 range. */ + + uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time. + This parameter can be a value of @ref RTC_AM_PM_Definitions */ +} RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay. + This parameter can be a value of @ref RTC_WeekDay_Definitions */ + + uint8_t RTC_Month; /*!< Specifies the RTC Date Month. + This parameter can be a value of @ref RTC_Month_Date_Definitions */ + + uint8_t RTC_Date; /*!< Specifies the RTC Date. + This parameter must be set to a value in the 1-31 range. */ + + uint8_t RTC_Year; /*!< Specifies the RTC Date Year. + This parameter must be set to a value in the 0-99 range. */ +} RTC_DateTypeDef; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + + uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks. + This parameter can be a value of @ref RTC_AlarmMask_Definitions */ + + uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay. + This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */ + + uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay. + This parameter must be set to a value in the 1-31 range + if the Alarm Date is selected. + This parameter can be a value of @ref RTC_WeekDay_Definitions + if the Alarm WeekDay is selected. */ +} RTC_AlarmTypeDef; + + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup RTC_Exported_Constants + * @{ + */ + + +/** @defgroup RTC_Hour_Formats + * @{ + */ +#define RTC_HourFormat_24 ((uint32_t)0x00000000) +#define RTC_HourFormat_12 RTC_CR_FMT +#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \ + ((FORMAT) == RTC_HourFormat_24)) +/** + * @} + */ + +/** @defgroup RTC_Asynchronous_Predivider PREDIV_A[6:0] + * @{ + */ +#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F) +/** + * @} + */ + + +/** @defgroup RTC_Synchronous_Predivider PREDIV_S[14:0] + * @{ + */ +#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF) +/** + * @} + */ + +/** @defgroup RTC_Weakup_counter WUT[15:0] + * @{ + */ +#define IS_RTC_WeakUp_CNT(CNT) ((CNT) <= 0xFFFF) +/** + * @} + */ + + +/** @defgroup RTC_Time_Definitions + * @{ + */ +#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12)) +#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23) +#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59) +#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59) +/** + * @} + */ + +/** @defgroup RTC_AM_PM_Definitions + * @{ + */ +#define RTC_H12_AM ((uint32_t)0x00000000) +#define RTC_H12_PM ((uint32_t)0x00000001) +#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM)) +/** + * @} + */ + +/** @defgroup RTC_Year_Date_Definitions + * @{ + */ +#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99) +/** + * @} + */ + +/** @defgroup RTC_Month_Date_Definitions + * @{ + */ +#define RTC_Month_January ((uint8_t)0x01) +#define RTC_Month_February ((uint8_t)0x02) +#define RTC_Month_March ((uint8_t)0x03) +#define RTC_Month_April ((uint8_t)0x04) +#define RTC_Month_May ((uint8_t)0x05) +#define RTC_Month_June ((uint8_t)0x06) +#define RTC_Month_July ((uint8_t)0x07) +#define RTC_Month_August ((uint8_t)0x08) +#define RTC_Month_September ((uint8_t)0x09) +#define RTC_Month_October ((uint8_t)0x10) +#define RTC_Month_November ((uint8_t)0x11) +#define RTC_Month_December ((uint8_t)0x12) +#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12)) +#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31)) +/** + * @} + */ + +/** @defgroup RTC_WeekDay_Definitions + * @{ + */ +#define RTC_Weekday_Monday ((uint8_t)0x01) +#define RTC_Weekday_Tuesday ((uint8_t)0x02) +#define RTC_Weekday_Wednesday ((uint8_t)0x03) +#define RTC_Weekday_Thursday ((uint8_t)0x04) +#define RTC_Weekday_Friday ((uint8_t)0x05) +#define RTC_Weekday_Saturday ((uint8_t)0x06) +#define RTC_Weekday_Sunday ((uint8_t)0x07) +#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday) ) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Definitions + * @{ + */ +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \ + ((WEEKDAY) == RTC_Weekday_Tuesday) || \ + ((WEEKDAY) == RTC_Weekday_Wednesday) || \ + ((WEEKDAY) == RTC_Weekday_Thursday) || \ + ((WEEKDAY) == RTC_Weekday_Friday) || \ + ((WEEKDAY) == RTC_Weekday_Saturday) || \ + ((WEEKDAY) == RTC_Weekday_Sunday) ) +/** + * @} + */ + + +/** @defgroup RTC_AlarmDateWeekDay_Definitions + * @{ + */ +#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000) +#define RTC_AlarmDateWeekDaySel_WeekDay RTC_ALRMAR_WDSEL + +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \ + ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay) ) +/** + * @} + */ + + +/** @defgroup RTC_AlarmMask_Definitions + * @{ + */ +#define RTC_AlarmMask_None ((uint32_t)0x00000000) +#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000) +#define RTC_AlarmMask_Hours ((uint32_t)0x00800000) +#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000) +#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080) +#define RTC_AlarmMask_All ((uint32_t)0x80808080) +#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Definitions(RTC_ALARMA or RTC_ALARMB) + * @{ + */ +#define RTC_Alarm_A ((uint32_t)0x00000100) +#define RTC_Alarm_B ((uint32_t)0x00000200) +#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B)) +#define IS_RTC_CMD_ALARM(ALARM) ((((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET) || \ + (((ALARM) & (RTC_Alarm_B)) != (uint32_t)RESET) ) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions. + * @{ + */ +#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked. + There is no comparison on sub second for Alarm */ +#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm + comparison. Only SS[6:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match + to activate alarm. */ +#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \ + ((MASK) == RTC_AlarmSubSecondMask_SS14) || \ + ((MASK) == RTC_AlarmSubSecondMask_None) ) +/** + * @} + */ + +/** @defgroup RTC_Alarm_Sub_Seconds_Value + * @{ + */ +#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF) +/** + * @} + */ + +/** + * @} + */ +/** @defgroup RTC_Time_Stamp_Edges_definitions + * @{ + */ +#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000) +#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008) +#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \ + ((EDGE) == RTC_TimeStampEdge_Falling) ) +/** + * @} + */ + +/** @defgroup RTC_Output_selection_Definitions + * @{ + */ +#define RTC_Output_Disable ((uint32_t)0x00000000) +#define RTC_Output_AlarmA ((uint32_t)0x00200000) +#define RTC_Output_AlarmB ((uint32_t)0x00400000) +#define RTC_Output_WakeUp ((uint32_t)0x00600000) +#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \ + ((OUTPUT) == RTC_Output_AlarmA) || \ + ((OUTPUT) == RTC_Output_AlarmB) || \ + ((OUTPUT) == RTC_Output_WakeUp) ) +/** + * @} + */ + +/** @defgroup RTC_Output_Polarity_Definitions + * @{ + */ +#define RTC_OutputPolarity_High ((uint32_t)0x00000000) +#define RTC_OutputPolarity_Low ((uint32_t)0x00100000) +#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \ + ((POL) == RTC_OutputPolarity_Low)) +/** + * @} + */ + + +/** @defgroup RTC_Calib_Output_selection_Definitions + * @{ + */ +#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000) +#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000) +#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \ + ((OUTPUT) == RTC_CalibOutput_1Hz)) +/** + * @} + */ + +/** @defgroup RTC_Rough_Calib_Symbol_selection_Definitions + * @{ + */ +#define RTC_RoughCalibSymbol_Positive ((uint32_t)0x00000000) +#define RTC_RoughCalibSymbol_Negative ((uint32_t)0x00000080) +#define IS_RTC_ROUGH_CALIB_SYMBOL(SYMBOL) (((SYMBOL) == RTC_RoughCalibSymbol_Positive) || \ + ((SYMBOL) == RTC_RoughCalibSymbol_Negative)) +/** + * @} + */ + +/** @defgroup RTC_Rough_Calib_Dc_Value + * @{ + */ +#define IS_RTC_ROUGH_CALIB_DC_VALUE(VALUE) ((VALUE) <= 0x0000001F) +/** + * @} + */ + + +/** @defgroup RTC_Smooth_calib_period_Definitions + * @{ + */ +#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 32s, else 2exp20 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 16s, else 2exp19 RTCCLK seconds */ +#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation + period is 8s, else 2exp18 RTCCLK seconds */ +#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \ + ((PERIOD) == RTC_SmoothCalibPeriod_8sec) ) +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions + * @{ + */ +#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added + during a X -second window = Y - CALM[8:0]. + with Y = 512, 256, 128 when X = 32, 16, 8 */ +#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited + during a 32-second window = CALM[8:0]. */ +#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \ + ((PLUS) == RTC_SmoothCalibPlusPulses_Reset) ) +/** + * @} + */ + +/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions + * @{ + */ +#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +/** + * @} + */ + +/** @defgroup RTC_DayLightSaving_Definitions + * @{ + */ +#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000) +#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000) +#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \ + ((SAVING) == RTC_DayLightSaving_ADD1H)) + +#define RTC_StoreOperation_Reset ((uint32_t)0x00000000) +#define RTC_StoreOperation_Set ((uint32_t)0x00040000) +#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \ + ((OPERATION) == RTC_StoreOperation_Set) ) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Trigger1_Definitions + * @{ + */ +#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000) +#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000002) +#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000) +#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000002) +#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \ + ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \ + ((TRIGGER) == RTC_TamperTrigger_HighLevel) ) +/** + * @} + */ + + +/** @defgroup RTC_Tamper_Filter_Definitions + * @{ + */ +#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ + +#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2 + consecutive samples at the active level */ +#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4 + consecutive samples at the active level */ +#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8 + consecutive samples at the active leve. */ +#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \ + ((FILTER) == RTC_TamperFilter_2Sample) || \ + ((FILTER) == RTC_TamperFilter_4Sample) || \ + ((FILTER) == RTC_TamperFilter_8Sample)) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions + * @{ + */ +#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Tamper inputs sampled frequency = RTCCLK/32768 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Tamper inputs sampled frequency = RTCCLK/16384 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Tamper inputs sampled frequency = RTCCLK/8192 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Tamper inputs sampled frequency = RTCCLK/4096 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Tamper inputs sampled frequency = RTCCLK/2048 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Tamper inputs sampled frequency = RTCCLK/1024 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Tamper inputs sampled frequency = RTCCLK/512 */ +#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Tamper inputs sampled frequency = RTCCLK/256 */ +#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \ + ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256) ) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions +* @{ +*/ +#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are precharged 1 RTCCLK */ +#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are precharged 2 RTCCLK */ +#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are precharged 4 RTCCLK */ +#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are precharged 8 RTCCLK */ + +#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \ + ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK) ) +/** + * @} + */ + +/** @defgroup RTC_Tamper_Pins_Definitions + * @{ + */ +#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for input tamper 1 */ +#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for input tamper 2 */ +#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) +/** + * @} + */ + +/** @defgroup RTC_Output_Type_ALARM_OUT + * @{ + */ +#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000) +#define RTC_OutputType_PushPull ((uint32_t)0x00040000) +#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \ + ((TYPE) == RTC_OutputType_PushPull)) +#define RTC_PC13_OutputType_GPIO ((uint32_t)0x00000000) +#define RTC_PC13_OutputType_PushPull ((uint32_t)0x00080000) +#define IS_RTC_PC13_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_PC13_OutputType_GPIO) || \ + ((TYPE) == RTC_PC13_OutputType_PushPull)) +/** + * @} + */ + +/** @defgroup RTC_Pc15_Output_Type_Data + * @{ + */ +#define RTC_PC15_OutputType_GPIO ((uint32_t)0x00000000) +#define RTC_PC15_OutputType_PushPull ((uint32_t)0x00800000) +#define IS_RTC_PC15_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_PC15_OutputType_GPIO) || \ + ((TYPE) == RTC_PC15_OutputType_PushPull)) +#define RTC_PC15_OutputData_0 ((uint32_t)0x00000000) +#define RTC_PC15_OutputData_1 ((uint32_t)0x00400000) +#define IS_RTC_PC15_OUTPUT_DATA(DATA) (((DATA) == RTC_PC15_OutputData_0) || \ + ((DATA) == RTC_PC15_OutputData_1)) +/** + * @} + */ + +/** @defgroup RTC_Pc14_Output_Type_Data + * @{ + */ +#define RTC_PC14_OutputType_GPIO ((uint32_t)0x00000000) +#define RTC_PC14_OutputType_PushPull ((uint32_t)0x00200000) +#define IS_RTC_PC14_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_PC14_OutputType_GPIO) || \ + ((TYPE) == RTC_PC14_OutputType_PushPull)) +#define RTC_PC14_OutputData_0 ((uint32_t)0x00000000) +#define RTC_PC14_OutputData_1 ((uint32_t)0x00100000) +#define IS_RTC_PC14_OUTPUT_DATA(DATA) (((DATA) == RTC_PC14_OutputData_0) || \ + ((DATA) == RTC_PC14_OutputData_1)) +/** + * @} + */ + +/** @defgroup RTC_Add_1_Second_Parameter_Definitions + * @{ + */ +#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000) +#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000) +#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \ + ((SEL) == RTC_ShiftAdd1S_Set)) +/** + * @} + */ + +/** @defgroup RTC_Substract_Fraction_Of_Second_Value + * @{ + */ +#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Input_parameter_format_definitions + * @{ + */ +#define RTC_Format_BIN ((uint32_t)0x000000000) +#define RTC_Format_BCD ((uint32_t)0x000000001) +#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD)) + +/** + * @} + */ + +/** @defgroup RTC_Flags_Definitions + * @{ + */ +#define RTC_FLAG_RECALPF RTC_ISR_RECALPF +#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F +#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F +#define RTC_FLAG_TSOVF RTC_ISR_TSOVF +#define RTC_FLAG_TSF RTC_ISR_TSF +#define RTC_FLAG_WUTF RTC_ISR_WUTF +#define RTC_FLAG_ALRBF RTC_ISR_ALRBF +#define RTC_FLAG_ALRAF RTC_ISR_ALRAF +#define RTC_FLAG_INITF RTC_ISR_INITF +#define RTC_FLAG_RSF RTC_ISR_RSF +#define RTC_FLAG_INITS RTC_ISR_INITS +#define RTC_FLAG_SHPF RTC_ISR_SHPF +#define RTC_FLAG_WUTWF RTC_ISR_WUTWF +#define RTC_FLAG_ALRBWF RTC_ISR_ALRBWF +#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF + +#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RECALPF) || ((FLAG) == RTC_FLAG_TAMP2F) || \ + ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TSOVF) || \ + ((FLAG) == RTC_FLAG_TSF) || ((FLAG) == RTC_FLAG_WUTF) || \ + ((FLAG) == RTC_FLAG_ALRBF) || ((FLAG) == RTC_FLAG_ALRAF) || \ + ((FLAG) == RTC_FLAG_INITF) || ((FLAG) == RTC_FLAG_RSF) || \ + ((FLAG) == RTC_FLAG_INITS) || ((FLAG) == RTC_FLAG_SHPF) || \ + ((FLAG) == RTC_FLAG_WUTWF) || ((FLAG) == RTC_FLAG_ALRBWF) || \ + ((FLAG) == RTC_FLAG_ALRAWF)) +#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) == RTC_FLAG_TAMP2F) || ((FLAG) == RTC_FLAG_TAMP1F) || \ + ((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \ + ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \ + ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_RSF) ) +/** + * @} + */ + +/** @defgroup RTC_Interrupts_Definitions + * @{ + */ +#define RTC_IT_TS_EN ((uint32_t)0x00008000) +#define RTC_IT_WUT_EN ((uint32_t)0x00004000) +#define RTC_IT_ALRB_EN ((uint32_t)0x00002000) +#define RTC_IT_ALRA_EN ((uint32_t)0x00001000) +#define RTC_IT_TAMP_EN ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */ + + +#define IS_RTC_CONFIG_IT(IT) (((IT) == RTC_IT_TS_EN) || ((IT) == RTC_IT_WUT_EN) || \ + ((IT) == RTC_IT_ALRB_EN) || ((IT) == RTC_IT_ALRA_EN) || \ + ((IT) == RTC_IT_TAMP_EN)) +#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS_EN) || ((IT) == RTC_IT_WUT_EN) || \ + ((IT) == RTC_IT_ALRB_EN) || ((IT) == RTC_IT_ALRA_EN) || \ + ((IT) == RTC_IT_TAMP_EN)) + +#define RTC_IT_TAMP2_FLAG ((uint32_t)0x00008000) +#define RTC_IT_TAMP1_FLAG ((uint32_t)0x00004000) +#define RTC_IT_TS_FLAG ((uint32_t)0x00000800) +#define RTC_IT_WUT_FLAG ((uint32_t)0x00000400) +#define RTC_IT_ALRB_FLAG ((uint32_t)0x00000200) +#define RTC_IT_ALRA_FLAG ((uint32_t)0x00000100) + +#define IS_RTC_CLEAR_IT(IT) (((IT) == RTC_IT_TAMP2_FLAG) || ((IT) == RTC_IT_TAMP1_FLAG) || \ + ((IT) == RTC_IT_TS_FLAG) || ((IT) == RTC_IT_WUT_FLAG) || \ + ((IT) == RTC_IT_ALRB_FLAG) || ((IT) == RTC_IT_ALRB_FLAG)) +/** + * @} + */ + +/** @defgroup RTC_WeakUp_Clk_Choose + * @{ + */ +#define RTC_WeakUp_RTCCLK_Div16 ((uint32_t)0x00000000)/*auto weakup cnt clk use rtcclk/16*/ +#define RTC_WeakUp_RTCCLK_Div8 ((uint32_t)0x00000001)/*auto weakup cnt clk use rtcclk/8*/ +#define RTC_WeakUp_RTCCLK_Div4 ((uint32_t)0x00000002)/*auto weakup cnt clk use rtcclk/4*/ +#define RTC_WeakUp_RTCCLK_Div2 ((uint32_t)0x00000003)/*auto weakup cnt clk use rtcclk/2*/ +#define RTC_WeakUp_RTCCLK_CkSpre4 ((uint32_t)0x00000004)/*auto weakup cnt clk use ck_spre */ +#define RTC_WeakUp_RTCCLK_CkSpre5 ((uint32_t)0x00000005)/*auto weakup cnt clk use ck_spre */ +#define RTC_WeakUp_RTCCLK_CkSpre6 ((uint32_t)0x00000006)/*auto weakup cnt clk use ck_spre */ +#define RTC_WeakUp_RTCCLK_CkSpre7 ((uint32_t)0x00000007)/*auto weakup cnt clk use ck_spre */ + + +#define IS_RTC_WEAKUP_COUNT_FREQ(FREQ) (((FREQ) == RTC_WeakUp_RTCCLK_Div16) || ((FREQ) == RTC_WeakUp_RTCCLK_Div8) || \ + ((FREQ) == RTC_WeakUp_RTCCLK_Div4) || ((FREQ) == RTC_WeakUp_RTCCLK_Div2) || \ + ((FREQ) == RTC_WeakUp_RTCCLK_CkSpre4) || ((FREQ) == RTC_WeakUp_RTCCLK_CkSpre5) || \ + ((FREQ) == RTC_WeakUp_RTCCLK_CkSpre6) || ((FREQ) == RTC_WeakUp_RTCCLK_CkSpre7)) + +/** @defgroup RTC_Auto_Weakup_Count_Value + * @{ + */ +#define IS_RTC_WKUP_COUNTER(COUNTER) ((COUNTER) <= 0x0000FFFF) +/** + * @} + */ + +#define RTC_BackUp0Reg ((uint32_t)0x00000000)/*choose rtc_bkp0 register*/ +#define RTC_BackUp1Reg ((uint32_t)0x00000001)/*choose rtc_bkp1 register*/ +#define RTC_BackUp2Reg ((uint32_t)0x00000002)/*choose rtc_bkp2 register*/ +#define RTC_BackUp3Reg ((uint32_t)0x00000003)/*choose rtc_bkp3 register*/ +#define RTC_BackUp4Reg ((uint32_t)0x00000004)/*choose rtc_bkp4 register*/ +#define RTC_BackUp5Reg ((uint32_t)0x00000005)/*choose rtc_bkp5 register*/ +#define RTC_BackUp6Reg ((uint32_t)0x00000006)/*choose rtc_bkp6 register*/ +#define RTC_BackUp7Reg ((uint32_t)0x00000007)/*choose rtc_bkp7 register*/ +#define RTC_BackUp8Reg ((uint32_t)0x00000008)/*choose rtc_bkp8 register*/ +#define RTC_BackUp9Reg ((uint32_t)0x00000009)/*choose rtc_bkp9 register*/ +#define RTC_BackUp10Reg ((uint32_t)0x0000000A)/*choose rtc_bkp10 register*/ +#define RTC_BackUp11Reg ((uint32_t)0x0000000B)/*choose rtc_bkp11 register*/ +#define RTC_BackUp12Reg ((uint32_t)0x0000000C)/*choose rtc_bkp12 register*/ +#define RTC_BackUp13Reg ((uint32_t)0x0000000D)/*choose rtc_bkp13 register*/ +#define RTC_BackUp14Reg ((uint32_t)0x0000000E)/*choose rtc_bkp14 register*/ +#define RTC_BackUp15Reg ((uint32_t)0x0000000F)/*choose rtc_bkp15 register*/ +#define RTC_BackUp16Reg ((uint32_t)0x00000010)/*choose rtc_bkp16 register*/ +#define RTC_BackUp17Reg ((uint32_t)0x00000011)/*choose rtc_bkp17 register*/ +#define RTC_BackUp18Reg ((uint32_t)0x00000012)/*choose rtc_bkp18 register*/ +#define RTC_BackUp19Reg ((uint32_t)0x00000013)/*choose rtc_bkp19 register*/ + +#define IS_RTC_BACKUP_REG(REG) (((REG) == RTC_BackUp0Reg) || ((REG) == RTC_BackUp1Reg) || \ + ((REG) == RTC_BackUp2Reg) || ((REG) == RTC_BackUp3Reg) || \ + ((REG) == RTC_BackUp4Reg) || ((REG) == RTC_BackUp5Reg) || \ + ((REG) == RTC_BackUp6Reg) || ((REG) == RTC_BackUp7Reg) || \ + ((REG) == RTC_BackUp8Reg) || ((REG) == RTC_BackUp9Reg) || \ + ((REG) == RTC_BackUp10Reg) || ((REG) == RTC_BackUp11Reg) || \ + ((REG) == RTC_BackUp12Reg) || ((REG) == RTC_BackUp13Reg) || \ + ((REG) == RTC_BackUp14Reg) || ((REG) == RTC_BackUp15Reg) || \ + ((REG) == RTC_BackUp16Reg) || ((REG) == RTC_BackUp17Reg) || \ + ((REG) == RTC_BackUp18Reg) || ((REG) == RTC_BackUp19Reg)) + +/** @defgroup RTC_Backup_Data_Value + * @{ + */ +#define IS_RTC_BACKUP_DATA(DATA) ((DATA) <= 0xFFFFFFFF) +/** + * @} + */ + + + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the RTC configuration to the default reset state *****/ +ErrorStatus RTC_DeInit(void);/* reset the rtc register */ + +/* Initialization and Configuration functions *********************************/ +void RTC_SetInit(RTC_InitTypeDef* RTC_InitStruct);/* config rtc's hour format,async and sync value struct */ +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);/* config rtc's hour format,async sync's specific value */ +void RTC_WriteProtectionCmd(FunctionalState NewState);/* Function used open rtc write protect */ +ErrorStatus RTC_EnterInitMode(void);/* Funtion used check enter initial mode if has error */ +void RTC_ExitInitMode(void);/* Function used exit initial mode */ +ErrorStatus RTC_WaitForSynchro(void);/* Function used wait calendar register be synchronized */ +void RTC_RefClockCmd(FunctionalState NewState);/* Function used enable reference clock detection */ +void RTC_BypassShadowCmd(FunctionalState NewState);/* Function used enable bypass */ + +/* Time and Date configuration functions **************************************/ +void RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);/* Function used set rtc time register */ +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);/* Function used set rtc time struct */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);/* get the rtc time from the rtc_tr register */ +uint32_t RTC_GetSubSecond(void);/* Function used get the rtc sub-seconds */ +void RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);/* Function used set rtc date register*/ +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);/* Function used set rtc date struct */ +uint32_t RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);/* get the rtc date from the rtc_dr register */ + +/* Alarms (Alarm A and Alarm B) configuration functions **********************************/ +/* Function used config alarma/amarmb */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);/*Function used set rtc alarm struct */ +/* Function used get alarma/amarmb */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct); +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);/* Function used alarm enable or disable */ +/* Function used config alarma/alarmb's subsecond */ +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask); +/* Function used get alarma/alarmb's subsecond */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm); + +/* Daylight Saving configuration functions ************************************/ +/* Function used config DayLightSaving ADD1H/SUB1H and Storeoperation set/clear BKP*/ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation); +uint32_t RTC_GetStoreOperation(void);/* Function used get StoreOperation RTC_CR[BKP]==0/1 */ + +/* Output pin Configuration function ******************************************/ +/* Function used config RTC_ALARM output select alraf/alrbf/wutf and polarity high/low*/ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity); + +/* Smooth Calibration configuration functions ********************************/ +void RTC_CalibOutputCmd(FunctionalState NewState);/* Function used config RTC_CALIB output enable */ +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);/* Function used config RTC_CALIB output 512Hz/1Hz */ +/* Function used config SmoothCalib CALP/CALW8/CALW16/CALM[8:0] */ +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmouthCalibMinusPulsesValue); + +/* Rough Digtial Calibration configuration functions ********************************/ +/* Function used config DigtialRoughCalib DCS/DC[4:0] */ +void RTC_RoughCalibration(FunctionalState NewState);/* Function used rough calibration enable or disable */ +void RTC_RoughDigtialCalibConfig(uint32_t RTC_RoughCalibPolarity, + uint32_t RTC_RoughCalibMinusPulsesValue); + +/* TimeStamp configuration functions ******************************************/ +/* Function used Enable RTC_TimeStamp and config occur edge */ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState); +/* Function used get RTC_TimeStamp TS and TD Register's value */ +void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct); +/* Function used get RTC_TimeStamp SubSecond Register's value */ +uint32_t RTC_GetTimeStampSubSecond(void); + +/* Tampers configuration functions ********************************************/ +/* Function used config tamp1trg and tamp2trg is edge or level */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger); +/* Function used enable tamp1 and tamp2 */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState); +/* Function used config tamp1 and tamp2's filter */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter); +/* Function used config tamp1 and tamp2's sampling frequence */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq); +/* Function used config tamp1 and tamp2's precharge time */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration); +/* Function used config tamp1 and tamp2 event as timestamp */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState); +/* Function used config tamp1 and tamp2 pull_up forbidden */ +void RTC_TamperPullUpCmd(FunctionalState NewState); + +/* Output Type Config configuration functions *********************************/ +/* Function used config RTC_ALARM(PC13) output type*/ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType); +/* Function used config RTC_ALARM(PC13) mode*/ +void RTC_OutputModeConfig(uint32_t RTC_OutputMode); +/* Function used config pc15 output type and data */ +void RTC_Pc15_OutputTypeDataConfig(uint32_t RTC_Pc15_OutputType, uint32_t RTC_Pc15_OutputData); +/* Function used config pc14 output type and data */ +void RTC_Pc14_OutputTypeDataConfig(uint32_t RTC_Pc14_OutputType, uint32_t RTC_Pc14_OutputData); + +/* RTC_Shift_control_synchonisation_functions *********************************/ +/* Function used config shif control register add1s or substract a number of second */ +/* Return config status error or success */ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS); + +/* Interrupts and flags management functions **********************************/ +/* Function used Enable rtc_ts/wut/alra/alrb/tamp interrupt */ +void RTC_ITConfig(uint32_t RTC_IT_ENABLE, FunctionalState NewState); +/* Function used get rtc_tsf/wutf/alraf/alrbf/tamp1f/tamp2f */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG); +/* Function used clear rtc_flag */ +void RTC_ClearFlag(uint32_t RTC_FLAG); +/* Function used get interrupt status */ +ITStatus RTC_GetITStatus(uint32_t RTC_IT_ENABLE); +/* Function used clear interrupt flag */ +void RTC_ClearITPendingBit(uint32_t RTC_IT_FLAG); + +/* Auto Weakup Config configuration functions **********************************/ +/* Function used Enable Auto WeakUp */ +void RTC_WeakUpCmd(FunctionalState NewState); +/* Function used set RTC Auto WeakUp Counter Register's value */ +void RTC_SetWeakUpCounter(uint32_t RTC_WeakUp_Counter); +/* Function used get RTC Auto WeakUp Counter Register's value */ +uint32_t RTC_GetWeakUpCounter(void); +/* Function used config Auto WeakUp Count frequence */ +void RTC_WeakUpCountFreqConfig(uint32_t RTC_WeakUpCountFreq); + +/* Backup Data Config configuration functions **********************************/ +/* Function used config backup register */ +void RTC_BackUpRegConfig(uint32_t RTC_BackUpReg, uint32_t RTC_BackUpRegData); +/* Function used get RTC_BackUp Register's value */ +uint32_t RTC_GetBackUpReg(uint32_t RTC_BackUpReg); + + + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_RTC_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_sdio.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_sdio.h new file mode 100644 index 00000000000..3ff67c69b77 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_sdio.h @@ -0,0 +1,1155 @@ +/** + ****************************************************************************** + * @file ft32f4xx_sdio.h + ****************************************************************************** +**/ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_SDIO_H +#define __FT32F4XX_SDIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*!< Includes ----------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SDIO_CTRL_Register **/ +/** @defgroup SDIO_OD_PULLUP + * @{ + */ +#define SDIO_OD_PULLUP_DISABLE ((uint32_t)0x00) +#define SDIO_OD_PULLUP_ENABLE SDIO_CTRL_ENABLE_OD_PULLUP + +#define IS_SDIO_OD_PULLUP(PULLUP) (((PULLUP) == SDIO_OD_PULLUP_DISABLE) || \ + ((PULLUP) == SDIO_OD_PULLUP_ENABLE)) + +/** @defgroup SDIO_Read_Wait + * @{ + */ +#define SDIO_READ_WAIT_DISABLE ((uint32_t)0x00) +#define SDIO_READ_WAIT_ENABLE SDIO_CTRL_READ_WAIT + +#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_DISABLE) || \ + ((MODE) == SDIO_READ_WAIT_ENABLE)) + +/** @defgroup SDIO_dma_enable + * @{ + */ +#define SDIO_DMA_ENABLE_DISABLE ((uint32_t)0x00) +#define SDIO_DMA_ENABLE_ENABLE SDIO_CTRL_DMA_ENABLE + +#define IS_SDIO_DMA_ENABLE(ENABLE) (((ENABLE) == SDIO_DMA_ENABLE_DISABLE) || \ + ((ENABLE) == SDIO_DMA_ENABLE_ENABLE)) + +/** @defgroup SDIO_INT_ENABLE + * @{ + */ +#define SDIO_INT_ENABLE_DISABLE ((uint32_t)0x00) +#define SDIO_INT_ENABLE_ENABLE SDIO_CTRL_INT_ENABLE + +#define IS_SDIO_INT_ENABLE(ENABLE) (((ENABLE) == SDIO_INT_ENABLE_DISABLE) || \ + ((ENABLE) == SDIO_INT_ENABLE_ENABLE)) + +/** @defgroup SDIO_FIFO_RESET + * @{ + */ +#define SDIO_FIFO_RESET_DISABLE ((uint32_t)0x00) +#define SDIO_FIFO_RESET_ENABLE SDIO_CTRL_FIFO_RESET + +#define IS_SDIO_FIFO_RESET(RESET) (((RESET) == SDIO_FIFO_RESET_DISABLE) || \ + ((RESET) == SDIO_FIFO_RESET_ENABLE)) + + +/** @defgroup SDIO_CONTROLLER_RESET + * @{ + */ +#define SDIO_CONTROLLER_RESET_DISABLE ((uint32_t)0x00) +#define SDIO_CONTROLLER_RESET_ENABLE SDIO_CTRL_CONTROLLER_RESET + +#define IS_SDIO_CONTROLLER_RESET(RESET) (((RESET) == SDIO_CONTROLLER_RESET_DISABLE) || \ + ((RESET) == SDIO_CONTROLLER_RESET_ENABLE)) + +/** @defgroup SDIO_PWREN_Register **/ +/** @defgroup SDIO_Power_ON + * @{ + */ +#define SDIO_POWER_ON_DISABLE ((uint32_t)0x00) +#define SDIO_POWER_ON_ENABLE SDIO_PWREN_POWER_ENABLE_0 + +#define IS_SDIO_POWER_ON(ON) (((ON) == SDIO_POWER_ON_DISABLE) || \ + ((ON) == SDIO_POWER_ON_ENABLE)) + +/** @defgroup SDIO_CLKDIV_Register **/ +/** @defgroup SDIO_Clock_Division + * @{ + */ +#define SDIO_CLKDIV1 ((uint32_t)0x00) +#define SDIO_CLKDIV2 ((uint32_t)0x01) +#define SDIO_CLKDIV4 ((uint32_t)0x02) +#define SDIO_CLKDIV6 ((uint32_t)0x03) +#define SDIO_CLKDIV8 ((uint32_t)0x04) +#define SDIO_CLKDIV10 ((uint32_t)0x05) +#define SDIO_CLKDIV12 ((uint32_t)0x06) +#define SDIO_CLKDIV14 ((uint32_t)0x07) +#define SDIO_CLKDIV16 ((uint32_t)0x08) +#define SDIO_CLKDIV18 ((uint32_t)0x09) +#define SDIO_CLKDIV20 ((uint32_t)0x0a) +#define SDIO_CLKDIV22 ((uint32_t)0x0b) +#define SDIO_CLKDIV24 ((uint32_t)0x0c) +#define SDIO_CLKDIV26 ((uint32_t)0x0d) +#define SDIO_CLKDIV28 ((uint32_t)0x0e) +#define SDIO_CLKDIV30 ((uint32_t)0x0f) +#define SDIO_CLKDIV32 ((uint32_t)0x10) +#define SDIO_CLKDIV34 ((uint32_t)0x11) +#define SDIO_CLKDIV36 ((uint32_t)0x12) +#define SDIO_CLKDIV38 ((uint32_t)0x13) +#define SDIO_CLKDIV40 ((uint32_t)0x14) +#define SDIO_CLKDIV42 ((uint32_t)0x15) +#define SDIO_CLKDIV44 ((uint32_t)0x16) +#define SDIO_CLKDIV46 ((uint32_t)0x17) +#define SDIO_CLKDIV48 ((uint32_t)0x18) +#define SDIO_CLKDIV50 ((uint32_t)0x19) +#define SDIO_CLKDIV52 ((uint32_t)0x1a) +#define SDIO_CLKDIV54 ((uint32_t)0x1b) +#define SDIO_CLKDIV56 ((uint32_t)0x1c) +#define SDIO_CLKDIV58 ((uint32_t)0x1d) +#define SDIO_CLKDIV60 ((uint32_t)0x1e) +#define SDIO_CLKDIV62 ((uint32_t)0x1f) +#define SDIO_CLKDIV64 ((uint32_t)0x20) +#define SDIO_CLKDIV66 ((uint32_t)0x21) +#define SDIO_CLKDIV68 ((uint32_t)0x22) +#define SDIO_CLKDIV70 ((uint32_t)0x23) +#define SDIO_CLKDIV72 ((uint32_t)0x24) +#define SDIO_CLKDIV74 ((uint32_t)0x25) +#define SDIO_CLKDIV76 ((uint32_t)0x26) +#define SDIO_CLKDIV78 ((uint32_t)0x27) +#define SDIO_CLKDIV80 ((uint32_t)0x28) +#define SDIO_CLKDIV82 ((uint32_t)0x29) +#define SDIO_CLKDIV84 ((uint32_t)0x2a) +#define SDIO_CLKDIV86 ((uint32_t)0x2b) +#define SDIO_CLKDIV88 ((uint32_t)0x2c) +#define SDIO_CLKDIV90 ((uint32_t)0x2d) +#define SDIO_CLKDIV92 ((uint32_t)0x2e) +#define SDIO_CLKDIV94 ((uint32_t)0x2f) +#define SDIO_CLKDIV96 ((uint32_t)0x30) +#define SDIO_CLKDIV98 ((uint32_t)0x31) +#define SDIO_CLKDIV100 ((uint32_t)0x32) +#define SDIO_CLKDIV102 ((uint32_t)0x33) +#define SDIO_CLKDIV104 ((uint32_t)0x34) +#define SDIO_CLKDIV106 ((uint32_t)0x35) +#define SDIO_CLKDIV108 ((uint32_t)0x36) +#define SDIO_CLKDIV110 ((uint32_t)0x37) +#define SDIO_CLKDIV112 ((uint32_t)0x38) +#define SDIO_CLKDIV114 ((uint32_t)0x39) +#define SDIO_CLKDIV116 ((uint32_t)0x3a) +#define SDIO_CLKDIV118 ((uint32_t)0x3b) +#define SDIO_CLKDIV120 ((uint32_t)0x3c) +#define SDIO_CLKDIV122 ((uint32_t)0x3d) +#define SDIO_CLKDIV124 ((uint32_t)0x3e) +#define SDIO_CLKDIV126 ((uint32_t)0x3f) +#define SDIO_CLKDIV128 ((uint32_t)0x40) +#define SDIO_CLKDIV130 ((uint32_t)0x41) +#define SDIO_CLKDIV132 ((uint32_t)0x42) +#define SDIO_CLKDIV134 ((uint32_t)0x43) +#define SDIO_CLKDIV136 ((uint32_t)0x44) +#define SDIO_CLKDIV138 ((uint32_t)0x45) +#define SDIO_CLKDIV140 ((uint32_t)0x46) +#define SDIO_CLKDIV142 ((uint32_t)0x47) +#define SDIO_CLKDIV144 ((uint32_t)0x48) +#define SDIO_CLKDIV146 ((uint32_t)0x49) +#define SDIO_CLKDIV148 ((uint32_t)0x4a) +#define SDIO_CLKDIV150 ((uint32_t)0x4b) +#define SDIO_CLKDIV152 ((uint32_t)0x4c) +#define SDIO_CLKDIV154 ((uint32_t)0x4d) +#define SDIO_CLKDIV156 ((uint32_t)0x4e) +#define SDIO_CLKDIV158 ((uint32_t)0x4f) +#define SDIO_CLKDIV160 ((uint32_t)0x50) +#define SDIO_CLKDIV162 ((uint32_t)0x51) +#define SDIO_CLKDIV164 ((uint32_t)0x52) +#define SDIO_CLKDIV166 ((uint32_t)0x53) +#define SDIO_CLKDIV168 ((uint32_t)0x54) +#define SDIO_CLKDIV170 ((uint32_t)0x55) +#define SDIO_CLKDIV172 ((uint32_t)0x56) +#define SDIO_CLKDIV174 ((uint32_t)0x57) +#define SDIO_CLKDIV176 ((uint32_t)0x58) +#define SDIO_CLKDIV178 ((uint32_t)0x59) +#define SDIO_CLKDIV180 ((uint32_t)0x5a) +#define SDIO_CLKDIV182 ((uint32_t)0x5b) +#define SDIO_CLKDIV184 ((uint32_t)0x5c) +#define SDIO_CLKDIV186 ((uint32_t)0x5d) +#define SDIO_CLKDIV188 ((uint32_t)0x5e) +#define SDIO_CLKDIV190 ((uint32_t)0x5f) +#define SDIO_CLKDIV192 ((uint32_t)0x60) +#define SDIO_CLKDIV194 ((uint32_t)0x61) +#define SDIO_CLKDIV196 ((uint32_t)0x62) +#define SDIO_CLKDIV198 ((uint32_t)0x63) +#define SDIO_CLKDIV200 ((uint32_t)0x64) +#define SDIO_CLKDIV202 ((uint32_t)0x65) +#define SDIO_CLKDIV204 ((uint32_t)0x66) +#define SDIO_CLKDIV206 ((uint32_t)0x67) +#define SDIO_CLKDIV208 ((uint32_t)0x68) +#define SDIO_CLKDIV210 ((uint32_t)0x69) +#define SDIO_CLKDIV212 ((uint32_t)0x6a) +#define SDIO_CLKDIV214 ((uint32_t)0x6b) +#define SDIO_CLKDIV216 ((uint32_t)0x6c) +#define SDIO_CLKDIV218 ((uint32_t)0x6d) +#define SDIO_CLKDIV220 ((uint32_t)0x6e) +#define SDIO_CLKDIV222 ((uint32_t)0x6f) +#define SDIO_CLKDIV224 ((uint32_t)0x70) +#define SDIO_CLKDIV226 ((uint32_t)0x71) +#define SDIO_CLKDIV228 ((uint32_t)0x72) +#define SDIO_CLKDIV230 ((uint32_t)0x73) +#define SDIO_CLKDIV232 ((uint32_t)0x74) +#define SDIO_CLKDIV234 ((uint32_t)0x75) +#define SDIO_CLKDIV236 ((uint32_t)0x76) +#define SDIO_CLKDIV238 ((uint32_t)0x77) +#define SDIO_CLKDIV240 ((uint32_t)0x78) +#define SDIO_CLKDIV242 ((uint32_t)0x79) +#define SDIO_CLKDIV244 ((uint32_t)0x7a) +#define SDIO_CLKDIV246 ((uint32_t)0x7b) +#define SDIO_CLKDIV248 ((uint32_t)0x7c) +#define SDIO_CLKDIV250 ((uint32_t)0x7d) +#define SDIO_CLKDIV252 ((uint32_t)0x7e) +#define SDIO_CLKDIV254 ((uint32_t)0x7f) +#define SDIO_CLKDIV256 ((uint32_t)0x80) +#define SDIO_CLKDIV258 ((uint32_t)0x81) +#define SDIO_CLKDIV260 ((uint32_t)0x82) +#define SDIO_CLKDIV262 ((uint32_t)0x83) +#define SDIO_CLKDIV264 ((uint32_t)0x84) +#define SDIO_CLKDIV266 ((uint32_t)0x85) +#define SDIO_CLKDIV268 ((uint32_t)0x86) +#define SDIO_CLKDIV270 ((uint32_t)0x87) +#define SDIO_CLKDIV272 ((uint32_t)0x88) +#define SDIO_CLKDIV274 ((uint32_t)0x89) +#define SDIO_CLKDIV276 ((uint32_t)0x8a) +#define SDIO_CLKDIV278 ((uint32_t)0x8b) +#define SDIO_CLKDIV280 ((uint32_t)0x8c) +#define SDIO_CLKDIV282 ((uint32_t)0x8d) +#define SDIO_CLKDIV284 ((uint32_t)0x8e) +#define SDIO_CLKDIV286 ((uint32_t)0x8f) +#define SDIO_CLKDIV288 ((uint32_t)0x90) +#define SDIO_CLKDIV290 ((uint32_t)0x91) +#define SDIO_CLKDIV292 ((uint32_t)0x92) +#define SDIO_CLKDIV294 ((uint32_t)0x93) +#define SDIO_CLKDIV296 ((uint32_t)0x94) +#define SDIO_CLKDIV298 ((uint32_t)0x95) +#define SDIO_CLKDIV300 ((uint32_t)0x96) +#define SDIO_CLKDIV302 ((uint32_t)0x97) +#define SDIO_CLKDIV304 ((uint32_t)0x98) +#define SDIO_CLKDIV306 ((uint32_t)0x99) +#define SDIO_CLKDIV308 ((uint32_t)0x9a) +#define SDIO_CLKDIV310 ((uint32_t)0x9b) +#define SDIO_CLKDIV312 ((uint32_t)0x9c) +#define SDIO_CLKDIV314 ((uint32_t)0x9d) +#define SDIO_CLKDIV316 ((uint32_t)0x9e) +#define SDIO_CLKDIV318 ((uint32_t)0x9f) +#define SDIO_CLKDIV320 ((uint32_t)0xa0) +#define SDIO_CLKDIV322 ((uint32_t)0xa1) +#define SDIO_CLKDIV324 ((uint32_t)0xa2) +#define SDIO_CLKDIV326 ((uint32_t)0xa3) +#define SDIO_CLKDIV328 ((uint32_t)0xa4) +#define SDIO_CLKDIV330 ((uint32_t)0xa5) +#define SDIO_CLKDIV332 ((uint32_t)0xa6) +#define SDIO_CLKDIV334 ((uint32_t)0xa7) +#define SDIO_CLKDIV336 ((uint32_t)0xa8) +#define SDIO_CLKDIV338 ((uint32_t)0xa9) +#define SDIO_CLKDIV340 ((uint32_t)0xaa) +#define SDIO_CLKDIV342 ((uint32_t)0xab) +#define SDIO_CLKDIV344 ((uint32_t)0xac) +#define SDIO_CLKDIV346 ((uint32_t)0xad) +#define SDIO_CLKDIV348 ((uint32_t)0xae) +#define SDIO_CLKDIV350 ((uint32_t)0xaf) +#define SDIO_CLKDIV352 ((uint32_t)0xb0) +#define SDIO_CLKDIV354 ((uint32_t)0xb1) +#define SDIO_CLKDIV356 ((uint32_t)0xb2) +#define SDIO_CLKDIV358 ((uint32_t)0xb3) +#define SDIO_CLKDIV360 ((uint32_t)0xb4) +#define SDIO_CLKDIV362 ((uint32_t)0xb5) +#define SDIO_CLKDIV364 ((uint32_t)0xb6) +#define SDIO_CLKDIV366 ((uint32_t)0xb7) +#define SDIO_CLKDIV368 ((uint32_t)0xb8) +#define SDIO_CLKDIV370 ((uint32_t)0xb9) +#define SDIO_CLKDIV372 ((uint32_t)0xba) +#define SDIO_CLKDIV374 ((uint32_t)0xbb) +#define SDIO_CLKDIV376 ((uint32_t)0xbc) +#define SDIO_CLKDIV378 ((uint32_t)0xbd) +#define SDIO_CLKDIV380 ((uint32_t)0xbe) +#define SDIO_CLKDIV382 ((uint32_t)0xbf) +#define SDIO_CLKDIV384 ((uint32_t)0xc0) +#define SDIO_CLKDIV386 ((uint32_t)0xc1) +#define SDIO_CLKDIV388 ((uint32_t)0xc2) +#define SDIO_CLKDIV390 ((uint32_t)0xc3) +#define SDIO_CLKDIV392 ((uint32_t)0xc4) +#define SDIO_CLKDIV394 ((uint32_t)0xc5) +#define SDIO_CLKDIV396 ((uint32_t)0xc6) +#define SDIO_CLKDIV398 ((uint32_t)0xc7) +#define SDIO_CLKDIV400 ((uint32_t)0xc8) +#define SDIO_CLKDIV402 ((uint32_t)0xc9) +#define SDIO_CLKDIV404 ((uint32_t)0xca) +#define SDIO_CLKDIV406 ((uint32_t)0xcb) +#define SDIO_CLKDIV408 ((uint32_t)0xcc) +#define SDIO_CLKDIV410 ((uint32_t)0xcd) +#define SDIO_CLKDIV412 ((uint32_t)0xce) +#define SDIO_CLKDIV414 ((uint32_t)0xcf) +#define SDIO_CLKDIV416 ((uint32_t)0xd0) +#define SDIO_CLKDIV418 ((uint32_t)0xd1) +#define SDIO_CLKDIV420 ((uint32_t)0xd2) +#define SDIO_CLKDIV422 ((uint32_t)0xd3) +#define SDIO_CLKDIV424 ((uint32_t)0xd4) +#define SDIO_CLKDIV426 ((uint32_t)0xd5) +#define SDIO_CLKDIV428 ((uint32_t)0xd6) +#define SDIO_CLKDIV430 ((uint32_t)0xd7) +#define SDIO_CLKDIV432 ((uint32_t)0xd8) +#define SDIO_CLKDIV434 ((uint32_t)0xd9) +#define SDIO_CLKDIV436 ((uint32_t)0xda) +#define SDIO_CLKDIV438 ((uint32_t)0xdb) +#define SDIO_CLKDIV440 ((uint32_t)0xdc) +#define SDIO_CLKDIV442 ((uint32_t)0xdd) +#define SDIO_CLKDIV444 ((uint32_t)0xde) +#define SDIO_CLKDIV446 ((uint32_t)0xdf) +#define SDIO_CLKDIV448 ((uint32_t)0xe0) +#define SDIO_CLKDIV450 ((uint32_t)0xe1) +#define SDIO_CLKDIV452 ((uint32_t)0xe2) +#define SDIO_CLKDIV454 ((uint32_t)0xe3) +#define SDIO_CLKDIV456 ((uint32_t)0xe4) +#define SDIO_CLKDIV458 ((uint32_t)0xe5) +#define SDIO_CLKDIV460 ((uint32_t)0xe6) +#define SDIO_CLKDIV462 ((uint32_t)0xe7) +#define SDIO_CLKDIV464 ((uint32_t)0xe8) +#define SDIO_CLKDIV466 ((uint32_t)0xe9) +#define SDIO_CLKDIV468 ((uint32_t)0xea) +#define SDIO_CLKDIV470 ((uint32_t)0xeb) +#define SDIO_CLKDIV472 ((uint32_t)0xec) +#define SDIO_CLKDIV474 ((uint32_t)0xed) +#define SDIO_CLKDIV476 ((uint32_t)0xee) +#define SDIO_CLKDIV478 ((uint32_t)0xef) +#define SDIO_CLKDIV480 ((uint32_t)0xf0) +#define SDIO_CLKDIV482 ((uint32_t)0xf1) +#define SDIO_CLKDIV484 ((uint32_t)0xf2) +#define SDIO_CLKDIV486 ((uint32_t)0xf3) +#define SDIO_CLKDIV488 ((uint32_t)0xf4) +#define SDIO_CLKDIV490 ((uint32_t)0xf5) +#define SDIO_CLKDIV492 ((uint32_t)0xf6) +#define SDIO_CLKDIV494 ((uint32_t)0xf7) +#define SDIO_CLKDIV496 ((uint32_t)0xf8) +#define SDIO_CLKDIV498 ((uint32_t)0xf9) +#define SDIO_CLKDIV500 ((uint32_t)0xfa) +#define SDIO_CLKDIV502 ((uint32_t)0xfb) +#define SDIO_CLKDIV504 ((uint32_t)0xfc) +#define SDIO_CLKDIV506 ((uint32_t)0xfd) +#define SDIO_CLKDIV508 ((uint32_t)0xfe) +#define SDIO_CLKDIV510 ((uint32_t)0xff) + +#define IS_SDIO_CLKDIV(CLKDIV) (((CLKDIV) == SDIO_CLKDIV1 ) || \ + ((CLKDIV) == SDIO_CLKDIV2 ) || \ + ((CLKDIV) == SDIO_CLKDIV4 ) || \ + ((CLKDIV) == SDIO_CLKDIV6 ) || \ + ((CLKDIV) == SDIO_CLKDIV8 ) || \ + ((CLKDIV) == SDIO_CLKDIV10 ) || \ + ((CLKDIV) == SDIO_CLKDIV12 ) || \ + ((CLKDIV) == SDIO_CLKDIV14 ) || \ + ((CLKDIV) == SDIO_CLKDIV16 ) || \ + ((CLKDIV) == SDIO_CLKDIV18 ) || \ + ((CLKDIV) == SDIO_CLKDIV20 ) || \ + ((CLKDIV) == SDIO_CLKDIV22 ) || \ + ((CLKDIV) == SDIO_CLKDIV24 ) || \ + ((CLKDIV) == SDIO_CLKDIV26 ) || \ + ((CLKDIV) == SDIO_CLKDIV28 ) || \ + ((CLKDIV) == SDIO_CLKDIV30 ) || \ + ((CLKDIV) == SDIO_CLKDIV32 ) || \ + ((CLKDIV) == SDIO_CLKDIV34 ) || \ + ((CLKDIV) == SDIO_CLKDIV36 ) || \ + ((CLKDIV) == SDIO_CLKDIV38 ) || \ + ((CLKDIV) == SDIO_CLKDIV40 ) || \ + ((CLKDIV) == SDIO_CLKDIV42 ) || \ + ((CLKDIV) == SDIO_CLKDIV44 ) || \ + ((CLKDIV) == SDIO_CLKDIV46 ) || \ + ((CLKDIV) == SDIO_CLKDIV48 ) || \ + ((CLKDIV) == SDIO_CLKDIV50 ) || \ + ((CLKDIV) == SDIO_CLKDIV52 ) || \ + ((CLKDIV) == SDIO_CLKDIV54 ) || \ + ((CLKDIV) == SDIO_CLKDIV56 ) || \ + ((CLKDIV) == SDIO_CLKDIV58 ) || \ + ((CLKDIV) == SDIO_CLKDIV60 ) || \ + ((CLKDIV) == SDIO_CLKDIV62 ) || \ + ((CLKDIV) == SDIO_CLKDIV64 ) || \ + ((CLKDIV) == SDIO_CLKDIV66 ) || \ + ((CLKDIV) == SDIO_CLKDIV68 ) || \ + ((CLKDIV) == SDIO_CLKDIV70 ) || \ + ((CLKDIV) == SDIO_CLKDIV72 ) || \ + ((CLKDIV) == SDIO_CLKDIV74 ) || \ + ((CLKDIV) == SDIO_CLKDIV76 ) || \ + ((CLKDIV) == SDIO_CLKDIV78 ) || \ + ((CLKDIV) == SDIO_CLKDIV80 ) || \ + ((CLKDIV) == SDIO_CLKDIV82 ) || \ + ((CLKDIV) == SDIO_CLKDIV84 ) || \ + ((CLKDIV) == SDIO_CLKDIV86 ) || \ + ((CLKDIV) == SDIO_CLKDIV88 ) || \ + ((CLKDIV) == SDIO_CLKDIV90 ) || \ + ((CLKDIV) == SDIO_CLKDIV92 ) || \ + ((CLKDIV) == SDIO_CLKDIV94 ) || \ + ((CLKDIV) == SDIO_CLKDIV96 ) || \ + ((CLKDIV) == SDIO_CLKDIV98 ) || \ + ((CLKDIV) == SDIO_CLKDIV100) || \ + ((CLKDIV) == SDIO_CLKDIV102) || \ + ((CLKDIV) == SDIO_CLKDIV104) || \ + ((CLKDIV) == SDIO_CLKDIV106) || \ + ((CLKDIV) == SDIO_CLKDIV108) || \ + ((CLKDIV) == SDIO_CLKDIV110) || \ + ((CLKDIV) == SDIO_CLKDIV112) || \ + ((CLKDIV) == SDIO_CLKDIV114) || \ + ((CLKDIV) == SDIO_CLKDIV116) || \ + ((CLKDIV) == SDIO_CLKDIV118) || \ + ((CLKDIV) == SDIO_CLKDIV120) || \ + ((CLKDIV) == SDIO_CLKDIV122) || \ + ((CLKDIV) == SDIO_CLKDIV124) || \ + ((CLKDIV) == SDIO_CLKDIV126) || \ + ((CLKDIV) == SDIO_CLKDIV128) || \ + ((CLKDIV) == SDIO_CLKDIV130) || \ + ((CLKDIV) == SDIO_CLKDIV132) || \ + ((CLKDIV) == SDIO_CLKDIV134) || \ + ((CLKDIV) == SDIO_CLKDIV136) || \ + ((CLKDIV) == SDIO_CLKDIV138) || \ + ((CLKDIV) == SDIO_CLKDIV140) || \ + ((CLKDIV) == SDIO_CLKDIV142) || \ + ((CLKDIV) == SDIO_CLKDIV144) || \ + ((CLKDIV) == SDIO_CLKDIV146) || \ + ((CLKDIV) == SDIO_CLKDIV148) || \ + ((CLKDIV) == SDIO_CLKDIV150) || \ + ((CLKDIV) == SDIO_CLKDIV152) || \ + ((CLKDIV) == SDIO_CLKDIV154) || \ + ((CLKDIV) == SDIO_CLKDIV156) || \ + ((CLKDIV) == SDIO_CLKDIV158) || \ + ((CLKDIV) == SDIO_CLKDIV160) || \ + ((CLKDIV) == SDIO_CLKDIV162) || \ + ((CLKDIV) == SDIO_CLKDIV164) || \ + ((CLKDIV) == SDIO_CLKDIV166) || \ + ((CLKDIV) == SDIO_CLKDIV168) || \ + ((CLKDIV) == SDIO_CLKDIV170) || \ + ((CLKDIV) == SDIO_CLKDIV172) || \ + ((CLKDIV) == SDIO_CLKDIV174) || \ + ((CLKDIV) == SDIO_CLKDIV176) || \ + ((CLKDIV) == SDIO_CLKDIV178) || \ + ((CLKDIV) == SDIO_CLKDIV180) || \ + ((CLKDIV) == SDIO_CLKDIV182) || \ + ((CLKDIV) == SDIO_CLKDIV184) || \ + ((CLKDIV) == SDIO_CLKDIV186) || \ + ((CLKDIV) == SDIO_CLKDIV188) || \ + ((CLKDIV) == SDIO_CLKDIV190) || \ + ((CLKDIV) == SDIO_CLKDIV192) || \ + ((CLKDIV) == SDIO_CLKDIV194) || \ + ((CLKDIV) == SDIO_CLKDIV196) || \ + ((CLKDIV) == SDIO_CLKDIV198) || \ + ((CLKDIV) == SDIO_CLKDIV200) || \ + ((CLKDIV) == SDIO_CLKDIV202) || \ + ((CLKDIV) == SDIO_CLKDIV204) || \ + ((CLKDIV) == SDIO_CLKDIV206) || \ + ((CLKDIV) == SDIO_CLKDIV208) || \ + ((CLKDIV) == SDIO_CLKDIV210) || \ + ((CLKDIV) == SDIO_CLKDIV212) || \ + ((CLKDIV) == SDIO_CLKDIV214) || \ + ((CLKDIV) == SDIO_CLKDIV216) || \ + ((CLKDIV) == SDIO_CLKDIV218) || \ + ((CLKDIV) == SDIO_CLKDIV220) || \ + ((CLKDIV) == SDIO_CLKDIV222) || \ + ((CLKDIV) == SDIO_CLKDIV224) || \ + ((CLKDIV) == SDIO_CLKDIV226) || \ + ((CLKDIV) == SDIO_CLKDIV228) || \ + ((CLKDIV) == SDIO_CLKDIV230) || \ + ((CLKDIV) == SDIO_CLKDIV232) || \ + ((CLKDIV) == SDIO_CLKDIV234) || \ + ((CLKDIV) == SDIO_CLKDIV236) || \ + ((CLKDIV) == SDIO_CLKDIV238) || \ + ((CLKDIV) == SDIO_CLKDIV240) || \ + ((CLKDIV) == SDIO_CLKDIV242) || \ + ((CLKDIV) == SDIO_CLKDIV244) || \ + ((CLKDIV) == SDIO_CLKDIV246) || \ + ((CLKDIV) == SDIO_CLKDIV248) || \ + ((CLKDIV) == SDIO_CLKDIV250) || \ + ((CLKDIV) == SDIO_CLKDIV252) || \ + ((CLKDIV) == SDIO_CLKDIV254) || \ + ((CLKDIV) == SDIO_CLKDIV256) || \ + ((CLKDIV) == SDIO_CLKDIV258) || \ + ((CLKDIV) == SDIO_CLKDIV260) || \ + ((CLKDIV) == SDIO_CLKDIV262) || \ + ((CLKDIV) == SDIO_CLKDIV264) || \ + ((CLKDIV) == SDIO_CLKDIV266) || \ + ((CLKDIV) == SDIO_CLKDIV268) || \ + ((CLKDIV) == SDIO_CLKDIV270) || \ + ((CLKDIV) == SDIO_CLKDIV272) || \ + ((CLKDIV) == SDIO_CLKDIV274) || \ + ((CLKDIV) == SDIO_CLKDIV276) || \ + ((CLKDIV) == SDIO_CLKDIV278) || \ + ((CLKDIV) == SDIO_CLKDIV280) || \ + ((CLKDIV) == SDIO_CLKDIV282) || \ + ((CLKDIV) == SDIO_CLKDIV284) || \ + ((CLKDIV) == SDIO_CLKDIV286) || \ + ((CLKDIV) == SDIO_CLKDIV288) || \ + ((CLKDIV) == SDIO_CLKDIV290) || \ + ((CLKDIV) == SDIO_CLKDIV282) || \ + ((CLKDIV) == SDIO_CLKDIV294) || \ + ((CLKDIV) == SDIO_CLKDIV296) || \ + ((CLKDIV) == SDIO_CLKDIV298) || \ + ((CLKDIV) == SDIO_CLKDIV300) || \ + ((CLKDIV) == SDIO_CLKDIV302) || \ + ((CLKDIV) == SDIO_CLKDIV304) || \ + ((CLKDIV) == SDIO_CLKDIV306) || \ + ((CLKDIV) == SDIO_CLKDIV308) || \ + ((CLKDIV) == SDIO_CLKDIV310) || \ + ((CLKDIV) == SDIO_CLKDIV312) || \ + ((CLKDIV) == SDIO_CLKDIV314) || \ + ((CLKDIV) == SDIO_CLKDIV316) || \ + ((CLKDIV) == SDIO_CLKDIV318) || \ + ((CLKDIV) == SDIO_CLKDIV320) || \ + ((CLKDIV) == SDIO_CLKDIV322) || \ + ((CLKDIV) == SDIO_CLKDIV324) || \ + ((CLKDIV) == SDIO_CLKDIV326) || \ + ((CLKDIV) == SDIO_CLKDIV328) || \ + ((CLKDIV) == SDIO_CLKDIV330) || \ + ((CLKDIV) == SDIO_CLKDIV332) || \ + ((CLKDIV) == SDIO_CLKDIV334) || \ + ((CLKDIV) == SDIO_CLKDIV336) || \ + ((CLKDIV) == SDIO_CLKDIV338) || \ + ((CLKDIV) == SDIO_CLKDIV340) || \ + ((CLKDIV) == SDIO_CLKDIV342) || \ + ((CLKDIV) == SDIO_CLKDIV344) || \ + ((CLKDIV) == SDIO_CLKDIV346) || \ + ((CLKDIV) == SDIO_CLKDIV348) || \ + ((CLKDIV) == SDIO_CLKDIV350) || \ + ((CLKDIV) == SDIO_CLKDIV352) || \ + ((CLKDIV) == SDIO_CLKDIV354) || \ + ((CLKDIV) == SDIO_CLKDIV356) || \ + ((CLKDIV) == SDIO_CLKDIV358) || \ + ((CLKDIV) == SDIO_CLKDIV360) || \ + ((CLKDIV) == SDIO_CLKDIV362) || \ + ((CLKDIV) == SDIO_CLKDIV364) || \ + ((CLKDIV) == SDIO_CLKDIV366) || \ + ((CLKDIV) == SDIO_CLKDIV368) || \ + ((CLKDIV) == SDIO_CLKDIV370) || \ + ((CLKDIV) == SDIO_CLKDIV372) || \ + ((CLKDIV) == SDIO_CLKDIV374) || \ + ((CLKDIV) == SDIO_CLKDIV376) || \ + ((CLKDIV) == SDIO_CLKDIV378) || \ + ((CLKDIV) == SDIO_CLKDIV380) || \ + ((CLKDIV) == SDIO_CLKDIV382) || \ + ((CLKDIV) == SDIO_CLKDIV384) || \ + ((CLKDIV) == SDIO_CLKDIV386) || \ + ((CLKDIV) == SDIO_CLKDIV388) || \ + ((CLKDIV) == SDIO_CLKDIV390) || \ + ((CLKDIV) == SDIO_CLKDIV392) || \ + ((CLKDIV) == SDIO_CLKDIV394) || \ + ((CLKDIV) == SDIO_CLKDIV396) || \ + ((CLKDIV) == SDIO_CLKDIV398) || \ + ((CLKDIV) == SDIO_CLKDIV400) || \ + ((CLKDIV) == SDIO_CLKDIV402) || \ + ((CLKDIV) == SDIO_CLKDIV404) || \ + ((CLKDIV) == SDIO_CLKDIV406) || \ + ((CLKDIV) == SDIO_CLKDIV408) || \ + ((CLKDIV) == SDIO_CLKDIV410) || \ + ((CLKDIV) == SDIO_CLKDIV412) || \ + ((CLKDIV) == SDIO_CLKDIV414) || \ + ((CLKDIV) == SDIO_CLKDIV416) || \ + ((CLKDIV) == SDIO_CLKDIV418) || \ + ((CLKDIV) == SDIO_CLKDIV420) || \ + ((CLKDIV) == SDIO_CLKDIV422) || \ + ((CLKDIV) == SDIO_CLKDIV424) || \ + ((CLKDIV) == SDIO_CLKDIV426) || \ + ((CLKDIV) == SDIO_CLKDIV428) || \ + ((CLKDIV) == SDIO_CLKDIV430) || \ + ((CLKDIV) == SDIO_CLKDIV432) || \ + ((CLKDIV) == SDIO_CLKDIV434) || \ + ((CLKDIV) == SDIO_CLKDIV436) || \ + ((CLKDIV) == SDIO_CLKDIV438) || \ + ((CLKDIV) == SDIO_CLKDIV440) || \ + ((CLKDIV) == SDIO_CLKDIV442) || \ + ((CLKDIV) == SDIO_CLKDIV444) || \ + ((CLKDIV) == SDIO_CLKDIV446) || \ + ((CLKDIV) == SDIO_CLKDIV448) || \ + ((CLKDIV) == SDIO_CLKDIV450) || \ + ((CLKDIV) == SDIO_CLKDIV452) || \ + ((CLKDIV) == SDIO_CLKDIV454) || \ + ((CLKDIV) == SDIO_CLKDIV456) || \ + ((CLKDIV) == SDIO_CLKDIV458) || \ + ((CLKDIV) == SDIO_CLKDIV460) || \ + ((CLKDIV) == SDIO_CLKDIV462) || \ + ((CLKDIV) == SDIO_CLKDIV464) || \ + ((CLKDIV) == SDIO_CLKDIV466) || \ + ((CLKDIV) == SDIO_CLKDIV468) || \ + ((CLKDIV) == SDIO_CLKDIV470) || \ + ((CLKDIV) == SDIO_CLKDIV472) || \ + ((CLKDIV) == SDIO_CLKDIV474) || \ + ((CLKDIV) == SDIO_CLKDIV476) || \ + ((CLKDIV) == SDIO_CLKDIV478) || \ + ((CLKDIV) == SDIO_CLKDIV480) || \ + ((CLKDIV) == SDIO_CLKDIV482) || \ + ((CLKDIV) == SDIO_CLKDIV484) || \ + ((CLKDIV) == SDIO_CLKDIV486) || \ + ((CLKDIV) == SDIO_CLKDIV488) || \ + ((CLKDIV) == SDIO_CLKDIV490) || \ + ((CLKDIV) == SDIO_CLKDIV492) || \ + ((CLKDIV) == SDIO_CLKDIV494) || \ + ((CLKDIV) == SDIO_CLKDIV496) || \ + ((CLKDIV) == SDIO_CLKDIV498) || \ + ((CLKDIV) == SDIO_CLKDIV500) || \ + ((CLKDIV) == SDIO_CLKDIV502) || \ + ((CLKDIV) == SDIO_CLKDIV504) || \ + ((CLKDIV) == SDIO_CLKDIV506) || \ + ((CLKDIV) == SDIO_CLKDIV508) || \ + ((CLKDIV) == SDIO_CLKDIV510)) + + +/** @defgroup SDIO_CLKENA_Register **/ +/** @defgroup SDIO_CCLK_ENABLE + * @{ + */ +#define SDIO_CCLK_ENABLE_DISABLE ((uint32_t)0x00) +#define SDIO_CCLK_ENABLE_ENABLE SDIO_CLKENA_CCLK_ENABLE_0 + +#define IS_SDIO_CCLK_ENABLE(ENABLE) (((ENABLE) == SDIO_CCLK_ENABLE_DISABLE) || \ + ((ENABLE) == SDIO_CCLK_ENABLE_ENABLE)) + + +/** @defgroup SDIO_TMOUT_Register **/ +/** @defgroup SDIO_response_timeout & SDIO_data_timeout + * @{ + */ +#define IS_SDIO_RESPONSE_TIMEOUT ((uint32_t)0x00000040) +#define IS_SDIO_DATA_TIMEOUT ((uint32_t)0xffffff00) +#define IS_SDIO_TIMEOUT(TIMEOUT) \ + ( \ + ((TIMEOUT) == SDIO_RESPONSE_TIMEOUT ) || \ + ((TIMEOUT) == SDIO_DATA_TIMEOUT ) || \ + ) + + +/** @defgroup SDIO_CTYPE_Register **/ +/** @defgroup SDIO_Card_Width + * @{ + */ +#define SDIO_CARD_WIDE_1B ((uint32_t)0x00) +#define SDIO_CARD_WIDE_4B SDIO_CTYPE_CARD0_WIDTH2 +#define SDIO_CARD_WIDE_8B SDIO_CTYPE_CARD0_WIDTH1 + +#define IS_SDIO_CARD_WIDE(WIDE) (((WIDE) == SDIO_CARD_WIDE_1B) || \ + ((WIDE) == SDIO_CARD_WIDE_4B) || \ + ((WIDE) == SDIO_CARD_WIDE_8B)) + + +/** @defgroup SDIO_BLKSIZ_Register **/ +/** @defgroup SDIO_Data_Block_Size Data Block Size + * @{ + */ +#define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000001) +#define SDIO_DATABLOCK_SIZE_2B ((uint32_t)0x00000002) +#define SDIO_DATABLOCK_SIZE_4B ((uint32_t)0x00000004) +#define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000008) +#define SDIO_DATABLOCK_SIZE_16B ((uint32_t)0x00000010) +#define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000020) +#define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000040) +#define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000080) +#define SDIO_DATABLOCK_SIZE_256B ((uint32_t)0x00000100) +#define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000200) + +#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ + ((SIZE) == SDIO_DATABLOCK_SIZE_512B)) + + +/** @defgroup SDIO_BYTCCNT_Register **/ +/** @defgroup SDIO_Data_Byte_Count + * @{ + */ +#define IS_SDIO_DATA_BYTE_COUNT(COUNT) ((COUNT) <= 0xFFFFFFFFU) + + +/** @defgroup SDIO_INTMASK_Register **/ +/** @defgroup SDIO_Interrupt_Mask_sources Interrupt Sources Mask + * @{ + */ +#define SDIO_IT_MASK_CARDDETECT SDIO_INTMASK_CD_INT_MASK +#define SDIO_IT_MASK_RE SDIO_INTMASK_RE_INT_MASK +#define SDIO_IT_MASK_CMDDONE SDIO_INTMASK_CMD_INT_MASK +#define SDIO_IT_MASK_DTO SDIO_INTMASK_DTO_INT_MASK +#define SDIO_IT_MASK_TXDR SDIO_INTMASK_TXDR_INT_MASK +#define SDIO_IT_MASK_RXDR SDIO_INTMASK_RXDR_INT_MASK +#define SDIO_IT_MASK_RCRC SDIO_INTMASK_RCRC_INT_MASK +#define SDIO_IT_MASK_DCRC SDIO_INTMASK_DCRC_INT_MASK +#define SDIO_IT_MASK_RTO SDIO_INTMASK_RTO_INT_MASK +#define SDIO_IT_MASK_DRTO SDIO_INTMASK_DRTO_INT_MASK +#define SDIO_IT_MASK_HTO SDIO_INTMASK_HTO_INT_MASK +#define SDIO_IT_MASK_FRUN SDIO_INTMASK_FRUN_INT_MASK +#define SDIO_IT_MASK_HLE SDIO_INTMASK_HLE_INT_MASK +#define SDIO_IT_MASK_SBE SDIO_INTMASK_SBE_BCI_INT_MASK +#define SDIO_IT_MASK_ACD SDIO_INTMASK_ACD_INT_MASK +#define SDIO_IT_MASK_EBE SDIO_INTMASK_EBE_INT_MASK +#define SDIO_IT_MASK_SDIOIT SDIO_INTMASK_SDIO_INT_MASK_CARD0 + +#define IS_SDIO_IT_MASK(MASK) (((MASK)==SDIO_IT_MASK_CARDDETECT) || \ + ((MASK)==SDIO_IT_MASK_RE) || \ + ((MASK)==SDIO_IT_MASK_CMDDONE) || \ + ((MASK)==SDIO_IT_MASK_DTO) || \ + ((MASK)==SDIO_IT_MASK_TXDR ) || \ + ((MASK)==SDIO_IT_MASK_RXDR ) || \ + ((MASK)==SDIO_IT_MASK_RCRC ) || \ + ((MASK)==SDIO_IT_MASK_DCRC ) || \ + ((MASK)==SDIO_IT_MASK_RTO ) || \ + ((MASK)==SDIO_IT_MASK_DRTO ) || \ + ((MASK)==SDIO_IT_MASK_HTO ) || \ + ((MASK)==SDIO_IT_MASK_FRUN ) || \ + ((MASK)==SDIO_IT_MASK_HLE ) || \ + ((MASK)==SDIO_IT_MASK_SBE ) || \ + ((MASK)==SDIO_IT_MASK_ACD ) || \ + ((MASK)==SDIO_IT_MASK_EBE ) || \ + ((MASK)==SDIO_IT_MASK_SDIOIT)) + +/** @defgroup SDIO_MINTSTS_Register **/ +/** @defgroup SDIO_Interrupt_Flags + * @{ + */ +#define SDIO_IT_FLAG_CARDDETECT SDIO_MINTSTS_CARD_DETECT_INTERRUPT +#define SDIO_IT_FLAG_RE SDIO_MINTSTS_RESPONSE_ERROR_INTERRUPT +#define SDIO_IT_FLAG_CMDDONE SDIO_MINTSTS_COMMAND_DONE_INTERRUPT +#define SDIO_IT_FLAG_DTO SDIO_MINTSTS_DATA_TRANSFER_OVER_INTERRUPT +#define SDIO_IT_FLAG_TXDR SDIO_MINTSTS_TRANSMIT_RECEIVE_FIFO_DATA_INTERRUPT +#define SDIO_IT_FLAG_RXDR SDIO_MINTSTS_RECEIVE_FIFO_DATA_REQUEST_INTERRUPT +#define SDIO_IT_FLAG_RCRC SDIO_MINTSTS_RESPONSE_CRC_ERROR_INTERRUPT +#define SDIO_IT_FLAG_DCRC SDIO_MINTSTS_DATA_CRC_ERROR_INTERRUPT +#define SDIO_IT_FLAG_RTO SDIO_MINTSTS_RESPONSE_TIMEOUT_INTERRUPT +#define SDIO_IT_FLAG_DRTO SDIO_MINTSTS_DATA_READ_TIMEOUT_INTERRUPT +#define SDIO_IT_FLAG_HTO SDIO_MINTSTS_HOST_TIMEOUT_INTERRUPT +#define SDIO_IT_FLAG_FRUN SDIO_MINTSTS_FIFO_UNDER_OVER_RUN_INTERRUPT +#define SDIO_IT_FLAG_HLE SDIO_MINTSTS_HARDWARE_LOCKED_WRITE_INTERRUPT +#define SDIO_IT_FLAG_SBE SDIO_MINTSTS_BUSY_COMPLETE_INTERRUPT +#define SDIO_IT_FLAG_ACD SDIO_MINTSTS_AUTO_COMMAND_DONE_INTERRUPT +#define SDIO_IT_FLAG_EBE SDIO_MINTSTS_END_BIT_ERROR_INTERRUPT +#define SDIO_IT_FLAG_SDIOIT SDIO_MINTSTS_SDIO_INTERRUPT_CARD0 + +#define IS_SDIO_IT_FLAG(FLAG) (((FLAG)==SDIO_IT_FLAG_CARDDETECT) || \ + ((FLAG)==SDIO_IT_FLAG_RE) || \ + ((FLAG)==SDIO_IT_FLAG_CMDDONE) || \ + ((FLAG)==SDIO_IT_FLAG_DTO) || \ + ((FLAG)==SDIO_IT_FLAG_TXDR ) || \ + ((FLAG)==SDIO_IT_FLAG_RXDR ) || \ + ((FLAG)==SDIO_IT_FLAG_RCRC ) || \ + ((FLAG)==SDIO_IT_FLAG_DCRC ) || \ + ((FLAG)==SDIO_IT_FLAG_RTO ) || \ + ((FLAG)==SDIO_IT_FLAG_DRTO ) || \ + ((FLAG)==SDIO_IT_FLAG_HTO ) || \ + ((FLAG)==SDIO_IT_FLAG_FRUN ) || \ + ((FLAG)==SDIO_IT_FLAG_HLE ) || \ + ((FLAG)==SDIO_IT_FLAG_SBE ) || \ + ((FLAG)==SDIO_IT_FLAG_ACD ) || \ + ((FLAG)==SDIO_IT_FLAG_EBE ) || \ + ((FLAG)==SDIO_IT_FLAG_SDIOIT)) + + +/** @defgroup SDIO_RINTSTS_Register **/ +/** @defgroup SDIO_Interrupt_Clean + * @{ + */ +#define SDIO_IT_CLEAN_CARDDETECT SDIO_RINTSTS_CARD_DETECT_STATUS +#define SDIO_IT_CLEAN_RE SDIO_RINTSTS_RESPONSE_ERROR_STATUS +#define SDIO_IT_CLEAN_CMDDONE SDIO_RINTSTS_COMMAND_DONE_STATUS +#define SDIO_IT_CLEAN_DTO SDIO_RINTSTS_DATA_TRANSFER_OVER_STATUS +#define SDIO_IT_CLEAN_TXDR SDIO_RINTSTS_TRANSMIT_FIFO_DATA_REQUEST_STATUS +#define SDIO_IT_CLEAN_RXDR SDIO_RINTSTS_RECEIVE_FIFO_DATA_REQUEST_STATUS +#define SDIO_IT_CLEAN_RCRC SDIO_RINTSTS_RESPONSE_CRC_ERROR_STATUS +#define SDIO_IT_CLEAN_DCRC SDIO_RINTSTS_DATA_CRC_ERROR_STATUS +#define SDIO_IT_CLEAN_RTO SDIO_RINTSTS_RESPONSE_TIMEOUT_STATUS +#define SDIO_IT_CLEAN_DRTO SDIO_RINTSTS_DATA_READ_TIMEOUT_STATUS +#define SDIO_IT_CLEAN_HTO SDIO_RINTSTS_HOST_TIMEOUT_STATUS +#define SDIO_IT_CLEAN_FRUN SDIO_RINTSTS_FIFO_UNDER_OVER_RUN_STATUS +#define SDIO_IT_CLEAN_HLE SDIO_RINTSTS_HARDWARE_LOCKED_WRITE_STATUS +#define SDIO_IT_CLEAN_SBE SDIO_RINTSTS_BUSY_COMPLETE_STATUS +#define SDIO_IT_CLEAN_ACD SDIO_RINTSTS_AUTO_COMMAND_DONE_STATUS +#define SDIO_IT_CLEAN_EBE SDIO_RINTSTS_END_BIT_ERROR_STATUS +#define SDIO_IT_CLEAN_SDIOIT SDIO_RINTSTS_SDIO_INTERRUPT_CARD0 + +#define IS_SDIO_IT_CLEAN(CLEAN) (((CLEAN)==SDIO_IT_CLEAN_CARDDETECT) || \ + ((CLEAN)==SDIO_IT_CLEAN_RE) || \ + ((CLEAN)==SDIO_IT_CLEAN_CMDDONE) || \ + ((CLEAN)==SDIO_IT_CLEAN_DTO) || \ + ((CLEAN)==SDIO_IT_CLEAN_TXDR ) || \ + ((CLEAN)==SDIO_IT_CLEAN_RXDR ) || \ + ((CLEAN)==SDIO_IT_CLEAN_RCRC ) || \ + ((CLEAN)==SDIO_IT_CLEAN_DCRC ) || \ + ((CLEAN)==SDIO_IT_CLEAN_RTO ) || \ + ((CLEAN)==SDIO_IT_CLEAN_DRTO ) || \ + ((CLEAN)==SDIO_IT_CLEAN_HTO ) || \ + ((CLEAN)==SDIO_IT_CLEAN_FRUN ) || \ + ((CLEAN)==SDIO_IT_CLEAN_HLE ) || \ + ((CLEAN)==SDIO_IT_CLEAN_SBE ) || \ + ((CLEAN)==SDIO_IT_CLEAN_ACD ) || \ + ((CLEAN)==SDIO_IT_CLEAN_EBE ) || \ + ((CLEAN)==SDIO_IT_CLEAN_SDIOIT)) + + +/** @defgroup SDIO_CMDARG_Register **/ +/** @defgroup SDIO_Command_Argument + * @{ + */ +#define IS_SDIO_CMD_ARG(ARG) ((ARG) <= 0xFFFFFFFFU) + + +/** @defgroup SDIO_CMD_Register **/ +/** @defgroup SDIO_LL_CMD_START + * @{ + */ +#define SDIO_CMD_START_DISABLE ((uint32_t)0x00) +#define SDIO_CMD_START_ENABLE SDIO_CMD_START_CMD + +#define IS_SDIO_CMD_START(START) (((START) == SDIO_CMD_START_DISABLE) || \ + ((START) == SDIO_CMD_START_ENABLE)) + + +/** @defgroup SDIO_Use_hold_reg + * @{ + */ +#define SDIO_USE_HOLD_REG_DISABLE ((uint32_t)0x00) +#define SDIO_USE_HOLD_REG_ENABLE SDIO_CMD_USE_HOLD_REG + +#define IS_SDIO_USE_HOLD_REG(ENABLE) (((ENABLE) == SDIO_USE_HOLD_REG_DISABLE) || \ + ((ENABLE) == SDIO_USE_HOLD_REG_ENABLE)) + + +/** @defgroup SDIO_UPDATE_CLOCK_REGISTER_ONLY + * @{ + */ +#define SDIO_UPDATE_CLOCK_REGISTER_ONLY_DISABLE ((uint32_t)0x00) +#define SDIO_UPDATE_CLOCK_REGISTER_ONLY_ENABLE SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY + +#define IS_SDIO_UPDATE_CLOCK_REGISTER_ONLY_ENABLE(ENABLE) (((ENABLE) == SDIO_UPDATE_CLOCK_REGISTER_ONLY_DISABLE) || \ + ((ENABLE) == SDIO_UPDATE_CLOCK_REGISTER_ONLY_ENABLE)) + +/** @defgroup SDIO_SEND_AUTO_STOP + * @{ + */ +#define SDIO_SEND_AUTO_STOP_DISABLE ((uint32_t)0x00) +#define SDIO_SEND_AUTO_STOP_ENABLE SDIO_CMD_SEND_AUTO_STOP + +#define IS_SDIO_SEND_AUTO_STOP_ENABLE(ENABLE) (((ENABLE) == SDIO_SEND_AUTO_STOP_DISABLE) || \ + ((ENABLE) == SDIO_SEND_AUTO_STOP_ENABLE)) + + +/** @defgroup SDIO_Transfer_Mode Block/stream + * @{ + */ +#define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00) +#define SDIO_TRANSFER_MODE_STREAM SDIO_CMD_TRANSFER_MODE + +#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ + ((MODE) == SDIO_TRANSFER_MODE_STREAM)) + +/** @defgroup SDIO_Transfer_Direction Read/Write + * @{ + */ +#define SDIO_TRANSFER_READ_FROM_CARD ((uint32_t)0x00) +#define SDIO_TRANSFER_WRITE_TO_CARD SDIO_CMD_READ_WRITE + +#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_READ_FROM_CARD) || \ + ((DIR) == SDIO_TRANSFER_WRITE_TO_CARD)) + +/** @defgroup SDIO_Data_Expected + * @{ + */ +#define SDIO_DATA_EXPECTED_DISABLE ((uint32_t)0x00) +#define SDIO_DATA_EXPECTED_ENABLE SDIO_CMD_DATA_EXPECTED + +#define IS_SDIO_DATA_EXPECT(EXPECT) (((EXPECT) == SDIO_DATA_EXPECTED_DISABLE) || \ + ((EXPECT) == SDIO_DATA_EXPECTED_ENABLE)) + +/** @defgroup SDIO_Check_Response_CRC + * @{ + */ +#define SDIO_CHECK_RESPONSE_CRC_DISABLE ((uint32_t)0x00) +#define SDIO_CHECK_RESPONSE_CRC_ENABLE SDIO_CMD_CHECK_RESPONSE_CRC + +#define IS_SDIO_CHECK_RESPONSE_CRC(CRC) (((CRC) == SDIO_CHECK_RESPONSE_CRC_DISABLE) || \ + ((CRC) == SDIO_CHECK_RESPONSE_CRC_ENABLE)) + +/** @defgroup SDIO_Response_Length + * @{ + */ +#define SDIO_RESPONSE_SHORT ((uint32_t)0x00) +#define SDIO_RESPONSE_LONG SDIO_CMD_RESPONSE_LENGTH + +#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_SHORT) || \ + ((RESPONSE) == SDIO_RESPONSE_LONG)) + +/** @defgroup SDIO_Response_Expect + * @{ + */ +#define SDIO_RESPONSE_EXPECT_DISABLE ((uint32_t)0x00) +#define SDIO_RESPONSE_EXPECT_ENABLE SDIO_CMD_RESPONSE_EXPECT + +#define IS_SDIO_RESPONSE_EXPECT(EXPECT) (((EXPECT) == SDIO_RESPONSE_EXPECT_DISABLE) || \ + ((EXPECT) == SDIO_RESPONSE_EXPECT_ENABLE)) + + +/** @defgroup SDIO_Command_Index Command Index + * @{ + */ +#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40U) + + +/** @defgroup SDIO_STATUS_Register **/ +/** @defgroup SDIO_status + * @{ + */ +#define SDIO_STAT_FIFO_RX_WATERMARK SDIO_STATUS_FIFO_RX_WATERMARK +#define SDIO_STAT_FIFO_TX_WATERMARK SDIO_STATUS_FIFO_TX_WATERMARK +#define SDIO_STAT_FIFO_EMPTY SDIO_STATUS_FIFO_EMPTY +#define SDIO_STAT_FIFO_FULL SDIO_STATUS_FIFO_FULL +#define SDIO_STAT_FSM_IDLE ((uint32_t)0x00) +#define SDIO_STAT_FSM_SED_INIT_SEQ ((uint32_t)0x01) +#define SDIO_STAT_FSM_TX_CMD_START_BIT ((uint32_t)0x02) +#define SDIO_STAT_FSM_TX_CMD_TX_BIT ((uint32_t)0x03) +#define SDIO_STAT_FSM_TX_CMD_INDEX_ARG ((uint32_t)0x04) +#define SDIO_STAT_FSM_TX_CMD_CRC7 ((uint32_t)0x05) +#define SDIO_STAT_FSM_TX_CMD_END_BIT ((uint32_t)0x06) +#define SDIO_STAT_FSM_RX_RESP_START_BIT ((uint32_t)0x07) +#define SDIO_STAT_FSM_RX_RESP_IRQ ((uint32_t)0x08) +#define SDIO_STAT_FSM_RX_RESP_TX_BIT ((uint32_t)0x09) +#define SDIO_STAT_FSM_RX_RESP_CMD_IDX ((uint32_t)0x0a) +#define SDIO_STAT_FSM_RX_RESP_DATA ((uint32_t)0x0b) +#define SDIO_STAT_FSM_RX_RESP_CRC7 ((uint32_t)0x0c) +#define SDIO_STAT_FSM_RX_RESP_END_BIT ((uint32_t)0x0d) +#define SDIO_STAT_FSM_CMD_PATH_WAIT_NCC ((uint32_t)0x0e) +#define SDIO_STAT_FSM_WAIT ((uint32_t)0x0f) +#define SDIO_STAT_DATA_3_STATUS SDIO_STATUS_DATA_3_STATUS +#define SDIO_STAT_DATA_BUSY SDIO_STATUS_DATA_BUSY +#define SDIO_STAT_DATA_STATE_MC_BUSY SDIO_STATUS_DATA_STATE_MC_BUSY +#define SDIO_STAT_RESPONSE_INDEX SDIO_STATUS_RESPONSE_INDEX +#define SDIO_STAT_FIFO_COUNT SDIO_STATUS_FIFO_COUNT +#define SDIO_STAT_DMA_ACK SDIO_STATUS_DMA_ACK +#define SDIO_STAT_DMA_REQ SDIO_STATUS_DMA_REQ + +#define IS_SDIO_STATUS(STATUS) (((STATUS)==SDIO_STAT_FIFO_RX_WATERMARK ) || \ + ((STATUS)==SDIO_STAT_FIFO_TX_WATERMARK ) || \ + ((STATUS)==SDIO_STAT_FIFO_EMPTY ) || \ + ((STATUS)==SDIO_STAT_FIFO_FULL ) || \ + ((STATUS)==SDIO_STAT_FSM_IDLE ) || \ + ((STATUS)==SDIO_STAT_FSM_SED_INIT_SEQ ) || \ + ((STATUS)==SDIO_STAT_FSM_TX_CMD_START_BIT ) || \ + ((STATUS)==SDIO_STAT_FSM_TX_CMD_TX_BIT ) || \ + ((STATUS)==SDIO_STAT_FSM_TX_CMD_INDEX_ARG ) || \ + ((STATUS)==SDIO_STAT_FSM_TX_CMD_CRC7 ) || \ + ((STATUS)==SDIO_STAT_FSM_TX_CMD_END_BIT ) || \ + ((STATUS)==SDIO_STAT_FSM_RX_RESP_START_BIT) || \ + ((STATUS)==SDIO_STAT_FSM_RX_RESP_IRQ ) || \ + ((STATUS)==SDIO_STAT_FSM_RX_RESP_TX_BIT ) || \ + ((STATUS)==SDIO_STAT_FSM_RX_RESP_CMD_IDX ) || \ + ((STATUS)==SDIO_STAT_FSM_RX_RESP_DATA ) || \ + ((STATUS)==SDIO_STAT_FSM_RX_RESP_CRC7 ) || \ + ((STATUS)==SDIO_STAT_FSM_RX_RESP_END_BIT ) || \ + ((STATUS)==SDIO_STAT_FSM_CMD_PATH_WAIT_NCC) || \ + ((STATUS)==SDIO_STAT_FSM_WAIT ) || \ + ((STATUS)==SDIO_STAT_DATA_3_STATUS ) || \ + ((STATUS)==SDIO_STAT_DATA_BUSY ) || \ + ((STATUS)==SDIO_STAT_DATA_STATE_MC_BUSY ) || \ + ((STATUS)==SDIO_STAT_RESPONSE_INDEX ) || \ + ((STATUS)==SDIO_STAT_FIFO_COUNT ) || \ + ((STATUS)==SDIO_STAT_DMA_ACK ) || \ + ((STATUS)==SDIO_STAT_DMA_REQ )) + + +/** @defgroup SDIO_FIFOTH_Register **/ +/** @defgroup SDIO_RX&Tx_WMark + * @{ + */ +#define SDIO_RX_WATERMARK SDIO_FIFOTH_RX_WMark +#define SDIO_TX_WATERMARK SDIO_FIFOTH_TX_WMark + +#define IS_SDIO_FIFOTH_WATERMARK(WATERMARK) (((WATERMARK)==SDIO_RX_WATERMARK) || \ + ((WATERMARK)==SDIO_TX_WATERMARK)) + + + +/** @defgroup all of sdio registers **/ +/** @defgroup SDIO_ALL_Registers + * @{ + */ +#define SDIO_CTRL ((uint8_t)0x00) +#define SDIO_PWREN ((uint8_t)0x04) +#define SDIO_CLKDIV ((uint8_t)0x08) +#define SDIO_CLKSRC ((uint8_t)0x0C) +#define SDIO_CLKENA ((uint8_t)0x10) +#define SDIO_TMOUT ((uint8_t)0x14) +#define SDIO_CTYPE ((uint8_t)0x18) +#define SDIO_BLKSIZ ((uint8_t)0x1C) +#define SDIO_BYTCNT ((uint8_t)0x20) +#define SDIO_INTMASK ((uint8_t)0x24) +#define SDIO_CMDARG ((uint8_t)0x28) +#define SDIO_CMD ((uint8_t)0x2C) +#define SDIO_RESP0 ((uint8_t)0x30) +#define SDIO_RESP1 ((uint8_t)0x34) +#define SDIO_RESP2 ((uint8_t)0x38) +#define SDIO_RESP3 ((uint8_t)0x3C) +#define SDIO_MINTSTS ((uint8_t)0x40) +#define SDIO_RINTSTS ((uint8_t)0x44) +#define SDIO_STATUS ((uint8_t)0x48) +#define SDIO_FIFOTH ((uint8_t)0x4C) + +#define IS_SDIO_REGISTER(REGISTER) (((REGISTER) == SDIO_CTRL) || \ + ((REGISTER) == SDIO_PWREN) || \ + ((REGISTER) == SDIO_CLKDIV) || \ + ((REGISTER) == SDIO_CLKSRC) || \ + ((REGISTER) == SDIO_CLKENA) || \ + ((REGISTER) == SDIO_TMOUT) || \ + ((REGISTER) == SDIO_CTYPE) || \ + ((REGISTER) == SDIO_BLKSIZ) || \ + ((REGISTER) == SDIO_BYTCNT) || \ + ((REGISTER) == SDIO_INTMASK) || \ + ((REGISTER) == SDIO_CMDARG) || \ + ((REGISTER) == SDIO_CMD) || \ + ((REGISTER) == SDIO_RESP0) || \ + ((REGISTER) == SDIO_RESP1) || \ + ((REGISTER) == SDIO_RESP2) || \ + ((REGISTER) == SDIO_RESP3) || \ + ((REGISTER) == SDIO_MINTSTS) || \ + ((REGISTER) == SDIO_RINTSTS) || \ + ((REGISTER) == SDIO_STATUS) || \ + ((REGISTER) == SDIO_FIFOTH)) + + +/******************************************************************************************/ +/** + * @brief SDMMC Commands Index + */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its + operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information + and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_READ_DAT_UNTIL_STOP 11U /*!< SD card doesn't support it. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands + (read, write, lock). Default block length is fixed to 512 Bytes. Not effective + for SDHS and SDXC. */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by + STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of + fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command + system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. + Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by + the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather + than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card + for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * SDMMC_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus + widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with + 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * SDMMC_CMD_APP_CMD should be sent before sending these commands. + */ +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U + + +/******************************************************************************************/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Configuration of the SDIO **********************************/ +void SDIO_DeInit(void); +void SDIO_odpullupConfig(uint32_t SDIO_odenable); +void SDIO_UseholdregConfig(uint32_t SDIO_Useholdregenable); +void SDIO_PowerEnableConfig(uint32_t SDIO_PowerEnable); +void SDIO_TimeOutConfig(uint32_t SDIO_TMOUTValue); +void SDIO_FifoThConfig(uint32_t SDIO_FIFOTHValue); +void SDIO_CardWidthConfig(uint32_t SDIO_CardWidth); +void SDIO_TransferModeConfig(uint32_t SDIO_TransferMode); +void SDIO_TransferDirectionConfig(uint32_t SDIO_ReadWrite); +void SDIO_DataExpectedConfig(uint32_t SDIO_DataExpected); +void SDIO_CheckResponseCRCConfig(uint32_t SDIO_CheckResponseCRC); +void SDIO_ResponseLengthConfig(uint32_t SDIO_ResponseLength); +void SDIO_ResponseLengthConfig(uint32_t SDIO_ResponseLength); +void SDIO_ResponseExpectConfig(uint32_t SDIO_ResponseExpect); +void SDIO_ChangeCardClock(uint32_t SDIO_Clkdiv); +void SDIO_SendCMD(uint32_t SDIO_CmdIndex); +void SDIO_CMDARGConfig(uint32_t SDIO_CmdArgument); +void SDIO_BlockSizeConfig(uint32_t SDIO_BlockSize); +void SDIO_ByteCountConfig(uint32_t SDIO_ByteCount); +void SDIO_ITConfig(uint32_t SDIO_IT); +FlagStatus SDIO_GetITFlag(uint32_t SDIO_FLAG); +void SDIO_ClearITFlag(uint32_t SDIO_FLAG); +uint32_t SDIO_GetFifoStatus(uint32_t SDIO_FIFOStatus); +uint32_t SDIO_GetStatus(uint32_t SDIO_Status); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_SDIO_H */ + +/** + * @} + */ + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_spdif.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_spdif.h new file mode 100644 index 00000000000..c8be3507f15 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_spdif.h @@ -0,0 +1,151 @@ +/** + ****************************************************************************** + * @file ft32f4xx_spdif.h + * @author xcao + * @brief Header file of SPDIF module. + ****************************************************************************** + * @attention + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef FT32F4XX_SPDIF_H +#define FT32F4XX_SPDIF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup SPDIF + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SPDIF_Exported_Types SPDIF Exported Types + * @{ + */ + +/** + * @brief SPDIF Init structure definition + */ + +typedef struct +{ + uint32_t StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode. + This parameter can be a value of @ref SPDIF_Stereo_Mode */ + + uint32_t ValidityBitMask; /*!< Specifies whether the frame is written or discarded. + This parameter can be a value of @ref SPDIF_V_Mask */ + + uint32_t ParityErrorMask; /*!< Specifies whether the parity error is checked. + This parameter can be a value of @ref SPDIF_PE_Mask */ + + uint16_t FifoAfullThreshold; /*!< Specifies read fifo almost full threshold. + This parameter can be a value of @ref SPDIF_FifoAF_THLD */ + + uint16_t FifoAemptyThreshold; /*!< Specifies read fifo almost empty threshold + This parameter can be a value of @ref SPDIF_FifoAE_THLD */ +} SPDIFRX_InitTypeDef; + + +/** + * @brief SPDIF handle Structure definition + */ +typedef struct +{ + SPDIF_TypeDef *Instance; /* SPDIFRX registers base address */ + + uint32_t *pRxBuffPtr; /* Pointer to SPDIF Rx transfer buffer */ + + + __IO uint16_t RxXferSize; /* SPDIF Rx transfer size */ + + __IO uint16_t RxXferCount; /* SPDIF Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received. + NbSamplesReceived = RxBufferSize-RxBufferCount) */ +} SPDIF_HandleTypeDef; + + + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPDIF_Exported_Constants SPDIF Exported Constants + * @{ + */ + +/** @defgroup SPDIF_Stereo_Mode SPDIF Stereo Mode + * @{ + */ +#define SPDIF_STEREOMODE_DISABLE ((uint32_t)0x00000000U) +#define SPDIF_STEREOMODE_ENABLE ((uint32_t)SPDIF_CTRL_CHANNEL_MODE) +/** + * @} + */ + +/** @defgroup SPDIF_V_Mask SPDIF VALID Mask + * @{ + */ +#define SPDIF_VALIDITYMASK_OFF ((uint32_t)0x00000000U) +#define SPDIF_VALIDITYMASK_ON ((uint32_t)SPDIF_CTRL_VALIDITYCHECK) +/** + * @} + */ + +/** @defgroup SPDIF_PE_Mask SPDIF PARITYERROR Mask + * @{ + */ +#define SPDIF_PARITYERRORMASK_OFF ((uint32_t)0x00000000U) +#define SPDIF_PARITYERRORMASK_ON ((uint32_t)SPDIF_CTRL_PARITY_MASK) +/** + * @} + */ + + + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPDIF_Private_Macros SPDIF Private Macros + * @{ + */ + +#define IS_STEREO_MODE(MODE) (((MODE) == SPDIF_STEREOMODE_DISABLE) || \ + ((MODE) == SPDIF_STEREOMODE_ENABLE)) + +#define IS_VALIDITY_MASK(VAL) (((VAL) == SPDIF_VALIDITYMASK_OFF) || \ + ((VAL) == SPDIF_VALIDITYMASK_ON)) + +#define IS_PARITY_ERROR_MASK(VAL) (((VAL) == SPDIF_PARITYERRORMASK_OFF) || \ + ((VAL) == SPDIF_PARITYERRORMASK_ON)) +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup SPDIF_Exported_Functions SPDIF Exported Functions + * @{ + */ +void SPDIFRX_Init(SPDIF_HandleTypeDef *spdif, SPDIFRX_InitTypeDef *spdifrx_init); +void SPDIF_ReceiveDataFlow(SPDIF_HandleTypeDef *spdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); +void SPDIFRX_ReceiveDataFlow_IT(SPDIF_HandleTypeDef *spdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout); +void SPDIF_MspInit(SPDIF_HandleTypeDef *spdif); +/** + * @} + */ + +#endif /* FT32F4XX_SPDIF_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_spi.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_spi.h new file mode 100644 index 00000000000..9039eb5e573 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_spi.h @@ -0,0 +1,443 @@ +/** + ****************************************************************************** + * @file ft32f4xx_spi.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the SPI + * firmware library. + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_SPI_H +#define __FT32F4XX_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup SPI + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief SPI Init structure definition + */ + +typedef struct +{ + uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /*!< Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ +} SPI_InitTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SPI_Exported_Constants + * @{ + */ + +#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ + ((PERIPH) == SPI2) || \ + ((PERIPH) == SPI3)) + +#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1)) + +/** @defgroup SPI_data_direction + * @{ + */ + +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) +#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ + ((MODE) == SPI_Direction_2Lines_RxOnly) || \ + ((MODE) == SPI_Direction_1Line_Rx) || \ + ((MODE) == SPI_Direction_1Line_Tx)) +/** + * @} + */ + +/** @defgroup SPI_mode + * @{ + */ + +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) +#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ + ((MODE) == SPI_Mode_Slave)) +/** + * @} + */ + +/** @defgroup SPI_data_size + * @{ + */ + +#define SPI_DataSize_4b ((uint16_t)0x0300) +#define SPI_DataSize_5b ((uint16_t)0x0400) +#define SPI_DataSize_6b ((uint16_t)0x0500) +#define SPI_DataSize_7b ((uint16_t)0x0600) +#define SPI_DataSize_8b ((uint16_t)0x0700) +#define SPI_DataSize_9b ((uint16_t)0x0800) +#define SPI_DataSize_10b ((uint16_t)0x0900) +#define SPI_DataSize_11b ((uint16_t)0x0A00) +#define SPI_DataSize_12b ((uint16_t)0x0B00) +#define SPI_DataSize_13b ((uint16_t)0x0C00) +#define SPI_DataSize_14b ((uint16_t)0x0D00) +#define SPI_DataSize_15b ((uint16_t)0x0E00) +#define SPI_DataSize_16b ((uint16_t)0x0F00) +#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \ + ((SIZE) == SPI_DataSize_5b) || \ + ((SIZE) == SPI_DataSize_6b) || \ + ((SIZE) == SPI_DataSize_7b) || \ + ((SIZE) == SPI_DataSize_8b) || \ + ((SIZE) == SPI_DataSize_9b) || \ + ((SIZE) == SPI_DataSize_10b) || \ + ((SIZE) == SPI_DataSize_11b) || \ + ((SIZE) == SPI_DataSize_12b) || \ + ((SIZE) == SPI_DataSize_13b) || \ + ((SIZE) == SPI_DataSize_14b) || \ + ((SIZE) == SPI_DataSize_15b) || \ + ((SIZE) == SPI_DataSize_16b)) +/** + * @} + */ + +/** @defgroup SPI_CRC_length + * @{ + */ + +#define SPI_CRCLength_8b ((uint16_t)0x0000) +#define SPI_CRCLength_16b SPI_CR1_CRCL +#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \ + ((LENGTH) == SPI_CRCLength_16b)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Polarity + * @{ + */ + +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High SPI_CR1_CPOL +#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ + ((CPOL) == SPI_CPOL_High)) +/** + * @} + */ + +/** @defgroup SPI_Clock_Phase + * @{ + */ + +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge SPI_CR1_CPHA +#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ + ((CPHA) == SPI_CPHA_2Edge)) +/** + * @} + */ + +/** @defgroup SPI_Slave_Select_management + * @{ + */ + +#define SPI_NSS_Soft SPI_CR1_SSM +#define SPI_NSS_Hard ((uint16_t)0x0000) +#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ + ((NSS) == SPI_NSS_Hard)) +/** + * @} + */ + +/** @defgroup SPI_BaudRate_Prescaler + * @{ + */ + +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) +#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ + ((PRESCALER) == SPI_BaudRatePrescaler_256)) +/** + * @} + */ + +/** @defgroup SPI_MSB_LSB_transmission + * @{ + */ + +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST +#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ + ((BIT) == SPI_FirstBit_LSB)) +/** + * @} + */ + +/** @defgroup SPI_FIFO_reception_threshold + * @{ + */ + +#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000) +#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH +#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \ + ((THRESHOLD) == SPI_RxFIFOThreshold_QF)) +/** + * @} + */ + +/** @defgroup SPI_DMA_transfer_requests + * @{ + */ + +#define SPI_DMAReq_Tx (SPI_CR2_TXDMAEN) +#define SPI_DMAReq_Rx (SPI_CR2_RXDMAEN) +#define IS_SPI_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00)) + +/** + * @} + */ + +/** @defgroup SPI_last_DMA_transfers + * @{ + */ + +#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000) +#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000) +#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000) +#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000) +#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \ + ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd)) +/** + * @} + */ +/** @defgroup SPI_NSS_internal_software_management + * @{ + */ + +#define SPI_NSSInternalSoft_Set SPI_CR1_SSI +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) +#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ + ((INTERNAL) == SPI_NSSInternalSoft_Reset)) +/** + * @} + */ + +/** @defgroup SPI_CRC_Transmit_Receive + * @{ + */ + +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) +#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) +/** + * @} + */ + +/** @defgroup SPI_direction_transmit_receive + * @{ + */ + +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) +#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ + ((DIRECTION) == SPI_Direction_Tx)) +/** + * @} + */ + +/** @defgroup SPI_interrupts_definition + * @{ + */ + +#define SPI_IT_TXE ((uint8_t)0x71) +#define SPI_IT_RXNE ((uint8_t)0x60) +#define SPI_IT_ERR ((uint8_t)0x50) + +#define IS_SPI_CONFIG_IT(IT) (((IT) == SPI_IT_TXE) || \ + ((IT) == SPI_IT_RXNE) || \ + ((IT) == SPI_IT_ERR)) + +#define IT_UDR ((uint8_t)0x53) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_OVR ((uint8_t)0x56) +#define SPI_IT_FRE ((uint8_t)0x58) + +#define IS_SPI_GET_IT(IT) (((IT) == SPI_IT_RXNE) || ((IT) == SPI_IT_TXE) || \ + ((IT) == SPI_IT_OVR) || ((IT) == SPI_IT_MODF) || \ + ((IT) == SPI_IT_FRE)|| ((IT) == IT_UDR)) +/** + * @} + */ + + +/** @defgroup SPI_transmission_fifo_status_level + * @{ + */ + +#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000) +#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800) +#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000) +#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800) + +/** + * @} + */ + +/** @defgroup SPI_reception_fifo_status_level + * @{ + */ +#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000) +#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200) +#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400) +#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600) + +/** + * @} + */ + + +/** @defgroup SPI_flags_definition + * @{ + */ + +#define SPI_FLAG_RXNE SPI_SR_RXNE +#define SPI_FLAG_TXE SPI_SR_TXE +#define SPI_FLAG_CRCERR SPI_SR_CRCERR +#define SPI_FLAG_MODF SPI_SR_MODF +#define SPI_FLAG_OVR SPI_SR_OVR +#define SPI_FLAG_BSY SPI_SR_BSY +#define SPI_FLAG_FRE SPI_SR_FRE + + + +#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) +#define IS_SPI_GET_FLAG(FLAG) (((FLAG) == SPI_FLAG_BUSY) || ((FLAG) == SPI_FLAG_OVR) || \ + ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ + ((FLAG) == SPI_FLAG_TXE) || ((FLAG) == SPI_FLAG_RXNE)|| \ + ((FLAG) == SPI_FLAG_FRE)) +/** + * @} + */ + +/** @defgroup SPI_CRC_polynomial + * @{ + */ + +#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Initialization and Configuration functions *********************************/ +void SPI_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); + +/* Data transfers functions ***************************************************/ +void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data); +void SPI_SendData16(SPI_TypeDef* SPIx, uint16_t Data); +uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx); +uint16_t SPI_ReceiveData16(SPI_TypeDef* SPIx); + +/* Hardware CRC Calculation functions *****************************************/ +void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); + +/* DMA transfers management functions *****************************************/ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState); +void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer); + +/* Interrupts and flags management functions **********************************/ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState); +uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx); +uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx); +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); +void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG); +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_SPI_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_ssi.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_ssi.h new file mode 100644 index 00000000000..3f08728d0d4 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_ssi.h @@ -0,0 +1,625 @@ +/** + ****************************************************************************** + * @file ft32f4xx_hal_sai.h + * @author xcao + * @brief Header file of SSI module. + ****************************************************************************** + * @attention + * + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4xx_SSI_H +#define __FT32F4xx_SSI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup SSI_Exported_Types SSI Exported Types + * @{ + */ + +/** + * @brief State structures definition + */ +typedef enum +{ + SSI_STATE_RESET = 0x00U, /*!< SSI not yet initialized or disabled */ + SSI_STATE_READY = 0x01U, /*!< SSI initialized and ready for use */ + SSI_STATE_BUSY = 0x02U, /*!< SSI internal process is ongoing */ + SSI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ + SSI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ + SSI_STATE_TIMEOUT = 0x03U, /*!< SSI timeout state */ + SSI_STATE_ERROR = 0x04U /*!< SSI error state */ +} SSI_StateTypeDef; + + +/** @defgroup SSI_Init_Structure_definition SSI Init Structure definition + * @brief SSI Init Structure definition + * @{ + */ +typedef struct +{ + uint32_t Mode; /*!< Specifies the SSI Mode. + This parameter can be a value of @ref SSI_MODE */ + + FunctionalState SyncMode; /*!< Configure the SSI synchronization Mode. */ + + FunctionalState TCHEN; /*!< Configure the SSI two-channel operation Mode. */ + + FunctionalState OVERSAMPLE; /*!< Configure the SSI oversample clk output. */ + + FunctionalState RFRCLKDIS; /*!< Configure the SSI receive frame clock disable + when ssi receive has been disabled */ + + FunctionalState TFRCLKDIS; /*!< Configure the SSI receive frame clock disable + when ssi transmit has been disabled */ + + uint32_t AC97FRDIV; /*!< Specifies the AC97 frame rate divider + This parameter can be a value from 0x00 - 0x3f + eg:0x01 = SSI will operate every 2 frames */ + + uint32_t AC97SLOTWIDTH; /*!< Specifies the AC97 frame slot data width + This parameter can be a value of @ref SSI_AC97SLOTWIDTH */ + + FunctionalState AC97RXTAGINFIFO; /*!< Configure the AC97 received tag data store to FIFO */ + + FunctionalState AC97VarMode; /*!< Configure the AC97 variable mode */ + +} SSI_InitTypeDef; +/** + * @} + */ + + +/** @defgroup SSI_TxInitType Structure_definition SSI Tx Init Structure definition + * @brief SSI Tx Init Structure definition + * @{ + */ +typedef struct +{ + FunctionalState FIFO0EN; /*!< Configure the SSI TX FIFO0 */ + + FunctionalState FIFO1EN; /*!< Configure the SSI TX FIFO1 */ + + uint32_t FIFO0WaterMark; /*!< Specifies the SSI FIFO WaterMark to determine the FIFO empty flag. + This parameter can be a value of @ref SSI_FIFO_WATERMARK */ + + uint32_t FIFO1WaterMark; /*!< Specifies the SSI FIFO WaterMark to determine the FIFO empty flag. + This parameter can be a value of @ref SSI_FIFO_WATERMARK */ + + uint32_t TxDataType; /*!< Specifies data transfers start from MSB or LSB bit and + data truncate high-order or truncate low-order. + This parameter can be a value of @ref SSI_TRANSDATA_TYPE */ + + uint32_t DataSize; /*!< Specifies the SSI WORD Data size. + This parameter can be a value of @ref SSI_DATA_SIZE */ + + uint32_t TxSlotMsk; /*!< Specifies the SSI frame slots mask. + This parameter can be a value of @ref SSI_SLOTMSK */ + + uint32_t AC97TxSlotEn; /*!< Specifies the SSI AC97 slots enable. + This parameter can be a value of @ref SSI_AC97SLOTEN + Only used for fixed mode */ + + uint32_t CODECCMDADDR; /*!< Specifies the SSI AC97 command addr slot + value Reference codec addr */ + + uint32_t CODECCMDDATA; /*!< Specifies the SSI AC97 data slot + value range can be 0x00000-0xfffff */ + + uint32_t FrameSyncPolarity; /*!< Specifies the SSI frame sync polarity + This parameter can be a value of @ref SSI_FRAMESYNC_POLARITY */ + + FunctionalState FrameSyncLenBit; /*!< Configure the SSI frame lenth for one-word or one-clock-bit */ + + FunctionalState FrameSyncEarly; /*!< Configure the SSI frame sync assert position */ + + FunctionalState FrameSyncFromExit; /*!< Configure the SSI frame sync from exit */ + + uint32_t FrameRate ; /*!< Specifies the SSI frame rate divide ration on the word clock. + In network mode , this ration sets the number of words of per frame. + In normal mode , specifies 5'b00000 equel to ratio of 1 provides continuous + periodic data word transfer.A bit-length frame sync must be used in this case. + this value range from 00000 to 11111 to control the nomber of words in a frame*/ + + FunctionalState TxClkFromExit; /*!< Configure the SSI Transmit Clock direction */ + + uint32_t TxClkPolarity; /*!< Specifies the SSI format of bit clock edge used to clock out data + This paramete can be a value of @ref SSI_CLOCK_POLARITY */ + + uint32_t FixedDivParam; /*!< Specifies fixed divider paramter + This parameter can be a value of @ref SSI_BITCLK_FIXDIV */ + + uint8_t CustomDivParam; /*!< Specifies custom divider parameter + This paramter from 1 to 256(PM = 0x00 to 0xFF) */ +} SSI_TxInitTypeDef; + +/** + * @} + */ + + +/** @defgroup SSI_RxInitType Structure_definition SSI Rx Init Structure definition + * @brief SSI Rx Init Structure definition + * @{ + */ +typedef struct +{ + FunctionalState FIFO0EN; /*!< Configure the SSI RX FIFO0 */ + + FunctionalState FIFO1EN; /*!< Configure the SSI RX FIFO1 */ + + uint32_t FIFO0WaterMark; /*!< Specifies the SSI FIFO WaterMark to determine the FIFO empty flag. + This parameter can be a value of @ref SSI_FIFO_WATERMARK */ + + uint32_t FIFO1WaterMark; /*!< Specifies the SSI FIFO WaterMark to determine the FIFO empty flag. + This parameter can be a value of @ref SSI_FIFO_WATERMARK */ + + uint32_t RxDataType; /*!< Specifies data transfers start from MSB or LSB bit and + data truncate high-order or truncate low-order. + This parameter can be a value of @ref SSI_TRANSDATA_TYPE */ + + uint32_t DataSize; /*!< Specifies the SSI WORD Data size. + This parameter can be a value of @ref SSI_DATA_SIZE */ + + uint32_t RxSlotMsk; /*!< Specifies the SSI frame slots mask. + This parameter can be a value of @ref SSI_SLOTMSK */ + + uint32_t FrameSyncPolarity; /*!< Specifies the SSI frame sync polarity + This parameter can be a value of @ref SSI_FRAMESYNC_POLARITY */ + + FunctionalState FrameSyncLenBit; /*!< Configure the SSI frame lenth for one-word or one-clock-bit */ + + FunctionalState FrameSyncEarly; /*!< Configure the SSI frame sync assert position */ + + FunctionalState FrameSyncFromExit; /*!< Configure the SSI frame sync from exit */ + + uint32_t FrameRate; /*!< Specifies the frame Rate */ + + FunctionalState RxClkFromExit; /*!< Configure the SSI Transmit Clock direction */ + + uint32_t RxClkPolarity; /*!< Specifies the SSI format of bit clock edge used to clock out data + This paramete can be a value of @ref SSI_CLOCK_POLARITY */ + + uint32_t FixedDivParam; /*!< Specifies fixed divider paramter + This parameter can be a value of @ref SSI_BITCLK_FIXDIV */ + + uint8_t CustomDivParam; /*!< Specifies custom divider parameter + This paramter from 1 to 256(PM = 0x00 to 0xFF) */ +} SSI_RxInitTypeDef; + +/** + * @} + */ + +/** @defgroup SSI_Handle_Structure_definition SSI Handle Structure definition + * @brief SSI handle Structure definition + * @{ + */ +typedef struct __SSI_HandleTypeDef +{ + SSI_TypeDef *Instance; /*!< SSI Blockx registers base address */ + + uint8_t *pBuffPtr0; /*!< Pointer to SSI transfer Buffer0 */ + + uint8_t *pBuffPtr1; /*!< Pointer to SSI transfer Buffer1 */ + + uint16_t XferSize0; /*!< SSI transfer size0 */ + + uint16_t XferSize1; /*!< SSI transfer size1 */ + + uint16_t XferCount0; /*!< SSI transfer counter0 */ + + uint16_t XferCount1; /*!< SSI transfer counter1 */ + + __IO SSI_StateTypeDef State; /*!< SSI communication state */ + + __IO uint32_t ErrorCode; /*!< SSI Error code */ + + +} SSI_HandleTypeDef; +/** + * @} + */ + + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup SSI_Exported_Functions SSI Exported Functions + * @{ + */ +void SSI_Init(SSI_HandleTypeDef *ssi, + SSI_InitTypeDef *ssi_init, + SSI_TxInitTypeDef *ssi_txinit, + SSI_RxInitTypeDef *ssi_rxinit); + +void SSI_Transmit(SSI_HandleTypeDef *ssi, + SSI_InitTypeDef *ssi_init, + SSI_TxInitTypeDef *ssi_txinit, + uint8_t *pData0, + uint8_t *pData1, + uint16_t Size0, + uint16_t Size1, + uint32_t Timeout); + +void SSI_Receive(SSI_HandleTypeDef *ssi, + SSI_InitTypeDef *ssi_init, + SSI_RxInitTypeDef *ssi_rxinit, + uint8_t *pData0, + uint8_t *pData1, + uint16_t Size0, + uint16_t Size1, + uint32_t Timeout); + +void TxConfigInit(SSI_HandleTypeDef *ssi, SSI_InitTypeDef *ssi_init, SSI_TxInitTypeDef *ssi_txinit); +void RxConfigInit(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit); + +void SSI_MspInit(SSI_HandleTypeDef *ssi); +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SSI_Exported_Constants SSI Exported Constants + * @{ + */ +/** @defgroup SAI_Error_Code SAI Error Code + * @{ + */ +#define SSI_ERROR_NONE 0x00000000U /*!< No error */ +#define SSI_ERROR_OVR 0x00000001U /*!< Overrun Error */ +#define SSI_ERROR_UDR 0x00000002U /*!< Underrun error */ +#define SSI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ +#define SSI_ERROR_DMA 0x00000080U /*!< DMA error */ +/** + * @} + */ + + +/** @defgroup SSI_BITCLK_FIXDIV Clock Divider Presets + * @{ + */ +//#define FIX_CLOCK_DIV2 0x00000000U /* Fixed 2x frequency division */ +#define FIX_CLOCK_DIV4 0x00000001U /* Fixed 4x frequency division */ +#define FIX_CLOCK_DIV16 0x00000003U /* Fixed 16x frequency division */ +#define FIX_CLOCK_DIV32 0x00000004U /* Fixed 32x frequency division */ +/** + * @} + */ + + +/** @defgroup SSI_MODE Presets + * @{ + */ +#define NET 0x00000001 +#define NORMAL 0x00000002 +#define I2S_MASTER 0x00000003 +#define I2S_SLAVE 0x00000004 +#define AC97 0x00000005 +/** + * @} + */ + +/** @defgroup I2S_MODE_PARAM Presets + * @{ + */ +#define I2S_MASTER_PARAM 0x00000020 +#define I2S_SLAVE_PARAM 0x00000040 +/** + * @} + */ + +/** @defgroup SSI_TRANSDATA_TYPE Presets + * @{ + */ +#define MSB_MSW 0x00000001 +#define MSB_LSW 0x00000002 +#define LSB_MSW 0x00000003 +//#define LSB_LSW 0x00000004 +/** + * @} + */ + +/** @defgroup SSI_FIFO_WATERMARK Presets + * @{ + */ +#define WATERMARKEQ0 0x00000000 +#define WATERMARKEQ1 0x00000001 +#define WATERMARKEQ2 0x00000002 +#define WATERMARKEQ3 0x00000003 +#define WATERMARKEQ4 0x00000004 +#define WATERMARKEQ5 0x00000005 +#define WATERMARKEQ6 0x00000006 +#define WATERMARKEQ7 0x00000007 +#define WATERMARKEQ8 0x00000008 +#define WATERMARKEQ9 0x00000009 +#define WATERMARKEQA 0x0000000A +#define WATERMARKEQB 0x0000000B +#define WATERMARKEQC 0x0000000C +#define WATERMARKEQD 0x0000000D +#define WATERMARKEQE 0x0000000E +#define WATERMARKEQF 0x0000000F +/** + * @} + */ + +/** @defgroup SSI_DATA_SIZE Presets + * @{ + */ +#define SSI_DATA_WL8 0x00000003 +#define SSI_DATA_WL10 0x00000004 +#define SSI_DATA_WL12 0x00000005 +#define SSI_DATA_WL16 0x00000007 +#define SSI_DATA_WL18 0x00000008 +#define SSI_DATA_WL20 0x00000009 +#define SSI_DATA_WL22 0x0000000A +#define SSI_DATA_WL24 0x0000000B +/** + * @} + */ + +/** @defgroup SSI_FRAME_LEGNTH Presets + * @{ + */ +#define SSI_FRAME_LEN0 0x00000000 /* bit-lenth frame sync must be used */ +#define SSI_FRAME_LEN1 0x00000100 +#define SSI_FRAME_LEN2 0x00000200 +#define SSI_FRAME_LEN3 0x00000300 +#define SSI_FRAME_LEN4 0x00000400 +#define SSI_FRAME_LEN5 0x00000500 +#define SSI_FRAME_LEN6 0x00000600 +#define SSI_FRAME_LEN7 0x00000700 +#define SSI_FRAME_LEN8 0x00000800 +#define SSI_FRAME_LEN9 0x00000900 +#define SSI_FRAME_LEN10 0x00000A00 +#define SSI_FRAME_LEN11 0x00000B00 +#define SSI_FRAME_LEN12 0x00000C00 +#define SSI_FRAME_LEN13 0x00000D00 +#define SSI_FRAME_LEN14 0x00000E00 +#define SSI_FRAME_LEN15 0x00000F00 +#define SSI_FRAME_LEN16 0x00001F00 +/** + * @} + */ + +/** @defgroup SSI_CLOCK_POLARITY Presets + * @{ + */ +#define RISINGEDGE 0x00000000 +#define FALLINGEDGE 0x00000001 +/** + * @} + */ + +/** @defgroup SSI_FRAMESYNC_POLARITY Presets + * @{ + */ +#define ACTIVEHIGH 0x00000000 +#define ACTIVELOW 0x00000001 +/** + * @} + */ + +/** @defgroup SSI_AC97SLOTWIDTH Presets + * @{ + */ +#define SLOTWIDEQ20 0x00000000 +#define SLOTWIDEQ16 0x00000001 +/** + * @} + */ + + +/** @defgroup SSI_SLOTMSK Presets + * @{ + */ +/*1 no data transmit in this time slot*/ +#define ENALLSLOTS 0x00000000 +#define ENSLOTS1 0xFFFFFFFE +#define ENSLOTS2 0xFFFFFFFD +#define ENSLOTS3 0xFFFFFFFB +#define ENSLOTS4 0xFFFFFFF7 +#define ENSLOTS5 0xFFFFFFEF +#define ENSLOTS6 0xFFFFFFDF +#define ENSLOTS7 0xFFFFFFBF +#define ENSLOTS8 0xFFFFFF7F +#define ENSLOTS9 0xFFFFFEFF +#define ENSLOTS10 0xFFFFFDFF +#define ENSLOTS11 0xFFFFFBFF +#define ENSLOTS12 0xFFFFF7FF +#define ENSLOTS13 0xFFFFEFFF +#define ENSLOTS14 0xFFFFDFFF +#define ENSLOTS15 0xFFFFBFFF +#define ENSLOTS16 0xFFFF7FFF +#define ENSLOTS17 0xFFFEFFFF +#define ENSLOTS18 0xFFFDFFFF +#define ENSLOTS19 0xFFFBFFFF +#define ENSLOTS20 0xFFF7FFFF +#define ENSLOTS21 0xFFEFFFFF +#define ENSLOTS22 0xFFDFFFFF +#define ENSLOTS23 0xFFBFFFFF +#define ENSLOTS24 0xFF7FFFFF +#define ENSLOTS25 0xFEFFFFFF +#define ENSLOTS26 0xFDFFFFFF +#define ENSLOTS27 0xFBFFFFFF +#define ENSLOTS28 0xF7FFFFFF +#define ENSLOTS29 0xEFFFFFFF +#define ENSLOTS30 0xDFFFFFFF +#define ENSLOTS31 0xBFFFFFFF +#define ENSLOTS32 0x7FFFFFFF +/** + * @} + */ + + +/** @defgroup SSI_AC97SLOTEN Presets + * @{ + */ +#define AC97SLOT0EN 0x00000004 +#define AC97SLOT1EN 0x00000008 +#define AC97SLOT2EN 0x00000010 +#define AC97SLOT3EN 0x00000020 +#define AC97SLOT4EN 0x00000040 +#define AC97SLOT5EN 0x00000080 +#define AC97SLOT6EN 0x00000100 +#define AC97SLOT7EN 0x00000200 +#define AC97SLOT8EN 0x00000400 +#define AC97SLOT9EN 0x00000800 +#define AC97SLOT10EN 0x00001000 +#define AC97SLOT11EN 0x00002000 +#define AC97SLOT12EN 0x00004000 +/** + * @} + */ + + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup SAI_Private_Macros + * @{ + */ +#define IS_SSI_MODE(MODE) (((MODE) == NET) ||\ + ((MODE) == NORMAL) ||\ + ((MODE) == I2S_MASTER) ||\ + ((MODE) == I2S_SLAVE) ||\ + ((MODE) == AC97)) + +#define IS_SSI_AC97SLOTWIDTH(SLOTWIDTH) (((SLOTWIDTH) == SLOTWIDEQ20) || \ + ((SLOTWIDTH) == SLOTWIDEQ16)) + + +#define IS_SSI_BITCLK_FIXDIV(FIXDIV) (((FIXDIV) == FIX_CLOCK_DIV4) || \ + ((FIXDIV) == FIX_CLOCK_DIV16) || \ + ((FIXDIV) == FIX_CLOCK_DIV32) \ + ) + +#define IS_SSI_DATA_SIZE(DATA_SIZE) (((DATA_SIZE) == SSI_DATA_WL8) || \ + ((DATA_SIZE) == SSI_DATA_WL10) || \ + ((DATA_SIZE) == SSI_DATA_WL12) || \ + ((DATA_SIZE) == SSI_DATA_WL14) || \ + ((DATA_SIZE) == SSI_DATA_WL16) || \ + ((DATA_SIZE) == SSI_DATA_WL18) || \ + ((DATA_SIZE) == SSI_DATA_WL20) || \ + ((DATA_SIZE) == SSI_DATA_WL22) || \ + ((DATA_SIZE) == SSI_DATA_WL24) \ + ) + +#define IS_SSI_FRAMELEN(FRLEN) (((FRLEN) == SSI_FRAME_LEN0) ||\ + ((FRLEN) == SSI_FRAME_LEN1 )||\ + ((FRLEN) == SSI_FRAME_LEN2 )||\ + ((FRLEN) == SSI_FRAME_LEN3 )||\ + ((FRLEN) == SSI_FRAME_LEN4 )||\ + ((FRLEN) == SSI_FRAME_LEN5 )||\ + ((FRLEN) == SSI_FRAME_LEN6 )||\ + ((FRLEN) == SSI_FRAME_LEN7 )||\ + ((FRLEN) == SSI_FRAME_LEN8 )||\ + ((FRLEN) == SSI_FRAME_LEN9 )||\ + ((FRLEN) == SSI_FRAME_LEN10 )||\ + ((FRLEN) == SSI_FRAME_LEN11 )||\ + ((FRLEN) == SSI_FRAME_LEN12 )||\ + ((FRLEN) == SSI_FRAME_LEN13 )||\ + ((FRLEN) == SSI_FRAME_LEN14 )||\ + ((FRLEN) == SSI_FRAME_LEN15 )||\ + ((FRLEN) == SSI_FRAME_LEN16 )) + + +#define IS_SSI_SLOTMSK(SLOTMSK) ( ((SLOTMSK) == ENALLSLOTS) || \ + ((SLOTMSK) == ENSLOTS0 ) || \ + ((SLOTMSK) == ENSLOTS1 ) || \ + ((SLOTMSK) == ENSLOTS2 ) || \ + ((SLOTMSK) == ENSLOTS3 ) || \ + ((SLOTMSK) == ENSLOTS4 ) || \ + ((SLOTMSK) == ENSLOTS5 ) || \ + ((SLOTMSK) == ENSLOTS6 ) || \ + ((SLOTMSK) == ENSLOTS7 ) || \ + ((SLOTMSK) == ENSLOTS8 ) || \ + ((SLOTMSK) == ENSLOTS9 ) || \ + ((SLOTMSK) == ENSLOTS10 ) || \ + ((SLOTMSK) == ENSLOTS11 ) || \ + ((SLOTMSK) == ENSLOTS12 ) || \ + ((SLOTMSK) == ENSLOTS13 ) || \ + ((SLOTMSK) == ENSLOTS14 ) || \ + ((SLOTMSK) == ENSLOTS15 ) || \ + ((SLOTMSK) == ENSLOTS16 ) || \ + ((SLOTMSK) == ENSLOTS17 ) || \ + ((SLOTMSK) == ENSLOTS18 ) || \ + ((SLOTMSK) == ENSLOTS19 ) || \ + ((SLOTMSK) == ENSLOTS20 ) || \ + ((SLOTMSK) == ENSLOTS21 ) || \ + ((SLOTMSK) == ENSLOTS22 ) || \ + ((SLOTMSK) == ENSLOTS23 ) || \ + ((SLOTMSK) == ENSLOTS24 ) || \ + ((SLOTMSK) == ENSLOTS25 ) || \ + ((SLOTMSK) == ENSLOTS26 ) || \ + ((SLOTMSK) == ENSLOTS27 ) || \ + ((SLOTMSK) == ENSLOTS28 ) || \ + ((SLOTMSK) == ENSLOTS29 ) || \ + ((SLOTMSK) == ENSLOTS30 ) || \ + ((SLOTMSK) == ENSLOTS31 )) + + +#define IS_SSI_AC97SLOTSEN(AC97SLOTEN) (((AC97SLOTEN) == AC97SLOT0EN ) ||\ + ((AC97SLOTEN) == AC97SLOT1EN ) ||\ + ((AC97SLOTEN) == AC97SLOT2EN ) ||\ + ((AC97SLOTEN) == AC97SLOT3EN ) ||\ + ((AC97SLOTEN) == AC97SLOT4EN ) ||\ + ((AC97SLOTEN) == AC97SLOT5EN ) ||\ + ((AC97SLOTEN) == AC97SLOT6EN ) ||\ + ((AC97SLOTEN) == AC97SLOT7EN ) ||\ + ((AC97SLOTEN) == AC97SLOT8EN ) ||\ + ((AC97SLOTEN) == AC97SLOT9EN ) ||\ + ((AC97SLOTEN) == AC97SLOT10EN) ||\ + ((AC97SLOTEN) == AC97SLOT11EN) ||\ + ((AC97SLOTEN) == AC97SLOT12EN)) + + +#define IS_SSI_TRANSDATA_TYPE(TRANSDATA) (((TRANSDATA) == MSB_MSW) || \ + ((TRANSDATA) == MSB_LSW) || \ + ((TRANSDATA) == LSB_MSW)\ + ) + +#define IS_SSI_FIFO_WATERMARK(WATERMARK) (((WATERMARK) == WATERMARKEQ0) || \ + ((WATERMARK) == WATERMARKEQ1) || \ + ((WATERMARK) == WATERMARKEQ2) || \ + ((WATERMARK) == WATERMARKEQ3) || \ + ((WATERMARK) == WATERMARKEQ4) || \ + ((WATERMARK) == WATERMARKEQ5) || \ + ((WATERMARK) == WATERMARKEQ6) || \ + ((WATERMARK) == WATERMARKEQ7) || \ + ((WATERMARK) == WATERMARKEQ8) || \ + ((WATERMARK) == WATERMARKEQ9) || \ + ((WATERMARK) == WATERMARKEQA) || \ + ((WATERMARK) == WATERMARKEQB) || \ + ((WATERMARK) == WATERMARKEQC) || \ + ((WATERMARK) == WATERMARKEQD) || \ + ((WATERMARK) == WATERMARKEQE) || \ + ((WATERMARK) == WATERMARKEQF)\ + ) + +#define IS_SSI_FRAMESYNC_POLARITY(FRPOLARITY) (((FRPOLARITY) == ACTIVEHIGH) || \ + ((FRPOLARITY) == ACTIVELOW)) + +#define IS_SSI_CLOCK_POLARITY(CKPOLARITY) (((CKPOLARITY) == RISINGEDGE) ||\ + ((CKPOLARITY) == FALLINGEDGE)) + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* FT32F4xx_SSI_H */ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_syscfg.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_syscfg.h new file mode 100644 index 00000000000..cd0aecb6d40 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_syscfg.h @@ -0,0 +1,275 @@ +/** + ****************************************************************************** + * @file ft32f4xx_syscfg.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the SYSCFG firmware + * library. + * @version V1.0.0 + * @data 2025-04-08 + ****************************************************************************** + */ + + +/*!< Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_SYSCFG_H +#define __FT32F4XX_SYSCFG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/*!< Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup SYSCFG + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup SYSCFG_Exported_Constants + * @{ + */ + +/** @defgroup SYSCFG_EXTI_Port_Sources + * @{ + */ +#define EXTI_PortSourceGPIOA ((uint8_t)0x00) +#define EXTI_PortSourceGPIOB ((uint8_t)0x01) +#define EXTI_PortSourceGPIOC ((uint8_t)0x02) +#define EXTI_PortSourceGPIOD ((uint8_t)0x03) +#define EXTI_PortSourceGPIOE ((uint8_t)0x04) +#define EXTI_PortSourceGPIOH ((uint8_t)0x07) + +#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \ + ((PORTSOURCE) == EXTI_PortSourceGPIOH)) +/** + * @} + */ + +/** @defgroup SYSCFG_EXTI_Pin_sources + * @{ + */ +#define EXTI_PinSource0 ((uint8_t)0x00) +#define EXTI_PinSource1 ((uint8_t)0x01) +#define EXTI_PinSource2 ((uint8_t)0x02) +#define EXTI_PinSource3 ((uint8_t)0x03) +#define EXTI_PinSource4 ((uint8_t)0x04) +#define EXTI_PinSource5 ((uint8_t)0x05) +#define EXTI_PinSource6 ((uint8_t)0x06) +#define EXTI_PinSource7 ((uint8_t)0x07) +#define EXTI_PinSource8 ((uint8_t)0x08) +#define EXTI_PinSource9 ((uint8_t)0x09) +#define EXTI_PinSource10 ((uint8_t)0x0A) +#define EXTI_PinSource11 ((uint8_t)0x0B) +#define EXTI_PinSource12 ((uint8_t)0x0C) +#define EXTI_PinSource13 ((uint8_t)0x0D) +#define EXTI_PinSource14 ((uint8_t)0x0E) +#define EXTI_PinSource15 ((uint8_t)0x0F) + +#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \ + ((PINSOURCE) == EXTI_PinSource1) || \ + ((PINSOURCE) == EXTI_PinSource2) || \ + ((PINSOURCE) == EXTI_PinSource3) || \ + ((PINSOURCE) == EXTI_PinSource4) || \ + ((PINSOURCE) == EXTI_PinSource5) || \ + ((PINSOURCE) == EXTI_PinSource6) || \ + ((PINSOURCE) == EXTI_PinSource7) || \ + ((PINSOURCE) == EXTI_PinSource8) || \ + ((PINSOURCE) == EXTI_PinSource9) || \ + ((PINSOURCE) == EXTI_PinSource10) || \ + ((PINSOURCE) == EXTI_PinSource11) || \ + ((PINSOURCE) == EXTI_PinSource12) || \ + ((PINSOURCE) == EXTI_PinSource13) || \ + ((PINSOURCE) == EXTI_PinSource14) || \ + ((PINSOURCE) == EXTI_PinSource15)) +/** + * @} + */ + +/** @defgroup SYSCFG_Memory_Remap_Config + * @{ + */ +#define SYSCFG_MemoryRemap_Flash ((uint32_t)0x00) +#define SYSCFG_MemoryRemap_SystemMemory ((uint32_t)0x01) +#define SYSCFG_MemoryRemap_SRAM ((uint32_t)0x03) +#define SYSCFG_MemoryRemap_FMC1 ((uint32_t)0x02) +#define SYSCFG_MemoryRemap_FMC2 ((uint32_t)0x04) +#define SYSCFG_MemoryRemap_QSPI ((uint32_t)0x05) + + +#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \ + ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \ + ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \ + ((REMAP) == SYSCFG_MemoryRemap_FMC1) || \ + ((REMAP) == SYSCFG_MemoryRemap_FMC2) || \ + ((REMAP) == SYSCFG_MemoryRemap_QSPI) ) + +/** + * @} + */ + +/** @defgroup SYSCFG_FMC_Memory_mapping_swap_Config + * @{ + */ +#define SYSCFG_FMC_SWP_ENABLE SYSCFG_MEMRMP_SWP_FMC_MAP +#define SYSCFG_FMC_SWP_DISABLE SYSCFG_MEMRMP_SWP_FMC_NO + + +#define IS_SYSCFG_FMC_SWP(FMCCFG) (((FMCCFG) == SYSCFG_FMC_SWP_ENABLE) || \ + ((FMCCFG) == SYSCFG_FMC_SWP_DISABLE) ) + +/** + * @} + */ + +/** @defgroup SYSCFG_ETH_MII_RMII_Config + * @{ + */ +#define SYSCFG_ETH_MII_RMII_SEL_MII ((uint32_t)0x00) +#define SYSCFG_ETH_MII_RMII_SEL_RMII SYSCFG_PMC_MII_RMII_SEL + + +#define IS_SYSCFG_ETH_MII_RMII_SEL(ETHCFG) (((ETHCFG) == SYSCFG_ETH_MII_RMII_SEL_MII) || \ + ((ETHCFG) == SYSCFG_ETH_MII_RMII_SEL_RMII) ) + +/** + * @} + */ + + + +/** @defgroup SYSCFG_BoostEN_Config + * @{ + */ +#define SYSCFG_PMC_BoostEN_ENABLE SYSCFG_PMC_BOOSTEN +#define SYSCFG_PMC_BoostEN_DISABLE ((uint32_t)0x00) + +#define IS_SYSCFG_PMC_BoostEN(BOOSTCFG) (((BOOSTCFG) == SYSCFG_PMC_BoostEN_ENABLE) || \ + ((BOOSTCFG) == SYSCFG_PMC_BoostEN_DISABLE) ) + +/** + * @} + */ + + +/** @defgroup SYSCFG_I2C_FastModePlus_Config + * @{ + */ +#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_PMC_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ +#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_PMC_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ +#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_PMC_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ +#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_PMC_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ +#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_PMC_I2C1_FMP /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7*/ +#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_PMC_I2C2_FMP /* Enable Fast Mode Plus on I2C2 pins*/ +#define SYSCFG_I2CFastModePlus_I2C3 SYSCFG_PMC_I2C3_FMP /* Enable Fast Mode Plus on I2C3 pins*/ + +#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ + ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \ + ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \ + ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \ + ((PIN) == SYSCFG_I2CFastModePlus_I2C3) ) + + +/** + * @} + */ + +/** @defgroup SYSCFG_Lock_Config + * @{ + */ +#define SYSCFG_Break_PVD SYSCFG_CFGR_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1 */ +#define SYSCFG_Break_Lockup SYSCFG_CFGR_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */ + +#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \ + ((CONFIG) == SYSCFG_Break_Lockup)) + +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup SYSCFG_ISR_WRAPPER + * @{ + */ +#define SYSCFG_ITLINE0 ((uint32_t) 0x00000000) +#define SYSCFG_ITLINE1 ((uint32_t) 0x00000001) +#define SYSCFG_ITLINE2 ((uint32_t) 0x00000002) +#define SYSCFG_ITLINE3 ((uint32_t) 0x00000003) +#define SYSCFG_ITLINE4 ((uint32_t) 0x00000004) +#define SYSCFG_ITLINE5 ((uint32_t) 0x00000005) +#define SYSCFG_ITLINE6 ((uint32_t) 0x00000006) +#define SYSCFG_ITLINE7 ((uint32_t) 0x00000007) +#define SYSCFG_ITLINE8 ((uint32_t) 0x00000008) +#define SYSCFG_ITLINE9 ((uint32_t) 0x00000009) +#define SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) +#define SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) +#define SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) +#define SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) +#define SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) +#define SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) +#define SYSCFG_ITLINE16 ((uint32_t) 0x00000010) +#define SYSCFG_ITLINE17 ((uint32_t) 0x00000011) +#define SYSCFG_ITLINE18 ((uint32_t) 0x00000012) +#define SYSCFG_ITLINE19 ((uint32_t) 0x00000013) +#define SYSCFG_ITLINE20 ((uint32_t) 0x00000014) +#define SYSCFG_ITLINE21 ((uint32_t) 0x00000015) +#define SYSCFG_ITLINE22 ((uint32_t) 0x00000016) +#define SYSCFG_ITLINE23 ((uint32_t) 0x00000017) +#define SYSCFG_ITLINE24 ((uint32_t) 0x00000018) +#define SYSCFG_ITLINE25 ((uint32_t) 0x00000019) +#define SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) +#define SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) +#define SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) +#define SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) +#define SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) +#define SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* Function used to set the SYSCFG configuration to the default reset state **/ +void SYSCFG_DeInit(void); + +/* SYSCFG configuration functions *********************************************/ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap); +void SYSCFG_FMCSWPConfig(uint32_t SYSCFG_FMCSWPCFG); +void SYSCFG_BoostENConfig(uint32_t SYSCFG_BoostENCFG); +void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); +void SYSCFG_MII_RMIIConfig(uint32_t SYSCFG_MII_RMIICFG); +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex); +void SYSCFG_BreakConfig(uint32_t SYSCFG_Break); + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_SYSCFG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_tim.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_tim.h new file mode 100644 index 00000000000..de7c0d60fc1 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_tim.h @@ -0,0 +1,1609 @@ +/** + ****************************************************************************** + * @file ft32f4xx_tim.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the TIM + * firmware library. + * @version V1.0.0 + * @date 2025-04-02 + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_TIM_H +#define __FT32F4XX_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + + +/** @addtogroup TIM + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** + * @brief TIM Time Base Init structure definition + * @note This sturcture is used with all TIMx. + */ + +typedef struct +{ + uint32_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint32_t TIM_CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF + @note The high 16-bit auto-reload value (TIM2 and TIM5 only) */ + + uint32_t TIM_ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint32_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/** + * @brief TIM Output Compare Init structure definition + */ + +typedef struct +{ + uint32_t TIM_OCMode; /*!< Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint32_t TIM_OutputState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint32_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF + for TIM2 and TIM5) */ + + uint32_t TIM_OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint32_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint32_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/** + * @brief TIM Input Capture Init structure definition + */ + +typedef struct +{ + + uint32_t TIM_Channel; /*!< Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint32_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint32_t TIM_ICSelection; /*!< Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint32_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint32_t TIM_ICFilter; /*!< Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/** + * @brief TIM_BDTR structure definition + * @note This sturcture is used only with TIM1 and TIM8. + */ + +typedef struct +{ + + uint32_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ + + uint32_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint32_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_Lock_level */ + + uint32_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_Break_Input_enable_disable */ + + uint32_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_Break_Polarity */ + + uint32_t TIM_BreakFilter; /*!< Specifies the break input filter. + This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ + + uint32_t TIM_BreakBIDMode; /*!< Specifies the bidirectional function mode of the break input. + This parameter can be a value of @ref TIM_Break_Input_Bidirectional_Mode */ + + uint32_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ + + uint32_t TIM_CtrlPWMOutput; /*!< Specifies whether the TIM Control PWM Output feature is enabled or not. + This parameter can be a value of @ref TIM_MOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/** + * @brief TIM Break input configuration + */ +typedef struct +{ + uint32_t TIM_Source; /*!< Specifies the source of the timer break input. + This parameter can be a value of @ref TIM_Break_Input_Source */ + uint32_t TIM_Enable; /*!< Specifies whether or not the break input source is enabled. + This parameter can be a value of @ref TIM_Break_Input_Source_Enable */ + uint32_t TIM_Polarity; /*!< Specifies the break input source polarity. + This parameter can be a value of @ref TIM_Break_Input_Source_Polarity */ +} TIM_BreakInputConfigTypeDef; + +/** + * + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup TIM_Exported_constants + * @{ + */ + +#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1 ) || \ + ((PERIPH) == TIM2 ) || \ + ((PERIPH) == TIM3 ) || \ + ((PERIPH) == TIM4 ) || \ + ((PERIPH) == TIM5 ) || \ + ((PERIPH) == TIM6 ) || \ + ((PERIPH) == TIM7 ) || \ + ((PERIPH) == TIM8 ) || \ + ((PERIPH) == TIM9 ) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + ((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14)) + +/* LIST1: TIM 1 */ +#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1) + +/* LIST2: TIM 1 and 8 */ +#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM8)) + +/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */ +#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM8)) + +/* LIST4: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 and 14 */ +#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1 ) || \ + ((PERIPH) == TIM2 ) || \ + ((PERIPH) == TIM3 ) || \ + ((PERIPH) == TIM4 ) || \ + ((PERIPH) == TIM5 ) || \ + ((PERIPH) == TIM8 ) || \ + ((PERIPH) == TIM9 ) || \ + ((PERIPH) == TIM10) || \ + ((PERIPH) == TIM11) || \ + ((PERIPH) == TIM12) || \ + ((PERIPH) == TIM13) || \ + ((PERIPH) == TIM14)) + +/* LIST5: TIM 1, 2, 3, 4, 5, 8, 9 and 12 */ +#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1 ) || \ + ((PERIPH) == TIM2 ) || \ + ((PERIPH) == TIM3 ) || \ + ((PERIPH) == TIM4 ) || \ + ((PERIPH) == TIM5 ) || \ + ((PERIPH) == TIM8 ) || \ + ((PERIPH) == TIM9 ) || \ + ((PERIPH) == TIM12)) + +/* LIST6: TIM 1, 2, 3, 4, 5, 6, 7 and 8 */ +#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \ + ((PERIPH) == TIM2) || \ + ((PERIPH) == TIM3) || \ + ((PERIPH) == TIM4) || \ + ((PERIPH) == TIM5) || \ + ((PERIPH) == TIM6) || \ + ((PERIPH) == TIM7) || \ + ((PERIPH) == TIM8)) + +/* LIST7: TIM 2 and 11 */ +#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM2 ) || \ + ((PERIPH) == TIM11)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_and_PWM_modes + * @{ + */ + +#define TIM_OCMode_Timing 0x00000000U /*!< Frozen */ +#define TIM_OCMode_Active TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ +#define TIM_OCMode_Inactive TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ +#define TIM_OCMode_Toggle (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ +#define TIM_OCMODE_Forced_Inactive TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define TIM_OCMODE_Forced_Active (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_OCMode_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ +#define TIM_OCMode_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ +#define TIM_OCMode_Combined_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ +#define TIM_OCMode_Combined_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Combined PWM mode 2 */ +#define TIM_OCMode_Asymmetric_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMode_Asymmetric_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing ) || \ + ((MODE) == TIM_OCMode_Active ) || \ + ((MODE) == TIM_OCMode_Inactive ) || \ + ((MODE) == TIM_OCMode_Toggle ) || \ + ((MODE) == TIM_OCMODE_Forced_Inactive) || \ + ((MODE) == TIM_OCMODE_Forced_Active ) || \ + ((MODE) == TIM_OCMode_PWM1 ) || \ + ((MODE) == TIM_OCMode_PWM2 ) || \ + ((MODE) == TIM_OCMode_Combined_PWM1 ) || \ + ((MODE) == TIM_OCMode_Combined_PWM2 ) || \ + ((MODE) == TIM_OCMode_Asymmetric_PWM1) || \ + ((MODE) == TIM_OCMode_Asymmetric_PWM2)) +#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing ) || \ + ((MODE) == TIM_OCMode_Active ) || \ + ((MODE) == TIM_OCMode_Inactive ) || \ + ((MODE) == TIM_OCMode_Toggle ) || \ + ((MODE) == TIM_OCMode_PWM1 ) || \ + ((MODE) == TIM_OCMode_PWM2 ) || \ + ((MODE) == TIM_ForcedAction_Active ) || \ + ((MODE) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_One_Pulse_Mode + * @{ + */ + +#define TIM_OPMode_Single TIM_CR1_OPM /*!< Counter stops counting at the next update event */ +#define TIM_OPMode_Repetitive 0x00000000U /*!< Counter is not stopped at update event */ +#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single ) || \ + ((MODE) == TIM_OPMode_Repetitive)) +/** + * @} + */ + +/** @defgroup TIM_Channel + * @{ + */ + +#define TIM_Channel_1 ((uint32_t)0x00000000) +#define TIM_Channel_2 ((uint32_t)0x00000004) +#define TIM_Channel_3 ((uint32_t)0x00000008) +#define TIM_Channel_4 ((uint32_t)0x0000000C) +#define TIM_Channel_5 ((uint32_t)0x00000010) +#define TIM_Channel_6 ((uint32_t)0x00000014) + +#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4) || \ + ((CHANNEL) == TIM_Channel_5) || \ + ((CHANNEL) == TIM_Channel_6)) + +#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3)) + +#define IS_TIM_2_TO_5_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2) || \ + ((CHANNEL) == TIM_Channel_3) || \ + ((CHANNEL) == TIM_Channel_4)) + +#define IS_TIM_9_AND_12_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \ + ((CHANNEL) == TIM_Channel_2)) + +#define IS_TIM_10_11_13_14_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1)) + +/** + * @} + */ + +/** @defgroup TIM_Clock_Division_CKD + * @{ + */ + +#define TIM_CKD_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ +#define TIM_CKD_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ +#define TIM_CKD_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ +#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \ + ((DIV) == TIM_CKD_DIV2) || \ + ((DIV) == TIM_CKD_DIV4)) +/** + * @} + */ + +/** @defgroup TIM_Counter_Mode + * @{ + */ + +#define TIM_CounterMode_Up 0x00000000U /*!< Counter used as up-counter */ +#define TIM_CounterMode_Down TIM_CR1_DIR /*!< Counter used as down-counter */ +#define TIM_CounterMode_CenterAligned1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ +#define TIM_CounterMode_CenterAligned2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ +#define TIM_CounterMode_CenterAligned3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ +#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up ) || \ + ((MODE) == TIM_CounterMode_Down ) || \ + ((MODE) == TIM_CounterMode_CenterAligned1) || \ + ((MODE) == TIM_CounterMode_CenterAligned2) || \ + ((MODE) == TIM_CounterMode_CenterAligned3) ) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Polarity + * @{ + */ + +#define TIM_OCPolarity_High 0x00000000U /*!< Capture/Compare 1 output Polarity */ +#define TIM_OCPolarity_Low TIM_CCER_CC1P /*!< Capture/Compare 1 output Polarity */ +#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \ + ((POLARITY) == TIM_OCPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Polarity + * @{ + */ + +#define TIM_OCNPolarity_High 0x00000000U /*!< Capture/Compare complementary output polarity */ +#define TIM_OCNPolarity_Low TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ +#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \ + ((POLARITY) == TIM_OCNPolarity_Low)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_state + * @{ + */ + +#define TIM_OutputState_Disable 0x00000000U /*!< Capture/Compare 1 output disable */ +#define TIM_OutputState_Enable TIM_CCER_CC1E /*!< Capture/Compare 1 output enable */ +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \ + ((STATE) == TIM_OutputState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_state + * @{ + */ + +#define TIM_OutputNState_Disable 0x00000000U /*!< Capture/Compare 1 Complementary output disable */ +#define TIM_OutputNState_Enable TIM_CCER_CC1NE /*!< Capture/Compare 1 Complementary output enable */ +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \ + ((STATE) == TIM_OutputNState_Enable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_state + * @{ + */ + +#define TIM_CCx_Disable 0x00000000U /*!< Capture/Compare 1 output disable */ +#define TIM_CCx_Enable TIM_CCER_CC1E /*!< Capture/Compare 1 output enable */ +#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable ) || \ + ((CCX) == TIM_CCx_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Capture_Compare_N_state + * @{ + */ + +#define TIM_CCxN_Disable 0x00000000U /*!< Capture/Compare 1 Complementary output disable */ +#define TIM_CCxN_Enable TIM_CCER_CC1NE /*!< Capture/Compare 1 Complementary output enable */ +#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable ) || \ + ((CCXN) == TIM_CCxN_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_enable_disable + * @{ + */ + +#define TIM_Break_Enable TIM_BDTR_BKE /*!< Break input BRK is enabled */ +#define TIM_Break_Disable 0x00000000U /*!< Break input BRK is disabled */ +#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable ) || \ + ((STATE) == TIM_Break_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Break_Polarity + * @{ + */ + +#define TIM_BreakPolarity_Low 0x00000000U /*!< Break input BRK is active low */ +#define TIM_BreakPolarity_High TIM_BDTR_BKP /*!< Break input BRK is active high */ +#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low ) || \ + ((POLARITY) == TIM_BreakPolarity_High)) +/** + * @} + */ + +/** @defgroup TIM_Break_Input_Bidirectional_Mode TIM Break Input Bidirectional Function Mode + * @{ + */ + +#define TIM_Break_Bid_MODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ +#define TIM_Break_Bid_MODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ +#define IS_TIM_BREAK_BID_MODE(MODE) ((MODE == TIM_Break_Bid_MODE_INPUT ) || \ + (MODE == TIM_Break_Bid_MODE_BIDIRECTIONAL)) + +/** + * @} + */ + +/** @defgroup TIM_AOE_Bit_Set_Reset + * @{ + */ + +#define TIM_AutomaticOutput_Enable TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event + (if none of the break inputs BRK is active) */ +#define TIM_AutomaticOutput_Disable 0x00000000U /*!< MOE can be set only by software */ +#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable ) || \ + ((STATE) == TIM_AutomaticOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_MOE_Bit_Set_Reset + * @{ + */ + +#define TIM_ControlPWMOutput_Enable TIM_BDTR_MOE /*!< Enable TIM main output */ +#define TIM_ControlPWMOutput_Disable 0x00000000U /*!< Disable TIM main output */ +#define IS_TIM_CONTROL_PWM_OUTPUT_STATE(STATE) (((STATE) == TIM_ControlPWMOutput_Enable ) || \ + ((STATE) == TIM_ControlPWMOutput_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Lock_level + * @{ + */ + +#define TIM_LOCKLevel_OFF 0x00000000U /*!< LOCK OFF */ +#define TIM_LOCKLevel_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ +#define TIM_LOCKLevel_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ +#define TIM_LOCKLevel_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ +#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \ + ((LEVEL) == TIM_LOCKLevel_1 ) || \ + ((LEVEL) == TIM_LOCKLevel_2 ) || \ + ((LEVEL) == TIM_LOCKLevel_3 )) +/** + * @} + */ + +/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state + * @{ + */ + +#define TIM_OSSIState_Enable TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSIState_Disable 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable ) || \ + ((STATE) == TIM_OSSIState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state + * @{ + */ + +#define TIM_OSSRState_Enable TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ +#define TIM_OSSRState_Disable 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ +#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable ) || \ + ((STATE) == TIM_OSSRState_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Idle_State + * @{ + */ + +#define TIM_OCIdleState_Set TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ +#define TIM_OCIdleState_Reset 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ +#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set ) || \ + ((STATE) == TIM_OCIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_N_Idle_State + * @{ + */ + +#define TIM_OCNIdleState_Set TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ +#define TIM_OCNIdleState_Reset 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ +#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set ) || \ + ((STATE) == TIM_OCNIdleState_Reset)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Polarity + * @{ + */ + +#define TIM_ICPolarity_Rising 0x00000000U /*!< Polarity for TIx source */ +#define TIM_ICPolarity_Falling TIM_CCER_CC1P /*!< Polarity for TIx source */ +#define TIM_ICPolarity_BothEdge (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ +#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising ) || \ + ((POLARITY) == TIM_ICPolarity_Falling ) || \ + ((POLARITY) == TIM_ICPolarity_BothEdge)) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Selection + * @{ + */ + +#define TIM_ICSelection_DirectTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively. */ +#define TIM_ICSelection_IndirectTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ +#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI ) || \ + ((SELECTION) == TIM_ICSelection_IndirectTI) || \ + ((SELECTION) == TIM_ICSelection_TRC )) +/** + * @} + */ + +/** @defgroup TIM_Input_Capture_Prescaler + * @{ + */ + +#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ +#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ +#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ +#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ +#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ + ((PRESCALER) == TIM_ICPSC_DIV2) || \ + ((PRESCALER) == TIM_ICPSC_DIV4) || \ + ((PRESCALER) == TIM_ICPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3 + * @{ + */ +#define TIM_GroupCH5_None 0x00000000U /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ +#define TIM_GroupCH5_OC1Refc TIM_CCR5_GC5C1 /* !< OC1REFC is the logical AND of OC1REFC and OC5REF */ +#define TIM_GroupCH5_OC2Refc TIM_CCR5_GC5C2 /* !< OC2REFC is the logical AND of OC2REFC and OC5REF */ +#define TIM_GroupCH5_OC3Refc TIM_CCR5_GC5C3 /* !< OC3REFC is the logical AND of OC3REFC and OC5REF */ +#define IS_TIM_GROUPCH5(OCREF) (((OCREF) == TIM_GroupCH5_None) || \ + ((OCREF) == TIM_CCR5_GC5C1 ) || \ + ((OCREF) == TIM_CCR5_GC5C2 ) || \ + ((OCREF) == TIM_CCR5_GC5C3 )) +/** + * @} + */ + +/** @defgroup TIM_interrupt_sources + * @{ + */ + +#define TIM_IT_Update TIM_DIER_UIE /*!< Update interrupt */ +#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ +#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ +#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ +#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ +#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ +#define TIM_IT_Trigger TIM_DIER_TIE /*!< Trigger interrupt */ +#define TIM_IT_Break TIM_DIER_BIE /*!< Break interrupt */ +#define IS_TIM_IT(IT) ((((IT) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update ) || \ + ((IT) == TIM_IT_CC1 ) || \ + ((IT) == TIM_IT_CC2 ) || \ + ((IT) == TIM_IT_CC3 ) || \ + ((IT) == TIM_IT_CC4 ) || \ + ((IT) == TIM_IT_COM ) || \ + ((IT) == TIM_IT_Trigger) || \ + ((IT) == TIM_IT_Break )) + +/** + * @} + */ + +/** @defgroup TIM_DMA_Base_address + * @{ + */ + +#define TIM_DMABase_CR1 ((uint32_t)0x00000000) +#define TIM_DMABase_CR2 ((uint32_t)0x00000001) +#define TIM_DMABase_SMCR ((uint32_t)0x00000002) +#define TIM_DMABase_DIER ((uint32_t)0x00000003) +#define TIM_DMABase_SR ((uint32_t)0x00000004) +#define TIM_DMABase_EGR ((uint32_t)0x00000005) +#define TIM_DMABase_CCMR1 ((uint32_t)0x00000006) +#define TIM_DMABase_CCMR2 ((uint32_t)0x00000007) +#define TIM_DMABase_CCER ((uint32_t)0x00000008) +#define TIM_DMABase_CNT ((uint32_t)0x00000009) +#define TIM_DMABase_PSC ((uint32_t)0x0000000A) +#define TIM_DMABase_ARR ((uint32_t)0x0000000B) +#define TIM_DMABase_RCR ((uint32_t)0x0000000C) +#define TIM_DMABase_CCR1 ((uint32_t)0x0000000D) +#define TIM_DMABase_CCR2 ((uint32_t)0x0000000E) +#define TIM_DMABase_CCR3 ((uint32_t)0x0000000F) +#define TIM_DMABase_CCR4 ((uint32_t)0x00000010) +#define TIM_DMABase_BDTR ((uint32_t)0x00000011) +#define TIM_DMABase_DCR ((uint32_t)0x00000012) +#define TIM_DMABase_OR ((uint32_t)0x00000014) +#define TIM_DMABase_CCMR3 ((uint32_t)0x00000015) +#define TIM_DMABase_CCR5 ((uint32_t)0x00000016) +#define TIM_DMABase_CCR6 ((uint32_t)0x00000017) +#define TIM_DMABase_AF1 ((uint32_t)0x00000018) +#define TIM_DMABase_AF2 ((uint32_t)0x00000019) +#define TIM_DMABase_TISEL ((uint32_t)0x0000001A) +#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1 ) || \ + ((BASE) == TIM_DMABase_CR2 ) || \ + ((BASE) == TIM_DMABase_SMCR ) || \ + ((BASE) == TIM_DMABase_DIER ) || \ + ((BASE) == TIM_DMABase_SR ) || \ + ((BASE) == TIM_DMABase_EGR ) || \ + ((BASE) == TIM_DMABase_CCMR1) || \ + ((BASE) == TIM_DMABase_CCMR2) || \ + ((BASE) == TIM_DMABase_CCER ) || \ + ((BASE) == TIM_DMABase_CNT ) || \ + ((BASE) == TIM_DMABase_PSC ) || \ + ((BASE) == TIM_DMABase_ARR ) || \ + ((BASE) == TIM_DMABase_RCR ) || \ + ((BASE) == TIM_DMABase_CCR1 ) || \ + ((BASE) == TIM_DMABase_CCR2 ) || \ + ((BASE) == TIM_DMABase_CCR3 ) || \ + ((BASE) == TIM_DMABase_CCR4 ) || \ + ((BASE) == TIM_DMABase_BDTR ) || \ + ((BASE) == TIM_DMABase_DCR ) || \ + ((BASE) == TIM_DMABase_OR ) || \ + ((BASE) == TIM_DMABase_CCMR3) || \ + ((BASE) == TIM_DMABase_CCR5 ) || \ + ((BASE) == TIM_DMABase_CCR6 ) || \ + ((BASE) == TIM_DMABase_AF1 ) || \ + ((BASE) == TIM_DMABase_AF2 ) || \ + ((BASE) == TIM_DMABase_TISEL)) +/** + * @} + */ + + +/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length + * @{ + */ + +#define TIM_DMABurstLength_1Transfer 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_2Transfers 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_3Transfers 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_4Transfers 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_5Transfers 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_6Transfers 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_7Transfers 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_8Transfers 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_9Transfers 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_10Transfers 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_11Transfers 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_12Transfers 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_13Transfers 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_14Transfers 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_15Transfers 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_16Transfers 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_17Transfers 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define TIM_DMABurstLength_18Transfers 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ +#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer ) || \ + ((LENGTH) == TIM_DMABurstLength_2Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_3Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_4Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_5Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_6Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_7Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_8Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_9Transfers ) || \ + ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ + ((LENGTH) == TIM_DMABurstLength_18Transfers)) +/** + * @} + */ + +/** @defgroup TIM_DMA_sources + * @{ + */ + +#define TIM_DMA_Update TIM_DIER_UDE /*!< DMA request is triggered by the update event */ +#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ +#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ +#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ +#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ +#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ +#define TIM_DMA_Trigger TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ +#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint32_t)0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000)) + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Prescaler + * @{ + */ + +#define TIM_ExtTRGPSC_OFF 0x00000000U /*!< No prescaler is used */ +#define TIM_ExtTRGPSC_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ +#define TIM_ExtTRGPSC_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ +#define TIM_ExtTRGPSC_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ +#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF ) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \ + ((PRESCALER) == TIM_ExtTRGPSC_DIV8)) +/** + * @} + */ + +/** @defgroup TIM_Internal_Trigger_Selection + * @{ + */ + +#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ +#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ +#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ +#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ +#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ +#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TS_ETRF TIM_SMCR_TS /*!< Filtered External Trigger input (ETRF) */ +#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0 ) || \ + ((SELECTION) == TIM_TS_ITR1 ) || \ + ((SELECTION) == TIM_TS_ITR2 ) || \ + ((SELECTION) == TIM_TS_ITR3 ) || \ + ((SELECTION) == TIM_TS_TI1F_ED) || \ + ((SELECTION) == TIM_TS_TI1FP1 ) || \ + ((SELECTION) == TIM_TS_TI2FP2 ) || \ + ((SELECTION) == TIM_TS_ETRF )) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) +/** + * @} + */ + +/** @defgroup TIM_TIx_External_Clock_Source + * @{ + */ + +#define TIM_TIxExternalCLK1Source_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ +#define TIM_TIxExternalCLK1Source_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ +#define TIM_TIxExternalCLK1Source_TI1ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ + +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Polarity + * @{ + */ +#define TIM_ExtTRGPolarity_Inverted TIM_SMCR_ETP /*!< Polarity for ETR source */ +#define TIM_ExtTRGPolarity_NonInverted 0x00000000U /*!< Polarity for ETR source */ +#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted ) || \ + ((POLARITY) == TIM_ExtTRGPolarity_NonInverted)) +/** + * @} + */ + +/** @defgroup TIM_Prescaler_Reload_Mode + * @{ + */ + +#define TIM_PSCReloadMode_Update 0x00000000U /*!< Prescaler reload PSC register value at update event */ +#define TIM_PSCReloadMode_Immediate TIM_EGR_UG /*!< Prescaler reload PSC register value at immediate */ +#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update ) || \ + ((RELOAD) == TIM_PSCReloadMode_Immediate)) +/** + * @} + */ + +/** @defgroup TIM_Forced_Action + * @{ + */ + +#define TIM_ForcedAction_Active (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ +#define TIM_ForcedAction_InActive TIM_CCMR1_OC1M_2 /*!< Force inactive level */ +#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active ) || \ + ((ACTION) == TIM_ForcedAction_InActive)) +/** + * @} + */ + +/** @defgroup TIM_Encoder_Mode + * @{ + */ + +#define TIM_EncoderMode_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, counts up/down on TI2FP2 edge depending on TI1FP1 level */ +#define TIM_EncoderMode_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, counts up/down on TI1FP1 edge depending on TI2FP2 level */ +#define TIM_EncoderMode_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ +#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1 ) || \ + ((MODE) == TIM_EncoderMode_TI2 ) || \ + ((MODE) == TIM_EncoderMode_TI12)) +/** + * @} + */ + + +/** @defgroup TIM_Event_Source + * @{ + */ + +#define TIM_EventSource_Update TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ +#define TIM_EventSource_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ +#define TIM_EventSource_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ +#define TIM_EventSource_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ +#define TIM_EventSource_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ +#define TIM_EventSource_COM TIM_EGR_COMG /*!< A commutation event is generated */ +#define TIM_EventSource_Trigger TIM_EGR_TG /*!< A trigger event is generated */ +#define TIM_EventSource_Break TIM_EGR_BG /*!< A break event is generated */ +#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint32_t)0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000)) + +/** + * @} + */ + +/** @defgroup TIM_Update_Source + * @{ + */ + +#define TIM_UpdateSource_Global 0x00000000U /*!< Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular 0x00000001U /*!< Source of update is counter overflow/underflow. */ +#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global ) || \ + ((SOURCE) == TIM_UpdateSource_Regular)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Preload_State + * @{ + */ + +#define TIM_OCPreload_Enable TIM_CCMR1_OC1PE /*!< Preload register on TIMx_CCR1 enabled */ +#define TIM_OCPreload_Disable 0x00000000U /*!< Preload register on TIMx_CCR1 disabled */ +#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable ) || \ + ((STATE) == TIM_OCPreload_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Fast_State + * @{ + */ + +#define TIM_OCFast_Enable TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ +#define TIM_OCFast_Disable 0x00000000U /*!< Output Compare fast disable */ +#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable ) || \ + ((STATE) == TIM_OCFast_Disable)) + +/** + * @} + */ + +/** @defgroup TIM_Output_Compare_Clear_State + * @{ + */ + +#define TIM_OCClear_Enable TIM_CCMR1_OC1CE /*!< OC1REF is cleared as soon as a high level is dected on OCREF_CLR_INPUT signal */ +#define TIM_OCClear_Disable 0x00000000U /*!< OC1REF is not effected by the OCREF_CLR_INPUT signal */ +#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable ) || \ + ((STATE) == TIM_OCClear_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Trigger_Output_Source (TRGO) + * @{ + */ + +#define TIM_TRGOSource_Reset 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ +#define TIM_TRGOSource_Enable TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ +#define TIM_TRGOSource_Update TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ +#define TIM_TRGOSource_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ +#define TIM_TRGOSource_OC1Ref TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ +#define TIM_TRGOSource_OC2Ref (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ +#define TIM_TRGOSource_OC3Ref (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ +#define TIM_TRGOSource_OC4Ref (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ +#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset ) || \ + ((SOURCE) == TIM_TRGOSource_Enable) || \ + ((SOURCE) == TIM_TRGOSource_Update) || \ + ((SOURCE) == TIM_TRGOSource_OC1 ) || \ + ((SOURCE) == TIM_TRGOSource_OC1Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC2Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC3Ref) || \ + ((SOURCE) == TIM_TRGOSource_OC4Ref)) +/** + * @} + */ + +/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) + * @{ + */ + +#define TIM_TRGO2Source_Reset 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_Enable TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_Update TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC1Ref TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC2Ref (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC3Ref (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC4Ref (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC5Ref TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC6Ref (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ +#define TIM_TRGO2Source_OC4Ref_RisingFalling (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2Source_OC6Ref_RisingFalling (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2Source_OC4Ref_Rising_OC6Ref_Rising (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2Source_OC4Ref_Rising_OC6Ref_Falling (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ +#define TIM_TRGO2Source_OC5Ref_Rising_OC6Ref_Rising (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define TIM_TRGO2Source_OC5Ref_Rising_OC6Ref_Falling (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ +#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset ) || \ + ((SOURCE) == TIM_TRGO2Source_Enable ) || \ + ((SOURCE) == TIM_TRGO2Source_Update ) || \ + ((SOURCE) == TIM_TRGO2Source_OC1 ) || \ + ((SOURCE) == TIM_TRGO2Source_OC1Ref ) || \ + ((SOURCE) == TIM_TRGO2Source_OC2Ref ) || \ + ((SOURCE) == TIM_TRGO2Source_OC3Ref ) || \ + ((SOURCE) == TIM_TRGO2Source_OC4Ref ) || \ + ((SOURCE) == TIM_TRGO2Source_OC5Ref ) || \ + ((SOURCE) == TIM_TRGO2Source_OC6Ref ) || \ + ((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling ) || \ + ((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling ) || \ + ((SOURCE) == TIM_TRGO2Source_OC4Ref_Rising_OC6Ref_Rising ) || \ + ((SOURCE) == TIM_TRGO2Source_OC4Ref_Rising_OC6Ref_Falling) || \ + ((SOURCE) == TIM_TRGO2Source_OC5Ref_Rising_OC6Ref_Rising ) || \ + ((SOURCE) == TIM_TRGO2Source_OC5Ref_Rising_OC6Ref_Falling)) + +/** + * @} + */ + +/** @defgroup TIM_Slave_Mode + * @{ + */ + +#define TIM_SlaveMode_Disable 0x00000000U /*!< Slave mode disabled */ +#define TIM_SlaveMode_Reset TIM_SMCR_SMS_2 /*!< Reset Mode */ +#define TIM_SlaveMode_Gated (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ +#define TIM_SlaveMode_Trigger (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ +#define TIM_SlaveMode_External1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ +#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Disable ) || \ + ((MODE) == TIM_SlaveMode_Reset ) || \ + ((MODE) == TIM_SlaveMode_Gated ) || \ + ((MODE) == TIM_SlaveMode_Trigger ) || \ + ((MODE) == TIM_SlaveMode_External1)) +/** + * @} + */ + +/** @defgroup TIM_Master_Slave_Mode + * @{ + */ + +#define TIM_MasterSlaveMode_Enable TIM_SMCR_MSM /*!< Master/slave mode is selected */ +#define TIM_MasterSlaveMode_Disable 0x00000000U /*!< No action */ +#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable ) || \ + ((STATE) == TIM_MasterSlaveMode_Disable)) +/** + * @} + */ + +/** @defgroup TIM_Flags + * @{ + */ + +#define TIM_FLAG_Update TIM_SR_UIF /*!< Update interrupt flag */ +#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ +#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ +#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ +#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ +#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ +#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ +#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ +#define TIM_FLAG_Trigger TIM_SR_TIF /*!< Trigger interrupt flag */ +#define TIM_FLAG_Break TIM_SR_BIF /*!< Break interrupt flag */ +#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ +#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ +#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ +#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ +#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update ) || \ + ((FLAG) == TIM_FLAG_CC1 ) || \ + ((FLAG) == TIM_FLAG_CC2 ) || \ + ((FLAG) == TIM_FLAG_CC3 ) || \ + ((FLAG) == TIM_FLAG_CC4 ) || \ + ((FLAG) == TIM_FLAG_CC5 ) || \ + ((FLAG) == TIM_FLAG_CC6 ) || \ + ((FLAG) == TIM_FLAG_COM ) || \ + ((FLAG) == TIM_FLAG_Trigger) || \ + ((FLAG) == TIM_FLAG_Break ) || \ + ((FLAG) == TIM_FLAG_CC1OF ) || \ + ((FLAG) == TIM_FLAG_CC2OF ) || \ + ((FLAG) == TIM_FLAG_CC3OF ) || \ + ((FLAG) == TIM_FLAG_CC4OF )) + + +#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xFFFCE100) == 0x00000000) && ((TIM_FLAG) != 0x00000000)) +/** + * @} + */ + + +/** @defgroup TIM_Input_Capture_Filer_Value + * @{ + */ + +#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_External_Trigger_Filter + * @{ + */ + +#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF) +/** + * @} + */ + +/** @defgroup TIM_DeadTime Filter + * @{ + */ + +#define IS_TIM_DEADTIME(DEADTIME) ((DEADTIME) <= 0xFFU) +/** + * @} + */ + +/** @defgroup TIM_BreakFilter + * @{ + */ + +#define IS_TIM_BREAK_FILTER(BRKFILTER) ((BRKFILTER) <= 0xFUL) +/** + * @} + */ + +/** @defgroup TIM_OCReferenceClear + * @{ + */ +#define TIM_OCReferenceClear_ETRF TIM_SMCR_OCCS /*!< OCREF clear select ETRF */ +#define TIM_OCReferenceClear_OCREFCLR 0x00000000U /*!< OCREF clear select OCREF_CLR int input signals */ +#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF ) || \ + ((SOURCE) == TIM_OCReferenceClear_OCREFCLR)) + +/** + * @} + */ +/** @defgroup TIM_Remap + * @{ + */ +#define TIM2_ITR1ConnectTIM8Trgo ((uint32_t)0x00000000) /*!< TIM8 TRGO is connected to TIM2_ITR1 input */ +#define TIM2_ITR1ConnectPTPTrgo ((uint32_t)0x00000001) /*!< PTP TRGO is connected to TIM2_ITR1 input */ +#define TIM2_ITR1ConnectOTGFSSOF ((uint32_t)0x00000002) /*!< OTG FS SOF is connected to TIM2_ITR1 input */ +#define TIM2_ITR1ConnectOTGHSSOF ((uint32_t)0x00000003) /*!< OTG HS SOF is connected to TIM2_ITR1 input */ + +#define TIM11_IT1ConnectGPIO_0 ((uint32_t)0x00000000) /*!< TIM11 GPIO is connected to TIM11_TI1 input */ +#define TIM11_IT1ConnectGPIO_1 ((uint32_t)0x00000001) /*!< TIM11 GPIO is connected to TIM11_TI1 input */ +#define TIM11_IT1ConnectHSE_RTC ((uint32_t)0x00000002) /*!< HSE RTC clock is connected to TIM11_TI1 input */ +#define TIM11_IT1ConnectGPIO_3 ((uint32_t)0x00000003) /*!< TIM11 GPIO is connected to TIM11_TI1 input */ + +#define IS_TIM2_ITR1REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_ITR1ConnectTIM8Trgo) || \ + ((TIM_REMAP) == TIM2_ITR1ConnectPTPTrgo ) || \ + ((TIM_REMAP) == TIM2_ITR1ConnectOTGFSSOF) || \ + ((TIM_REMAP) == TIM2_ITR1ConnectOTGHSSOF)) + +#define IS_TIM11_ITR1REMAP(TIM_REMAP) (((TIM_REMAP) == TIM11_IT1ConnectGPIO_0 ) || \ + ((TIM_REMAP) == TIM11_IT1ConnectGPIO_1 ) || \ + ((TIM_REMAP) == TIM11_IT1ConnectHSE_RTC) || \ + ((TIM_REMAP) == TIM11_IT1ConnectGPIO_3 )) +/** + * @} + */ + +/** @defgroup TIM_ETRSel_Remap + * @{ + */ + +#define TIM_ETR_GPIO 0x00000000U /* !< ETR input is connected to GPIO */ +#define TIM_ETR_COMP1 TIM_AF1_ETRSEL_0 /* !< ETR input is connected to COMP1_OUT */ +#define TIM_ETR_COMP2 TIM_AF1_ETRSEL_1 /* !< ETR input is connected to COMP2_OUT */ +#define TIM_ETR_COMP3 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to COMP3_OUT */ +#define TIM_ETR_COMP4 TIM_AF1_ETRSEL_2 /* !< ETR input is connected to COMP4_OUT */ +#define TIM_ETR_COMP5 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to COMP5_OUT */ +#define TIM_ETR_COMP6 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /* !< ETR input is connected to COMP6_OUT */ +#define TIM_ETR_ADC1_AWD1 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ADC1 analog watchdog 1 */ +#define TIM_ETR_ADC1_AWD2 TIM_AF1_ETRSEL_3 /* !< ETR input is connected to ADC1 analog watchdog 2 */ +#define TIM_ETR_ADC1_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ADC1 analog watchdog 3 */ +#define TIM_ETR_ADC2_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /* !< ETR input is connected to ADC2 analog watchdog 1 */ +#define TIM_ETR_ADC2_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ADC2 analog watchdog 2 */ +#define TIM_ETR_ADC2_AWD3 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /* !< ETR input is connected to ADC2 analog watchdog 3 */ +#define TIM_ETR_ADC3_AWD1 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ADC3 analog watchdog 1 */ +#define TIM_ETR_ADC3_AWD2 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /* !< ETR input is connected to ADC3 analog watchdog 2 */ +#define TIM_ETR_ADC3_AWD3 TIM_AF1_ETRSEL /* !< ETR input is connected to ADC3 analog watchdog 3 */ +#define IS_TIM_ETRSEL_LIST1_REMAP(REMAP) (((REMAP) == TIM_ETR_GPIO ) || \ + ((REMAP) == TIM_ETR_COMP1 ) || \ + ((REMAP) == TIM_ETR_COMP2 ) || \ + ((REMAP) == TIM_ETR_COMP3 ) || \ + ((REMAP) == TIM_ETR_COMP4 ) || \ + ((REMAP) == TIM_ETR_COMP5 ) || \ + ((REMAP) == TIM_ETR_COMP6 ) || \ + ((REMAP) == TIM_ETR_ADC1_AWD1) || \ + ((REMAP) == TIM_ETR_ADC1_AWD2) || \ + ((REMAP) == TIM_ETR_ADC1_AWD3) || \ + ((REMAP) == TIM_ETR_ADC2_AWD1) || \ + ((REMAP) == TIM_ETR_ADC2_AWD2) || \ + ((REMAP) == TIM_ETR_ADC2_AWD3) || \ + ((REMAP) == TIM_ETR_ADC3_AWD1) || \ + ((REMAP) == TIM_ETR_ADC3_AWD2) || \ + ((REMAP) == TIM_ETR_ADC3_AWD3)) + +#define TIM_ETR_1 TIM_AF1_ETRSEL_0 /* !< ETR input is connected to ETR[ 1] */ +#define TIM_ETR_2 TIM_AF1_ETRSEL_1 /* !< ETR input is connected to ETR[ 2] */ +#define TIM_ETR_3 (TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ETR[ 3] */ +#define TIM_ETR_4 TIM_AF1_ETRSEL_2 /* !< ETR input is connected to ETR[ 4] */ +#define TIM_ETR_5 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ETR[ 5] */ +#define TIM_ETR_6 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /* !< ETR input is connected to ETR[ 6] */ +#define TIM_ETR_7 (TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ETR[ 7] */ +#define TIM_ETR_8 TIM_AF1_ETRSEL_3 /* !< ETR input is connected to ETR[ 8] */ +#define TIM_ETR_9 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ETR[ 9] */ +#define TIM_ETR_10 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1) /* !< ETR input is connected to ETR[10] */ +#define TIM_ETR_11 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_1 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ETR[11] */ +#define TIM_ETR_12 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2) /* !< ETR input is connected to ETR[12] */ +#define TIM_ETR_13 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_0) /* !< ETR input is connected to ETR[13] */ +#define TIM_ETR_14 (TIM_AF1_ETRSEL_3 | TIM_AF1_ETRSEL_2 | TIM_AF1_ETRSEL_1) /* !< ETR input is connected to ETR[14] */ +#define TIM_ETR_15 TIM_AF1_ETRSEL /* !< ETR input is connected to ETR[15] */ +#define IS_TIM_ETRSEL_LIST2_REMAP(REMAP) (((REMAP) == TIM_ETR_GPIO) || \ + ((REMAP) == TIM_ETR_1 ) || \ + ((REMAP) == TIM_ETR_2 ) || \ + ((REMAP) == TIM_ETR_3 ) || \ + ((REMAP) == TIM_ETR_4 ) || \ + ((REMAP) == TIM_ETR_5 ) || \ + ((REMAP) == TIM_ETR_6 ) || \ + ((REMAP) == TIM_ETR_7 ) || \ + ((REMAP) == TIM_ETR_8 ) || \ + ((REMAP) == TIM_ETR_9 ) || \ + ((REMAP) == TIM_ETR_10 ) || \ + ((REMAP) == TIM_ETR_11 ) || \ + ((REMAP) == TIM_ETR_12 ) || \ + ((REMAP) == TIM_ETR_13 ) || \ + ((REMAP) == TIM_ETR_14 ) || \ + ((REMAP) == TIM_ETR_15 )) + +/** + * @} + */ + +/** @defgroup TIM_OCRSel_Remap + * @{ + */ + +#define TIM_OCR_COMP1 (uint32_t)0x00000000 /* !< OCxref clear source select COMP1_OUT */ +#define TIM_OCR_COMP2 (uint32_t)0x00000001 /* !< OCxref clear source select COMP2_OUT */ +#define TIM_OCR_COMP3 (uint32_t)0x00000002 /* !< OCxref clear source select COMP3_OUT */ +#define TIM_OCR_COMP4 (uint32_t)0x00000003 /* !< OCxref clear source select COMP4_OUT */ +#define TIM_OCR_COMP5 (uint32_t)0x00000004 /* !< OCxref clear source select COMP5_OUT */ +#define TIM_OCR_COMP6 (uint32_t)0x00000005 /* !< OCxref clear source select COMP6_OUT */ +#define IS_TIM_OCRSEL_LIST1_REMAP(REMAP) (((REMAP) == TIM_OCR_COMP1) || \ + ((REMAP) == TIM_OCR_COMP2) || \ + ((REMAP) == TIM_OCR_COMP3) || \ + ((REMAP) == TIM_OCR_COMP4) || \ + ((REMAP) == TIM_OCR_COMP5) || \ + ((REMAP) == TIM_OCR_COMP6)) + +#define TIM_OCR_CLEAR_0 0x00000000U /* !< OCxref clear source select ocrefcr[0] */ +#define TIM_OCR_CLEAR_1 TIM_AF2_OCRSEL_0 /* !< OCxref clear source select ocrefcr[1] */ +#define TIM_OCR_CLEAR_2 TIM_AF2_OCRSEL_1 /* !< OCxref clear source select ocrefcr[2] */ +#define TIM_OCR_CLEAR_3 (TIM_AF2_OCRSEL_1 | TIM_AF2_OCRSEL_0) /* !< OCxref clear source select ocrefcr[3] */ +#define TIM_OCR_CLEAR_4 TIM_AF2_OCRSEL_2 /* !< OCxref clear source select ocrefcr[4] */ +#define TIM_OCR_CLEAR_5 (TIM_AF2_OCRSEL_2 | TIM_AF2_OCRSEL_0) /* !< OCxref clear source select ocrefcr[5] */ +#define TIM_OCR_CLEAR_6 (TIM_AF2_OCRSEL_2 | TIM_AF2_OCRSEL_1) /* !< OCxref clear source select ocrefcr[6] */ +#define TIM_OCR_CLEAR_7 TIM_AF2_OCRSEL /* !< OCxref clear source select ocrefcr[7] */ +#define IS_TIM_OCRSEL_LIST2_REMAP(REMAP) (((REMAP) == TIM_OCR_CLEAR_0) || \ + ((REMAP) == TIM_OCR_CLEAR_1) || \ + ((REMAP) == TIM_OCR_CLEAR_2) || \ + ((REMAP) == TIM_OCR_CLEAR_3) || \ + ((REMAP) == TIM_OCR_CLEAR_4) || \ + ((REMAP) == TIM_OCR_CLEAR_5) || \ + ((REMAP) == TIM_OCR_CLEAR_6) || \ + ((REMAP) == TIM_OCR_CLEAR_7)) + + +/** + * @} + */ + +/** @defgroup TIM_TISel_Remap + * @{ + */ + +#define TIM_TI1_CH1 0x00000000U /* !< TIM_CH1 input select GPIO */ +#define TIM_TI1_COMP1 TIM_TISEL_TI1SEL_0 /* !< TIM_CH1 input select COMP1_OUT */ +#define TIM_TI1_COMP2 TIM_TISEL_TI1SEL_1 /* !< TIM_CH1 input select COMP2_OUT */ +#define TIM_TI1_COMP3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /* !< TIM_CH1 input select COMP3_OUT */ +#define TIM_TI1_COMP4 TIM_TISEL_TI1SEL_2 /* !< TIM_CH1 input select COMP4_OUT */ +#define TIM_TI1_COMP5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM_CH1 input select COMP5_OUT */ +#define TIM_TI1_COMP6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM_CH1 input select COMP6_OUT */ +#define IS_TIM_TISEL_LIST1_REMAP(REMAP) (((REMAP) == TIM_TI1_CH1 ) || \ + ((REMAP) == TIM_TI1_COMP1) || \ + ((REMAP) == TIM_TI1_COMP2) || \ + ((REMAP) == TIM_TI1_COMP3) || \ + ((REMAP) == TIM_TI1_COMP4) || \ + ((REMAP) == TIM_TI1_COMP5) || \ + ((REMAP) == TIM_TI1_COMP6)) + +#define TIM_TI_CH 0x00000000U /* !< TIM_CH input select GPIO */ +#define TIM_TI_I1 TIM_TISEL_TI1SEL_0 /* !< TIM_CH input select ti_i[ 1] */ +#define TIM_TI_I2 TIM_TISEL_TI1SEL_1 /* !< TIM_CH input select ti_i[ 2] */ +#define TIM_TI_I3 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0 ) /* !< TIM_CH input select ti_i[ 3] */ +#define TIM_TI_I4 TIM_TISEL_TI1SEL_2 /* !< TIM_CH input select ti_i[ 4] */ +#define TIM_TI_I5 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0 ) /* !< TIM_CH input select ti_i[ 5] */ +#define TIM_TI_I6 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 ) /* !< TIM_CH input select ti_i[ 6] */ +#define TIM_TI_I7 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /* !< TIM_CH input select ti_i[ 7] */ +#define TIM_TI_I8 TIM_TISEL_TI1SEL_3 /* !< TIM_CH input select ti_i[ 8] */ +#define TIM_TI_I9 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0 ) /* !< TIM_CH input select ti_i[ 9] */ +#define TIM_TI_I10 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1 ) /* !< TIM_CH input select ti_i[10] */ +#define TIM_TI_I11 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /* !< TIM_CH input select ti_i[11] */ +#define TIM_TI_I12 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_2 ) /* !< TIM_CH input select ti_i[12] */ +#define TIM_TI_I13 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM_CH input select ti_i[13] */ +#define TIM_TI_I14 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM_CH input select ti_i[14] */ +#define TIM_TI_I15 TIM_TISEL_TI1SEL /* !< TIM_CH input select ti_i[15] */ +#define IS_TIM_TISEL_LIST2_REMAP(REMAP) (((REMAP) == TIM_TI_CH ) || \ + ((REMAP) == TIM_TI_I1 ) || \ + ((REMAP) == TIM_TI_I2 ) || \ + ((REMAP) == TIM_TI_I3 ) || \ + ((REMAP) == TIM_TI_I4 ) || \ + ((REMAP) == TIM_TI_I5 ) || \ + ((REMAP) == TIM_TI_I6 ) || \ + ((REMAP) == TIM_TI_I7 ) || \ + ((REMAP) == TIM_TI_I8 ) || \ + ((REMAP) == TIM_TI_I9 ) || \ + ((REMAP) == TIM_TI_I10) || \ + ((REMAP) == TIM_TI_I11) || \ + ((REMAP) == TIM_TI_I12) || \ + ((REMAP) == TIM_TI_I13) || \ + ((REMAP) == TIM_TI_I14) || \ + ((REMAP) == TIM_TI_I15)) + +/** + * @} + */ + +/** @defgroup TIM_TISel_Channel + * @{ + */ + +#define TIM_TISel_Channel1 (uint32_t)0x00000000 /* !< TIM_CH input select channel1 */ +#define TIM_TISel_Channel2 (uint32_t)0x00000008 /* !< TIM_CH input select channel2 */ +#define TIM_TISel_Channel3 (uint32_t)0x00000010 /* !< TIM_CH input select channel3 */ +#define TIM_TISel_Channel4 (uint32_t)0x00000018 /* !< TIM_CH input select channel4 */ + +/** + * @} + */ + +/** @defgroup TIM_Break_Input_Source TIM Extended Break input source + * @{ + */ + +#define TIM_BREAKINPUTSOURCE_BKIN TIM_AF_BKINE /* !< An external source (GPIO) is connected to the BKIN pin */ +#define TIM_BREAKINPUTSOURCE_COMP1 TIM_AF_BKCMP1E /* !< The COMP1 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP2 TIM_AF_BKCMP2E /* !< The COMP2 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP3 TIM_AF_BKCMP3E /* !< The COMP3 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP4 TIM_AF_BKCMP4E /* !< The COMP4 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP5 TIM_AF_BKCMP5E /* !< The COMP5 output is connected to the break input */ +#define TIM_BREAKINPUTSOURCE_COMP6 TIM_AF_BKCMP6E /* !< The COMP6 output is connected to the break input */ +#define IS_TIM_BREAKINPUTSOURCE(SOURCE) (((SOURCE) == TIM_BREAKINPUTSOURCE_BKIN ) || \ + ((SOURCE) == TIM_BREAKINPUTSOURCE_COMP1) || \ + ((SOURCE) == TIM_BREAKINPUTSOURCE_COMP2) || \ + ((SOURCE) == TIM_BREAKINPUTSOURCE_COMP3) || \ + ((SOURCE) == TIM_BREAKINPUTSOURCE_COMP4) || \ + ((SOURCE) == TIM_BREAKINPUTSOURCE_COMP5) || \ + ((SOURCE) == TIM_BREAKINPUTSOURCE_COMP6)) + +/** + * @} + */ + +/** @defgroup TIM_Break_Input_Source_Enable TIM Extended Break input source enabling + * @{ + */ + +#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /* !< Break input source is disabled */ +#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /* !< Break input source is enabled */ +#define IS_TIM_BREAKINPUTSOURCE_STATE(STATE) (((STATE) == TIM_BREAKINPUTSOURCE_DISABLE) || \ + ((STATE) == TIM_BREAKINPUTSOURCE_ENABLE )) + +/** + * @} + */ + +/** @defgroup TIM_Break_Input_Source_Polarity TIM Extended Break input polarity + * @{ + */ + +#define TIM_BREAKINPUTSOURCE_POLARITY_INVERTED 0x00000001U /* !< Break input source is inverted + (active high if BKP = 0, active low if BKP = 1) */ +#define TIM_BREAKINPUTSOURCE_POLARITY_NOT_INVERTED 0x00000000U /* !< Break input source is not inverted + (active low if BKP = 0, active high if BKP = 1) */ +#define IS_TIM_BREAKINPUTSOURCE_POLARITY(POLARITY) (((POLARITY) == TIM_BREAKINPUTSOURCE_POLARITY_INVERTED ) || \ + ((POLARITY) == TIM_BREAKINPUTSOURCE_POLARITY_NOT_INVERTED)) + +/** + * @} + */ + +/** @defgroup TIM_AF1 + * @{ + */ +#define TIM_AF_BKINE_Pos (0U) +#define TIM_AF_BKCMP1E_Pos (1U) +#define TIM_AF_BKCMP2E_Pos (2U) +#define TIM_AF_BKCMP3E_Pos (3U) +#define TIM_AF_BKCMP4E_Pos (4U) +#define TIM_AF_BKCMP5E_Pos (5U) +#define TIM_AF_BKCMP6E_Pos (6U) + +#define TIM_AF_BKINP_Pos (9U) +#define TIM_AF_BKCMP1P_Pos (10U) +#define TIM_AF_BKCMP2P_Pos (11U) +#define TIM_AF_BKCMP3P_Pos (12U) +#define TIM_AF_BKCMP4P_Pos (13U) + +/** + * @} + */ + +/** @defgroup TIM_Legacy + * @{ + */ + +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +/* TimeBase management ********************************************************/ +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint32_t TIM_CounterMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload); +void TIM_SetRepetitionCounter(TIM_TypeDef* TIMx, uint32_t RepetitionCounter); +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint32_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint32_t TIM_UpdateSource); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint32_t TIM_OPMode); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint32_t TIM_CKD); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Advanced-control timers (TIM1 and TIM8) specific features*******************/ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_ConfigBreakInput(TIM_TypeDef* TIMx, TIM_BreakInputConfigTypeDef* BreakInputConfig); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_DisarmBreakInput(TIM_TypeDef* TIMx); +FlagStatus TIM_WaitBkdsrmIsHardwareClear(TIM_TypeDef* TIMx); + +/* Output Compare management **************************************************/ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_GroupChannel5(TIM_TypeDef* TIMx, uint32_t TIM_Group_Channel5); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_OCMode); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4); +void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5); +void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); +void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); +void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); +void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); +void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); +void TIM_OC5FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); +void TIM_OC6FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear); +void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear); +void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); +void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); +void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity); +void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint32_t TIM_OCReferenceClear); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_CCxN); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Input Capture management ***************************************************/ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture5(TIM_TypeDef* TIMx); +uint32_t TIM_GetCapture6(TIM_TypeDef* TIMx); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC); + +/* Interrupts, DMA and flags management ***************************************/ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint32_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint32_t TIM_EventSource); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint32_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint32_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint32_t TIM_IT); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint32_t TIM_DMABase, uint32_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint32_t TIM_DMASource, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Clocks management **********************************************************/ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_TIxExternalCLKSource, + uint32_t TIM_ICPolarity, uint32_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); + + +/* Synchronization management *************************************************/ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_TRGOSource); +void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_MasterSlaveMode); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, + uint32_t ExtTRGFilter); + +/* Specific interface management **********************************************/ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint32_t TIM_EncoderMode, + uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); + +/* Specific remapping management **********************************************/ +/* For TIM2 & TIM11 OR register */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap); +/* For TIM1/TIM8 and TIM2-5 ETRSEL bits of AF1 register */ +void TIM_ETRSelRemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_ETRSel_Remap); +/* For TIM1/TIM8 and TIM2-5 AF2 register */ +void TIM_OCRSelRemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCRSel_Remap); +/* For TIM1/TIM8 and TIM2-5 TISEL register */ +void TIM_TISelRemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_TISel_Channel, uint32_t TIM_TISel_Remap); + + +#ifdef __cplusplus +} +#endif + +#endif /*__FT32F4XX_TIM_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_uart.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_uart.h new file mode 100644 index 00000000000..07348b0281c --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_uart.h @@ -0,0 +1,917 @@ +/** + * @file ft32f4xx_uart.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the UART + * fireware library. + * @version V1.0.0 + * @date 2025-03-28 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_UART_H +#define __FT32F4XX_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup ft32f4xx_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types SART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t UART_BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate is computed using the following formula: + - CD = 0: Disable baud rate clock + + - Asynchronous mode + - X16 : IntegerDivider = ((PCLKx) / (16 * (UART_InitStruct->UART_BaudRate))) + - X8 : IntegerDivider = ((PCLKx) / (8 * (UART_InitStruct->UART_BaudRate))) + */ + + uint32_t UART_FiDiRatio; /*!< Specifies the value of FI over DI ratio value in IrDA mode. + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_IrDAFilter; /*!< Specifies the value of IrDA filter in IrDA mode. + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UART_Char_Length & UART_Char_Length9*/ + + uint32_t UART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits*/ + + uint32_t UART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t UART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode*/ + + uint32_t UART_CLKSelect; /*!< Specifies the selection of clock. + This parameter can be a value of @ref UART_Clock_Select*/ + + uint32_t UART_OperationMode; /*!< Specifies the mode of operation. + This parameter can be a value of @ref UART_Mode_Operation*/ + + uint32_t UART_BitOrder; /*!< Specifies whether the Least or Most Significant Bit is sent/received first. + This parameter can be a value of @ref UART_BIT_ORDER*/ + + uint32_t UART_ChannelMode; /*!< Specifies the channel mode select. + this parameter can be a value of @ref UART_Channel_Mode*/ + + uint32_t UART_OverSampling; /*!< Specifies whether 16x oversampling or 8x oversampling. + This parameter can be a value of @ref UART_OverSampling*/ + + uint32_t UART_INVData; /*!< Specifies whether the data is inverted. + This parameter can be a value of @ref UART_InvertData + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_SYNCDisable; /*!< Specifies whether disable the synchronization in LIN mode. + This parameter can be a value of @ref UART_Sync_Disable + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_PDCMode; /*!< Specifies the DMA mode selection in LIN mode. + This parameter can be a value of @ref UART_PDC_Mode + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_DataLengthControl; /*!< Specifies define the response data length when DataLengthMode = 0 in LIN mode. + 0-255: the response data length is equal to DLC+1 bytes. + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_WkupType; /*!< Specifies whether the wakeup signal type is LIN2.0 wakup signal or LIN1.3 wakup signal. + This parameter can be a value of @ref UART_Wkup_Type + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_FrameSlotDisable; /*!< Specifies whether disable the frame slot mode in LIN mode. + This parameter can be a value of @ref UART_Frame_Slot_Disable + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_DataLengthMode; /*!< Specifies the data length mode in LIN mode. + This parameter can be a value of @ref UART_Data_Length_Mode + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_CheckSumType; /*!< Specifies the checksum type in LIN mode. + This parameter can be a value of @ref UART_Checksum_Type + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_CheckSumDisable; /*!< Specifies whether disable the checksum in LIN mode. + This parameter can be a value of @ref UART_Checksum_Disable + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_ParityDisable; /*!< Specifies whether disable the parity in LIN mode. + This parameter can be a value of @ref UART_Parity_Disable + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + + uint32_t UART_NodeAction; /*!< Specifies the LIN Node Active. + This parameter can be a value of @ref UART_Node_Active + @note This parameter is valid only for UART4, UART5 and UART7, except for LPUART.*/ + +} UART_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +#define IS_UART_ALL_PERIPH(PERIPH) ( \ + ((PERIPH) == UART4 ) || \ + ((PERIPH) == UART5 ) || \ + ((PERIPH) == UART7 ) || \ + ((PERIPH) == LPUART) \ + ) + +#define IS_UART_45_PERIPH(PERIPH) ( \ + ((PERIPH) == UART4 ) || \ + ((PERIPH) == UART5 ) \ + ) + +#define IS_UART_457_PERIPH(PERIPH) ( \ + ((PERIPH) == UART4 ) || \ + ((PERIPH) == UART5 ) || \ + ((PERIPH) == UART7 ) \ + ) + +#define IS_UART_LP_PERIPH(PERIPH) ( \ + ((PERIPH) == LPUART) \ + ) + +/** @defgroup UART_InvertData UART Invert Data + * @{ + */ +#define UART_INVDATA_DISABLE ((uint32_t)0x00000000U) /*!< UART invert data disbale */ +#define UART_INVDATA_ENABLE USART_MR_INVDATA /*!< UART invert data enable */ + +#define IS_UART_INVDATA(INVDATA) \ + ( \ + ((INVDATA) == UART_INVDATA_DISABLE) || \ + ((INVDATA) == UART_INVDATA_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup UART_OverSampling UART Oversampling mode + * @{ + */ +#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000U) /*!< UART 16x sampling */ +#define UART_OVERSAMPLING_8 USART_MR_OVER /*!< UART 8x sampling */ + +#define IS_UART_OVERSAMPLING(OVERSAMPLING) \ + ( \ + ((OVERSAMPLING) == UART_OVERSAMPLING_16) || \ + ((OVERSAMPLING) == UART_OVERSAMPLING_8 ) \ + ) +/** + * @} + */ + +/** @defgroup UART_Char_Length9 UART 9-bit character length + * @{ + */ +#define UART_CHAR_LENGTH9_DISABLE ((uint32_t)0x00000000U) /*!< UART CHRL defined character length */ +#define UART_CHAR_LENGTH9_ENABLE USART_MR_MODE9 /*!< UART 9-bit character length */ + +/** + * @} + */ + +/** @defgroup UART_BIT_ORDER UART bit order + * @{ + */ +#define UART_BIT_ORDER_LSBF ((uint32_t)0x00000000U) /*!< UART Least Significant Bit is sent/received first */ +#define UART_BIT_ORDER_MSBF USART_MR_MSBF /*!< UART Most Significant Bit is sent/received first */ + +#define IS_UART_BIT_ORDER(ORDER) \ + ( \ + ((ORDER) == UART_BIT_ORDER_LSBF) || \ + ((ORDER) == UART_BIT_ORDER_MSBF) \ + ) +/** + * @} + */ + +/** @defgroup UART_Channel_Mode UART channel mode + * @{ + */ +#define UART_CHANNEL_MODE_NORMAL (0x0UL << 14U ) /*!< UART operates in normal mode */ +#define UART_CHANNEL_MODE_AUTOMATIC (0x1UL << 14U ) /*!< UART operates in automatic echo mode */ +#define UART_CHANNEL_MODE_LOCAL_LOOPBACK (0x2UL << 14U ) /*!< UART operates in local loopback mode */ +#define UART_CHANNEL_MODE_REMOTE_LOOPBACK (0x3UL << 14U ) /*!< UART operates in remote loopback mode */ + +#define IS_UART_CHANNEL_MODE(MODE) \ + ( \ + ((MODE) == UART_CHANNEL_MODE_NORMAL ) || \ + ((MODE) == UART_CHANNEL_MODE_AUTOMATIC ) || \ + ((MODE) == UART_CHANNEL_MODE_LOCAL_LOOPBACK ) || \ + ((MODE) == UART_CHANNEL_MODE_REMOTE_LOOPBACK) \ + ) +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_1 ((uint32_t)0x00000000U) /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (0x1UL << 12U) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 (0x2UL << 12U) /*!< UART frame with 2 stop bits */ + +#define IS_UART_STOPBITS(STOPBITS) \ + ( \ + ((STOPBITS) == UART_STOPBITS_1 ) || \ + ((STOPBITS) == UART_STOPBITS_1_5) || \ + ((STOPBITS) == UART_STOPBITS_2 ) \ + ) +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_EVEN (0x0 << 9U) /*!< Even parity */ +#define UART_PARITY_ODD (0x1 << 9U) /*!< Odd parity */ +#define UART_PARITY_SPACE (0x2 << 9U) /*!< Space parity */ +#define UART_PARITY_MARK (0x3 << 9U) /*!< Mark parity */ +#define UART_PARITY_NONE (0x4 << 9U) /*!< No parity */ +#define UART_PARITY_MULTIDROP (0x6 << 9U) /*!< Multidrop Mode */ + +#define IS_UART_PARITY(PARITY) \ + ( \ + ((PARITY) == UART_PARITY_EVEN ) || \ + ((PARITY) == UART_PARITY_ODD ) || \ + ((PARITY) == UART_PARITY_SPACE ) || \ + ((PARITY) == UART_PARITY_MARK ) || \ + ((PARITY) == UART_PARITY_NONE ) || \ + ((PARITY) == UART_PARITY_MULTIDROP) \ + ) +/** + * @} + */ + +/** @defgroup UART_Char_Length UART character length + * @{ + */ +#define UART_CHAR_LENGTH_5BIT ((uint32_t)0x00000000U) /*!< UART charcter length is 5bits */ +#define UART_CHAR_LENGTH_6BIT (0x1U << 6U) /*!< UART charcter length is 6bits */ +#define UART_CHAR_LENGTH_7BIT (0x2U << 6U) /*!< UART charcter length is 7bits */ +#define UART_CHAR_LENGTH_8BIT (0x3U << 6U) /*!< UART charcter length is 8bits */ + +#define IS_UART_CHAR_LENGTH(LENGTH) \ + ( \ + ((LENGTH) == UART_CHAR_LENGTH_5BIT) || \ + ((LENGTH) == UART_CHAR_LENGTH_6BIT) || \ + ((LENGTH) == UART_CHAR_LENGTH_7BIT) || \ + ((LENGTH) == UART_CHAR_LENGTH_8BIT) || \ + ((LENGTH) == UART_CHAR_LENGTH9_DISABLE) || \ + ((LENGTH) == UART_CHAR_LENGTH9_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup UART_Clock_Select UART clock select + * @{ + */ +#define UART_CLOCK_SELECT_MCK ((uint32_t)0x00000000U) /*!< UART clock source MCK */ +#define UART_CLOCK_SELECT_MCKDIV8 (0x1U << 4U) /*!< UART clock source MCK / 8 */ + +#define IS_UART_CLOCK_SELECT(SELECT) \ + ( \ + ((SELECT) == UART_CLOCK_SELECT_MCK ) || \ + ((SELECT) == UART_CLOCK_SELECT_MCKDIV8) \ + ) +/** + * @} + */ + +/** @defgroup UART_Mode_Operation UART mode of operation + * @{ + */ +#define UART_MODE_OPERATION_NORMAL ((uint32_t)0x00000000U) /*!< UART mode of operation select normal */ +#define UART_MODE_OPERATION_IrDA (0x8U << 0U) /*!< UART mode of operation select irda + @note This define is valid only for UART4, UART5 and UART7, except for LPUART.*/ +#define UART_MODE_OPERATION_LIN_MASTER (0xAU << 0U) /*!< UART mode of operation select lin master + @note This define is valid only for UART4, UART5 and UART7, except for LPUART.*/ +#define UART_MODE_OPERATION_LIN_SLAVE (0xBU << 0U) /*!< UART mode of operation select lin slave + @note This define is valid only for UART4, UART5 and UART7, except for LPUART.*/ + +#define IS_UART_MODE_OPERATION(OPERATION) \ + ( \ + ((OPERATION) == UART_MODE_OPERATION_NORMAL ) || \ + ((OPERATION) == UART_MODE_OPERATION_IrDA ) || \ + ((OPERATION) == UART_MODE_OPERATION_LIN_MASTER ) || \ + ((OPERATION) == UART_MODE_OPERATION_LIN_SLAVE ) \ + ) +/** + * @} + */ + +/** @defgroup UART_Mode UART Mode + * @{ + */ +#define UART_MODE_RX USART_CR_RXEN /*!< RX mode */ +#define UART_MODE_TX USART_CR_TXEN /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR_TXEN | USART_CR_RXEN) /*!< RX and TX mode */ +#define IS_UART_MODE(MODE) \ + ( \ + ((MODE) == UART_MODE_RX ) || \ + ((MODE) == UART_MODE_TX ) || \ + ((MODE) == UART_MODE_TX_RX) \ + ) +/** + * @} + */ + +/** @defgroup UART_Sync_Disable UART synchronization disable in lin mode + * @{ + */ +#define UART_SYNC_DISABLE_NONE ((uint32_t)0x00000000) /*!< the synchronization procedure is performed in LIN Slave node configuration in LIN mode */ +#define UART_SYNC_DISABLE_ACTIVE USART_LINMR_SYNCDIS /*!< the synchronization procedure is not performed in LIN Slave node configuration in LIN mode */ + +#define IS_UART_SYNC_DISABLE(DISABLE) \ + ( \ + ((DISABLE) == UART_SYNC_DISABLE_NONE ) || \ + ((DISABLE) == UART_SYNC_DISABLE_ACTIVE) \ + ) +/** + * @} + */ + +/** @defgroup UART_PDC_Mode UART DMA mode in LIN mode + * @{ + */ +#define UART_PDC_MODE_LINMR_NOTWRITE ((uint32_t)0x00000000) /*!< The LIN mode register LINMR is not writted by the DMA */ +#define UART_PDC_MODE_LINMR_WRITE USART_LINMR_PDCM /*!< The LIN mode register LINMR(excepting that flag) is writted by the DMA */ + +#define IS_UART_PDC_MODE_LINMR(LINMR) \ + ( \ + ((LINMR) == UART_PDC_MODE_LINMR_NOTWRITE) || \ + ((LINMR) == UART_PDC_MODE_LINMR_WRITE ) \ + ) +/** + * @} + */ + +/** @defgroup UART_Wkup_Type UART wakeup signal type in LIN mode + * @{ + */ +#define UART_WKUP_TYPE_LIN_2_0 ((uint32_t)0x00000000) /*!< Setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal */ +#define UART_WKUP_TYPE_LIN_1_3 USART_LINMR_WKUPTYP /*!< Setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal */ +#define IS_UART_WKUP_TYPE(TYPE) \ + ( \ + ((TYPE) == UART_WKUP_TYPE_LIN_2_0) || \ + ((TYPE) == UART_WKUP_TYPE_LIN_1_3) \ + ) +/** + * @} + */ + +/** @defgroup UART_Frame_Slot_Disable UART frame slot mode disable in LIN mode + * @{ + */ +#define UART_FRAME_SLOT_DISABLE_NONE ((uint32_t)0x00000000) /*!< The frame slot mode is enabled in LIN mode */ +#define UART_FRAME_SLOT_DISABLE_ACTIVE USART_LINMR_FSDIS /*!< The frame slot mode is disabled in LIN mode */ +#define IS_UART_FRAME_SLOT_DISABLE(DISABLE) \ + ( \ + ((DISABLE) == UART_FRAME_SLOT_DISABLE_NONE ) || \ + ((DISABLE) == UART_FRAME_SLOT_DISABLE_ACTIVE) \ + ) +/** + * @} + */ + +/** @defgroup UART_Data_Length_Mode UART data length mode in LIN mode + * @{ + */ +#define UART_DATA_LENGTH_MODE_DLC ((uint32_t)0x00000000) /*!< The response data length is defined by the field DLC in LIN mode */ +#define UART_DATA_LENGTH_MODE_ID_5_6 USART_LINMR_DLM /*!< The response data length is defined by the bits 5 and 6 of the identifier (IDCHR in LINIR) in LIN mode */ +#define IS_UART_DATA_LENGTH_MODE(MODE) \ + ( \ + ((MODE) == UART_DATA_LENGTH_MODE_DLC ) || \ + ((MODE) == UART_DATA_LENGTH_MODE_ID_5_6) \ + ) +/** + * @} + */ + +/** @defgroup UART_Checksum_Type UART checksum type in LIN mode + * @{ + */ +#define UART_CHECKSUM_TYPE_ENHANCED ((uint32_t)0x00000000) /*!< LIN 2.0 "Enhanced" Checksum */ +#define UART_CHECKSUM_TYPE_CLASSIC USART_LINMR_CHKTYP /*!< LIN 1.3 "Classic " Checksum */ + +#define IS_UART_CHECKSUM_TYPE(TYPE) \ + ( \ + ((TYPE) == UART_CHECKSUM_TYPE_ENHANCED) || \ + ((TYPE) == UART_CHECKSUM_TYPE_CLASSIC ) \ + ) +/** + * @} + */ + +/** @defgroup UART_Checksum_Disable UART checksum disable in LIN mode + * @{ + */ +#define UART_CHECKSUM_DISABLE_NONE ((uint32_t)0x00000000) /*!< LIN Checksum not disable */ +#define UART_CHECKSUM_DISABLE_ACTIVE USART_LINMR_CHKDIS /*!< LIN Checksum disable */ + +#define IS_UART_CHECKSUM_DISABLE(DISABLE) \ + ( \ + ((DISABLE) == UART_CHECKSUM_DISABLE_NONE ) || \ + ((DISABLE) == UART_CHECKSUM_DISABLE_ACTIVE) \ + ) +/** + * @} + */ + +/** @defgroup UART_Parity_Disable UART parity disable in LIN mode + * @{ + */ +#define UART_PARITY_DISABLE_NONE ((uint32_t)0x00000000) /*!< LIN Parity not disable */ +#define UART_PARITY_DISABLE_ACTIVE USART_LINMR_PARDIS /*!< LIN Parity disable */ + +#define IS_UART_PARITY_DISABLE(DISABLE) \ + ( \ + ((DISABLE) == UART_PARITY_DISABLE_NONE ) || \ + ((DISABLE) == UART_PARITY_DISABLE_ACTIVE) \ + ) +/** + * @} + */ + +/** @defgroup UART_Node_Active UART checksum disable in LIN mode + * @{ + */ +#define UART_NODE_ACTIVE_PUBLISH ((uint32_t)0x00000000) /*!< The UART transmits the response */ +#define UART_NODE_ACTIVE_SUBSCRIBE (0x1U << 0U) /*!< The UART receives the response */ +#define UART_NODE_ACTIVE_IGNORE (0x2U << 0U) /*!< The UART does not transmit and does not receive the response */ + +#define IS_UART_NODE_ACTIVE(ACTIVE) \ + ( \ + ((ACTIVE) == UART_NODE_ACTIVE_PUBLISH ) || \ + ((ACTIVE) == UART_NODE_ACTIVE_SUBSCRIBE) || \ + ((ACTIVE) == UART_NODE_ACTIVE_IGNORE ) \ + ) +/** + * @} + */ + +/** @defgroup UART_DMA_TX UART DMA enable transmitter + * @{ + */ +#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< DMA mode is disable for transmission */ +#define UART_DMA_TX_ENABLE USART_CR_DMAT_EN /*!< DMA mode is enable for transmission */ + +#define IS_UART_DMA_TX_ENABLE(ENABLE) \ + ( \ + ((ENABLE) == UART_DMA_TX_DISABLE) || \ + ((ENABLE) == UART_DMA_TX_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup UART_DMA_RX UART DMA enable receiver + * @{ + */ +#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< DMA mode is disable for reception */ +#define UART_DMA_RX_ENABLE USART_CR_DMAR_EN /*!< DMA mode is enable for reception */ + +#define IS_UART_DMA_RX_ENABLE(ENABLE) \ + ( \ + ((ENABLE) == UART_DMA_RX_DISABLE) || \ + ((ENABLE) == UART_DMA_RX_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup UART_Flags + * @brief Flag mask in the CSR register + * @{ + */ +#define UART_FLAG_TXEMPTY USART_CSR_TXEMPTY /*!< UART transmitter empty */ +#define UART_FLAG_TIMEOUT USART_CSR_TIMEOUT /*!< UART receiver time-out */ +#define UART_FLAG_PARE USART_CSR_PARE /*!< UART parity error */ +#define UART_FLAG_FRAME USART_CSR_FRAME /*!< UART framing error */ +#define UART_FLAG_OVER USART_CSR_OVRE /*!< UART overrun error */ +#define UART_FLAG_RXBRK USART_CSR_RXBRK /*!< UART break receive/end of break */ +#define UART_FLAG_TXRDY USART_CSR_TXRDY /*!< UART transmitter ready */ +#define UART_FLAG_RXRDY USART_CSR_RXRDY /*!< UART receiver ready */ + +#define UART_FLAG_LINHTE USART_CSR_LINHTE /*!< UART LIN header timeout error */ +#define UART_FLAG_LINSTE USART_CSR_LINSTE /*!< UART LIN synch tolerance eror */ +#define UART_FLAG_LINSNRE USART_CSR_LINSNRE /*!< UART LIN slave not response error */ +#define UART_FLAG_LINCE USART_CSR_LINCE /*!< UART LIN checksum error */ +#define UART_FLAG_LINIPE USART_CSR_LINIPE /*!< UART LIN identifier parity error */ +#define UART_FLAG_LINISFE USART_CSR_LINISFE /*!< UART LIN inconsistent synch field error */ +#define UART_FLAG_LINBE USART_CSR_LINBE /*!< UART LIN bit error */ +#define UART_FLAG_LINBLS USART_CSR_LINBLS /*!< UART LIN bus line status */ +#define UART_FLAG_LINTC USART_CSR_LINTC /*!< UART LIN transfer completed */ +#define UART_FLAG_LINID USART_CSR_LINID /*!< UART LIN identifier sent or LIN identifier received */ +#define UART_FLAG_LINBK USART_CSR_LINBK /*!< UART LIN break sent or LIN break received */ +/** + * @} + */ + +/** @defgroup UART_Clear_Flags + * @brief Flag clear in the CR register + * @{ + */ +#define UART_CLEAR_TXEMPTY USART_CR_RSTTX /*!< UART transmitter empty interrupt clear */ +#define UART_CLEAR_TIMEOUT USART_CR_STTTO /*!< UART receiver time-out interrupt clear */ +#define UART_CLEAR_PARE USART_CR_RSTSTA /*!< UART parity error interrupt clear */ +#define UART_CLEAR_FRAME USART_CR_RSTSTA /*!< UART framing error interrupt clear */ +#define UART_CLEAR_OVER USART_CR_RSTSTA /*!< UART overrun error interrupt clear */ +#define UART_CLEAR_RXBRK USART_CR_RSTSTA /*!< UART break receive/end of break interrupt clear */ +#define UART_CLEAR_TXRDY USART_CR_RSTTX /*!< UART transmitter ready interrupt clear */ +#define UART_CLEAR_RXRDY USART_CR_RSTRX /*!< UART receiver ready interrupt clear */ + +#define UART_CLEAR_LINHTE USART_CR_RSTSTA /*!< UART LIN header timeout error interrupt clear */ +#define UART_CLEAR_LINSTE USART_CR_RSTSTA /*!< UART LIN synch tolerance eror interrupt clear */ +#define UART_CLEAR_LINSNRE USART_CR_RSTSTA /*!< UART LIN slave not response error interrupt clear */ +#define UART_CLEAR_LINCE USART_CR_RSTSTA /*!< UART LIN checksum error interrupt clear */ +#define UART_CLEAR_LINIPE USART_CR_RSTSTA /*!< UART LIN identifier parity error interrupt clear */ +#define UART_CLEAR_LINISFE USART_CR_RSTSTA /*!< UART LIN inconsistent synch field error interrupt clear */ +#define UART_CLEAR_LINBE USART_CR_RSTSTA /*!< UART LIN bit error interrupt clear */ +#define UART_CLEAR_LINTC USART_CR_RSTSTA /*!< UART LIN transfer completed interrupt clear */ +#define UART_CLEAR_LINID USART_CR_RSTSTA /*!< UART LIN identifier sent or LIN identifier received interrupt clear */ +#define UART_CLEAR_LINBK USART_CR_RSTSTA /*!< UART LIN break sent or LIN break received interrupt clear */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition + * @brief Interrupt enable register - IER register + * @{ + */ +#define UART_IT_TXEMPTY USART_IER_TXEMPTY /*!< UART transmitter empty interruption */ +#define UART_IT_TIMEOUT USART_IER_TIMEOUT /*!< UART receiver time-out interruption */ +#define UART_IT_PARE USART_IER_PARE /*!< UART parity error interruption */ +#define UART_IT_FRAME USART_IER_FRAME /*!< UART framing error interruption */ +#define UART_IT_OVER USART_IER_OVRE /*!< UART overrun error interruption */ +#define UART_IT_RXBRK USART_IER_RXBRK /*!< UART break receive/end of break interruption */ +#define UART_IT_TXRDY USART_IER_TXRDY /*!< UART transmitter ready interruption */ +#define UART_IT_RXRDY USART_IER_RXRDY /*!< UART receiver ready interruption */ + +#define UART_IT_LINHTE USART_IER_LINHTE /*!< UART LIN header timeout error interruption */ +#define UART_IT_LINSTE USART_IER_LINSTE /*!< UART LIN synch tolerance eror interruption */ +#define UART_IT_LINSNRE USART_IER_LINSNRE /*!< UART LIN slave not response error interruption */ +#define UART_IT_LINCE USART_IER_LINCE /*!< UART LIN checksum error interruption */ +#define UART_IT_LINIPE USART_IER_LINIPE /*!< UART LIN identifier parity error interruption */ +#define UART_IT_LINISFE USART_IER_LINISFE /*!< UART LIN inconsistent synch field error interruption */ +#define UART_IT_LINBE USART_IER_LINBE /*!< UART LIN bit error interruption */ +#define UART_IT_LINTC USART_IER_LINTC /*!< UART LIN transfer completed interruption */ +#define UART_IT_LINID USART_IER_LINID /*!< UART LIN identifier sent or LIN identifier received interruption */ +#define UART_IT_LINBK USART_IER_LINBK /*!< UART LIN break sent or LIN break received interruption */ + +/** + * @} + */ + +/** @defgroup UART_Interrupt_disable + * @brief Interrupt disable register - IDR register + * @{ + */ +#define UART_DIS_TXEMPTY USART_IDR_TXEMPTY /*!< UART transmitter empty interrupt disable */ +#define UART_DIS_TIMEOUT USART_IDR_TIMEOUT /*!< UART receiver time-out interrupt disable */ +#define UART_DIS_PARE USART_IDR_PARE /*!< UART parity error interrupt disable */ +#define UART_DIS_FRAME USART_IDR_FRAME /*!< UART framing error interrupt disable */ +#define UART_DIS_OVER USART_IDR_OVRE /*!< UART overrun error interrupt disable */ +#define UART_DIS_RXBRK USART_IDR_RXBRK /*!< UART break receive/end of break interrupt disable */ +#define UART_DIS_TXRDY USART_IDR_TXRDY /*!< UART transmitter ready interrupt disable */ +#define UART_DIS_RXRDY USART_IDR_RXRDY /*!< UART receiver ready interrupt disable */ + +#define UART_DIS_LINHTE USART_IDR_LINHTE /*!< UART LIN header timeout error interrupt disable */ +#define UART_DIS_LINSTE USART_IDR_LINSTE /*!< UART LIN synch tolerance eror interrupt disable */ +#define UART_DIS_LINSNRE USART_IDR_LINSNRE /*!< UART LIN slave not response error interrupt disable */ +#define UART_DIS_LINCE USART_IDR_LINCE /*!< UART LIN checksum error interrupt disable */ +#define UART_DIS_LINIPE USART_IDR_LINIPE /*!< UART LIN identifier parity error interrupt disable */ +#define UART_DIS_LINISFE USART_IDR_LINISFE /*!< UART LIN inconsistent synch field error interrupt disable */ +#define UART_DIS_LINBE USART_IDR_LINBE /*!< UART LIN bit error interrupt disable */ +#define UART_DIS_LINTC USART_IDR_LINTC /*!< UART LIN transfer completed interrupt disable */ +#define UART_DIS_LINID USART_IDR_LINID /*!< UART LIN identifier sent or LIN identifier received interrupt disable */ +#define UART_DIS_LINBK USART_IDR_LINBK /*!< UART LIN break sent or LIN break received interrupt disable */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask + * @brief Interrupt mask register - IMR register + * @{ + */ +#define UART_MASK_TXEMPTY USART_IMR_TXEMPTY /*!< UART transmitter empty interrupt mask */ +#define UART_MASK_TIMEOUT USART_IMR_TIMEOUT /*!< UART receiver time-out interrupt mask */ +#define UART_MASK_PARE USART_IMR_PARE /*!< UART parity error interrupt mask */ +#define UART_MASK_FRAME USART_IMR_FRAME /*!< UART framing error interrupt mask */ +#define UART_MASK_OVER USART_IMR_OVRE /*!< UART overrun error interrupt mask */ +#define UART_MASK_RXBRK USART_IMR_RXBRK /*!< UART break receive/end of break interrupt mask */ +#define UART_MASK_TXRDY USART_IMR_TXRDY /*!< UART transmitter ready interrupt mask */ +#define UART_MASK_RXRDY USART_IMR_RXRDY /*!< UART receiver ready interrupt mask */ + +#define UART_MASK_LINHTE USART_IMR_LINHTE /*!< UART LIN header timeout error interrupt mask */ +#define UART_MASK_LINSTE USART_IMR_LINSTE /*!< UART LIN synch tolerance eror interrupt mask */ +#define UART_MASK_LINSNRE USART_IMR_LINSNRE /*!< UART LIN slave not response error interrupt mask */ +#define UART_MASK_LINCE USART_IMR_LINCE /*!< UART LIN checksum error interrupt mask */ +#define UART_MASK_LINIPE USART_IMR_LINIPE /*!< UART LIN identifier parity error interrupt mask */ +#define UART_MASK_LINISFE USART_IMR_LINISFE /*!< UART LIN inconsistent synch field error interrupt mask */ +#define UART_MASK_LINBE USART_IMR_LINBE /*!< UART LIN bit error interrupt mask */ +#define UART_MASK_LINTC USART_IMR_LINTC /*!< UART LIN transfer completed interrupt mask */ +#define UART_MASK_LINID USART_IMR_LINID /*!< UART LIN identifier sent or LIN identifier received interrupt mask */ +#define UART_MASK_LINBK USART_IMR_LINBK /*!< UART LIN break sent or LIN break received interrupt mask */ + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Check whether the specified UART flag is set or not. + * @param None + * @retval None + */ +#define IS_UART_GET_FLAG(FLAG) \ + ( \ + ((FLAG) == UART_FLAG_TXEMPTY) || \ + ((FLAG) == UART_FLAG_TIMEOUT) || \ + ((FLAG) == UART_FLAG_PARE ) || \ + ((FLAG) == UART_FLAG_FRAME ) || \ + ((FLAG) == UART_FLAG_OVER ) || \ + ((FLAG) == UART_FLAG_RXBRK ) || \ + ((FLAG) == UART_FLAG_TXRDY ) || \ + ((FLAG) == UART_FLAG_RXRDY ) || \ + ((FLAG) == UART_FLAG_LINHTE ) || \ + ((FLAG) == UART_FLAG_LINSTE ) || \ + ((FLAG) == UART_FLAG_LINSNRE) || \ + ((FLAG) == UART_FLAG_LINCE ) || \ + ((FLAG) == UART_FLAG_LINIPE ) || \ + ((FLAG) == UART_FLAG_LINISFE) || \ + ((FLAG) == UART_FLAG_LINBE ) || \ + ((FLAG) == UART_FLAG_LINBLS ) || \ + ((FLAG) == UART_FLAG_LINTC ) || \ + ((FLAG) == UART_FLAG_LINID ) || \ + ((FLAG) == UART_FLAG_LINBK ) \ + ) + +/** @brief Clear the specified UART pending flag enable. + * @param None + * @retval None + */ +#define IS_UART_CLEAR_FLAG(FLAG) \ + ( \ + ((FLAG) == UART_CLEAR_TXEMPTY) || \ + ((FLAG) == UART_CLEAR_TIMEOUT) || \ + ((FLAG) == UART_CLEAR_PARE ) || \ + ((FLAG) == UART_CLEAR_FRAME ) || \ + ((FLAG) == UART_CLEAR_OVER ) || \ + ((FLAG) == UART_CLEAR_RXBRK ) || \ + ((FLAG) == UART_CLEAR_TXRDY ) || \ + ((FLAG) == UART_CLEAR_RXRDY ) || \ + ((FLAG) == UART_CLEAR_LINHTE ) || \ + ((FLAG) == UART_CLEAR_LINSTE ) || \ + ((FLAG) == UART_CLEAR_LINSNRE) || \ + ((FLAG) == UART_CLEAR_LINCE ) || \ + ((FLAG) == UART_CLEAR_LINIPE ) || \ + ((FLAG) == UART_CLEAR_LINISFE) || \ + ((FLAG) == UART_CLEAR_LINBE ) || \ + ((FLAG) == UART_CLEAR_LINTC ) || \ + ((FLAG) == UART_CLEAR_LINID ) || \ + ((FLAG) == UART_CLEAR_LINBK ) \ + ) + +/** @brief Enable the specified UART interrupt. + * @param None + * @retval None + */ +#define IS_UART_ENABLE_IT(IT) \ + ( \ + ((IT) == UART_IT_TXEMPTY) || \ + ((IT) == UART_IT_TIMEOUT) || \ + ((IT) == UART_IT_PARE ) || \ + ((IT) == UART_IT_FRAME ) || \ + ((IT) == UART_IT_OVER ) || \ + ((IT) == UART_IT_RXBRK ) || \ + ((IT) == UART_IT_TXRDY ) || \ + ((IT) == UART_IT_RXRDY ) || \ + ((IT) == UART_IT_LINHTE ) || \ + ((IT) == UART_IT_LINSTE ) || \ + ((IT) == UART_IT_LINSNRE) || \ + ((IT) == UART_IT_LINCE ) || \ + ((IT) == UART_IT_LINIPE ) || \ + ((IT) == UART_IT_LINISFE) || \ + ((IT) == UART_IT_LINBE ) || \ + ((IT) == UART_IT_LINTC ) || \ + ((IT) == UART_IT_LINID ) || \ + ((IT) == UART_IT_LINBK ) \ + ) + +/** @brief Disable the specified UART interrupt. + * @param None + * @retval None + */ +#define IS_UART_CLEAR_IT(IT) \ + ( \ + ((IT) == UART_DIS_TXEMPTY) || \ + ((IT) == UART_DIS_TIMEOUT) || \ + ((IT) == UART_DIS_PARE ) || \ + ((IT) == UART_DIS_FRAME ) || \ + ((IT) == UART_DIS_OVER ) || \ + ((IT) == UART_DIS_RXBRK ) || \ + ((IT) == UART_DIS_TXRDY ) || \ + ((IT) == UART_DIS_RXRDY ) || \ + ((IT) == UART_DIS_LINHTE ) || \ + ((IT) == UART_DIS_LINSTE ) || \ + ((IT) == UART_DIS_LINSNRE) || \ + ((IT) == UART_DIS_LINCE ) || \ + ((IT) == UART_DIS_LINIPE ) || \ + ((IT) == UART_DIS_LINISFE) || \ + ((IT) == UART_DIS_LINBE ) || \ + ((IT) == UART_DIS_LINTC ) || \ + ((IT) == UART_DIS_LINID ) || \ + ((IT) == UART_DIS_LINBK ) \ + ) + + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param None + * @retval None + */ +#define IS_UART_GET_IT(IT) \ + ( \ + ((IT) == UART_MASK_TXEMPTY) || \ + ((IT) == UART_MASK_TIMEOUT) || \ + ((IT) == UART_MASK_PARE ) || \ + ((IT) == UART_MASK_FRAME ) || \ + ((IT) == UART_MASK_OVER ) || \ + ((IT) == UART_MASK_RXBRK ) || \ + ((IT) == UART_MASK_TXRDY ) || \ + ((IT) == UART_MASK_RXRDY ) || \ + ((IT) == UART_MASK_LINHTE ) || \ + ((IT) == UART_MASK_LINSTE ) || \ + ((IT) == UART_MASK_LINSNRE) || \ + ((IT) == UART_MASK_LINCE ) || \ + ((IT) == UART_MASK_LINIPE ) || \ + ((IT) == UART_MASK_LINISFE) || \ + ((IT) == UART_MASK_LINBE ) || \ + ((IT) == UART_MASK_LINTC ) || \ + ((IT) == UART_MASK_LINID ) || \ + ((IT) == UART_MASK_LINBK ) \ + ) + +/** + * @} + */ + +/** @defgroup UART_Global_definition + * @{ + */ +#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE ) <= 6562500U) +#define IS_UART_FIDIRATIO(FIDIRATE) ((FIDIRATE ) <= 2047U ) +#define IS_UART_IF(IF) ((IF ) <= 0xFFU ) +#define IS_UART_TIMEOUT(TIMEOUT) ((TIMEOUT ) <= 0x1FFFF ) +#define IS_UART_TIMGUARD(TIMEGUARD) ((TIMEGUARD) <= 0xFF ) +#define IS_UART_LINIR_WR(LINIR_WR) ((LINIR_WR ) <= 0xFF ) +#define IS_UART_DATA(DATA) ((DATA ) <= 0x1FF ) +#define IS_UART_DLC(DATA) ((DATA ) <= 0xFF ) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void UART_Init(USART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct); +void UART_StructInit(UART_InitTypeDef* UART_InitStruct); +void UART_DeInit(USART_TypeDef* UARTx); + +/* Normal command and configuration functions *********************************/ +/* Normal Cmd */ void UART_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_RSTSTA_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_TXDIS_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_TXEN_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_RXDIS_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_RXEN_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_RSTTX_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_RSTRX_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cfg */ void UART_InvData_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cfg */ void UART_OverSampling8_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cfg */ void UART_DataLength9_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cfg */ void UART_MSBFirst_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cfg */ void UART_ChannelMode_Cfg(USART_TypeDef* UARTx, uint32_t UART_ChannelMode); +/* Normal Cfg */ void UART_StopBit_Cfg(USART_TypeDef* UARTx, uint32_t UART_StopBits); +/* Normal Cfg */ void UART_Parity_Cfg(USART_TypeDef* UARTx, uint32_t UART_Parity); +/* Normal Cfg */ void UART_DataLength_Cfg(USART_TypeDef* UARTx, uint32_t UART_WordLength); +/* Normal Cfg */ void UART_CLKSelect_Cfg(USART_TypeDef* UARTx, uint32_t UART_CLKSelect); +/* Normal Cfg */ void UART_OperationMode_Cfg(USART_TypeDef* UARTx, uint32_t UART_OperationMode); + +/* Fractional baudrate function ***********************************************/ +/* Normal Cfg */ void UART_FracDivider_Cfg(USART_TypeDef* UARTx, uint32_t UART_BaudRate); + +/* Break command functions ****************************************************/ +/* Normal Cmd */ void UART_STPBRK_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_STTBRK_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); + +/* Receiver time-out and transmitter timeguard functions **********************/ +/* Normal Cfg */ void UART_Receiver_TimeOut_Cfg(USART_TypeDef* UARTx, uint32_t UART_ReceiverTimeOut); +/* Normal Cmd */ void UART_RETTO_After_Timeout_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cmd */ void UART_STTTO_After_Timeout_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* Normal Cfg */ void UART_Transmitter_TimeGuard_Cfg(USART_TypeDef* UARTx, uint32_t UART_TransmitterTimeGuard); + +/* Multidrop mode command function ********************************************/ +/* Normal Cmd */ void UART_SENDAInMultidropMode_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); + +/* IrDA mode function *********************************************************/ +/* IrDA Cfg */ void UART_IrDAFilter_Cfg(USART_TypeDef* UARTx, uint32_t UART_IrDAFilter); + +/* LIN mode functions *********************************************************/ +/* LIN Cmd */ void UART_LINWKUP_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cmd */ void UART_LINABT_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_Write_LINIR_In_LIN_Master(USART_TypeDef* UARTx, uint32_t UART_LINIR_Data); +/* LIN Read */ uint32_t UART_Read_LINIR_In_LIN_Slave(USART_TypeDef* UARTx); +/* LIN Cfg */ void UART_SYNCDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_PDCMode_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_DataLengthControl_Cfg(USART_TypeDef* UARTx, uint32_t UART_DataLengthControl); +/* LIN Cfg */ void UART_WkupType_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_FrameSlotDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_DataLengthMode_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_CheckSumType_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_CheckSumDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_ParityDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState); +/* LIN Cfg */ void UART_NodeAction_Cfg(USART_TypeDef* UARTx, uint32_t UART_NodeAction); +/* LIN Read */ uint32_t UART_LINBaudRate(USART_TypeDef* UARTx); + +/* Data transfers functions ***************************************************/ +void UART_Transmit(USART_TypeDef* UARTx, uint16_t Data); +uint16_t UART_Receive(USART_TypeDef* UARTx); + +/* DMA transfers management functions *****************************************/ +void UART_DMATxEnable_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); +void UART_DMARxEnable_Cmd(USART_TypeDef* UARTx, FunctionalState NewState); + +/* Low-Power SLEEP and STOP wakeup management functions ***********************/ +void UART_LowPowerSleepWkupConfig(USART_TypeDef* UARTx, FunctionalState NewState); +void LPUART_LowPowerStopWkupConfig(USART_TypeDef* UARTx, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void UART_ITConfig(USART_TypeDef* UARTx, uint32_t UART_IT, FunctionalState NewState); +FlagStatus UART_GetFlagStatus(USART_TypeDef* UARTx, uint32_t UART_FLAG); +void UART_ClearFlag(USART_TypeDef* UARTx, uint32_t UART_FLAG); +ITStatus UART_GetITStatus(USART_TypeDef* UARTx, uint32_t UART_IT); +void UART_ITDisableConfig(USART_TypeDef* UARTx, uint32_t UART_IT, FunctionalState NewState); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_UART_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usart.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usart.h new file mode 100644 index 00000000000..e46f3f7bd35 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usart.h @@ -0,0 +1,1188 @@ +/** + * @file ft32f4xx_usart.h + * @author FMD AE + * @brief This file contains all the functions prototypes for the USART + * fireware library. + * @version V1.0.0 + * @date 2025-03-19 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_USART_H +#define __FT32F4XX_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup ft32f4xx_Driver + * @{ + */ + +/** @addtogroup USART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + +/** + * @brief USART Init Structure definition + */ +typedef struct +{ + uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - CD = 0: Disable baud rate clock + + - Non ISO7816 mode + - ASYNC X16 : IntegerDivider = ((PCLKx) / (16 * (USRAT_InitStruct->USART_BaudRate))) + - ASYNC X8 : IntegerDivider = ((PCLKx) / (8 * (USRAT_InitStruct->USART_BaudRate))) + - SYNC or SPI: IntegerDivider = ((PCLKx) / ( (USRAT_InitStruct->USART_BaudRate))) + - ISO7816 mode + - ISO7816 : IntegerDivider = ((PCLKx) / (USRAT_InitStruct->USART_FiDiRatio * + (USRAT_InitStruct->USART_BaudRate))) + + - Fractional baud rate in asynchronous mode + - X16 : FractionDivider = (((PCLKx) / (16 * (USRAT_InitStruct->USART_BaudRate))) - IntegerDivider) * 8 + - X8 : FractionDivider = (((PCLKx) / (8 * (USRAT_InitStruct->USART_BaudRate))) - IntegerDivider) * 8 + */ + + uint32_t USART_FiDiRatio; /*!< Specifies the value of FI over DI ratio value in ISO7816 mode and IrDA mode.*/ + + uint32_t USART_IrDAFilter; /*!< Specifies the value of IrDA filter in IrDA mode.*/ + + uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Char_Length & USART_Char_Length9*/ + + uint32_t USART_ClockOutput; /*!< Specifies whether the USART clock SCK is output or not. + This parameter can be a value of @ref USART_Clock_Output*/ + + uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits*/ + + uint32_t USART_Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t USART_Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode*/ + + uint32_t USART_CLKSelect; /*!< Specifies the selection of clock. + This parameter can be a value of @ref USART_Clock_Select*/ + + uint32_t USART_OperationMode; /*!< Specifies the mode of operation. + This parameter can be a value of @ref USART_Mode_Operation*/ + + uint32_t USART_HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control*/ + + uint32_t USART_Sync; /*!< Specifies the synchronous mode select. + This parameter can be a value of @ref USART_Sync_Mode*/ + + uint32_t USART_BitOrder; /*!< Specifies whether the Least or Most Significant Bit is sent/received first. + This parameter can be a value of @ref USART_BIT_ORDER*/ + + uint32_t USART_ChannelMode; /*!< Specifies the channel mode select. + this parameter can be a value of @ref USART_Channel_Mode*/ + + uint32_t USART_WRDBT; /*!< Specifies whether wait read data before transfer is enabled or disabled. + This parameter can be a value of @ref USART_WRDBT*/ + + uint32_t USART_OverSampling; /*!< Specifies whether 16x oversampling or 8x oversampling. + This parameter can be a value of @ref USART_OverSampling*/ + + uint32_t USART_CLKPolarity; /*!< Specifies the inactive state value of the serial clock in SPI mode. + This parameter can be a value of @ref USART_Clock_Polarity*/ + + uint32_t USART_CLKPhase; /*!< Specifies the clock transition on which the bit capture and which bit change + is made in SPI mode. + This parameter can be a value of @ref USART_Clock_Phase*/ + + uint32_t USART_INVData; /*!< Specifies whether the data is inverted. + This parameter can be a value of @ref USART_InvertData*/ + + uint32_t USART_InhibitNACK; /*!< Specifies whether the NACK is generated in ISO7816 protocol T = 0. + This parameter can be a value of @ref USART_INACK*/ + + uint32_t USART_DisSuccessiveNACK; /*!< Specifies whether disable the successive NACK in ISO7816 protocol T = 0. + This parameter can be a value of @ref USART_DSNACK*/ + + uint32_t USART_MAXIteration; /*!< Specifies the maximum number of automatic iteration in ISO7816 protocol T = 0. + This parameter can be a value of @ref USART_Max_Iteration*/ + + uint32_t USART_SYNCDisable; /*!< Specifies whether disable the synchronization in LIN mode. + This parameter can be a value of @ref USART_Sync_Disable*/ + + uint32_t USART_PDCMode; /*!< Specifies the DMA mode selection in LIN mode. + This parameter can be a value of @ref USART_PDC_Mode*/ + + uint32_t USART_DataLengthControl; /*!< Specifies define the response data length when DataLengthMode = 0 in LIN mode. + 0-255: the response data length is equal to DLC+1 bytes.*/ + + uint32_t USART_WkupType; /*!< Specifies whether the wakeup signal type is LIN2.0 wakup signal or LIN1.3 wakup signal. + This parameter can be a value of @ref USART_Wkup_Type*/ + + uint32_t USART_FrameSlotDisable; /*!< Specifies whether disable the frame slot mode in LIN mode. + This parameter can be a value of @ref USART_Frame_Slot_Disable*/ + + uint32_t USART_DataLengthMode; /*!< Specifies the data length mode in LIN mode. + This parameter can be a value of @ref USART_Data_Length_Mode*/ + + uint32_t USART_CheckSumType; /*!< Specifies the checksum type in LIN mode. + This parameter can be a value of @ref USART_Checksum_Type*/ + + uint32_t USART_CheckSumDisable; /*!< Specifies whether disable the checksum in LIN mode. + This parameter can be a value of @ref USART_Checksum_Disable*/ + + uint32_t USART_ParityDisable; /*!< Specifies whether disable the parity in LIN mode. + This parameter can be a value of @ref USART_Parity_Disable*/ + + uint32_t USART_NodeAction; /*!< Specifies the LIN Node Active. + This parameter can be a value of @ref USART_Node_Active*/ + +} USART_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_Exported_Constants USART Exported Constants + * @{ + */ + +#define IS_USART_ALL_PERIPH(PERIPH) ( \ + ((PERIPH) == USART1) || \ + ((PERIPH) == USART2) || \ + ((PERIPH) == USART3) || \ + ((PERIPH) == USART6) \ + ) + +#define IS_USART_ALL_PERIPH_WP(PERIPH_WP) ( \ + ((PERIPH_WP) == USART1_WP) || \ + ((PERIPH_WP) == USART2_WP) || \ + ((PERIPH_WP) == USART3_WP) || \ + ((PERIPH_WP) == USART6_WP) \ + ) + +#define IS_USART_12_PERIPH(PERIPH) ( \ + ((PERIPH) == USART1) || \ + ((PERIPH) == USART2) \ + ) + +#define IS_USART_36_PERIPH(PERIPH) ( \ + ((PERIPH) == USART3) || \ + ((PERIPH) == USART6) \ + ) + + +/** @defgroup USART_Max_Iteration USART Number of MAX_ITERATION for ISO7816 T = 0 + * @{ + */ +#define USART_ISO7816_T0_MAX_ITERATION_0 ((uint32_t)0x00000000U << (uint32_t)24U) /*!< USART max_iteration with 0 times */ +#define USART_ISO7816_T0_MAX_ITERATION_1 ((uint32_t)0x00000001U << (uint32_t)24U) /*!< USART max_iteration with 1 times */ +#define USART_ISO7816_T0_MAX_ITERATION_2 ((uint32_t)0x00000002U << (uint32_t)24U) /*!< USART max_iteration with 2 times */ +#define USART_ISO7816_T0_MAX_ITERATION_3 ((uint32_t)0x00000003U << (uint32_t)24U) /*!< USART max_iteration with 3 times */ +#define USART_ISO7816_T0_MAX_ITERATION_4 ((uint32_t)0x00000004U << (uint32_t)24U) /*!< USART max_iteration with 4 times */ +#define USART_ISO7816_T0_MAX_ITERATION_5 ((uint32_t)0x00000005U << (uint32_t)24U) /*!< USART max_iteration with 5 times */ +#define USART_ISO7816_T0_MAX_ITERATION_6 ((uint32_t)0x00000006U << (uint32_t)24U) /*!< USART max_iteration with 6 times */ +#define USART_ISO7816_T0_MAX_ITERATION_7 ((uint32_t)0x00000007U << (uint32_t)24U) /*!< USART max_iteration with 7 times */ + +#define IS_USART_ISO7816_T0_MAX_ITERATION(ITERATION) \ + ( \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_0) || \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_1) || \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_2) || \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_3) || \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_4) || \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_5) || \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_6) || \ + ((ITERATION) == USART_ISO7816_T0_MAX_ITERATION_7) \ + ) +/** + * @} + */ + +/** @defgroup USART_InvertData USART Invert Data + * @{ + */ +#define USART_INVDATA_DISABLE ((uint32_t)0x00000000U) /*!< USART invert data disbale */ +#define USART_INVDATA_ENABLE USART_MR_INVDATA /*!< USART invert data enable */ + +#define IS_USART_INVDATA(INVDATA) \ + ( \ + ((INVDATA) == USART_INVDATA_DISABLE) || \ + ((INVDATA) == USART_INVDATA_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_DSNACK USART disable successive NACK for ISO7816 T = 0 + * @{ + */ +#define USART_ISO7816_T0_DSNACK_DISABLE ((uint32_t)0x00000000U) /*!< USART successive NACK disable*/ +#define USART_ISO7816_T0_DSNACK_ENABLE USART_MR_DSNACK /*!< USART successive NACK enable */ + +#define IS_USART_ISO7816_T0_DSNACK(DSNACK) \ + ( \ + ((DSNACK) == USART_ISO7816_T0_DSNACK_DISABLE) || \ + ((DSNACK) == USART_ISO7816_T0_DSNACK_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_INACK USART inhibit Non Acknowledge for ISO7816 T = 0 + * @{ + */ +#define USART_ISO7816_T0_INACK_DISABLE ((uint32_t)0x00000000U) /*!< USART inhibit Non Acknowledge */ +#define USART_ISO7816_T0_INACK_ENABLE USART_MR_INACK /*!< USART Non Acknowledge */ + +#define IS_USART_ISO7816_T0_INACK(INACK) \ + ( \ + ((INACK) == USART_ISO7816_T0_DSNACK_DISABLE) || \ + ((INACK) == USART_ISO7816_T0_DSNACK_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_OverSampling USART Oversampling mode + * @{ + */ +#define USART_OVERSAMPLING_16 ((uint32_t)0x00000000U) /*!< USART 16x sampling */ +#define USART_OVERSAMPLING_8 USART_MR_OVER /*!< USART 8x sampling */ + +#define IS_USART_OVERSAMPLING(OVERSAMPLING) \ + ( \ + ((OVERSAMPLING) == USART_OVERSAMPLING_16) || \ + ((OVERSAMPLING) == USART_OVERSAMPLING_8 ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Clock_Output USART clock output select + * @{ + */ +#define USART_CLOCK_OUTPUT_DISABLE ((uint32_t)0x00000000U) /*!< USART don't drive the SCK pin */ +#define USART_CLOCK_OUTPUT_ENABLE USART_MR_CLKO /*!< USART drive the SCK pin if don't select the external clock SCK */ + +#define IS_USART_CLOCK_OUTPUT(OUTPUT) \ + ( \ + ((OUTPUT) == USART_CLOCK_OUTPUT_DISABLE) || \ + ((OUTPUT) == USART_CLOCK_OUTPUT_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Char_Length9 USART 9-bit character length + * @{ + */ +#define USART_CHAR_LENGTH9_DISABLE ((uint32_t)0x00000000U) /*!< USART CHRL defined character length */ +#define USART_CHAR_LENGTH9_ENABLE USART_MR_MODE9 /*!< USART 9-bit character length */ + +/** + * @} + */ + +/** @defgroup USART_BIT_ORDER USART bit order + * @{ + */ +#define USART_BIT_ORDER_LSBF ((uint32_t)0x00000000U) /*!< USART Least Significant Bit is sent/received first */ +#define USART_BIT_ORDER_MSBF USART_MR_MSBF /*!< USART Most Significant Bit is sent/received first */ + +#define IS_USART_BIT_ORDER(ORDER) \ + ( \ + ((ORDER) == USART_BIT_ORDER_LSBF) || \ + ((ORDER) == USART_BIT_ORDER_MSBF) \ + ) +/** + * @} + */ + +/** @defgroup USART_Channel_Mode USART channel mode + * @{ + */ +#define USART_CHANNEL_MODE_NORMAL (0x0UL << 14U ) /*!< USART operates in normal mode */ +#define USART_CHANNEL_MODE_AUTOMATIC (0x1UL << 14U ) /*!< USART operates in automatic echo mode */ +#define USART_CHANNEL_MODE_LOCAL_LOOPBACK (0x2UL << 14U ) /*!< USART operates in local loopback mode */ +#define USART_CHANNEL_MODE_REMOTE_LOOPBACK (0x3UL << 14U ) /*!< USART operates in remote loopback mode */ + +#define IS_USART_CHANNEL_MODE(MODE) \ + ( \ + ((MODE) == USART_CHANNEL_MODE_NORMAL ) || \ + ((MODE) == USART_CHANNEL_MODE_AUTOMATIC ) || \ + ((MODE) == USART_CHANNEL_MODE_LOCAL_LOOPBACK ) || \ + ((MODE) == USART_CHANNEL_MODE_REMOTE_LOOPBACK) \ + ) +/** + * @} + */ + +/** @defgroup USART_Stop_Bits USART Number of Stop Bits + * @{ + */ +#define USART_STOPBITS_1 ((uint32_t)0x00000000U) /*!< USART frame with 1 stop bit */ +#define USART_STOPBITS_1_5 (0x1UL << 12U) /*!< USART frame with 1.5 stop bits */ +#define USART_STOPBITS_2 (0x2UL << 12U) /*!< USART frame with 2 stop bits */ + +#define IS_USART_STOPBITS(STOPBITS) \ + ( \ + ((STOPBITS) == USART_STOPBITS_1 ) || \ + ((STOPBITS) == USART_STOPBITS_1_5) || \ + ((STOPBITS) == USART_STOPBITS_2 ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Parity USART Parity + * @{ + */ +#define USART_PARITY_EVEN (0x0 << 9U) /*!< Even parity */ +#define USART_PARITY_ODD (0x1 << 9U) /*!< Odd parity */ +#define USART_PARITY_SPACE (0x2 << 9U) /*!< Space parity */ +#define USART_PARITY_MARK (0x3 << 9U) /*!< Mark parity */ +#define USART_PARITY_NONE (0x4 << 9U) /*!< No parity */ +#define USART_PARITY_MULTIDROP (0x6 << 9U) /*!< Multidrop Mode */ + +#define IS_USART_PARITY(PARITY) \ + ( \ + ((PARITY) == USART_PARITY_EVEN ) || \ + ((PARITY) == USART_PARITY_ODD ) || \ + ((PARITY) == USART_PARITY_SPACE ) || \ + ((PARITY) == USART_PARITY_MARK ) || \ + ((PARITY) == USART_PARITY_NONE ) || \ + ((PARITY) == USART_PARITY_MULTIDROP) \ + ) +/** + * @} + */ + +/** @defgroup USART_Sync_Mode USART synchronous mode select + * @{ + */ +#define USART_SYNC_MODE_ASYNC ((uint32_t)0x00000000U) /*!< USART operates in asynchronous mode */ +#define USART_SYNC_MODE_SYNC USART_MR_SYNC /*!< USART operates in synchronous mode */ + +#define IS_USART_SYNC_MODE(MODE) \ + ( \ + ((MODE) == USART_SYNC_MODE_ASYNC) || \ + ((MODE) == USART_SYNC_MODE_SYNC ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Char_Length USART character length + * @{ + */ +#define USART_CHAR_LENGTH_5BIT ((uint32_t)0x00000000U) /*!< USART charcter length is 5bits */ +#define USART_CHAR_LENGTH_6BIT (0x1U << 6U) /*!< USART charcter length is 6bits */ +#define USART_CHAR_LENGTH_7BIT (0x2U << 6U) /*!< USART charcter length is 7bits */ +#define USART_CHAR_LENGTH_8BIT (0x3U << 6U) /*!< USART charcter length is 8bits */ + +#define IS_USART_CHAR_LENGTH(LENGTH) \ + ( \ + ((LENGTH) == USART_CHAR_LENGTH_5BIT) || \ + ((LENGTH) == USART_CHAR_LENGTH_6BIT) || \ + ((LENGTH) == USART_CHAR_LENGTH_7BIT) || \ + ((LENGTH) == USART_CHAR_LENGTH_8BIT) || \ + ((LENGTH) == USART_CHAR_LENGTH9_DISABLE) || \ + ((LENGTH) == USART_CHAR_LENGTH9_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Clock_Select USART clock select + * @{ + */ +#define USART_CLOCK_SELECT_MCK ((uint32_t)0x00000000U) /*!< USART clock source MCK */ +#define USART_CLOCK_SELECT_MCKDIV8 (0x1U << 4U) /*!< USART clock source MCK / 8 */ +#define USART_CLOCK_SELECT_SCK (0x3U << 4U) /*!< USART clock source SCK */ + +#define IS_USART_CLOCK_SELECT(SELECT) \ + ( \ + ((SELECT) == USART_CLOCK_SELECT_MCK ) || \ + ((SELECT) == USART_CLOCK_SELECT_MCKDIV8) || \ + ((SELECT) == USART_CLOCK_SELECT_SCK ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Mode_Operation USART mode of operation + * @{ + */ +#define USART_MODE_OPERATION_NORMAL ((uint32_t)0x00000000U) /*!< USART mode of operation select normal */ +#define USART_MODE_OPERATION_RS485 (0x1U << 0U) /*!< USART mode of operation select rs485 */ +#define USART_MODE_OPERATION_MODEM (0x3U << 0U) /*!< USART mode of operation select mode */ +#define USART_MODE_OPERATION_ISO7816_T_0 (0x4U << 0U) /*!< USART mode of operation select iso7816 protocol: t = 0 */ +#define USART_MODE_OPERATION_ISO7816_T_1 (0x6U << 0U) /*!< USART mode of operation select iso7816 protocol: t = 1 */ +#define USART_MODE_OPERATION_IrDA (0x8U << 0U) /*!< USART mode of operation select irda */ +#define USART_MODE_OPERATION_LIN_MASTER (0xAU << 0U) /*!< USART mode of operation select lin master */ +#define USART_MODE_OPERATION_LIN_SLAVE (0xBU << 0U) /*!< USART mode of operation select lin slave */ +#define USART_MODE_OPERATION_SPI_MASTER (0xEU << 0U) /*!< USART mode of operation select spi master */ +#define USART_MODE_OPERATION_SPI_SLAVE (0xFU << 0U) /*!< USART mode of operation select spi slave */ + +#define IS_USART_MODE_OPERATION(OPERATION) \ + ( \ + ((OPERATION) == USART_MODE_OPERATION_NORMAL ) || \ + ((OPERATION) == USART_MODE_OPERATION_RS485 ) || \ + ((OPERATION) == USART_MODE_OPERATION_MODEM ) || \ + ((OPERATION) == USART_MODE_OPERATION_ISO7816_T_0) || \ + ((OPERATION) == USART_MODE_OPERATION_ISO7816_T_1) || \ + ((OPERATION) == USART_MODE_OPERATION_IrDA ) || \ + ((OPERATION) == USART_MODE_OPERATION_LIN_MASTER ) || \ + ((OPERATION) == USART_MODE_OPERATION_LIN_SLAVE ) || \ + ((OPERATION) == USART_MODE_OPERATION_SPI_MASTER ) || \ + ((OPERATION) == USART_MODE_OPERATION_SPI_SLAVE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_WRDBT USART wait read data before transfer in spi mode + * @{ + */ +#define USART_WRDBT_DISABLE ((uint32_t)0x00000000) /*!< the character transmission starts as soon as a character is written into US_THR in SPI mode */ +#define USART_WRDBT_ENABLE USART_MR_WRDBT /*!< the character transmission starts when a character and only if RXRDY flag is cleared in SPI mode */ + +#define IS_USART_WRDBT(TRANSFER) \ + ( \ + ((TRANSFER) == USART_WRDBT_DISABLE) || \ + ((TRANSFER) == USART_WRDBT_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Clock_Polarity USART Clock Polarity in spi mode + * @{ + */ +#define USART_POLARITY_LOW ((uint32_t)0x00000000) /*!< Driver enable signal is active low in SPI mode */ +#define USART_POLARITY_HIGH USART_MR_CPOL /*!< Driver enable signal is active high in SPI mode */ + +#define IS_USART_POLARITY(POLARITY) \ + ( \ + ((POLARITY) == USART_POLARITY_LOW ) || \ + ((POLARITY) == USART_POLARITY_HIGH) \ + ) +/** + * @} + */ + +/** @defgroup USART_Clock_Phase USART Clock Phase in spi mode + * @{ + */ +#define USART_PHASE_2EDGE ((uint32_t)0x00000000) /*!< USART frame phase on second clock capture */ +#define USART_PHASE_1EDGE USART_MR_CPHA /*!< USART frame phase on first clock capture */ + +#define IS_USART_PHASE(PHASE) \ + ( \ + ((PHASE) == USART_PHASE_2EDGE) || \ + ((PHASE) == USART_PHASE_1EDGE) \ + ) +/** + * @} + */ + +/** @defgroup USART_Mode USART Mode + * @{ + */ +#define USART_MODE_RX USART_CR_RXEN /*!< RX mode enable > */ +#define USART_MODE_TX USART_CR_TXEN /*!< TX mode enable > */ +#define USART_MODE_TX_RX (USART_CR_RXEN | USART_CR_TXEN) /*!< TX & RX mode enable > */ +#define IS_USART_MODE(MODE) \ + ( \ + ((MODE) == USART_MODE_RX ) || \ + ((MODE) == USART_MODE_TX ) || \ + ((MODE) == USART_MODE_TX_RX) \ + ) +/** + * @} + */ + +/** @defgroup USART_Sync_Disable USART synchronization disable in LIN mode + * @{ + */ +#define USART_SYNC_DISABLE_NONE ((uint32_t)0x00000000) /*!< the synchronization procedure is performed in LIN Slave node configuration in LIN mode */ +#define USART_SYNC_DISABLE_ACTIVE USART_LINMR_SYNCDIS /*!< the synchronization procedure is not performed in LIN Slave node configuration in LIN mode */ + +#define IS_USART_SYNC_DISABLE(DISABLE) (((DISABLE) == USART_SYNC_DISABLE_NONE ) || \ + ((DISABLE) == USART_SYNC_DISABLE_ACTIVE)) +/** + * @} + */ + +/** @defgroup USART_PDC_Mode USART dma mode in LIN mode + * @{ + */ +#define USART_PDC_MODE_LINMR_NOTWRITE ((uint32_t)0x00000000) /*!< The LIN mode register LINMR is not writted by the DMA */ +#define USART_PDC_MODE_LINMR_WRITE USART_LINMR_PDCM /*!< The LIN mode register LINMR(excepting that flag) is writted by the DMA */ + +#define IS_USART_PDC_MODE_LINMR(LINMR) \ + ( \ + ((LINMR) == USART_PDC_MODE_LINMR_NOTWRITE) || \ + ((LINMR) == USART_PDC_MODE_LINMR_WRITE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Wkup_Type USART wakeup signal type in LIN mode + * @{ + */ +#define USART_WKUP_TYPE_LIN_2_0 ((uint32_t)0x00000000) /*!< Setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal */ +#define USART_WKUP_TYPE_LIN_1_3 USART_LINMR_WKUPTYP /*!< Setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal */ +#define IS_USART_WKUP_TYPE(TYPE) \ + ( \ + ((TYPE) == USART_WKUP_TYPE_LIN_2_0) || \ + ((TYPE) == USART_WKUP_TYPE_LIN_1_3) \ + ) +/** + * @} + */ + +/** @defgroup USART_Frame_Slot_Disable USART frame slot mode disable in LIN mode + * @{ + */ +#define USART_FRAME_SLOT_DISABLE_NONE ((uint32_t)0x00000000) /*!< The frame slot mode is enabled in LIN mode */ +#define USART_FRAME_SLOT_DISABLE_ACTIVE USART_LINMR_FSDIS /*!< The frame slot mode is disabled in LIN mode */ +#define IS_USART_FRAME_SLOT_DISABLE(DISABLE) \ + ( \ + ((DISABLE) == USART_FRAME_SLOT_DISABLE_NONE ) || \ + ((DISABLE) == USART_FRAME_SLOT_DISABLE_ACTIVE) ) +/** + * @} + */ + +/** @defgroup USART_Data_Length_Mode USART data length mode in LIN mode + * @{ + */ +#define USART_DATA_LENGTH_MODE_DLC ((uint32_t)0x00000000) /*!< The response data length is defined by the field DLC in LIN mode */ +#define USART_DATA_LENGTH_MODE_ID_5_6 USART_LINMR_DLM /*!< The response data length is defined by the bits 5 and 6 of the identifier (IDCHR in LINIR) in LIN mode */ +#define IS_USART_DATA_LENGTH_MODE(MODE) \ + ( \ + ((MODE) == USART_DATA_LENGTH_MODE_DLC ) || \ + ((MODE) == USART_DATA_LENGTH_MODE_ID_5_6) \ + ) +/** + * @} + */ + +/** @defgroup USART_Checksum_Type USART checksum type in LIN mode + * @{ + */ +#define USART_CHECKSUM_TYPE_ENHANCED ((uint32_t)0x00000000) /*!< LIN 2.0 "Enhanced" Checksum */ +#define USART_CHECKSUM_TYPE_CLASSIC USART_LINMR_CHKTYP /*!< LIN 1.3 "Classic " Checksum */ + +#define IS_USART_CHECKSUM_TYPE(TYPE) \ + ( \ + ((TYPE) == USART_CHECKSUM_TYPE_ENHANCED) || \ + ((TYPE) == USART_CHECKSUM_TYPE_CLASSIC ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Checksum_Disable USART checksum disable in LIN mode + * @{ + */ +#define USART_CHECKSUM_DISABLE_NONE ((uint32_t)0x00000000) /*!< LIN Checksum not disable */ +#define USART_CHECKSUM_DISABLE_ACTIVE USART_LINMR_CHKDIS /*!< LIN Checksum disable */ + +#define IS_USART_CHECKSUM_DISABLE(DISABLE) \ + ( \ + ((DISABLE) == USART_CHECKSUM_DISABLE_NONE ) || \ + ((DISABLE) == USART_CHECKSUM_DISABLE_ACTIVE) \ + ) +/** + * @} + */ + +/** @defgroup USART_Parity_Disable USART parity disable in LIN mode + * @{ + */ +#define USART_PARITY_DISABLE_NONE ((uint32_t)0x00000000) /*!< LIN Parity not disable */ +#define USART_PARITY_DISABLE_ACTIVE USART_LINMR_PARDIS /*!< LIN Parity disable */ + +#define IS_USART_PARITY_DISABLE(DISABLE) \ + ( \ + ((DISABLE) == USART_PARITY_DISABLE_NONE ) || \ + ((DISABLE) == USART_PARITY_DISABLE_ACTIVE) \ + ) +/** + * @} + */ + +/** @defgroup USART_Node_Active USART checksum disable in LIN mode + * @{ + */ +#define USART_NODE_ACTIVE_PUBLISH ((uint32_t)0x00000000) /*!< The USART transmits the response */ +#define USART_NODE_ACTIVE_SUBSCRIBE (0x1U << 0U) /*!< The USART receives the response */ +#define USART_NODE_ACTIVE_IGNORE (0x2U << 0U) /*!< The USART does not transmit and does not receive the response */ + +#define IS_USART_NODE_ACTIVE(ACTIVE) \ + ( \ + ((ACTIVE) == USART_NODE_ACTIVE_PUBLISH ) || \ + ((ACTIVE) == USART_NODE_ACTIVE_SUBSCRIBE) || \ + ((ACTIVE) == USART_NODE_ACTIVE_IGNORE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_DMA_TX USART DMA enable transmitter + * @{ + */ +#define USART_DMA_TX_DISABLE ((uint32_t)0x00000000) /*!< DMA mode is disable for transmission */ +#define USART_DMA_TX_ENABLE USART_CR_DMAT_EN /*!< DMA mode is enable for transmission */ + +#define IS_USART_DMA_TX_ENABLE(ENABLE) \ + ( \ + ((ENABLE) == USART_DMA_TX_DISABLE) || \ + ((ENABLE) == USART_DMA_TX_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_DMA_RX USART DMA enable receiver + * @{ + */ +#define USART_DMA_RX_DISABLE ((uint32_t)0x00000000) /*!< DMA mode is disable for reception */ +#define USART_DMA_RX_ENABLE USART_CR_DMAR_EN /*!< DMA mode is enable for reception */ + +#define IS_USART_DMA_RX_ENABLE(ENABLE) \ + ( \ + ((ENABLE) == USART_DMA_RX_DISABLE) || \ + ((ENABLE) == USART_DMA_RX_ENABLE ) \ + ) +/** + * @} + */ + +/** @defgroup USART_Hardware_Flow_Control + * @{ + */ + +#define USART_HardwareFlowControl_None ((uint32_t)0x00000000) +#define USART_HardwareFlowControl_RTS (USART_CR_RTSEN | USART_CR_FCS) +#define USART_HardwareFlowControl_DTR USART_CR_DTREN +#define USART_HardwareFlowControl_RTS_DTR ((USART_CR_RTSEN | USART_CR_FCS) | USART_CR_DTREN) +#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL) \ + ( \ + ((CONTROL) == USART_HardwareFlowControl_None ) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS ) || \ + ((CONTROL) == USART_HardwareFlowControl_DTR ) || \ + ((CONTROL) == USART_HardwareFlowControl_RTS_DTR) \ + ) + +/** + * @} + */ + +/** @defgroup USART_Flags + * @brief Flag mask in the CSR register + * @{ + */ +#define USART_FLAG_CTS USART_CSR_CTS /*!< USART image of CTS input */ +#define USART_FLAG_DSR USART_CSR_DSR /*!< USART image of DSR input */ +#define USART_FLAG_CTSIC USART_CSR_CTSIC /*!< USART Clear to Send input change flag */ +#define USART_FLAG_DSRIC USART_CSR_DSRIC /*!< USART Data Set Ready input change flag */ +#define USART_FLAG_NACK USART_CSR_NACK /*!< USART non acknowledge interrupt */ +#define USART_FLAG_ITER USART_CSR_ITER /*!< USART max number of repetitions reached */ +#define USART_FLAG_TXEMPTY USART_CSR_TXEMPTY /*!< USART transmitter empty */ +#define USART_FLAG_TIMEOUT USART_CSR_TIMEOUT /*!< USART receiver time-out */ +#define USART_FLAG_PARE USART_CSR_PARE /*!< USART parity error */ +#define USART_FLAG_FRAME USART_CSR_FRAME /*!< USART framing error */ +#define USART_FLAG_OVER USART_CSR_OVRE /*!< USART overrun error */ +#define USART_FLAG_RXBRK USART_CSR_RXBRK /*!< USART break receive/end of break */ +#define USART_FLAG_TXRDY USART_CSR_TXRDY /*!< USART transmitter ready */ +#define USART_FLAG_RXRDY USART_CSR_RXRDY /*!< USART receiver ready */ + +#define USART_FLAG_UNRE USART_CSR_UNRE /*!< USART underrun error */ + +#define USART_FLAG_LINHTE USART_CSR_LINHTE /*!< USART LIN header timeout error */ +#define USART_FLAG_LINSTE USART_CSR_LINSTE /*!< USART LIN synch tolerance eror */ +#define USART_FLAG_LINSNRE USART_CSR_LINSNRE /*!< USART LIN slave not response error */ +#define USART_FLAG_LINCE USART_CSR_LINCE /*!< USART LIN checksum error */ +#define USART_FLAG_LINIPE USART_CSR_LINIPE /*!< USART LIN identifier parity error */ +#define USART_FLAG_LINISFE USART_CSR_LINISFE /*!< USART LIN inconsistent synch field error */ +#define USART_FLAG_LINBE USART_CSR_LINBE /*!< USART LIN bit error */ +#define USART_FLAG_LINBLS USART_CSR_LINBLS /*!< USART LIN bus line status */ +#define USART_FLAG_LINTC USART_CSR_LINTC /*!< USART LIN transfer completed */ +#define USART_FLAG_LINID USART_CSR_LINID /*!< USART LIN identifier sent or LIN identifier received */ +#define USART_FLAG_LINBK USART_CSR_LINBK /*!< USART LIN break sent or LIN break received */ +/** + * @} + */ + +/** @defgroup USART_Clear_Flags + * @brief Flag clear in the CR register + * @{ + */ +#define USART_CLEAR_CTSIC USART_CR_RSTTX /*!< USART Clear to Send input interrupt clear */ +#define USART_CLEAR_DSRIC USART_CR_RSTRX /*!< USART Data Set Ready input change clear */ +#define USART_CLEAR_NACK USART_CR_RSTNACK /*!< USART non acknowledge interrupt clear */ +#define USART_CLEAR_ITER USART_CR_RSTIT /*!< USART max number of repetitions reached interrupt clear */ +#define USART_CLEAR_TXEMPTY USART_CR_RSTTX /*!< USART transmitter empty interrupt clear */ +#define USART_CLEAR_TIMEOUT USART_CR_STTTO /*!< USART receiver time-out interrupt clear */ +#define USART_CLEAR_PARE USART_CR_RSTSTA /*!< USART parity error interrupt clear */ +#define USART_CLEAR_FRAME USART_CR_RSTSTA /*!< USART framing error interrupt clear */ +#define USART_CLEAR_OVER USART_CR_RSTSTA /*!< USART overrun error interrupt clear */ +#define USART_CLEAR_RXBRK USART_CR_RSTSTA /*!< USART break receive/end of break interrupt clear */ +#define USART_CLEAR_TXRDY USART_CR_RSTTX /*!< USART transmitter ready interrupt clear */ +#define USART_CLEAR_RXRDY USART_CR_RSTRX /*!< USART receiver ready interrupt clear */ + +#define USART_CLEAR_UNRE USART_CR_RSTSTA /*!< USART underrun error interrupt clear */ + +#define USART_CLEAR_LINHTE USART_CR_RSTSTA /*!< USART LIN header timeout error interrupt clear */ +#define USART_CLEAR_LINSTE USART_CR_RSTSTA /*!< USART LIN synch tolerance eror interrupt clear */ +#define USART_CLEAR_LINSNRE USART_CR_RSTSTA /*!< USART LIN slave not response error interrupt clear */ +#define USART_CLEAR_LINCE USART_CR_RSTSTA /*!< USART LIN checksum error interrupt clear */ +#define USART_CLEAR_LINIPE USART_CR_RSTSTA /*!< USART LIN identifier parity error interrupt clear */ +#define USART_CLEAR_LINISFE USART_CR_RSTSTA /*!< USART LIN inconsistent synch field error interrupt clear */ +#define USART_CLEAR_LINBE USART_CR_RSTSTA /*!< USART LIN bit error interrupt clear */ +#define USART_CLEAR_LINTC USART_CR_RSTSTA /*!< USART LIN transfer completed interrupt clear */ +#define USART_CLEAR_LINID USART_CR_RSTSTA /*!< USART LIN identifier sent or LIN identifier received interrupt clear */ +#define USART_CLEAR_LINBK USART_CR_RSTSTA /*!< USART LIN break sent or LIN break received interrupt clear */ +/** + * @} + */ + +/** @defgroup USART_Interrupt_definition + * @brief Interrupt enable register - IER register + * @{ + */ +#define USART_IT_CTSIC USART_IER_CTSIC /*!< USART Clear to Send input interruption */ +#define USART_IT_DSRIC USART_IER_DSRIC /*!< USART Data Set Ready input change interruption */ +#define USART_IT_NACK USART_IER_NACK /*!< USART non acknowledge interruption */ +#define USART_IT_ITER USART_IER_ITER /*!< USART max number of repetitions reached interruption */ +#define USART_IT_TXEMPTY USART_IER_TXEMPTY /*!< USART transmitter empty interruption */ +#define USART_IT_TIMEOUT USART_IER_TIMEOUT /*!< USART receiver time-out interruption */ +#define USART_IT_PARE USART_IER_PARE /*!< USART parity error interruption */ +#define USART_IT_FRAME USART_IER_FRAME /*!< USART framing error interruption */ +#define USART_IT_OVER USART_IER_OVRE /*!< USART overrun error interruption */ +#define USART_IT_RXBRK USART_IER_RXBRK /*!< USART break receive/end of break interruption */ +#define USART_IT_TXRDY USART_IER_TXRDY /*!< USART transmitter ready interruption */ +#define USART_IT_RXRDY USART_IER_RXRDY /*!< USART receiver ready interruption */ + +#define USART_IT_UNRE USART_IER_UNRE /*!< USART underrun error interruption */ + +#define USART_IT_LINHTE USART_IER_LINHTE /*!< USART LIN header timeout error interruption */ +#define USART_IT_LINSTE USART_IER_LINSTE /*!< USART LIN synch tolerance eror interruption */ +#define USART_IT_LINSNRE USART_IER_LINSNRE /*!< USART LIN slave not response error interruption */ +#define USART_IT_LINCE USART_IER_LINCE /*!< USART LIN checksum error interruption */ +#define USART_IT_LINIPE USART_IER_LINIPE /*!< USART LIN identifier parity error interruption */ +#define USART_IT_LINISFE USART_IER_LINISFE /*!< USART LIN inconsistent synch field error interruption */ +#define USART_IT_LINBE USART_IER_LINBE /*!< USART LIN bit error interruption */ +#define USART_IT_LINTC USART_IER_LINTC /*!< USART LIN transfer completed interruption */ +#define USART_IT_LINID USART_IER_LINID /*!< USART LIN identifier sent or LIN identifier received interruption */ +#define USART_IT_LINBK USART_IER_LINBK /*!< USART LIN break sent or LIN break received interruption */ +/** + * @} + */ + +/** @defgroup USART_Interrupt_disable + * @brief Interrupt disable register - IDR register + * @{ + */ +#define USART_DIS_CTSIC USART_IDR_CTSIC /*!< USART Clear to Send input interrupt disable */ +#define USART_DIS_DSRIC USART_IDR_DSRIC /*!< USART Data Set Ready input change interrupt disable */ +#define USART_DIS_NACK USART_IDR_NACK /*!< USART non acknowledge interrupt disable */ +#define USART_DIS_ITER USART_IDR_ITER /*!< USART max number of repetitions reached interrupt disable */ +#define USART_DIS_TXEMPTY USART_IDR_TXEMPTY /*!< USART transmitter empty interrupt disable */ +#define USART_DIS_TIMEOUT USART_IDR_TIMEOUT /*!< USART receiver time-out interrupt disable */ +#define USART_DIS_PARE USART_IDR_PARE /*!< USART parity error interrupt disable */ +#define USART_DIS_FRAME USART_IDR_FRAME /*!< USART framing error interrupt disable */ +#define USART_DIS_OVER USART_IDR_OVRE /*!< USART overrun error interrupt disable */ +#define USART_DIS_RXBRK USART_IDR_RXBRK /*!< USART break receive/end of break interrupt disable */ +#define USART_DIS_TXRDY USART_IDR_TXRDY /*!< USART transmitter ready interrupt disable */ +#define USART_DIS_RXRDY USART_IDR_RXRDY /*!< USART receiver ready interrupt disable */ + +#define USART_DIS_UNRE USART_IDR_UNRE /*!< USART underrun error interrupt disable */ + +#define USART_DIS_LINHTE USART_IDR_LINHTE /*!< USART LIN header timeout error interrupt disable */ +#define USART_DIS_LINSTE USART_IDR_LINSTE /*!< USART LIN synch tolerance eror interrupt disable */ +#define USART_DIS_LINSNRE USART_IDR_LINSNRE /*!< USART LIN slave not response error interrupt disable */ +#define USART_DIS_LINCE USART_IDR_LINCE /*!< USART LIN checksum error interrupt disable */ +#define USART_DIS_LINIPE USART_IDR_LINIPE /*!< USART LIN identifier parity error interrupt disable */ +#define USART_DIS_LINISFE USART_IDR_LINISFE /*!< USART LIN inconsistent synch field error interrupt disable */ +#define USART_DIS_LINBE USART_IDR_LINBE /*!< USART LIN bit error interrupt disable */ +#define USART_DIS_LINTC USART_IDR_LINTC /*!< USART LIN transfer completed interrupt disable */ +#define USART_DIS_LINID USART_IDR_LINID /*!< USART LIN identifier sent or LIN identifier received interrupt disable */ +#define USART_DIS_LINBK USART_IDR_LINBK /*!< USART LIN break sent or LIN break received interrupt disable */ +/** + * @} + */ + +/** @defgroup USART_Interruption_Mask + * @brief Interrupt mask register - IMR register + * @{ + */ +#define USART_MASK_CTSIC USART_IMR_CTSIC /*!< USART Clear to Send input interrupt mask */ +#define USART_MASK_DSRIC USART_IMR_DSRIC /*!< USART Data Set Ready input change mask */ +#define USART_MASK_NACK USART_IMR_NACK /*!< USART non acknowledge interrupt mask */ +#define USART_MASK_ITER USART_IMR_ITER /*!< USART max number of repetitions reached interrupt mask */ +#define USART_MASK_TXEMPTY USART_IMR_TXEMPTY /*!< USART transmitter empty interrupt mask */ +#define USART_MASK_TIMEOUT USART_IMR_TIMEOUT /*!< USART receiver time-out interrupt mask */ +#define USART_MASK_PARE USART_IMR_PARE /*!< USART parity error interrupt mask */ +#define USART_MASK_FRAME USART_IMR_FRAME /*!< USART framing error interrupt mask */ +#define USART_MASK_OVER USART_IMR_OVRE /*!< USART overrun error interrupt mask */ +#define USART_MASK_RXBRK USART_IMR_RXBRK /*!< USART break receive/end of break interrupt mask */ +#define USART_MASK_TXRDY USART_IMR_TXRDY /*!< USART transmitter ready interrupt mask */ +#define USART_MASK_RXRDY USART_IMR_RXRDY /*!< USART receiver ready interrupt mask */ + +#define USART_MASK_UNRE USART_IMR_UNRE /*!< USART underrun error interrupt mask */ + +#define USART_MASK_LINHTE USART_IMR_LINHTE /*!< USART LIN header timeout error interrupt mask */ +#define USART_MASK_LINSTE USART_IMR_LINSTE /*!< USART LIN synch tolerance eror interrupt mask */ +#define USART_MASK_LINSNRE USART_IMR_LINSNRE /*!< USART LIN slave not response error interrupt mask */ +#define USART_MASK_LINCE USART_IMR_LINCE /*!< USART LIN checksum error interrupt mask */ +#define USART_MASK_LINIPE USART_IMR_LINIPE /*!< USART LIN identifier parity error interrupt mask */ +#define USART_MASK_LINISFE USART_IMR_LINISFE /*!< USART LIN inconsistent synch field error interrupt mask */ +#define USART_MASK_LINBE USART_IMR_LINBE /*!< USART LIN bit error interrupt mask */ +#define USART_MASK_LINTC USART_IMR_LINTC /*!< USART LIN transfer completed interrupt mask */ +#define USART_MASK_LINID USART_IMR_LINID /*!< USART LIN identifier sent or LIN identifier received interrupt mask */ +#define USART_MASK_LINBK USART_IMR_LINBK /*!< USART LIN break sent or LIN break received interrupt mask */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup USART_Exported_Macros USART Exported Macros + * @{ + */ + +/** @brief Check whether the specified USART flag is set or not. + * @param None + * @retval None + */ +#define IS_USART_GET_FLAG(FLAG) \ + ( \ + ((FLAG) == USART_FLAG_CTS ) || \ + ((FLAG) == USART_FLAG_DSR ) || \ + ((FLAG) == USART_FLAG_CTSIC ) || \ + ((FLAG) == USART_FLAG_DSRIC ) || \ + ((FLAG) == USART_FLAG_NACK ) || \ + ((FLAG) == USART_FLAG_ITER ) || \ + ((FLAG) == USART_FLAG_TXEMPTY) || \ + ((FLAG) == USART_FLAG_TIMEOUT) || \ + ((FLAG) == USART_FLAG_PARE ) || \ + ((FLAG) == USART_FLAG_FRAME ) || \ + ((FLAG) == USART_FLAG_OVER ) || \ + ((FLAG) == USART_FLAG_RXBRK ) || \ + ((FLAG) == USART_FLAG_TXRDY ) || \ + ((FLAG) == USART_FLAG_RXRDY ) || \ + ((FLAG) == USART_FLAG_UNRE ) || \ + ((FLAG) == USART_FLAG_LINHTE ) || \ + ((FLAG) == USART_FLAG_LINSTE ) || \ + ((FLAG) == USART_FLAG_LINSNRE) || \ + ((FLAG) == USART_FLAG_LINCE ) || \ + ((FLAG) == USART_FLAG_LINIPE ) || \ + ((FLAG) == USART_FLAG_LINISFE) || \ + ((FLAG) == USART_FLAG_LINBE ) || \ + ((FLAG) == USART_FLAG_LINBLS ) || \ + ((FLAG) == USART_FLAG_LINTC ) || \ + ((FLAG) == USART_FLAG_LINID ) || \ + ((FLAG) == USART_FLAG_LINBK ) \ + ) + +/** @brief Clear the specified USART pending flag enable. + * @param None + * @retval None + */ +#define IS_USART_CLEAR_FLAG(FLAG) \ + ( \ + ((FLAG) == USART_CLEAR_CTSIC ) || \ + ((FLAG) == USART_CLEAR_DSRIC ) || \ + ((FLAG) == USART_CLEAR_NACK ) || \ + ((FLAG) == USART_CLEAR_ITER ) || \ + ((FLAG) == USART_CLEAR_TXEMPTY) || \ + ((FLAG) == USART_CLEAR_TIMEOUT) || \ + ((FLAG) == USART_CLEAR_PARE ) || \ + ((FLAG) == USART_CLEAR_FRAME ) || \ + ((FLAG) == USART_CLEAR_OVER ) || \ + ((FLAG) == USART_CLEAR_RXBRK ) || \ + ((FLAG) == USART_CLEAR_TXRDY ) || \ + ((FLAG) == USART_CLEAR_RXRDY ) || \ + ((FLAG) == USART_CLEAR_UNRE ) || \ + ((FLAG) == USART_CLEAR_LINHTE ) || \ + ((FLAG) == USART_CLEAR_LINSTE ) || \ + ((FLAG) == USART_CLEAR_LINSNRE) || \ + ((FLAG) == USART_CLEAR_LINCE ) || \ + ((FLAG) == USART_CLEAR_LINIPE ) || \ + ((FLAG) == USART_CLEAR_LINISFE) || \ + ((FLAG) == USART_CLEAR_LINBE ) || \ + ((FLAG) == USART_CLEAR_LINTC ) || \ + ((FLAG) == USART_CLEAR_LINID ) || \ + ((FLAG) == USART_CLEAR_LINBK ) \ + ) + +/** @brief Enable the specified USART interrupt. + * @param None + * @retval None + */ +#define IS_USART_ENABLE_IT(IT) \ + ( \ + ((IT) == USART_IT_CTSIC ) || \ + ((IT) == USART_IT_DSRIC ) || \ + ((IT) == USART_IT_NACK ) || \ + ((IT) == USART_IT_ITER ) || \ + ((IT) == USART_IT_TXEMPTY) || \ + ((IT) == USART_IT_TIMEOUT) || \ + ((IT) == USART_IT_PARE ) || \ + ((IT) == USART_IT_FRAME ) || \ + ((IT) == USART_IT_OVER ) || \ + ((IT) == USART_IT_RXBRK ) || \ + ((IT) == USART_IT_TXRDY ) || \ + ((IT) == USART_IT_RXRDY ) || \ + ((IT) == USART_IT_UNRE ) || \ + ((IT) == USART_IT_LINHTE ) || \ + ((IT) == USART_IT_LINSTE ) || \ + ((IT) == USART_IT_LINSNRE) || \ + ((IT) == USART_IT_LINCE ) || \ + ((IT) == USART_IT_LINIPE ) || \ + ((IT) == USART_IT_LINISFE) || \ + ((IT) == USART_IT_LINBE ) || \ + ((IT) == USART_IT_LINTC ) || \ + ((IT) == USART_IT_LINID ) || \ + ((IT) == USART_IT_LINBK ) \ + ) + +/** @brief Disable the specified USART interrupt. + * @param None + * @retval None + */ +#define IS_USART_CLEAR_IT(IT) \ + ( \ + ((IT) == USART_DIS_CTSIC ) || \ + ((IT) == USART_DIS_DSRIC ) || \ + ((IT) == USART_DIS_NACK ) || \ + ((IT) == USART_DIS_ITER ) || \ + ((IT) == USART_DIS_TXEMPTY) || \ + ((IT) == USART_DIS_TIMEOUT) || \ + ((IT) == USART_DIS_PARE ) || \ + ((IT) == USART_DIS_FRAME ) || \ + ((IT) == USART_DIS_OVER ) || \ + ((IT) == USART_DIS_RXBRK ) || \ + ((IT) == USART_DIS_TXRDY ) || \ + ((IT) == USART_DIS_RXRDY ) || \ + ((IT) == USART_DIS_UNRE ) || \ + ((IT) == USART_DIS_LINHTE ) || \ + ((IT) == USART_DIS_LINSTE ) || \ + ((IT) == USART_DIS_LINSNRE) || \ + ((IT) == USART_DIS_LINCE ) || \ + ((IT) == USART_DIS_LINIPE ) || \ + ((IT) == USART_DIS_LINISFE) || \ + ((IT) == USART_DIS_LINBE ) || \ + ((IT) == USART_DIS_LINTC ) || \ + ((IT) == USART_DIS_LINID ) || \ + ((IT) == USART_DIS_LINBK ) \ + ) + + +/** @brief Check whether the specified USART interrupt has occurred or not. + * @param None + * @retval None + */ +#define IS_USART_GET_IT(IT) \ + ( \ + ((IT) == USART_MASK_CTSIC ) || \ + ((IT) == USART_MASK_DSRIC ) || \ + ((IT) == USART_MASK_NACK ) || \ + ((IT) == USART_MASK_ITER ) || \ + ((IT) == USART_MASK_TXEMPTY) || \ + ((IT) == USART_MASK_TIMEOUT) || \ + ((IT) == USART_MASK_PARE ) || \ + ((IT) == USART_MASK_FRAME ) || \ + ((IT) == USART_MASK_OVER ) || \ + ((IT) == USART_MASK_RXBRK ) || \ + ((IT) == USART_MASK_TXRDY ) || \ + ((IT) == USART_MASK_RXRDY ) || \ + ((IT) == USART_MASK_UNRE ) || \ + ((IT) == USART_MASK_LINHTE ) || \ + ((IT) == USART_MASK_LINSTE ) || \ + ((IT) == USART_MASK_LINSNRE) || \ + ((IT) == USART_MASK_LINCE ) || \ + ((IT) == USART_MASK_LINIPE ) || \ + ((IT) == USART_MASK_LINISFE) || \ + ((IT) == USART_MASK_LINBE ) || \ + ((IT) == USART_MASK_LINTC ) || \ + ((IT) == USART_MASK_LINID ) || \ + ((IT) == USART_MASK_LINBK ) \ + ) + +/** + * @} + */ + +/** @defgroup USART_Global_definition + * @{ + */ +#define IS_USART_BAUDRATE(BAUDRATE) ((BAUDRATE ) <= 105000000U) +#define IS_USART_BAUDRATE_APB1(BAUDRATE) ((BAUDRATE ) <= 52500000U ) +#define IS_USART_FIDIRATIO(FIDIRATE) ((FIDIRATE ) <= 2047U ) +#define IS_USART_IF(IF) ((IF ) <= 0xFFU ) +#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT ) <= 0x1FFFF ) +#define IS_USART_TIMGUARD(TIMEGUARD) ((TIMEGUARD) <= 0xFF ) +#define IS_USART_LINIR_WR(LINIR_WR) ((LINIR_WR ) <= 0xFF ) +#define IS_USART_DATA(DATA) ((DATA ) <= 0x1FF ) +#define IS_USART_DLC(DATA) ((DATA ) <= 0xFF ) + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_Exported_Functions USART Exported Functions + * @{ + */ +/* Initialization and de-initialization functions *****************************/ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_DeInit(USART_TypeDef* USARTx); + +/* Normal command and configuration functions *********************************/ +/* Normal Cmd */ void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Hardware Cmd */ void USART_RTSDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Hardware Cmd */ void USART_RTSEN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Hardware Cmd */ void USART_DTRDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Hardware Cmd */ void USART_DTREN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_RSTSTA_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_TXDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_TXEN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_RXDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_RXEN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_RSTTX_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_RSTRX_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_InvData_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_OverSampling8_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_ClkOutput_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_DataLength9_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_MSBFirst_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_ChannelMode_Cfg(USART_TypeDef* USARTx, uint32_t USART_ChannelMode); +/* Normal Cfg */ void USART_StopBit_Cfg(USART_TypeDef* USARTx, uint32_t USART_StopBits); +/* Normal Cfg */ void USART_Parity_Cfg(USART_TypeDef* USARTx, uint32_t USART_Parity); +/* Normal Cfg */ void USART_SYNCMode_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_DataLength_Cfg(USART_TypeDef* USARTx, uint32_t USART_WordLength); +/* Normal Cfg */ void USART_CLKSelect_Cfg(USART_TypeDef* USARTx, uint32_t USART_CLKSelect); +/* Normal Cfg */ void USART_OperationMode_Cfg(USART_TypeDef* USARTx, uint32_t USART_OperationMode); + +/* Fractional baudrate function ***********************************************/ +/* Normal Cfg */ void USART_FracDivider_Cfg(USART_TypeDef* USARTx, uint32_t USART_BaudRate); + +/* Break command functions ****************************************************/ +/* Normal Cmd */ void USART_STPBRK_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_STTBRK_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Receiver time-out and transmitter timeguard functions **********************/ +/* Normal Cfg */ void USART_Receiver_TimeOut_Cfg(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut); +/* Normal Cmd */ void USART_RETTO_After_Timeout_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cmd */ void USART_STTTO_After_Timeout_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* Normal Cfg */ void USART_Transmitter_TimeGuard_Cfg(USART_TypeDef* USARTx, uint32_t USART_TransmitterTimeGuard); + +/* Multidrop mode command function ********************************************/ +/* Normal Cmd */ void USART_SENDAInMultidropMode_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* SPI mode functions *********************************************************/ +/* SPI Cmd */ void USART_RCS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* SPI Cmd */ void USART_FCS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* SPI Cfg */ void USART_WRDBT_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* SPI Cfg */ void USART_CLKPolarity_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* SPI Cfg */ void USART_CLKPhase_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); + +/* ISO7816 mode functions *****************************************************/ +/* ISO7816_T0 Cmd */ void USART_RSTNACK_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* ISO7816_T0 Cmd */ void USART_RSTIT_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* ISO7816_T0 Cfg */ void USART_MaxIteration_Cfg(USART_TypeDef* USARTx, uint32_t USART_MAXIteration); +/* ISO7816_T0 Cfg */ void USART_DsNack_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* ISO7816_T0 Cfg */ void USART_INack_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* ISO7816_T0 Read */ uint32_t USART_GetNumberOfError(USART_TypeDef* USARTx); +/* ISO7816 Cfg */ void USART_FiDiRatio_Cfg(USART_TypeDef* USARTx, uint32_t USART_FiDiRatio, uint32_t USART_BaudRate); + +/* IrDA mode function *********************************************************/ +/* IrDA Cfg */ void USART_IrDAFilter_Cfg(USART_TypeDef* USARTx, uint32_t USART_IrDAFilter); + +/* LIN mode functions *********************************************************/ +/* LIN Cmd */ void USART_LINWKUP_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cmd */ void USART_LINABT_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_Write_LINIR_In_LIN_Master(USART_TypeDef* USARTx, uint32_t USART_LINIR_Data); +/* LIN Read */ uint32_t USART_Read_LINIR_In_LIN_Slave(USART_TypeDef* USARTx); +/* LIN Cfg */ void USART_SYNCDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_PDCMode_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_DataLengthControl_Cfg(USART_TypeDef* USARTx, uint32_t USART_DataLengthControl); +/* LIN Cfg */ void USART_WkupType_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_FrameSlotDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_DataLengthMode_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_CheckSumType_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_CheckSumDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_ParityDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState); +/* LIN Cfg */ void USART_NodeAction_Cfg(USART_TypeDef* USARTx, uint32_t USART_NodeAction); +/* LIN Read */ uint32_t USART_LINBaudRate(USART_TypeDef* USARTx); + +/* Write protection register mode functions ***********************************/ +void USART_WriteProtectionRegisterConfig(USART_WP_TypeDef* USARTx_WP, FunctionalState NewState); +FlagStatus USART_GetWriteProtectionRegisterStatus(USART_WP_TypeDef* USARTx_WP); +uint32_t USART_GetWriteProtectionRegisterSource(USART_WP_TypeDef* USARTx_WP); +uint32_t USART_ClearWPSRField(USART_WP_TypeDef* USARTx_WP); + +/* Data transfers functions ***************************************************/ +void USART_Transmit(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_Receive(USART_TypeDef* USARTx); + +/* DMA transfers management functions *****************************************/ +void USART_DMATxEnable_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_DMARxEnable_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Low-Power SLEEP wakeup management function *********************************/ +void USART_LowPowerSleepWkupConfig(USART_TypeDef* USARTx, FunctionalState NewState); + +/* Interrupts and flags management functions **********************************/ +void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT); +void USART_ITDisableConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4XX_USART_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usb_fs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usb_fs.h new file mode 100644 index 00000000000..082bb1656ce --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usb_fs.h @@ -0,0 +1,472 @@ +/** + ****************************************************************************** + * @file ft32f4xx_usb_fs.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the USB_OTG_FS + * >>->-and USB_OTG_FS firmware library. + * @version V1.0.0 + * @data 2025-05-28 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_USB_FS_H +#define __FT32F4XX_USB_FS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +#if defined (USB_OTG_FS) + + +/* Exported types ------------------------------------------------------------*/ + +#ifndef BYTE + typedef unsigned char BYTE; +#endif +#ifndef WORD + typedef unsigned short WORD; +#endif + +/** + * @brief Register read/write macros + */ + +#define READ_BYTE(addr) *((BYTE *)(addr)) +#define WRITE_BYTE(addr,data) *((BYTE *)(addr)) = data + + +#if !defined(UNUSED) +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ +#endif /* UNUSED */ + + +/** + * @brief USB Mode definition + */ + +typedef enum +{ + USB_FS_DEVICE_MODE = 0, + USB_FS_HOST_MODE = 1, + USB_FS_DRD_MODE = 2 +} USB_FS_ModeTypeDef; + +/** + * @brief URB States definition + * URB : USB Request Block + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_ERROR, + URB_STALL +} USB_OTG_FS_URBStateTypeDef; + +/** + * @brief host endpoint state definition + */ +typedef enum +{ + EP_IDLE = 0, + EP_XFRC, + EP_HALTED, + EP_ACK, + EP_NAK, + EP_NYET, + EP_STALL, + EP_XACTERR, + EP_BBLERR, + EP_DATATGLERR +} USB_OTG_FS_HEPStateTypeDef; + +/** + * @brief host endpoint control state definition + */ +typedef enum +{ + CTRL_SETUP_P = 0, + CTRL_DATA, + CTRL_STATUS, +} USB_OTG_FS_CtlStateTypeDef; + +/** + * @brief USB OTG Initialization Structure definition + */ +typedef struct +{ + uint32_t endpoints; /*!< Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t Host_eps; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint8_t OTGState; /*!< OTG State. */ + +} USB_OTG_FS_CfgTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ep_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t epnum; /*!< Endpoint number. index register value + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t XferSize; /*!< OTG Channel transfer size. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + + uint8_t interval; /* host tx or rx interval/nakmit*/ + + USB_OTG_FS_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_FS_HEPStateTypeDef state; /*!< Host endpoint state. + This parameter can be any value of @ref USB_OTG_HEPStateTypeDef */ + USB_OTG_FS_CtlStateTypeDef ctrl_state; /*control state + this parameter can be any value of @ref USB_OTG_CtlStateTypeDef */ +} USB_OTG_FS_HEPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type */ + + uint16_t maxpacket; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t data_pid_start; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t xfer_size; /*!< OTG endpoint transfer size. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ +} USB_OTG_FS_DEPTypeDef; + +/** + *@brief USB_FS status structures definition + */ +typedef enum +{ + USB_FS_OK = 0x00U, + USB_FS_ERROR = 0x01U, + USB_FS_BUSY = 0x02U, +} USB_FS_StatusTypeDef; + +/** + *@brief USB_FS lock status structures definition + */ +typedef enum +{ + USB_FS_UNLOCKED = 0x00U, + USB_FS_LOCKED = 0x01U, +} USB_FS_LockTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +#if defined (USB_OTG_FS) + +#define VBUS_MASK 0x70U + +#define ADDR_FIFO_EP0 OTG_FS_BASE + 0x20U + +#define VBUS_BELOW_SESSION_END 0 +#define VBUS_ABOVE_SESSION_END 1 +#define VBUS_ABOVE_AVALID 2 +#define VBUS_ABOVE_VBUS_VALID 3 +#define VBUS_ERROR 256 + +#define USB_FS_EPNUM 4U /* ep0 + ep1~3 */ +#define EP0_SIZE 64 + + + +#define AB_IDLE 0x00 +#define WAIT_VRISE 0x01 + +#define A_PERIPHERAL 0x21 +#define A_WAIT_BCON 0x22 +#define A_HOST 0x23 +#define A_SUSPEND 0x24 + +#define B_PERIPHERAL 0x11 +#define B_WAIT_ACON 0x12 +#define B_HOST 0x13 +#define B_SRP_INIT 0x14 + +#define S_TRANSITION 0x30 + +/* Using bitstuffing of (7/6) * 8 * bytecount : Sec 5.11.3 */ +#define BitTransferTime(byte_count) (7 * 8 * byte_count / 6) +#define USB_DELAY (1000L) /* Temp : Info from HW Team reqd */ +#define USB_LS_SETUP_TIME (1000L) /* Temp : Info from HW Team reqd */ + +/* Low Speed : 1.5 MBPS -> 1 Frame = 1 msec Hence 1.5 * 1000 * 1000 / 1000 */ +#define USB_LS_FRAME_BITS 1500L + +/* Full Speed : 12 MBPS -> 1 Frame = 1 msec. Hence 12 * 1000 * 1000 / 1000 */ +#define USB_FS_FRAME_BITS 12000L + +/* Frame Time in Micro Sec : Max is 90 % for Low and Full SPeed + * 1 Frame = 1 msec = 1000 micro Sec + * 90 % of it is = 90 * 1000 / 100 = 900 micro sec + */ +#define USB_FRAME_MAX_USECS_ALLOC (900L) + +#define FRAME_OFFSET (1) +#define MAX_POLLING_INTERVAL (255) + + + +/** @defgroup USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 4U + + + +/** @defgroup USB Device Speed + * @{ + */ +#define USB_FS_SPEED 0U +#define USB_LS_SPEED 1U +/** + * @} + */ + +/** @defgroup USB_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_FULL 0U +#define USB_OTG_SPEED_LOW 1U + +#define FIFO_TX 0U +#define FIFO_RX 1U + +/** + * @} + */ + +/** @defgroup USB_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_FS_MAX_BULK_PACKET_SIZE 64U +#define USB_OTG_FS_MAX_INTR_PACKET_SIZE 64U +#define USB_OTG_LS_MAX_INTR_PACKET_SIZE 8U +#define USB_OTG_FS_MAX_ISOC_PACKET_SIZE 1023U +/** + * @} + */ + + +#endif /* USB_OTG_FS */ + + +/** @defgroup USB_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +/** + * @} + */ + +/** @defgroup USB_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U + + +#define EP_PID_DATA0 0U +#define EP_PID_DATA2 1U +#define EP_PID_DATA1 2U +#define EP_PID_SETUP 3U + +/** + * @} + */ + +#define EP_ADDR_MSK 0xFU + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_Exported_Macros USB Low Layer Exported Macros + * @{ + */ + + +#define __USB_FS_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == USB_FS_LOCKED) \ + { \ + return USB_FS_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = USB_FS_LOCKED; \ + } \ + }while (0U) + +#define __USB_FS_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = USB_FS_UNLOCKED; \ + }while (0U) + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_FS_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_FS) + +USB_FS_StatusTypeDef USB_FS_CoreInit(void); +USB_FS_StatusTypeDef USB_FS_DevInit(USB_OTG_FS_CfgTypeDef cfg); +USB_FS_StatusTypeDef USB_FS_HostInit(USB_OTG_FS_CfgTypeDef cfg); +USB_FS_StatusTypeDef USB_FS_IndexSel(uint8_t epnum); +USB_FS_StatusTypeDef USB_FS_RstEP0Regs(void); +USB_FS_StatusTypeDef USB_FS_RstEPRegs(uint8_t epnum); +USB_FS_StatusTypeDef USB_FS_FlushEp0Fifo(void); +USB_FS_StatusTypeDef USB_FS_FlushTxFifo(uint8_t epnum); +USB_FS_StatusTypeDef USB_FS_FlushRxFifo(uint8_t epnum); +USB_FS_StatusTypeDef USB_FS_SendStall(USB_OTG_FS_DEPTypeDef *dep); +USB_FS_StatusTypeDef USB_FS_ClrStall(USB_OTG_FS_DEPTypeDef *dep); +USB_FS_StatusTypeDef USB_FS_HEP_Init(uint8_t epnum, uint8_t dev_address, + uint8_t ep_type, uint8_t interval, + uint16_t xfersize); +int32_t usb_log2(int32_t x); +uint32_t USB_FS_Get_VBusStatus(void); +uint16_t USB_FS_Read_RxCount(void); +uint32_t USB_FS_GetCurrentFrame(void); +uint32_t USB_FS_GetSpeed(void); +uint8_t USB_FS_Read_Count0(void); +uint8_t USB_FS_GetMode(void); +uint8_t USB_FS_GetCID(void); +uint8_t USB_FS_GetAddress(void); +uint8_t USB_FS_GetPower(void); +uint8_t USB_FS_GetrDevctl(void); +int8_t USB_FS_Exiting_Host(uint8_t toOTG, USB_OTG_FS_CfgTypeDef *cfg); +uint32_t USB_FS_ReadInterrupts(void); + +void USB_FS_Enable_HEP(USB_OTG_FS_HEPTypeDef *hep); +void USB_FS_Enable_DEP(USB_OTG_FS_DEPTypeDef *dep); +void USB_FS_DEPStartXfer(USB_OTG_FS_DEPTypeDef *dep); +void USB_FS_DEP0StartXfer(USB_OTG_FS_DEPTypeDef *dep); +void USB_FS_HEP_StartXfer(USB_OTG_FS_HEPTypeDef *hep); +void USB_FS_HEP0_StartXfer(USB_OTG_FS_HEPTypeDef *hep, uint8_t ctl_state); +void USB_FS_FIFORead(uint8_t *dstP, uint8_t ep_num, uint16_t len); +void USB_FS_FIFOWrite(uint8_t *srcP, uint8_t ep_num, uint16_t len); +//void USB_FS_IntHandle(void); +void USB_FS_SetEPInt(uint8_t cfg); +void USB_FS_SetUSBInt(uint8_t cfg); +void USB_FS_ClrUSBInt(void); +void USB_FS_ClrEPInt(void); +void USB_FS_SetTxFiFo(uint8_t epnum, uint8_t size, uint8_t address, uint8_t dpb); +void USB_FS_SetRxFiFo(uint8_t epnum, uint8_t size, uint8_t address, uint8_t dpb); +void USB_FS_DrvSess(uint8_t state); +void USB_FS_Set_Polling_Interval(uint8_t epdir, uint8_t interval); +void USB_FS_Set_NAKLMT(uint8_t epnum, uint8_t epdir, uint8_t naklmt); +void USB_FS_SetAddress(uint8_t address); +void USB_FS_SetPower(uint8_t powercfg); +void USB_FS_ClrPower(uint8_t powercfg); +void USB_FS_SetDevctl(uint8_t cfg); +void USB_FS_ClrDevctl(uint8_t cfg); +void USB_FS_Activate_Resume(void); +void USB_FS_DeActivate_Resume(void); +void USB_FS_ResetPort(void); +void USB_FS_Enable_Suspend(void); +void USB_FS_Disable_Suspend(void); +void USB_FS_ActivateSetup(void); + + +#endif /* defined (USB_OTG_FS) */ + + +#endif /* defined (USB_OTG_FS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* FT32F4xx_USB_FS_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usb_hs.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usb_hs.h new file mode 100644 index 00000000000..9f14c6b3397 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_usb_hs.h @@ -0,0 +1,585 @@ +/** + ****************************************************************************** + * @file ft32f4xx_usb_hs.h + * @author FMD XA + * @brief This file contains all the functions prototypes for the USB_OTG_FS + * >>->-and USB_OTG_HS firmware library. + * @version V1.0.0 + * @data 2025-03-20 + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4XX_USB_HS_H +#define __FT32F4XX_USB_HS_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +#if defined (USB_OTG_HS) +/** @addtogroup ft32f4xx Drive + * @ + */ + +/** @addtogroup USB_OTG_HS + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +#ifndef USB_TIMEOUT +#define USB_TIMEOUT 0xF000000U +#endif /* define USB_TIMEOUT */ + +#ifndef USB_HS_CURRENT_MODE_MAX_DELAY_MS +#define USB_HS_CURRENT_MODE_MAX_DELAY_MS 200U +#endif /* define USB_HS_CURRENT_MODE_MAX_DELAY_MS */ + + +/* compile define */ +//struct __attribute__((packed)) T_UINT32_READ{ +// uint32_t v; +//}; +//#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + +//struct __attribute__((packed)) T_UINT32_WRITE{ +// uint32_t v; +//}; +//#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + +#if !defined(UNUSED) +#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */ +#endif /* UNUSED */ + +/** + * @brief USB Mode definition + */ + +typedef enum +{ + USB_DEVICE_MODE = 0, + USB_HOST_MODE = 1, + USB_DRD_MODE = 2 +} USB_ModeTypeDef; + +/** + * @brief URB States definition + * URB : USB Request Block + */ +typedef enum +{ + URB_IDLE = 0, + URB_DONE, + URB_NOTREADY, + URB_NYET, + URB_ERROR, + URB_STALL +} USB_OTG_HS_URBStateTypeDef; + +/** + * @brief Host channel States definition + */ +typedef enum +{ + HC_IDLE = 0, + HC_XFRC, + HC_HALTED, + HC_ACK, + HC_NAK, + HC_NYET, + HC_STALL, + HC_XACTERR, + HC_BBLERR, + HC_DATATGLERR +} USB_OTG_HS_HCStateTypeDef; + +/** + * @brief USB OTG Initialization Structure definition + */ +typedef struct +{ + uint32_t dev_endpoints; /*!< Device Endpoints number. + This parameter depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t Host_channels; /*!< Host Channels number. + This parameter Depends on the used USB core. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t speed; /*!< USB Core speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint32_t dma_enable; /*!< Enable or disable of the USB embedded DMA used only for OTG HS. */ + + uint32_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ + + uint32_t low_power_enable; /*!< Enable or disable the low power mode. */ + + uint32_t bvalid_override_enable; /*!< Enable or disable the bvalid value override feature. */ + + uint32_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ + +} USB_OTG_HS_CfgTypeDef; + +typedef struct +{ + uint8_t num; /*!< Endpoint number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_stall; /*!< Endpoint stall condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t is_iso_incomplete; /*!< Endpoint isoc condition + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t type; /*!< Endpoint type + This parameter can be any value of @ref USB_LL_EP_Type */ + + uint8_t data_pid_start; /*!< Initial data PID + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t even_odd_frame; /*!< IFrame parity + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint16_t tx_fifo_num; /*!< Transmission FIFO number + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint32_t maxpacket; /*!< Endpoint Max packet size + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ + + uint32_t xfer_len; /*!< Current transfer length */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ + + uint32_t xfer_size; /*!< Requested transfer size */ +} USB_OTG_HS_EPTypeDef; + +typedef struct +{ + uint8_t dev_addr; /*!< USB device address. + This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ + + uint8_t ch_num; /*!< Host channel number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_num; /*!< Endpoint number. + This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ + + uint8_t ep_is_in; /*!< Endpoint direction + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t speed; /*!< USB Host Channel speed. + This parameter can be any value of @ref USB_Core_Speed_ */ + + uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ + uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ + uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ + uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule. */ + uint8_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ + + uint8_t hub_port_nbr; /*!< USB HUB port number */ + uint8_t hub_addr; /*!< USB HUB address */ + + uint8_t ep_type; /*!< Endpoint Type. + This parameter can be any value of @ref USB_EP_Type */ + + uint16_t max_packet; /*!< Endpoint Max packet size. + This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ + + uint8_t data_pid; /*!< Initial data PID. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ + + uint32_t XferSize; /*!< OTG Channel transfer size. */ + + uint32_t xfer_len; /*!< Current transfer length. */ + + uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ + + uint8_t toggle_in; /*!< IN transfer current toggle flag. + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint8_t toggle_out; /*!< OUT transfer current toggle flag + This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ + + uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ + + uint32_t ErrCnt; /*!< Host channel error count. */ + uint32_t NyetErrCnt; /*!< Complete split NYET Host channel error count. */ + + USB_OTG_HS_URBStateTypeDef urb_state; /*!< URB state. + This parameter can be any value of @ref USB_OTG_URBStateTypeDef */ + + USB_OTG_HS_HCStateTypeDef state; /*!< Host Channel state. + This parameter can be any value of @ref USB_OTG_HCStateTypeDef */ +} USB_OTG_HS_HCTypeDef; + + +/** + *@brief USB_HS status structures definition + */ +typedef enum +{ + USB_HS_OK = 0x00U, + USB_HS_ERROR = 0x01U, + USB_HS_BUSY = 0x02U, + USB_HS_TIMEOUT = 0x03U +} USB_HS_StatusTypeDef; + +/** + *@brief USB_HS lock status structures definition + */ +typedef enum +{ + USB_HS_UNLOCKED = 0x00U, + USB_HS_LOCKED = 0x01U, +} USB_HS_LockTypeDef; + + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup PCD_Exported_Constants PCD Exported Constants + * @{ + */ + +#if defined (USB_OTG_HS) + +/** @defgroup USB Core Mode + * @{ + */ +#define USB_OTG_MODE_DEVICE 0U +#define USB_OTG_MODE_HOST 1U +#define USB_OTG_MODE_DRD 2U +/** + * @} + */ + +/** @defgroup USB Device Speed + * @{ + */ +#define USBD_HS_SPEED 0U +#define USBD_HSINFS_SPEED 1U +#define USBH_HS_SPEED 0U +#define USBD_FS_SPEED 2U +#define USBH_FSLS_SPEED 1U +/** + * @} + */ + +/** @defgroup USB_Core_Speed USB Low Layer Core Speed + * @{ + */ +#define USB_OTG_SPEED_HIGH 0U +#define USB_OTG_SPEED_HIGH_IN_FULL 1U +/** + * @} + */ + +#if !defined (USB_HS_PHYC_TUNE_VALUE) +#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /* value of USB HS PHY Tune waiting for update */ +#endif /* USB_HS_PHYC_TUNE_VALUE */ + +/** @defgroup USB_Turnaround_Timeout Turnaround Timeout Value + * @{ + */ +#ifndef USBD_HS_TRDT_VALUE +#define USBD_HS_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +#ifndef USBD_FS_TRDT_VALUE +#define USBD_FS_TRDT_VALUE 5U +#define USBD_DEFAULT_TRDT_VALUE 9U +#endif /* USBD_HS_TRDT_VALUE */ +/** + * @} + */ + +/** @defgroup USB_Core_MPS USB Low Layer Core MPS + * @{ + */ +#define USB_OTG_HS_MAX_PACKET_SIZE 512U +#define USB_OTG_FS_MAX_PACKET_SIZE 64U +#define USB_OTG_MAX_EP0_SIZE 64U +/** + * @} + */ + +/** @defgroup USB_Core_PHY_Frequency USB Low Layer Core PHY Frequency + * @{ + */ +#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) +#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) +/** + * @} + */ + +/** @defgroup USB_CORE_Frame_Interval USB Low Layer Core Frame Interval + * @{ + */ +#define DCFG_FRAME_INTERVAL_80 0U +#define DCFG_FRAME_INTERVAL_85 1U +#define DCFG_FRAME_INTERVAL_90 2U +#define DCFG_FRAME_INTERVAL_95 3U +/** + * @} + */ +#endif /* USB_OTG_HS */ +/** @defgroup USB_EP0_MPS USB Low Layer EP0 MPS + * @{ + */ +#define EP_MPS_64 0U +#define EP_MPS_32 1U +#define EP_MPS_16 2U +#define EP_MPS_8 3U +/** + * @} + */ + +/** @defgroup USB_EP_Speed USB Low Layer EP Speed + * @{ + */ +#define EP_SPEED_LOW 0U +#define EP_SPEED_FULL 1U +#define EP_SPEED_HIGH 2U +/** + * @} + */ + +/** @defgroup USB_EP_Type USB Low Layer EP Type + * @{ + */ +#define EP_TYPE_CTRL 0U +#define EP_TYPE_ISOC 1U +#define EP_TYPE_BULK 2U +#define EP_TYPE_INTR 3U +#define EP_TYPE_MSK 3U +/** + * @} + */ +#if defined (USB_OTG_HS) +/** @defgroup USB_STS_Defines USB Low Layer STS Defines + * @{ + */ +#define STS_GOUT_NAK 1U +#define STS_DATA_UPDT 2U +#define STS_XFER_COMP 3U +#define STS_SETUP_COMP 4U +#define STS_SETUP_UPDT 6U +/** + * @} + */ + +/** @defgroup USB_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines + * @{ + */ +#define HCFG_30_60_MHZ 0U +#define HCFG_48_MHZ 1U +#define HCFG_6_MHZ 2U +/** + * @} + */ + +/** @defgroup USB_HFIR_Defines USB Low Layer frame interval Defines + * @{ + */ +#define HFIR_60_MHZ 60000U +#define HFIR_48_MHZ 48000U +#define HFIR_6_MHZ 6000U +/** + * @} + */ + +/** @defgroup USB_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines + * @{ + */ +#define HPRT0_PRTSPD_HIGH_SPEED 0U +#define HPRT0_PRTSPD_FULL_SPEED 1U +#define HPRT0_PRTSPD_LOW_SPEED 2U +/** + * @} + */ + +#define HCCHAR_CTRL 0U +#define HCCHAR_ISOC 1U +#define HCCHAR_BULK 2U +#define HCCHAR_INTR 3U + +#define HC_PID_DATA0 0U +#define HC_PID_DATA2 1U +#define HC_PID_DATA1 2U +#define HC_PID_SETUP 3U + +#define GRXSTS_PKTSTS_IN 2U +#define GRXSTS_PKTSTS_IN_XFER_COMP 3U +#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U +#define GRXSTS_PKTSTS_CH_HALTED 7U + +#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU +#define HC_MAX_PKT_CNT 256U +#define ISO_SPLT_MPS 188U + +#define HCSPLT_BEGIN 1U +#define HCSPLT_MIDDLE 2U +#define HCSPLT_END 3U +#define HCSPLT_FULL 4U + +#define TEST_J 1U +#define TEST_K 2U +#define TEST_SE0_NAK 3U +#define TEST_PACKET 4U +#define TEST_FORCE_EN 5U + +#define USB_HS_PCGCCTL *(__IO uint32_t *)((uint32_t)OTG_HS_BASE + USB_OTG_HS_PCGCCTL_BASE) +#define USB_HS_HPRT0 *(__IO uint32_t *)((uint32_t)OTG_HS_BASE + USB_OTG_HS_HOST_PORT_BASE) + +#define USB_HS_DEVICE ((USB_OTG_HS_DeviceTypeDef *)(OTG_HS_BASE + USB_OTG_HS_DEVICE_BASE)) +#define USB_HS_INEP(i) ((USB_OTG_HS_INEndpointTypeDef *)(OTG_HS_BASE + USB_OTG_HS_IN_ENDPOINT_BASE\ + + ((i) * USB_OTG_HS_EP_REG_SIZE))) +#define USB_HS_OUTEP(i) ((USB_OTG_HS_OUTEndpointTypeDef *)(OTG_HS_BASE + USB_OTG_HS_OUT_ENDPOINT_BASE\ + + ((i) * USB_OTG_HS_EP_REG_SIZE))) +#define USB_HS_DFIFO(i) *(__IO uint32_t *)(OTG_HS_BASE + USB_OTG_HS_FIFO_BASE + ((i) * USB_OTG_HS_FIFO_SIZE)) + +#define USB_HS_HOST ((USB_OTG_HS_HostTypeDef *)(OTG_HS_BASE + USB_OTG_HS_HOST_BASE)) +#define USB_HS_HC(i) ((USB_OTG_HS_HostChannelTypeDef *)(OTG_HS_BASE + USB_OTG_HS_HOST_CHANNEL_BASE \ + + ((i) * USB_OTG_HS_HOST_CHANNEL_SIZE))) + + +#define USB_HS_PKEY *(__IO uint32_t *)((uint32_t)OTG_HS_BASE + USB_OTG_HS_PKEY_BASE) +#define USB_HS_PREG *(__IO uint32_t *)((uint32_t)OTG_HS_BASE + USB_OTG_HS_PREG_BASE) + + +#endif /* defined (USB_OTG_HS) */ + +#define EP_ADDR_MSK 0xFU + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USB_Exported_Macros USB Low Layer Exported Macros + * @{ + */ +#if defined (USB_OTG_HS) +#define USB_HS_MASK_INTERRUPT(__INTERRUPT__) (USB_HS->GINTMSK &= ~(__INTERRUPT__)) +#define USB_HS_UNMASK_INTERRUPT(__INTERRUPT__) (USB_HS->GINTMSK |= (__INTERRUPT__)) + +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USB_HS_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USB_HS_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) + +#define __USB_HS_LOCK(__HANDLE__) \ + do{ \ + if((__HANDLE__)->Lock == USB_HS_LOCKED) \ + { \ + return USB_HS_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = USB_HS_LOCKED; \ + } \ + }while (0U) + +#define __USB_HS_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = USB_HS_UNLOCKED; \ + }while (0U) + +#endif /* defined (USB_OTG_HS) */ +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USB_HS_Exported_Functions USB Low Layer Exported Functions + * @{ + */ +#if defined (USB_OTG_HS) +void USB_HS_Delayms(uint32_t num); +USB_HS_StatusTypeDef USB_HS_CoreInit(USB_OTG_HS_CfgTypeDef cfg); +USB_HS_StatusTypeDef USB_HS_DevInit(USB_OTG_HS_CfgTypeDef cfg); +void USB_HS_EnableGlobalInt(void); +void USB_HS_DisableGlobalInt(void); +void USB_HS_SetTurnaroundTime(uint32_t hclk, uint8_t speed); +USB_HS_StatusTypeDef USB_HS_SetCurrentMode(USB_ModeTypeDef mode); +void USB_HS_SetDevSpeed(uint8_t speed); +USB_HS_StatusTypeDef USB_HS_FlushRxFifo(void); +USB_HS_StatusTypeDef USB_HS_FlushTxFifo(uint32_t num); +void USB_HS_ActivateEndpoint(USB_OTG_HS_EPTypeDef *ep); +void USB_HS_DeactivateEndpoint(USB_OTG_HS_EPTypeDef *ep); +void USB_HS_ActivateDedicatedEndpoint(USB_OTG_HS_EPTypeDef *ep); +void USB_HS_DeactivateDedicatedEndpoint(USB_OTG_HS_EPTypeDef *ep); +void USB_HS_EPStartXfer(USB_OTG_HS_EPTypeDef *ep, uint8_t dma); +void USB_HS_WritePacket(uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma); +void *USB_HS_ReadPacket(uint8_t *dest, uint16_t len); +void USB_HS_EPSetStall(USB_OTG_HS_EPTypeDef *ep); +void USB_HS_EPClearStall(USB_OTG_HS_EPTypeDef *ep); +USB_HS_StatusTypeDef USB_HS_EPStopXfer(USB_OTG_HS_EPTypeDef *ep); +void USB_HS_SetDevAddress(uint8_t address); +void USB_HS_DevConnect(void); +void USB_HS_DevDisconnect(void); +USB_HS_StatusTypeDef USB_HS_StopDevice(void); +void USB_HS_ActivateSetup(void); +USB_HS_StatusTypeDef USB_HS_EP0_OutStart(uint8_t dma, uint8_t *psetup); +uint8_t USB_HS_GetDevSpeed(void); +uint32_t USB_HS_GetMode(void); +uint32_t USB_HS_ReadInterrupts(void); +uint32_t USB_HS_ReadChInterrupts(uint8_t chnum); +uint32_t USB_HS_ReadDevAllOutEpInterrupt(void); +uint32_t USB_HS_ReadDevOutEPInterrupt(uint8_t epnum); +uint32_t USB_HS_ReadDevAllInEpInterrupt(void); +uint32_t USB_HS_ReadDevInEPInterrupt(uint8_t epnum); +void USB_HS_ClearInterrupts(uint32_t interrupt); + +USB_HS_StatusTypeDef USB_HS_HostInit(USB_OTG_HS_CfgTypeDef cfg); +USB_HS_StatusTypeDef USB_HS_InitFSLSPClkSel(uint8_t freq); +void USB_HS_ResetPort(void); +void USB_HS_DriveVbus(uint8_t state); +uint32_t USB_HS_GetHostSpeed(void); +uint32_t USB_HS_GetCurrentFrame(void); +USB_HS_StatusTypeDef USB_HS_HC_Init(uint8_t ch_num, uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps); +void USB_HS_HC_StartXfer(USB_OTG_HS_HCTypeDef *hc, uint8_t dma); +uint32_t USB_HS_HC_ReadInterrupt(void); +void USB_HS_HC_Halt(uint8_t hc_num); +void USB_HS_DoPing(uint8_t ch_num); +USB_HS_StatusTypeDef USB_HS_StopHost(void); +void USB_HS_ActivateRemoteWakeup(void); +void USB_HS_DeActivateRemoteWakeup(void); +void USB_HS_DriveID(uint8_t state); +#endif /* defined (USB_OTG_HS) */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (USB_OTG_HS) */ + +#ifdef __cplusplus +} +#endif + + +#endif /* FT32F4xx_USB_HS_H */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_wwdg.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_wwdg.h new file mode 100644 index 00000000000..c1d7768c238 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/inc/ft32f4xx_wwdg.h @@ -0,0 +1,91 @@ +/** + ****************************************************************************** + * @file ft32f407xe_wwdg.h + * @author MCD Application Team + * @version V0.0.1 + * @date 2025-03-05 + * @brief This file contains all the functions prototypes for the WWDG + * firmware library. + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F407XE_WWDG_H +#define __FT32F407XE_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/** @addtogroup FT32F407XE_StdPeriph_Driver + * @{ + */ + +/** @addtogroup WWDG + * @{ + */ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup WWDG_Exported_Constants + * @{ + */ + +/** @defgroup WWDG_Prescaler + * @{ + */ + +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) +#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ + ((PRESCALER) == WWDG_Prescaler_2) || \ + ((PRESCALER) == WWDG_Prescaler_4) || \ + ((PRESCALER) == WWDG_Prescaler_8)) +#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) +#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ +/* Function used to set the WWDG configuration to the default reset state ****/ +void WWDG_DeInit(void); + +/* Prescaler, Refresh window and Counter configuration functions **************/ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); + +/* WWDG activation functions **************************************************/ +void WWDG_Enable(uint8_t Counter); + +/* Interrupts and flags management functions **********************************/ +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F407XE_WWDG_H */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_adc.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_adc.c new file mode 100644 index 00000000000..c3b30472651 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_adc.c @@ -0,0 +1,2214 @@ +/** + ****************************************************************************** + * @file ft32f4xx_adc.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Analog to Digital Convertor (ADC) peripheral: + * + Initialization and Configuration + * + Power saving + * + Analog Watchdog configuration + * + Temperature Sensor, Vrefint (Internal Reference Voltage) and + * Vbat (Voltage battery) management + * + ADC Channels Configuration + * + ADC Channels DMA Configuration + * + Interrupts and flags management. + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_adc.h" +#include "ft32f4xx_rcc.h" + + +/* ADC CFGR mask */ +#define CFGR1_CLEAR_MASK ((uint32_t)0x80000000) + +/* Calibration time out */ +#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000) + +/* ADC register bits groups */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ + | ADC_CR_JADSTART | ADC_CR_JADSTP \ + | ADC_CR_ADSTART | ADC_CR_ADSTP) +/* ADC register CR bits with HW property "rs": + * Software can read as well as set this bit. + * Writing '0' has no effect on the bit value. */ + +/** + * @brief Deinitializes ADCx peripheral registers to their default reset values. + * @param ADCx: where x can be 1/2/3 to select the ADC peripheral. + * @retval None + */ +void ADC_DeInit(void) +{ + /* Enable ADC1 reset state */ + //RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE); + + /* Release ADC1 from reset state */ + //RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE); +} + +/** + * @brief Initializes the ADCx peripheral according to the specified parameters + * in the ADC_InitStruct. + * @note This function is used to configure the global features of the ADC ( + * Common clock prescaler ,Resolution, Data Alignment, continuous mode activation, External + * trigger source and edge, Data Gain, regular/injected channel, Discontinuous mode, + * Auto injected mode, injected queue contexts, DMA mode, Auto delayed mode, + * Overrun mode, Sampling mode and oversampling mode). + * @param ADCx: where x can be 1/2/3 to select the ADC peripheral. + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains + * the configuration information for the specified ADC peripheral. + * @retval None + */ +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->Resolution)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ContinuousConvMode)); + assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ExternalTrigConvEdge)); + assert_param(IS_ADC_REGULAR_EXTTRIG_SOURCE(ADCx, ADC_InitStruct->ExternalTrigConv)); + assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->DataAlign)); + assert_param(IS_ADC_GAIN_COMPENSATION(ADC_InitStruct->GainCompensation)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->DiscontinuousConvMode)); + assert_param(IS_ADC_DMA_MODE(ADC_InitStruct->DMAMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->AutoDelayedConvMode)); + assert_param(IS_ADC_OVERRUN(ADC_InitStruct->Overrun)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->InjectedDiscontinuousConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->AutoInjectedConvMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->QueueInjectedContext)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->QueueMode)); + assert_param(IS_ADC_SAMPLINGMODE(ADC_InitStruct->SamplingMode)); + assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->OversamplingMode)); + assert_param(IS_ADC_SAMPLE_PLUS_TIME(ADC_InitStruct->SamplingPlusTime)); + + /* Get the ADCx CFGR value */ + tmpreg = ADCx->CFGR1; + + /* Clear RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */ + tmpreg &= CFGR1_CLEAR_MASK; + + /*---------------------------- ADCx CFGR Configuration ---------------------*/ + /* Set DMACFG bit according to ADC_ value */ + /* Set RES[1:0] bits according to ADC_Resolution value */ + /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */ + /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */ + /* Set OVRMOD bit according to ADC_ value */ + /* Set CONT bit according to ADC_ContinuousConvMode value */ + /* Set ALIGN bit according to ADC_DataAlign value */ + /* Set AUTDLY bit according to ADC_ value */ + /* Set DISCEN bit according to ADC_ value */ + /* Set DISCNUM[2:0] bits according to ADC_ value */ + /* Set JAUTO bit according to ADC_ value */ + /* Set JQM bit according to ADC_ value */ + /* Set JDISCEN bit according to ADC_ value */ + /* Set JQDIS bit according to ADC_ value */ + + if (ADC_InitStruct->DiscontinuousConvMode == ENABLE) + { + assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(ADC_InitStruct->NbrOfDiscConversion)); + tmpreg |= (uint32_t)(ADC_CFGR1_DISCEN | ((ADC_InitStruct->NbrOfDiscConversion - 1) << 17)); + } + + if (ADC_InitStruct->InjectedDiscontinuousConvMode == ENABLE) + { + tmpreg |= (uint32_t)ADC_CFGR1_JDISCEN; + } + + if (ADC_InitStruct->AutoInjectedConvMode == ENABLE) + { + tmpreg |= (uint32_t)ADC_CFGR1_JAUTO; + tmpreg &= (uint32_t)~(ADC_CFGR1_DISCEN | ADC_CFGR1_JDISCEN); + } + + if (ADC_InitStruct->QueueInjectedContext == DISABLE) + { + tmpreg |= (uint32_t)ADC_CFGR1_JQDIS; + } + else + { + tmpreg &= (uint32_t)~ADC_CFGR1_JQDIS; + /* Only when the QueueInjectedContext is enabled, QueueMode can be enabled */ + if (ADC_InitStruct->QueueMode == ENABLE) + { + tmpreg |= (uint32_t)ADC_CFGR1_JQM; + } + } + + /* ADC group regular and injected auto delay conversion mode enable */ + if (ADC_InitStruct->AutoDelayedConvMode == ENABLE) + { + tmpreg |= (uint32_t)ADC_CFGR1_AUTDLY; + } + + /* ADC group regular continuous mode enable */ + if (ADC_InitStruct->ContinuousConvMode == ENABLE) + { + tmpreg |= (uint32_t)ADC_CFGR1_CONT; + } + + /*Set the ADC minimum sampling clock period for all channels */ + if (ADC_InitStruct->SamplingPlusTime == ADC_SAMPLETIMEPLUS_1_5CYCLES) + { + ADCx->SMPR1 &= (uint32_t)(~ADC_SMPR1_SMPLUS); + } + else + { + ADCx->SMPR1 &= (uint32_t)(~ADC_SMPR1_SMPLUS); + ADCx->SMPR1 |= (uint32_t)ADC_InitStruct->SamplingPlusTime; + } + + + if (ADC_InitStruct->ExternalTrigConvEdge == ADC_SOFTWARE_START) + { + tmpreg |= (uint32_t)(ADC_InitStruct->DataAlign | ADC_InitStruct->Resolution | ADC_InitStruct->Overrun | ADC_InitStruct->DMAMode); + } + else + { + tmpreg |= (uint32_t)(ADC_InitStruct->ExternalTrigConvEdge | ADC_InitStruct->ExternalTrigConv | ADC_InitStruct->DataAlign | ADC_InitStruct->Resolution | ADC_InitStruct->Overrun | ADC_InitStruct->DMAMode); + } + + + if (ADC_InitStruct->SamplingMode == ADC_SAMPLING_MODE_TRIGGER_CONTROLED) + { + /* Clear BULB enable bit */ + ADCx->CFGR2 &= (uint32_t)~ADC_CFGR2_BULB; + + /* Set Sampling time control trigger mode enable bit */ + ADCx->CFGR2 |= (uint32_t)ADC_CFGR2_SMPTRIG; + + if (ADC_InitStruct->ExternalTrigConvEdge == ADC_SOFTWARE_START) + { + tmpreg &= (uint32_t)~ADC_CFGR1_EXTEN; + } + else + { + /* If select hardware trigger when sampling time control trigger mode + * external trigger enable and polarity selection for regular channel must set rising edge */ + tmpreg &= (uint32_t)~ADC_CFGR1_EXTEN; + tmpreg |= (uint32_t)ADC_CFGR1_EXTEN_0; + } + } + + + if (ADC_InitStruct->SamplingMode == ADC_SAMPLING_MODE_BULB) + { + ADCx->CFGR2 &= (uint32_t)~ADC_CFGR2_SMPTRIG; + ADCx->CFGR2 |= (uint32_t)ADC_CFGR2_BULB; + } + + /* If the GainCompensation is not 0, Gain mode can be enabled + * Otherwise, disable Gain mode */ + if (ADC_InitStruct->GainCompensation != 0) + { + ADCx->CFGR2 |= (uint32_t)ADC_CFGR2_GCOMP; + ADCx->GCOMP |= (uint32_t)ADC_InitStruct->GainCompensation; + } + else + { + ADCx->CFGR2 &= (uint32_t)~ADC_CFGR2_GCOMP; + ADCx->GCOMP &= (uint32_t)~ADC_GCOMP_GCOMPCOEFF; + } + + + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + /* - Triggered mode */ + /* - Oversampling mode (continued/resumed) */ + if (ADC_InitStruct->OversamplingMode == ENABLE) + { + + assert_param(IS_ADC_OVERSAMPLING_RATIO(ADC_InitStruct->Oversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(ADC_InitStruct->Oversampling.RightBitShift)); + assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(ADC_InitStruct->Oversampling.TriggeredMode)); + assert_param(IS_ADC_REGOVERSAMPLING_MODE(ADC_InitStruct->Oversampling.OversamplingStopReset)); + + + /* Reset the Oversampling config */ + ADCx->CFGR2 &= (uint32_t)~(ADC_CFGR2_ROVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS | ADC_CFGR2_TROVS | ADC_CFGR2_ROVSM); + + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + /* - Triggered mode */ + /* - Oversampling mode (continued/resumed) */ + ADCx->CFGR2 |= (uint32_t)(ADC_InitStruct->Oversampling.Ratio | ADC_InitStruct->Oversampling.RightBitShift | ADC_InitStruct->Oversampling.TriggeredMode | ADC_InitStruct->Oversampling.OversamplingStopReset | ADC_CFGR2_ROVSE); + + } + else + { + /* Reset the Oversampling config */ + ADCx->CFGR2 &= (uint32_t)~(ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS | ADC_CFGR2_ROVSM); + } + + + /* Write to ADCx CFGR */ + ADCx->CFGR1 = tmpreg; + + /* Write Regular channel length to ADCx SQR1 and clear all channels config */ + if (ADC_InitStruct->NbrOfConversion == RESET) + { + ADCx->SQR1 = (uint32_t)RESET; + } + else + { + assert_param(IS_ADC_REGULAR_NUMBER(ADC_InitStruct->NbrOfConversion)); + ADCx->SQR1 = (uint32_t)(ADC_InitStruct->NbrOfConversion - 1); + } + +} + +/** + * @brief Fills each ADC_InitStruct member with its default value. + * @note This function is used to initialize the global features of the ADC ( + * Resolution, Data Alignment, continuous mode activation, External + * trigger source and edge, Sequence Scan Direction). + * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + /* Reset ADC init structure parameters values */ + /* Initialize the ADC_Resolution member */ + ADC_InitStruct->Resolution = ADC_RESOLUTION_12B; + + /* Initialize the ADC_ContinuousConvMode member */ + ADC_InitStruct->ContinuousConvMode = DISABLE; + + /* Initialize the ADC_ExternalTrigConvEdge member */ + ADC_InitStruct->ExternalTrigConvEdge = ADC_SOFTWARE_START; + + /* Initialize the ADC_DataAlign member */ + ADC_InitStruct->DataAlign = ADC_DATAALIGN_RIGHT; + + /* Initialize the ADC_NbrOfConversion member */ + ADC_InitStruct->NbrOfConversion = 8; + +} + +/** + * @brief Enables or disables the specified ADC peripheral. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the ADCx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ADEN bit to Enable the ADC peripheral */ + ADCx->CR |= (uint32_t)ADC_CR_ADEN; + } + else + { + /* Set the ADDIS to Disable the ADC peripheral */ + ADCx->CR |= (uint32_t)ADC_CR_ADDIS; + } +} +/** + * @} + */ + +/** + * @brief Set parameter common to several ADC: Clock source and prescaler. + * This parameter can be a value of @ref ADC_ClockMode. + * @note On this FT32F4xx series, if ADC group injected is used, some + * clock ratio constraints between ADC clock and AHB clock + * must be respected. + * Refer to reference manual. + * @note On this FT32F4xx series, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * @param ADC_Common ADC common instance + * @param CommonClock This parameter can be one of the following values: + * @arg @ref ADC_CLOCK_SYNC_HCLK_DIV1 + * @arg @ref ADC_CLOCK_SYNC_HCLK_DIV2 + * @arg @ref ADC_CLOCK_SYNC_HCLK_DIV4 + * @arg @ref ADC_CLOCK_ASYNC_DIV1 + * @arg @ref ADC_CLOCK_ASYNC_DIV2 + * @arg @ref ADC_CLOCK_ASYNC_DIV4 + * @arg @ref ADC_CLOCK_ASYNC_DIV6 + * @arg @ref ADC_CLOCK_ASYNC_DIV8 + * @arg @ref ADC_CLOCK_ASYNC_DIV10 + * @arg @ref ADC_CLOCK_ASYNC_DIV12 + * @arg @ref ADC_CLOCK_ASYNC_DIV16 + * @arg @ref ADC_CLOCK_ASYNC_DIV32 + * @arg @ref ADC_CLOCK_ASYNC_DIV64 + * @arg @ref ADC_CLOCK_ASYNC_DIV128 + * @arg @ref ADC_CLOCK_ASYNC_DIV256 + * @retval None + */ +void ADC_ClockModeConfig(uint32_t CommonClock) +{ + assert_param(IS_ADC_CLOCKPRESCALER(CommonClock)); + + /* Clear Clock Mode previous config */ + ADC_Common->CCR &= (uint32_t)~ADC_CCR_CKMODE; + + /* Set ADC Common clock mode and prescaler factor */ + if ((CommonClock != ADC_CLOCK_SYNC_HCLK_DIV1) || (CommonClock != ADC_CLOCK_SYNC_HCLK_DIV2) || (CommonClock != ADC_CLOCK_SYNC_HCLK_DIV4)) + { + /* Set Clock Mode on Async mode */ + ADC_Common->CCR &= (uint32_t)~ADC_CCR_PRESC; + + /* Set prescaler factor to Async mode */ + ADC_Common->CCR |= (uint32_t)CommonClock; + } + else + { + /* Set Clock Mode on Sync and select the HCLK prescaler factor */ + ADC_Common->CCR |= (uint32_t)CommonClock; + } +} +/** + * @} + */ + +/** + * @brief Enable ADC multimode and configure multimode parameters + * @note Possibility to update parameters on the fly: + * This function initializes multimode parameters, following + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_MultiModeTypeDef" on the fly, without resetting + * the ADCs. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_MultiModeTypeDef". + * @note To move back configuration from multimode to single mode, ADC must + * be reset (using function ADC_Init() ). + * @param hadc Master ADC handle + * @param Multimode Structure of ADC multimode configuration + * @retval None + */ +void ADC_MultiModeConfig(ADC_MultiModeTypeDef* MultiMode) +{ + /* Check the parameters */ + assert_param(IS_ADC_MULTIMODE(MultiMode->Mode)); + assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(MultiMode->DMAAccessMode)); + assert_param(IS_ADC_MULTI_DMA_MODE(MultiMode->DMAMode)); + assert_param(IS_ADC_TWOSAMPLING_DELAY(MultiMode->TwoSamplingDelay)); + + /* Config ADCx multi mode */ + if (MultiMode->Mode != ADC_MODE_INDEPENDENT) + { + ADC_Common->CCR &= (uint32_t)(~(ADC_CCR_MDMA | ADC_CCR_DMACFG | ADC_CCR_DELAY | ADC_CCR_MULTI)); + ADC_Common->CCR |= (uint32_t)(MultiMode->Mode | MultiMode->DMAAccessMode | MultiMode->DMAMode | MultiMode->TwoSamplingDelay); + + } + else + { + ADC_Common->CCR &= (uint32_t)(~(ADC_CCR_MDMA | ADC_CCR_DMACFG | ADC_CCR_DELAY | ADC_CCR_MULTI)); + } +} +/** + * @} + */ + +/** + * @brief Start ADC sampling phase for sampling time trigger mode + * @note This function is relevant only when + * - @ref ADC_InitTypeDef->SamplingMode has been set + * using @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED + * - @ref ADC_SOFTWARE_TRIGCONV is used as trigger source + * @note On this FT32F4xx series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CFGR2 SWTRIG ADC_StartSamplingPhase + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval None + */ +void ADC_StartSamplingPhase(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Start sampling */ + ADCx->CFGR2 |= (uint32_t)ADC_CFGR2_SWTRIG; + SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG); + +} +/** + * @} + */ + +/** + * @brief Stop ADC sampling phase for sampling time trigger mode + * and start conversion + * @note This function is relevant only when + * - @ref ADC_InitTypeDef->SamplingMode has been set + * using @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED + * - @ref ADC_SOFTWARE_TRIGCONV is used as trigger source + * - @ref ADC_StartSampling has been called to start + * the sampling phase + * @note On this FT32F4xx series, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CFGR2 SWTRIG ADC_StopSamplingPhase + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval None + */ +void ADC_StoptSamplingPhase(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Start sampling */ + ADCx->CFGR2 &= (uint32_t)~ADC_CFGR2_SWTRIG; +} +/** + * @} + */ + +/** + * @brief Enables or disables the Wait conversion mode. + * @note When the CPU clock is not fast enough to manage the data rate, a + * Hardware delay can be introduced between ADC conversions to reduce + * this data rate. + * @note The Hardware delay is inserted after each conversions and until the + * previous data is read from the ADC data register + * @note This is a way to automatically adapt the speed of the ADC to the speed + * of the system which will read the data. + * @note Any hardware triggers wich occur while a conversion is on going or + * while the automatic Delay is applied are ignored + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the ADCx Auto-Delay. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AutoDelayModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ADC Automatic Delayed conversion */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_AUTDLY; + } + else + { + /* Disable the ADC Automatic Delayed conversion */ + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTDLY; + } +} +/** + * @} + */ + +/** + * @brief Enable the Continuous mode for the selected ADCx channels. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the Continuous mode. + * This parameter can be: ENABLE or DISABLE. + * @note It is not possible to have both discontinuous mode and continuous mode + * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves + * as if continuous mode was disabled + * @retval None + */ +void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Continuous mode*/ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT; + } + else + { + /* Disable the Continuous mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT); + } +} +/** + * @} + */ + +/** + * @brief Enable the automatic injected mode for the selected ADCx injected channels. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the automatic injected mode. + * This parameter can be: ENABLE or DISABLE. + * @note It is not possible to enable both ADC group injected + * auto-injected mode and sequencer discontinuous mode. + * @retval None + */ +void ADC_AutoInjectedModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Continuous mode*/ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_JAUTO; + } + else + { + /* Disable the Continuous mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_JAUTO); + } +} +/** + * @} + */ + +/** + * @brief Enable the discontinuous mode for the selected ADC regular channels. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param DiscontNum: This parameter can be one of the following values: + * ADC_REG_SEQ_DISCONT_DISABLE + * ADC_REG_SEQ_DISCNUM_1_CHANNEL + * ADC_REG_SEQ_DISCNUM_2_CHANNELS + * ADC_REG_SEQ_DISCNUM_3_CHANNELS + * ADC_REG_SEQ_DISCNUM_4_CHANNELS + * ADC_REG_SEQ_DISCNUM_5_CHANNELS + * ADC_REG_SEQ_DISCNUM_6_CHANNELS + * ADC_REG_SEQ_DISCNUM_7_CHANNELS + * ADC_REG_SEQ_DISCNUM_8_CHANNELS + * @note It is not possible to have both discontinuous mode and continuous mode + * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves + * as if continuous mode was disabled + * @retval None + */ +void ADC_REG_DiscModeCmd(ADC_TypeDef* ADCx, uint32_t DiscontNum) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + if (DiscontNum != ADC_REG_SEQ_DISCONT_DISABLE) + { + /* Enable the Discontinuous mode and Config the Discontinuous number of channels */ + ADCx->CFGR1 |= (uint32_t)DiscontNum; + } + else + { + /* Disable the Discontinuous mode and clear the Discontinuous number of channels */ + ADCx->CFGR1 &= (uint32_t)~(ADC_CFGR1_DISCNUM | ADC_CFGR1_DISCEN); + } +} +/** + * @} + */ + +/** + * @brief Enable the discontinuous mode for the selected ADC injected channels. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the discontinuous mode. + * This parameter can be: ENABLE or DISABLE. + * @note It is not possible to have both discontinuous mode and continuous mode + * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves + * as if continuous mode was disabled + * @note ADC group injected each conversion only one channel. + * @retval None + */ +void ADC_INJ_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Discontinuous mode */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_JDISCEN; + } + else + { + /* Disable the Discontinuous mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_JDISCEN); + } +} +/** + * @} + */ + +/** + * @brief Enable the Overrun mode for the selected ADC channels. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the Overrun mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Overrun mode */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD; + } + else + { + /* Disable the Overrun mode */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD); + } +} +/** + * @} + */ + +/** + * @brief Put ADC instance in deep power down state. + * @note In case of ADC calibration necessary: When ADC is in deep-power-down + * state, the internal analog calibration is lost. After exiting from + * deep power down, calibration must be relaunched or calibration factor + * (preliminarily saved) must be set back into calibration register. + * @note On this FT32F4xx series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the ADCx DeepPowerDown. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_DeepPWDModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits. */ + ADCx->CR &= (uint32_t)~ADC_CR_BITS_PROPERTY_RS; + + if (NewState != DISABLE) + { + /* Enable the ADC enter Deep Power Down Mode */ + ADCx->CR |= (uint32_t)ADC_CR_DEEPPWD; + } + else + { + /* Disable the ADC exti Deep Power Down Mode */ + ADCx->CR &= (uint32_t)~ADC_CR_DEEPPWD; + } +} +/** + * @} + */ + +/** + * @brief Enable ADC instance internal voltage regulator. + * @note On this FT32 series, after ADC internal voltage regulator enable, + * a delay for ADC internal voltage regulator stabilization + * is required before performing a ADC calibration or ADC enable. + * Refer to device datasheet, parameter tADCVREG_STUP. + * @note On this FT32F4xx series, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param NewState: new state of the ADCx DeepPowerDown. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_InternalRegulatorCmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + ADCx->CR &= (uint32_t)~ADC_CR_BITS_PROPERTY_RS; + + if (NewState != DISABLE) + { + /* Enable the ADC enable ADCx internal voltage regulator */ + ADCx->CR |= (uint32_t)ADC_CR_ADVREGEN; + } + else + { + /* Disable the ADC disable ADCx internal voltage regulator */ + ADCx->CR &= (uint32_t)~ADC_CR_ADVREGEN; + } +} +/** + * @} + */ + +/** + * @brief Enables or disables the temperature sensor channel. + * @param NewState: new state of the temperature sensor input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_TempSensorCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the temperature sensor channel*/ + ADC_Common->CCR |= (uint32_t)ADC_CCR_VSENSESEL; + } + else + { + /* Disable the temperature sensor channel*/ + ADC_Common->CCR &= (uint32_t)(~ADC_CCR_VSENSESEL); + } +} +/** + * @} + */ + +/** + * @brief Enables or disables the Vrefint channel. + * @param NewState: new state of the Vref input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VrefintCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vrefint channel*/ + ADC_Common->CCR |= (uint32_t)ADC_CCR_VREFEN; + } + else + { + /* Disable the Vrefint channel*/ + ADC_Common->CCR &= (uint32_t)(~ADC_CCR_VREFEN); + } +} +/** + * @} + */ + +/** + * @brief Enables or disables the Vbat channel. + * @param NewState: new state of the Vbat input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_VbatCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vbat channel */ + ADC_Common->CCR |= (uint32_t)ADC_CCR_VBATSEL; + } + else + { + /* Disable the Vbat channel */ + ADC_Common->CCR &= (uint32_t)(~ADC_CCR_VBATSEL); + } +} +/** + * @} + */ + +/** + * @brief Enables or disables the Analog Watchdog 2 monitor Vbat channel. + * @param NewState: new state of the monitor Vbat input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AWD2MonitorVbatCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Sel the AWD2 monitor the Vbat channel */ + ADC_Common->CCR &= (uint32_t)(~ADC_CCR_AWDSEL); + } + else + { + /* Sel the AWD3 monitor the Vbat channel */ + ADC_Common->CCR |= (uint32_t)ADC_CCR_AWDSEL; + } +} +/** + * @} + */ + +/** + * @brief Enables or disables the Analog Watchdog 3 monitor Vbat channel. + * @param NewState: new state of the monitor Vbat input channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_AWD3MonitorVbatCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Sel the AWD3 monitor the Vbat channel */ + ADC_Common->CCR |= (uint32_t)ADC_CCR_AWDSEL; + } + else + { + /* Sel the AWD2 monitor the Vbat channel */ + ADC_Common->CCR &= (uint32_t)(~ADC_CCR_AWDSEL); + } +} +/** + * @} + */ + +/** + * @brief Enables or disables the Battery charging when voltage is lower than threshold. + * @param NewState: This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_BatteryAutoChargingCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vbat channel automatic charging for battery */ + ADC_Common->CCR |= (uint32_t)ADC_CCR_VBEAUTO; + } + else + { + /* Disable the Vbat channel automatic charging for battery */ + ADC_Common->CCR &= (uint32_t)(~ADC_CCR_VBEAUTO); + } +} +/** + * @} + */ + +/** + * @} + */ +/** + * @brief Configures for the selected ADC and its sampling time. + * @param ADCx: where x can be 1/2/3 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be any combination of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @arg ADC_Channel_19: ADC Channel19 selected + * @arg ADC_Channel_20: ADC Channel20 selected + * @arg ADC_Channel_21: ADC Channel21 selected + * @param ADC_SampleTime: The sample time value to be set for the selected channel. + * This parameter can be one of the following values: + * @arg ADC_SAMPLETIME_1_5CYCLES: Sample time equal to 1.5 cycles + * @arg ADC_SAMPLETIME_6_5CYCLES: Sample time equal to 6.5 cycles + * @arg ADC_SAMPLETIME_12_5CYCLES: Sample time equal to 12.5 cycles + * @arg ADC_SAMPLETIME_24_5CYCLES: Sample time equal to 24.5 cycles + * @arg ADC_SAMPLETIME_47_5CYCLES: Sample time equal to 47.5 cycles + * @arg ADC_SAMPLETIME_92_5CYCLES: Sample time equal to 92.5 cycles + * @arg ADC_SAMPLETIME_247_5CYCLES: Sample time equal to 247.5 cycles + * @arg ADC_SAMPLETIME_640_5CYCLES: Sample time equal to 640.5 cycles + * @retval None + */ +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, ADC_ChannelConfTypeDef* RegularConfig) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(RegularConfig->Channel)); + assert_param(IS_ADC_REGULAR_RANK(RegularConfig->Rank)); + assert_param(IS_ADC_SAMPLE_TIME(RegularConfig->SamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(RegularConfig->SingleDiff)); + assert_param(IS_ADC_OFFSET_NUMBER(RegularConfig->OffsetNumber)); + assert_param(IS_ADC_OFFSET_SIGN(RegularConfig->OffsetSign)); + assert_param(IS_FUNCTIONAL_STATE(RegularConfig->OffsetSaturation)); + + + /* Clear th Channel Selection bits, and Configure the ADC Channel */ + if (RegularConfig->Rank <= ADC_REGULAR_RANK_4) + { + ADCx->SQR1 &= (uint32_t)(~(0x1f << ((RegularConfig->Rank + 1) * 6))); + ADCx->SQR1 |= RegularConfig->Channel << ((RegularConfig->Rank + 1) * 6); + } + else if (RegularConfig->Rank <= ADC_REGULAR_RANK_9) + { + ADCx->SQR2 &= (uint32_t)(~(0x1f << ((RegularConfig->Rank - 4) * 6))); + ADCx->SQR2 |= RegularConfig->Channel << ((RegularConfig->Rank - 4) * 6); + } + else if (RegularConfig->Rank <= ADC_REGULAR_RANK_14) + { + ADCx->SQR3 &= (uint32_t)(~(0x1f << ((RegularConfig->Rank - 9) * 6))); + ADCx->SQR3 |= RegularConfig->Channel << ((RegularConfig->Rank - 9) * 6); + } + else if (RegularConfig->Rank <= ADC_REGULAR_RANK_16) + { + ADCx->SQR4 &= (uint32_t)(~(0x1f << ((RegularConfig->Rank - 14) * 6))); + ADCx->SQR4 |= RegularConfig->Channel << ((RegularConfig->Rank - 14) * 6); + } + + + /* Clear the Sampling time Selection bits, and Set the ADC Sampling Time register */ + /* Set sampling time of the selected ADC channel */ + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ + if (RegularConfig->Channel <= ADC_CHANNEL_9) + { + ADCx->SMPR1 &= (uint32_t)(~(0x7 << (RegularConfig->Channel * 3))); + ADCx->SMPR1 |= RegularConfig->SamplingTime << (RegularConfig->Channel * 3); + } + else if (RegularConfig->Channel <= ADC_CHANNEL_18) + { + ADCx->SMPR2 &= (uint32_t)(~(0x7 << (RegularConfig->Channel - 10))); + ADCx->SMPR2 |= RegularConfig->SamplingTime << ((RegularConfig->Channel - 10) * 3); + } + else if (RegularConfig->Channel <= ADC_CHANNEL_21) + { + ADCx->SMPR3 &= (uint32_t)(~(0x7 << (RegularConfig->Channel - 19))); + ADCx->SMPR3 |= RegularConfig->SamplingTime << ((RegularConfig->Channel - 19) * 3); + } + + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Single or differential mode */ + if (RegularConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) + { + /* Set mode differential input of the selected ADC channel */ + ADCx->DIFSEL |= (uint32_t)(ADC_DIFFERENTIAL_ENDED << RegularConfig->Channel); + } + else + { + /* Set mode single-ended input of the selected ADC channel */ + ADCx->DIFSEL &= (uint32_t)~(ADC_DIFFERENTIAL_ENDED << RegularConfig->Channel); + } + + + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is enable or disabled. */ + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group or injected group: */ + /* - Channel offset */ + /* Shift the offset with respect to the selected ADC resolution. */ + /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + /* Set ADC selected offset sign & saturation by @param OffsetSign and OffsetSaturation */ + if (RegularConfig->OffsetNumber != ADC_OFFSET_NONE) + { + /* Config register OFR1 */ + if (RegularConfig->OffsetNumber == ADC_OFFSET_1) + { + ADCx->OFR1 = ADC_OFR1_OFFSET_EN | RegularConfig->OffsetSign | (RegularConfig->Channel << 26) | + (RegularConfig->OffsetSaturation << 25) | RegularConfig->Offset ; + } + + /* Config register OFR2 */ + if (RegularConfig->OffsetNumber == ADC_OFFSET_2) + { + ADCx->OFR2 = ADC_OFR2_OFFSET_EN | RegularConfig->OffsetSign | (RegularConfig->Channel << 26) | + (RegularConfig->OffsetSaturation << 25) | RegularConfig->Offset ; + } + + /* Config register OFR3 */ + if (RegularConfig->OffsetNumber == ADC_OFFSET_3) + { + ADCx->OFR3 = ADC_OFR3_OFFSET_EN | RegularConfig->OffsetSign | (RegularConfig->Channel << 26) | + (RegularConfig->OffsetSaturation << 25) | RegularConfig->Offset ; + } + + /* Config register OFR4 */ + if (RegularConfig->OffsetNumber == ADC_OFFSET_4) + { + ADCx->OFR4 = ADC_OFR4_OFFSET_EN | RegularConfig->OffsetSign | (RegularConfig->Channel << 26) | + (RegularConfig->OffsetSaturation << 25) | RegularConfig->Offset ; + } + } + else + { + /* Reset register OFR1 */ + if (RegularConfig->Channel == ((ADCx->OFR1 >> 26) & 0x1f)) + { + ADCx->OFR1 = (uint32_t)RESET; + } + + /* Reset register OFR2 */ + if (RegularConfig->Channel == ((ADCx->OFR2 >> 26) & 0x1f)) + { + ADCx->OFR2 = (uint32_t)RESET; + } + + /* Reset register OFR3 */ + if (RegularConfig->Channel == ((ADCx->OFR3 >> 26) & 0x1f)) + { + ADCx->OFR3 = (uint32_t)RESET; + } + + /* Reset register OFR4 */ + if (RegularConfig->Channel == ((ADCx->OFR4 >> 26) & 0x1f)) + { + ADCx->OFR4 = (uint32_t)RESET; + } + } +} + + + +/** + * @brief Configures for the selected ADC and its sampling time. + * @param ADCx: where x can be 1 to select the ADC peripheral. + * @param ADC_Channel: the ADC channel to configure. + * This parameter can be any combination of the following values: + * @arg ADC_Channel_0: ADC Channel0 selected + * @arg ADC_Channel_1: ADC Channel1 selected + * @arg ADC_Channel_2: ADC Channel2 selected + * @arg ADC_Channel_3: ADC Channel3 selected + * @arg ADC_Channel_4: ADC Channel4 selected + * @arg ADC_Channel_5: ADC Channel5 selected + * @arg ADC_Channel_6: ADC Channel6 selected + * @arg ADC_Channel_7: ADC Channel7 selected + * @arg ADC_Channel_8: ADC Channel8 selected + * @arg ADC_Channel_9: ADC Channel9 selected + * @arg ADC_Channel_10: ADC Channel10 selected + * @arg ADC_Channel_11: ADC Channel11 selected + * @arg ADC_Channel_12: ADC Channel12 selected + * @arg ADC_Channel_13: ADC Channel13 selected + * @arg ADC_Channel_14: ADC Channel14 selected + * @arg ADC_Channel_15: ADC Channel15 selected + * @arg ADC_Channel_16: ADC Channel16 selected + * @arg ADC_Channel_17: ADC Channel17 selected + * @arg ADC_Channel_18: ADC Channel18 selected + * @arg ADC_Channel_19: ADC Channel19 selected + * @arg ADC_Channel_20: ADC Channel20 selected + * @arg ADC_Channel_21: ADC Channel21 selected + * This parameter can be one of the following values: + * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles + * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles + * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles + * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles + * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles + * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles + * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles + * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles + * @retval None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, ADC_InjectedConfTypeDef* InjectedConfig) +{ + static uint32_t tmp_jsqr = 0x0, channel_count = 0x0; + + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CHANNEL(InjectedConfig->InjectedChannel)); + assert_param(IS_ADC_REGULAR_RANK(InjectedConfig->InjectedRank)); + assert_param(IS_ADC_SAMPLE_TIME(InjectedConfig->InjectedSamplingTime)); + assert_param(IS_ADC_SINGLE_DIFFERENTIAL(InjectedConfig->InjectedSingleDiff)); + assert_param(IS_ADC_OFFSET_NUMBER(InjectedConfig->InjectedOffsetNumber)); + assert_param(IS_ADC_OFFSET_SIGN(InjectedConfig->InjectedOffsetSign)); + assert_param(IS_FUNCTIONAL_STATE(InjectedConfig->InjectedOffsetSaturation)); + assert_param(IS_FUNCTIONAL_STATE(InjectedConfig->InjectedOversamplingMode)); + assert_param(IS_ADC_INJECTED_NUMBER(InjectedConfig->InjectedNbrOfConversion)); + assert_param(IS_ADC_EXTTRIG_INJEC_EDGE(InjectedConfig->ExternalTrigInjecConvEdge)); + assert_param(IS_ADC_INJECTED_EXTTRIG_SOURCE(ADCx, InjectedConfig->ExternalTrigInjecConv)); + + + if (InjectedConfig->InjectedRank == ADC_INJECTED_RANK_1) + { + if (channel_count != (uint32_t)RESET) + { + channel_count = (uint32_t)RESET; + } + + tmp_jsqr |= (uint32_t)(InjectedConfig->InjectedChannel << 9); + } + else if (InjectedConfig->InjectedRank == ADC_INJECTED_RANK_2) + { + tmp_jsqr |= (uint32_t)(InjectedConfig->InjectedChannel << 15); + } + else if (InjectedConfig->InjectedRank == ADC_INJECTED_RANK_3) + { + tmp_jsqr |= (uint32_t)(InjectedConfig->InjectedChannel << 21); + } + else if (InjectedConfig->InjectedRank == ADC_INJECTED_RANK_4) + { + tmp_jsqr |= (uint32_t)(InjectedConfig->InjectedChannel << 27); + } + + channel_count ++; + + if (channel_count == InjectedConfig->InjectedNbrOfConversion) + { + ADCx->JSQR = tmp_jsqr + (uint32_t)(InjectedConfig->InjectedNbrOfConversion - 1) + (uint32_t)InjectedConfig->ExternalTrigInjecConv + (uint32_t)InjectedConfig->ExternalTrigInjecConvEdge; + + /* ADC group injected config reset when all injected channels set */ + tmp_jsqr = RESET; + + channel_count = RESET; + + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + /* - Triggered mode */ + /* - Oversampling mode (continued/resumed) */ + if (InjectedConfig->InjectedOversamplingMode == ENABLE) + { + + assert_param(IS_ADC_OVERSAMPLING_RATIO(InjectedConfig->InjectedOversampling.Ratio)); + assert_param(IS_ADC_RIGHT_BIT_SHIFT(InjectedConfig->InjectedOversampling.RightBitShift)); + + /* Reset the Oversampling config */ + ADCx->CFGR2 &= (uint32_t)~(ADC_CFGR2_JOVSE | ADC_CFGR2_OVSR | ADC_CFGR2_OVSS); + + /* Configuration of Oversampler: */ + /* - Oversampling Ratio */ + /* - Right bit shift */ + ADCx->CFGR2 |= (uint32_t)(InjectedConfig->InjectedOversampling.Ratio | InjectedConfig->InjectedOversampling.RightBitShift | ADC_CFGR2_JOVSE); + + } + else + { + /* Reset the Oversampling config */ + ADCx->CFGR2 &= (uint32_t)~ADC_CFGR2_JOVSE; + } + } + + + /* Clear the Sampling time Selection bits, and Set the ADC Sampling Time register */ + /* Set sampling time of the selected ADC channel */ + /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */ + if (InjectedConfig->InjectedChannel <= ADC_CHANNEL_9) + { + ADCx->SMPR1 &= (uint32_t)(~(0x7 << (InjectedConfig->InjectedChannel * 3))); + ADCx->SMPR1 |= (uint32_t)(InjectedConfig->InjectedSamplingTime << (InjectedConfig->InjectedChannel * 3)); + } + else if (InjectedConfig->InjectedChannel <= ADC_CHANNEL_18) + { + ADCx->SMPR2 &= (uint32_t)(~(0x7 << (InjectedConfig->InjectedChannel - 10))); + ADCx->SMPR2 |= (uint32_t)(InjectedConfig->InjectedSamplingTime << ((InjectedConfig->InjectedChannel - 10) * 3)); + } + else if (InjectedConfig->InjectedChannel <= ADC_CHANNEL_21) + { + ADCx->SMPR3 &= (uint32_t)(~(0x7 << (InjectedConfig->InjectedChannel - 19))); + ADCx->SMPR3 |= (uint32_t)(InjectedConfig->InjectedSamplingTime << ((InjectedConfig->InjectedChannel - 19) * 3)); + } + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated only when ADC is disabled: */ + /* - Single or differential mode */ + if (InjectedConfig->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED) + { + /* Set mode differential input of the selected ADC channel */ + ADCx->DIFSEL |= (uint32_t)(ADC_DIFFERENTIAL_ENDED << InjectedConfig->InjectedChannel); + } + else + { + /* Set mode single-ended input of the selected ADC channel */ + ADCx->DIFSEL &= (uint32_t)~(ADC_DIFFERENTIAL_ENDED << InjectedConfig->InjectedChannel); + } + + + /* Scan each offset register to check if the selected channel is targeted. */ + /* If this is the case, the corresponding offset number is enable or disabled. */ + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going on regular group or injected group: */ + /* - Channel offset */ + /* Shift the offset with respect to the selected ADC resolution. */ + /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ + /* Set ADC selected offset sign & saturation by @param OffsetSign and OffsetSaturation */ + if (InjectedConfig->InjectedOffsetNumber != ADC_OFFSET_NONE) + { + /* Config register OFRx */ + if (InjectedConfig->InjectedOffsetNumber == ADC_OFFSET_1) + { + ADCx->OFR1 = ADC_OFR1_OFFSET_EN | (uint32_t)InjectedConfig->InjectedOffsetSign | (uint32_t)(InjectedConfig->InjectedChannel << 26) | + (uint32_t)(InjectedConfig->InjectedOffsetSaturation << 25) | (uint32_t)InjectedConfig->InjectedOffset ; + } + + /* Config register OFRx */ + if (InjectedConfig->InjectedOffsetNumber == ADC_OFFSET_2) + { + ADCx->OFR2 = ADC_OFR2_OFFSET_EN | (uint32_t)InjectedConfig->InjectedOffsetSign | (uint32_t)(InjectedConfig->InjectedChannel << 26) | + (uint32_t)(InjectedConfig->InjectedOffsetSaturation << 25) | (uint32_t)InjectedConfig->InjectedOffset ; + } + + /* Config register OFRx */ + if (InjectedConfig->InjectedOffsetNumber == ADC_OFFSET_3) + { + ADCx->OFR3 = ADC_OFR3_OFFSET_EN | (uint32_t)InjectedConfig->InjectedOffsetSign | (uint32_t)(InjectedConfig->InjectedChannel << 26) | + (uint32_t)(InjectedConfig->InjectedOffsetSaturation << 25) | (uint32_t)InjectedConfig->InjectedOffset ; + } + + /* Config register OFRx */ + if (InjectedConfig->InjectedOffsetNumber == ADC_OFFSET_4) + { + ADCx->OFR4 = ADC_OFR4_OFFSET_EN | (uint32_t)InjectedConfig->InjectedOffsetSign | (uint32_t)(InjectedConfig->InjectedChannel << 26) | + (uint32_t)(InjectedConfig->InjectedOffsetSaturation << 25) | (uint32_t)InjectedConfig->InjectedOffset ; + } + } + else + { + /* Reset register OFR1 */ + if (InjectedConfig->InjectedChannel == ((ADCx->OFR1 >> 26) & 0x1f)) + { + ADCx->OFR1 = (uint32_t)RESET; + } + + /* Reset register OFR2 */ + if (InjectedConfig->InjectedChannel == ((ADCx->OFR2 >> 26) & 0x1f)) + { + ADCx->OFR2 = (uint32_t)RESET; + } + + /* Reset register OFR3 */ + if (InjectedConfig->InjectedChannel == ((ADCx->OFR3 >> 26) & 0x1f)) + { + ADCx->OFR3 = (uint32_t)RESET; + } + + /* Reset register OFR4 */ + if (InjectedConfig->InjectedChannel == ((ADCx->OFR4 >> 26) & 0x1f)) + { + ADCx->OFR4 = (uint32_t)RESET; + } + } +} + + +/** + * @brief Configure the analog watchdog. + * @note Possibility to update parameters on the fly: + * This function initializes the selected analog watchdog, successive + * calls to this function can be used to reconfigure some parameters + * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting + * the ADC. + * The setting of these parameters is conditioned to ADC state. + * For parameters constraints, see comments of structure + * "ADC_AnalogWDGConfTypeDef". + * @note On this FT32 series, analog watchdog thresholds can be modified + * while ADC conversion is on going. + * In this case, some constraints must be taken into account: + * the programmed threshold values are effective from the next + * ADC EOC (end of unitary conversion). + * Considering that registers write delay may happen due to + * bus activity, this might cause an uncertainty on the + * effective timing of the new programmed threshold values. + * @param AnalogWDGConfig Structure of ADC analog watchdog 1 configuration + * AnalogWDG 1 Mode can be any combination of the following values: + * ADC_ANALOGWATCHDOG_SINGLE_REG + * ADC_ANALOGWATCHDOG_SINGLE_INJEC + * ADC_ANALOGWATCHDOG_SINGLE_REGINJEC + * ADC_ANALOGWATCHDOG_ALL_REG + * ADC_ANALOGWATCHDOG_ALL_INJEC + * ADC_ANALOGWATCHDOG_ALL_REGINJEC + * @param ADC_AnalogWatchdog23_Channel: the ADC channel to configure for the analog watchdog. + * This parameter can be one of the following values: + * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected + * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected + * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected + * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected + * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected + * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected + * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected + * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected + * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected + * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected + * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected + * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected + * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected + * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected + * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected + * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected + * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected + * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected + * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected + * @note The channel selected on the AWDCH must be also set into the AWDxCR + * register + * @retval None + */ + +void ADC_AnalogWDGConfig(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_ANALOG_WATCHDOG_1_MODE(AnalogWDGConfig->WatchdogMode)); + assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); + assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig)); + + if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || + (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) + { + assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); + } + + /* Set AnologWatchdog */ + if (((ADCx->CR & ADC_CR_ADSTART) != ADC_CR_ADSTART) || ((ADCx->CR & ADC_CR_JADSTART) != ADC_CR_JADSTART)) + { + /* Analog watchdog configuration */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* Configuration of analog watchdog: */ + /* - Set the analog watchdog enable mode: one or overall group of */ + /* channels, on groups regular and-or injected. */ + if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)) + { + ADCx->CFGR1 &= (uint32_t)~(ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1CH); + ADCx->CFGR1 |= (uint32_t)(AnalogWDGConfig->WatchdogMode | (AnalogWDGConfig->Channel << 26)); + } + else if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_ALL_REG) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_ALL_INJEC) || (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_ALL_REGINJEC)) + { + ADCx->CFGR1 &= (uint32_t)~(ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1SGL); + ADCx->CFGR1 |= (uint32_t)AnalogWDGConfig->WatchdogMode; + } + else + { + /* Disable Analog watchdog 1 configuration */ + ADCx->CFGR1 &= (uint32_t)~(ADC_CFGR1_AWD1EN | ADC_CFGR1_JAWD1EN | ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1SGL); + } + + /* Set the filtering configuration */ + ADCx->TR1 &= (uint32_t)~ADC_TR1_AWDFILT; + ADCx->TR1 |= (uint32_t)AnalogWDGConfig->FilteringConfig; + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for ADC_IRQHandler() */ + /* (in case left enabled by previous ADC operations). */ + ADCx->ISR |= (uint32_t)ADC_ISR_AWD1; + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + ADC_ITConfig(ADCx, ADC_IT_AWD1, ENABLE); + } + else + { + ADC_ITConfig(ADCx, ADC_IT_AWD1, DISABLE); + } + } + else + { + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + if (AnalogWDGConfig->Channel == (uint32_t)RESET) + { + ADCx->AWD2CR = (uint32_t)AnalogWDGConfig->Channel; + } + else + { + ADCx->AWD2CR = (uint32_t)RESET; + } + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for ADC_IRQHandler() */ + /* (in case left enabled by previous ADC operations). */ + ADCx->ISR |= ADC_ISR_AWD2; + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + ADC_ITConfig(ADCx, ADC_IT_AWD2, ENABLE); + } + else + { + ADC_ITConfig(ADCx, ADC_IT_AWD2, DISABLE); + } + } + else if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) + { + if (AnalogWDGConfig->Channel == (uint32_t)RESET) + { + ADCx->AWD3CR = (uint32_t)AnalogWDGConfig->Channel; + } + else + { + ADCx->AWD3CR = (uint32_t)RESET; + } + + /* Clear flag ADC analog watchdog */ + /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ + /* to use for ADC_IRQHandler() */ + /* (in case left enabled by previous ADC operations). */ + ADCx->ISR |= ADC_ISR_AWD3; + + /* Configure ADC analog watchdog interrupt */ + if (AnalogWDGConfig->ITMode == ENABLE) + { + ADC_ITConfig(ADCx, ADC_IT_AWD3, ENABLE); + } + else + { + ADC_ITConfig(ADCx, ADC_IT_AWD3, DISABLE); + } + } + } + } + + + /* Analog watchdog thresholds configuration */ + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) + { + /* These value configure the ADC threshold value depending of ADC resolution */ + if (ADC_InitStruct->Resolution == ADC_RESOLUTION_6B) + { + ADCx->TR1 &= (uint32_t)~(ADC_TR1_LT1 | ADC_TR1_HT1); + ADCx->TR1 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xfc0) << 16) | (AnalogWDGConfig->LowThreshold & 0xfc0)); + } + else if (ADC_InitStruct->Resolution == ADC_RESOLUTION_8B) + { + ADCx->TR1 &= (uint32_t)~(ADC_TR1_LT1 | ADC_TR1_HT1); + ADCx->TR1 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xff0) << 16) | (AnalogWDGConfig->LowThreshold & 0xff0)); + } + else if (ADC_InitStruct->Resolution == ADC_RESOLUTION_10B) + { + ADCx->TR1 &= (uint32_t)~(ADC_TR1_LT1 | ADC_TR1_HT1); + ADCx->TR1 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xffc) << 16) | (AnalogWDGConfig->LowThreshold & 0xffc)); + } + else + { + ADCx->TR1 &= (uint32_t)~(ADC_TR1_LT1 | ADC_TR1_HT1); + ADCx->TR1 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xfff) << 16) | (AnalogWDGConfig->LowThreshold & 0xfff)); + } + } + + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) + { + if (ADC_InitStruct->Resolution == ADC_RESOLUTION_6B) + { + ADCx->TR2 &= (uint32_t)~(ADC_TR2_LT2 | ADC_TR2_HT2); + ADCx->TR2 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xfc) << 16) | (AnalogWDGConfig->LowThreshold & 0xfc)); + } + else if (ADC_InitStruct->Resolution == ADC_RESOLUTION_8B) + { + ADCx->TR2 &= (uint32_t)~(ADC_TR2_LT2 | ADC_TR2_HT2); + ADCx->TR2 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xff) << 16) | (AnalogWDGConfig->LowThreshold & 0xff)); + } + else if (ADC_InitStruct->Resolution == ADC_RESOLUTION_10B) + { + ADCx->TR2 &= (uint32_t)~(ADC_TR2_LT2 | ADC_TR2_HT2); + ADCx->TR2 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xff) << 16) | (AnalogWDGConfig->LowThreshold & 0xff)); + } + else + { + ADCx->TR2 &= (uint32_t)~(ADC_TR2_LT2 | ADC_TR2_HT2); + ADCx->TR2 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xff) << 16) | (AnalogWDGConfig->LowThreshold & 0xff)); + } + } + + if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) + { + if (ADC_InitStruct->Resolution == ADC_RESOLUTION_6B) + { + ADCx->TR3 &= (uint32_t)~(ADC_TR3_LT3 | ADC_TR3_HT3); + ADCx->TR3 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xfc) << 16) | (AnalogWDGConfig->LowThreshold & 0xfc)); + } + else if (ADC_InitStruct->Resolution == ADC_RESOLUTION_8B) + { + ADCx->TR3 &= (uint32_t)~(ADC_TR3_LT3 | ADC_TR3_HT3); + ADCx->TR3 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xff) << 16) | (AnalogWDGConfig->LowThreshold & 0xff)); + } + else if (ADC_InitStruct->Resolution == ADC_RESOLUTION_10B) + { + ADCx->TR3 &= (uint32_t)~(ADC_TR3_LT3 | ADC_TR3_HT3); + ADCx->TR3 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xff) << 16) | (AnalogWDGConfig->LowThreshold & 0xff)); + } + else + { + ADCx->TR3 &= (uint32_t)~(ADC_TR3_LT3 | ADC_TR3_HT3); + ADCx->TR3 |= (uint32_t)(((AnalogWDGConfig->HighThreshold & 0xff) << 16) | (AnalogWDGConfig->LowThreshold & 0xff)); + } + } +} + + +/** + * @brief Active the Calibration operation in the mode single-ended + * for the selected ADC. + * @note The Calibration can be initiated only when ADC is still in the + * reset configuration (ADEN must be equal to 0). + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval ADC Calibration factor + */ +uint32_t ADC_StartSingleCalibration(ADC_TypeDef* ADCx) +{ + uint32_t tmpreg = 0x0, calibrationcounter = 0x0, calibrationstatus = 0x0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Set the diff calibration mode */ + ADCx->CR &= (uint32_t)~ADC_CR_ADCALDIF; + + /* Set the ADC calibration */ + ADCx->CR |= (uint32_t)ADC_CR_ADCAL; + + /* Wait until no ADC calibration is completed */ + do + { + calibrationstatus = ADCx->CR & ADC_CR_ADCAL; + calibrationcounter++; + } + while ((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00)); + + if ((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET) + { + /*Get the calibration factor from the ADC data register */ + tmpreg = (uint32_t)(ADCx->CALFACT & ADC_CALFACT_S); + } + else + { + /* Error factor */ + tmpreg = (uint32_t)RESET; + } + return tmpreg; +} + + +/** + * @brief Get ADC calibration factor in the mode single-ended. + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref ADC_SingleCalibrationStart(). + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7F + */ +uint32_t ADC_GetSingleCalibrationFactor(ADC_TypeDef* ADCx) +{ + uint32_t tmpreg = 0x0, calibrationcounter = 0x0, calibrationstatus = 0x0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /*Get the calibration factor from the ADC data register */ + tmpreg = (uint32_t)(ADCx->CALFACT & ADC_CALFACT_S); + + return tmpreg; +} + + +/** + * @brief Active the Calibration operation in the mode differential + * for the selected ADC. + * @note The Calibration can be initiated only when ADC is still in the + * reset configuration (ADEN must be equal to 0). + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval ADC Calibration factor + */ +uint32_t ADC_StartDiffCalibration(ADC_TypeDef* ADCx) +{ + uint32_t tmpreg = 0x0, calibrationcounter = 0x0, calibrationstatus = 0x0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Set the diff calibration mode */ + ADCx->CR |= (uint32_t)ADC_CR_ADCALDIF; + + /* Set the ADC calibration */ + ADCx->CR |= (uint32_t)ADC_CR_ADCAL; + + /* Wait until no ADC calibration is completed */ + do + { + calibrationstatus = ADCx->CR & ADC_CR_ADCAL; + calibrationcounter++; + } + while ((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00)); + + if ((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET) + { + /*Get the calibration factor from the ADC data register */ + tmpreg = (uint32_t)((ADCx->CALFACT & ADC_CALFACT_D) >> 16); + } + else + { + /* Error factor */ + tmpreg = (uint32_t)RESET; + } + return tmpreg; +} + + +/** + * @brief Get ADC calibration factor in the mode differential. + * @note Calibration factors are set by hardware after performing + * a calibration run using function @ref ADC_DiffCalibrationStart(). + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x7F + */ +uint32_t ADC_GetDiffCalibrationFactor(ADC_TypeDef* ADCx) +{ + uint32_t tmpreg = 0x0, calibrationcounter = 0x0, calibrationstatus = 0x0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /*Get the calibration factor from the ADC data register */ + tmpreg = (uint32_t)((ADCx->CALFACT & ADC_CALFACT_D) >> 16); + + return tmpreg; +} + + +/** + * @brief Set ADC calibration factor in the mode single-ended + * for the selected ADC. + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref ADC_GetSingleCalibrationFactor(). + * @note Set calibration factor must ensure ADEN=1, ADSTART + * and JADSTART equal to 0. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param Calfact_S Value between Min_Data=0x00 and Max_Data=0x7F + * @retval None + */ +void ADC_SetSingleCalibrationFactor(ADC_TypeDef* ADCx, uint32_t Calfact_S) +{ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Reset the ADC Single mode calibration factor */ + ADCx->CALFACT &= (uint32_t)~ADC_CALFACT_S; + + /* Set the ADC Single mode calibration factor */ + ADCx->CALFACT |= (uint32_t)Calfact_S; +} + + +/** + * @brief Set ADC calibration factor in the mode differential + * for the selected ADC. + * @note This function is intended to set calibration parameters + * without having to perform a new calibration using + * @ref ADC_GetDiffCalibrationFactor(). + * @note Set calibration factor must ensure ADEN=1, ADSTART + * and JADSTART equal to 0. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param Calfact_D Value between Min_Data=0x00 and Max_Data=0x7F + * @retval None + */ +void ADC_SetDiffCalibrationFactor(ADC_TypeDef* ADCx, uint32_t Calfact_D) +{ + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Reset the ADC Single mode calibration factor */ + ADCx->CALFACT &= (uint32_t)~ADC_CALFACT_D; + + /* Set the ADC Single mode calibration factor */ + ADCx->CALFACT |= (uint32_t)(Calfact_D << 16); +} + + + +/** + * @brief Start Conversion for the selected ADC regular channels. + * @note In continuous mode, ADSTART is not cleared by hardware with the + * assertion of EOSEQ because the sequence is automatic relaunched + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval None + */ +void ADC_REG_StartOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_ADSTART; +} + + +/** + * @brief Stop the on going ADCx group regular conversions for the selected ADC. + * @note When ADSTP is set, any on ADCx group regular going conversion is aborted, + * and the ADC data register is not updated with current conversion. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval None + */ +void ADC_REG_StopOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_ADSTP; +} + + +/** + * @brief Start Conversion for the selected ADC injected channels. + * @note In continuous mode, JADSTART is not cleared by hardware with the + * assertion of EOSEQ because the sequence is automatic relaunched + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval None + */ +void ADC_INJ_StartOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_JADSTART; +} + + +/** + * @brief Stop the on going ADCx group injected conversions for the selected ADC. + * @note When JADSTP is set, any on ADCx group injected going conversion is aborted, + * and the ADC data register is not updated with current conversion. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval None + */ +void ADC_INJ_StopOfConversion(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CR |= (uint32_t)ADC_CR_JADSTP; +} + + +/** + * @brief Returns the last ADCx conversion result data for ADC regular channel. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @retval The Data conversion value. + */ +uint16_t ADC_REG_GetConversionValue(ADC_TypeDef* ADCx) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + /* Return the selected ADC conversion value */ + return (uint16_t)ADCx->DR; +} + + +/** + * @brief Returns the last ADCx conversion result data for ADC injected channel. + * @param ADCx: where x can be 1/2/3 to select the ADCx peripheral. + * @param INJ_RANK can be one of the following values: + * @ref ADC_INJECTED_RANK_1 : return to JDR1 data + * @ref ADC_INJECTED_RANK_2 : return to JDR2 data + * @ref ADC_INJECTED_RANK_3 : return to JDR3 data + * @ref ADC_INJECTED_RANK_4 : return to JDR4 data + * @retval The Data conversion value. + */ +uint16_t ADC_INJ_GetConversionValue(ADC_TypeDef* ADCx, uint32_t INJ_RANK) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_INJECTED_RANK(INJ_RANK)); + + /* Return the selected ADC conversion value */ + if (INJ_RANK == ADC_INJECTED_RANK_1) + { + return (uint16_t)ADCx->JDR1; + } + else if (INJ_RANK == ADC_INJECTED_RANK_2) + { + return (uint16_t)ADCx->JDR2; + } + else if (INJ_RANK == ADC_INJECTED_RANK_3) + { + return (uint16_t)ADCx->JDR3; + } + else if (INJ_RANK == ADC_INJECTED_RANK_4) + { + return (uint16_t)ADCx->JDR4; + } + else + { + return 0x00; + } +} + +/** + * @} + */ + + +/** + * @brief Get ADC multimode conversion data of ADC master, ADC slave + * or raw data with ADC master and slave concatenated. + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +uint32_t ADC_ReadMultiConversionData32(void) +{ + return (uint32_t)ADC_Common->CDR; +} + + +/** + * @brief Enables or disables the specified ADC DMA request. + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param NewState: new state of the selected ADC DMA transfer. + * This parameter can be: ENABLE or DISABLE. + * @note This function must be configured before group injected + * otherwise, the configuration of the group injected may + * be reset when JQDIS=1. + * @retval None + */ +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC DMA request */ + ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN; + } + else + { + /* Disable the selected ADC DMA request */ + ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN); + } +} + +/** + * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode) + * @param ADCx: where x can be 1 to select the ADC1 peripheral. + * @param ADC_DMARequestMode: the ADC channel to configure. + * This parameter can be one of the following values: + * @arg ADC_DMAMode_OneShot: DMA One Shot Mode + * @arg ADC_DMAMode_Circular: DMA Circular Mode + * @note This function must be configured before group injected + * otherwise, the configuration of the group injected may + * be reset when JQDIS=1. + * @retval None + */ +void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + + ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG; + ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode; +} + +/** + * @} + */ +/** + * @brief Enables or disables the specified ADC interrupts. + * @param ADCx: where x can be 1/2/3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC Ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: ADC group regular end of conversion interrupt + * @arg ADC_IT_EOSEQ: ADC group regular end of Sequence interrupt + * @arg ADC_IT_OVR: ADC group regular overrun interrupt + * @arg ADC_IT_JEOC: ADC group injected end of conversion interrupt + * @arg ADC_IT_JEOSEQ: ADC group injected end of Sequence interrupt + * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt + * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt + * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt + * @arg ADC_IT_JQOVF: ADC group injected contexts queue overflow interrupt + * @param NewState: new state of the specified ADC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_ADC_CONFIG_IT(ADC_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected ADC interrupts */ + ADCx->IER |= ADC_IT; + } + else + { + /* Disable the selected ADC interrupts */ + ADCx->IER &= (~(uint32_t)ADC_IT); + } +} + +/** + * @brief Checks whether the specified ADC flag is set or not. + * @param ADCx: where x can be 1/2/3 to select the ADC1 peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_ADRDY: ADC Ready flag + * @arg ADC_FLAG_EOSMP: End of sampling flag + * @arg ADC_FLAG_EOC: ADC group regular end of conversion flag + * @arg ADC_FLAG_EOSEQ: ADC group regular end of Sequence flag + * @arg ADC_FLAG_OVR: ADC group regular overrun flag + * @arg ADC_FLAG_JEOC: ADC group injected end of conversion flag + * @arg ADC_FLAG_JEOSEQ: ADC group injected end of Sequence flag + * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag + * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag + * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag + * @arg ADC_FLAG_JQOVF: ADC group injected contexts queue overflow flag + * @arg ADC_FLAG_ADEN: ADC enable flag + * @arg ADC_FLAG_ADDIS: ADC disable flag + * @arg ADC_FLAG_ADSTART: ADC start flag + * @arg ADC_FLAG_ADSTP: ADC stop flag + * @arg ADC_FLAG_ADCAL: ADC Calibration flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + if ((uint32_t)(ADC_FLAG & 0x01000000)) + { + tmpreg = ADCx->CR & 0xFEFFFFFF; + } + else + { + tmpreg = ADCx->ISR; + } + + /* Check the status of the specified ADC flag */ + if ((tmpreg & ADC_FLAG) != (uint32_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ADC_FLAG status */ + return bitstatus; +} + + +/** + * @brief Checks whether the specified ADC MultiMode flag is set or not. + * @param ADCx: where x can be 1/2/3 to select the ADC1 peripheral. + * @param ADC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg ADC_FLAG_ADRDY: ADC Ready flag + * @arg ADC_FLAG_EOSMP: End of sampling flag + * @arg ADC_FLAG_EOC: ADC group regular end of conversion flag + * @arg ADC_FLAG_EOSEQ: ADC group regular end of Sequence flag + * @arg ADC_FLAG_OVR: ADC group regular overrun flag + * @arg ADC_FLAG_JEOC: ADC group injected end of conversion flag + * @arg ADC_FLAG_JEOSEQ: ADC group injected end of Sequence flag + * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag + * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag + * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag + * @arg ADC_FLAG_JQOVF: ADC group injected contexts queue overflow flag + * @retval The new state of ADC_FLAG (SET or RESET). + */ +FlagStatus ADC_GetMultiFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_FLAG(ADC_FLAG)); + + /* Check the status of the specified ADC flag */ + if (ADCx == ADC1) + { + if ((ADC_Common->CSR1 & ADC_FLAG) != (uint32_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + } + else if (ADCx == ADC2) + { + if ((ADC_Common->CSR1 & (ADC_FLAG << 16)) != (uint32_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + } + else if (ADCx == ADC3) + { + if ((ADC_Common->CSR2 & ADC_FLAG) != (uint32_t)RESET) + { + /* ADC_FLAG is set */ + bitstatus = SET; + } + else + { + /* ADC_FLAG is reset */ + bitstatus = RESET; + } + } + + /* Return the ADC_FLAG status */ + return bitstatus; +} + + +/** + * @brief Clears the ADCx's pending flags. + * @param ADCx: where x can be 1/2/3 to select the ADC1 peripheral. + * @param ADC_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg ADC_FLAG_ADRDY: ADC Ready flag + * @arg ADC_FLAG_EOSMP: End of sampling flag + * @arg ADC_FLAG_EOC: ADC group regular end of conversion flag + * @arg ADC_FLAG_EOSEQ: ADC group regular end of Sequence flag + * @arg ADC_FLAG_OVR: ADC group regular overrun flag + * @arg ADC_FLAG_JEOC: ADC group injected end of conversion flag + * @arg ADC_FLAG_JEOSEQ: ADC group injected end of Sequence flag + * @arg ADC_FLAG_AWD1: ADC Analog watchdog 1 flag + * @arg ADC_FLAG_AWD2: ADC Analog watchdog 2 flag + * @arg ADC_FLAG_AWD3: ADC Analog watchdog 3 flag + * @arg ADC_FLAG_JQOVF: ADC group injected contexts queue overflow flag + * @retval None + */ +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG)); + + /* Clear the selected ADC flags */ + ADCx->ISR = (uint32_t)ADC_FLAG; +} + +/** + * @brief Checks whether the specified ADC interrupt has occurred or not. + * @param ADCx: where x can be 1/2/3 to select the ADC peripheral + * @param ADC_IT: specifies the ADC interrupt source to check. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC Ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: ADC group regular end of conversion interrupt + * @arg ADC_IT_EOSEQ: ADC group regular end of Sequence interrupt + * @arg ADC_IT_OVR: ADC group regular overrun interrupt + * @arg ADC_IT_JEOC: ADC group injected end of conversion interrupt + * @arg ADC_IT_JEOSEQ: ADC group injected end of Sequence interrupt + * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt + * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt + * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt + * @arg ADC_IT_JQOVF: ADC group injected contexts queue overflow interrupt + * @retval The new state of ADC_IT (SET or RESET). + */ +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_GET_IT(ADC_IT)); + + /* Get the ADC_IT enable bit status */ + enablestatus = (uint32_t)(ADCx->IER & ADC_IT); + + /* Check the status of the specified ADC interrupt */ + if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + /* ADC_IT is set */ + bitstatus = SET; + } + else + { + /* ADC_IT is reset */ + bitstatus = RESET; + } + /* Return the ADC_IT status */ + return bitstatus; +} + + +/** + * @brief Clears the ADCx's interrupt pending bits. + * @param ADCx: where x can be 1/2/3 to select the ADC peripheral. + * @param ADC_IT: specifies the ADC interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg ADC_IT_ADRDY: ADC Ready interrupt + * @arg ADC_IT_EOSMP: End of sampling interrupt + * @arg ADC_IT_EOC: ADC group regular end of conversion interrupt + * @arg ADC_IT_EOSEQ: ADC group regular end of Sequence interrupt + * @arg ADC_IT_OVR: ADC group regular overrun interrupt + * @arg ADC_IT_JEOC: ADC group injected end of conversion interrupt + * @arg ADC_IT_JEOSEQ: ADC group injected end of Sequence interrupt + * @arg ADC_IT_AWD1: ADC Analog watchdog 1 interrupt + * @arg ADC_IT_AWD2: ADC Analog watchdog 2 interrupt + * @arg ADC_IT_AWD3: ADC Analog watchdog 3 interrupt + * @arg ADC_IT_JQOVF: ADC group injected contexts queue overflow interrupt + * @retval None + */ +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT) +{ + /* Check the parameters */ + assert_param(IS_ADC_ALL_PERIPH(ADCx)); + assert_param(IS_ADC_CLEAR_IT(ADC_IT)); + + /* Clear the selected ADC interrupt pending bits */ + ADCx->ISR = (uint32_t)ADC_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_comp.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_comp.c new file mode 100644 index 00000000000..b0046646987 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_comp.c @@ -0,0 +1,689 @@ +/** + ****************************************************************************** + * @file ft32f4xx_comp.c + * @author FMD xzhang + * @brief This file provides firmware functions to manage the following + * functionalities of the comparators (COMP1 COMP2 COMP3 COMP4 COMP5 COMP6) peripheral: + * + Comparators configuration + * + Window mode control + * + RAMP mode control + * + QUALIFICATION mode control + * @version V1.0.0 + * @date 2025-03-20 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_comp.h" + +/** + * @brief Initializes the COMP peripheral according to the specified parameters + * in COMP_InitStruct + * @note If the selected comparator is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @arg COMP_Selection_COMP3: COMP3 selected + * @arg COMP_Selection_COMP4: COMP4 selected + * @arg COMP_Selection_COMP5: COMP5 selected + * @arg COMP_Selection_COMP6: COMP6 selected + * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains + * the configuration information for the specified COMP peripheral. + * @retval None + */ +void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef *COMP_InitStruct) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + assert_param(IS_COMP_BLANKING(COMP_InitStruct ->COMP_Blanking_Sel)); + assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct ->COMP_Hysteresis_Sel)); + assert_param(IS_COMP_POL(COMP_InitStruct ->COMP_Pol)); + + /*!< Configure COMP: COMP_VipSel, COMP_VinSel,COMP_Blanking_Sel ,COMP_Hysteresis_Sel , COMP_Pol */ + tmpreg = (uint32_t)((COMP_InitStruct ->COMP_VipSel | COMP_InitStruct ->COMP_VinSel | COMP_InitStruct -> COMP_Blanking_Sel | COMP_InitStruct ->COMP_Hysteresis_Sel | COMP_InitStruct ->COMP_Pol)); + + if (COMP_Selection == COMP_Selection_COMP1) + { + /* Check the parameters */ + assert_param(IS_COMP1_VIP_SEL(COMP_InitStruct ->COMP_VipSel)); + assert_param(IS_COMP1_VIN_SEL(COMP_InitStruct ->COMP_VinSel)); + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC -> COMP1_CSR = tmpreg; + } + else if (COMP_Selection == COMP_Selection_COMP2) + { + /* Check the parameters */ + assert_param(IS_COMP2_VIP_SEL(COMP_InitStruct ->COMP_VipSel)); + assert_param(IS_COMP2_VIN_SEL(COMP_InitStruct ->COMP_VinSel)); + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC -> COMP2_CSR = tmpreg; + } + else if (COMP_Selection == COMP_Selection_COMP3) + { + /* Check the parameters */ + assert_param(IS_COMP3_VIP_SEL(COMP_InitStruct ->COMP_VipSel)); + assert_param(IS_COMP3_VIN_SEL(COMP_InitStruct ->COMP_VinSel)); + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC -> COMP3_CSR = tmpreg; + } + else if (COMP_Selection == COMP_Selection_COMP4) + { + /* Check the parameters */ + assert_param(IS_COMP4_VIP_SEL(COMP_InitStruct ->COMP_VipSel)); + assert_param(IS_COMP4_VIN_SEL(COMP_InitStruct ->COMP_VinSel)); + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC -> COMP4_CSR = tmpreg; + } + else if (COMP_Selection == COMP_Selection_COMP5) + { + /* Check the parameters */ + assert_param(IS_COMP5_VIP_SEL(COMP_InitStruct ->COMP_VipSel)); + assert_param(IS_COMP5_VIN_SEL(COMP_InitStruct ->COMP_VinSel)); + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC -> COMP5_CSR = tmpreg; + } + else if (COMP_Selection == COMP_Selection_COMP6) + { + /* Check the parameters */ + assert_param(IS_COMP6_VIP_SEL(COMP_InitStruct ->COMP_VipSel)); + assert_param(IS_COMP6_VIN_SEL(COMP_InitStruct ->COMP_VinSel)); + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC -> COMP6_CSR = tmpreg; + } +} + +/** + * @brief Deinitializes COMP peripheral registers to their default reset values. + * @note Deinitialization can't be performed if the COMP configuration is locked. + * To unlock the configuration, perform a system reset. + * @param None + * @retval None + */ +void COMP_DeInit(uint32_t COMP_Selection) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + + if (COMP_Selection == COMP_Selection_COMP1) + { + COMP_OPAM_DAC -> COMP1_CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ + COMP_OPAM_DAC -> COMP1_RAMPMAXREF_SHADOW = ((uint32_t)0x00000000); /*!< Set COMP1_RAMPMAXREF_SHADOW register to reset value */ + COMP_OPAM_DAC -> COMP1_RAMPDECVAL_SHADOW = ((uint32_t)0x00000000); /*!< Set COMP1_RAMPDECVAL_SHADOW register to reset value */ + } + else if (COMP_Selection == COMP_Selection_COMP2) + { + COMP_OPAM_DAC -> COMP2_CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ + COMP_OPAM_DAC -> COMP2_RAMPMAXREF_SHADOW = ((uint32_t)0x00000000); /*!< Set COMP2_RAMPMAXREF_SHADOW register to reset value */ + COMP_OPAM_DAC -> COMP2_RAMPDECVAL_SHADOW = ((uint32_t)0x00000000); /*!< Set COMP2_RAMPDECVAL_SHADOW register to reset value */ + } + else if (COMP_Selection == COMP_Selection_COMP3) + { + COMP_OPAM_DAC -> COMP3_CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ + } + else if (COMP_Selection == COMP_Selection_COMP4) + { + COMP_OPAM_DAC -> COMP4_CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ + } + else if (COMP_Selection == COMP_Selection_COMP5) + { + COMP_OPAM_DAC -> COMP5_CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ + } + else if (COMP_Selection == COMP_Selection_COMP6) + { + COMP_OPAM_DAC -> COMP6_CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */ + } + +} + + +/** + * @brief Enable or disable the COMP peripheral. + * @note If the selected comparator is locked, enable/disable can't be performed. + * To unlock the configuration, perform a system reset. + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @arg COMP_Selection_COMP3: COMP3 selected + * @arg COMP_Selection_COMP4: COMP4 selected + * @arg COMP_Selection_COMP5: COMP5 selected + * @arg COMP_Selection_COMP6: COMP6 selected + * @param NewState: new state of the COMP peripheral. + * This parameter can be: ENABLE or DISABLE. + * @note When enabled, the comparator compares the non inverting input with + * the inverting input and the comparison result is available on comparator output. + * @note When disabled, the comparator doesn't perform comparison and the + * output level is low. + * @retval None + */ +void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + if (COMP_Selection == COMP_Selection_COMP1) + { + COMP_OPAM_DAC -> COMP1_CSR |= COMP_EN; //enable comp1 + } + else if (COMP_Selection == COMP_Selection_COMP2) + { + COMP_OPAM_DAC -> COMP2_CSR |= COMP_EN; //enable comp2 + } + else if (COMP_Selection == COMP_Selection_COMP3) + { + COMP_OPAM_DAC -> COMP3_CSR |= COMP_EN; //enable comp3 + } + else if (COMP_Selection == COMP_Selection_COMP4) + { + COMP_OPAM_DAC -> COMP4_CSR |= COMP_EN; //enable comp4 + } + else if (COMP_Selection == COMP_Selection_COMP5) + { + COMP_OPAM_DAC -> COMP5_CSR |= COMP_EN; //enable comp5 + } + else if (COMP_Selection == COMP_Selection_COMP6) + { + COMP_OPAM_DAC -> COMP6_CSR |= COMP_EN; //enable comp6 + } + } + else + { + if (COMP_Selection == COMP_Selection_COMP1) + { + COMP_OPAM_DAC -> COMP1_CSR &= ~COMP_EN; //disable comp1 + } + else if (COMP_Selection == COMP_Selection_COMP2) + { + COMP_OPAM_DAC -> COMP2_CSR &= ~COMP_EN; //disable comp2 + } + else if (COMP_Selection == COMP_Selection_COMP3) + { + COMP_OPAM_DAC -> COMP3_CSR &= ~COMP_EN; //disable comp3 + } + else if (COMP_Selection == COMP_Selection_COMP4) + { + COMP_OPAM_DAC -> COMP4_CSR &= ~COMP_EN; //disable comp4 + } + else if (COMP_Selection == COMP_Selection_COMP5) + { + COMP_OPAM_DAC -> COMP5_CSR &= ~COMP_EN; //disable comp5 + } + else if (COMP_Selection == COMP_Selection_COMP6) + { + COMP_OPAM_DAC -> COMP6_CSR &= ~COMP_EN; //disable comp6 + } + } +} +/** + * @} + */ +/** + * @brief Enables or disables the window mode. + * @note In window mode, COMP3 COMP4 are connected together,COMP5 COMP6 are connected together + * if select COMP3 's window mode as output ,COMP4 will not enable COMPx_OUTSEL; + * if select COMP4 's window mode as output ,COMP3 will not enable COMPx_OUTSEL; + * if select COMP5 's window mode as output ,COMP6 will not enable COMPx_OUTSEL; + * if select COMP6 's window mode as output ,COMP5 will not enable COMPx_OUTSEL; + * @param NewState: new state of the window mode. + * This parameter can be : + * @arg ENABLE: COMP3 and COMP4 or COMP5 and COMP6 are connected together. + * @arg DISABLE: COMP3 and COMP4 or COMP5 and COMP6 are disconnected. + * @param COMP_WIN_Selection: the selected comparator of Window mode. + * This parameter can be one of the following values: + * COMP_WIN_Selection_COMP3 : Connect INP of COMP3 to INP of COMP4 + * COMP_WIN_Selection_COMP4 : Connect INP of COMP4 to INP of COMP3 + * COMP_WIN_Selection_COMP5 : Connect INP of COMP5 to INP of COMP6 + * COMP_WIN_Selection_COMP6 : Connect INP of COMP6 to INP of COMP5 + * @retval None + */ +void COMP_WindowCmd(FunctionalState NewState, uint32_t COMP_WIN_Selection) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_COMP_WIN_PERIPH(COMP_WIN_Selection)); + + if (NewState != DISABLE) + { + if (COMP_WIN_Selection == COMP_WIN_Selection_COMP3) //comp3 inp to comp4 inp + { + /* Enable the window mode of COMP3*/ + COMP_OPAM_DAC -> COMP3_CSR |= WINMODE | OUTSEL; //enable Comp3_outsel + COMP_OPAM_DAC -> COMP4_CSR &= ~WINMODE & ~OUTSEL; //disable Comp4_outsel + } + else if (COMP_WIN_Selection == COMP_WIN_Selection_COMP4) //comp4 inp to comp3 inp + { + /* Enable the window mode of COMP4*/ + COMP_OPAM_DAC -> COMP4_CSR |= WINMODE | OUTSEL ; //enable Comp4_outsel; + COMP_OPAM_DAC -> COMP3_CSR &= ~WINMODE & ~OUTSEL ; //disable Comp3_outsel; + } + else if (COMP_WIN_Selection == COMP_WIN_Selection_COMP5)//comp5 inp to comp6 inp + { + /* Enable the window mode of COMP5*/ + COMP_OPAM_DAC -> COMP5_CSR |= WINMODE | OUTSEL ; //enable Comp5_outsel; + COMP_OPAM_DAC -> COMP6_CSR &= ~WINMODE & ~OUTSEL ; //disable Comp6_outsel; + } + else if (COMP_WIN_Selection == COMP_WIN_Selection_COMP6) //comp6 inp to comp5 inp + { + /* Enable the window mode of COMP6*/ + COMP_OPAM_DAC -> COMP6_CSR |= WINMODE | OUTSEL; //enable Comp6_outsel; + COMP_OPAM_DAC -> COMP5_CSR &= ~WINMODE & ~OUTSEL ; //disable Comp5_outsel; + } + } + else + { + if (COMP_WIN_Selection == COMP_WIN_Selection_COMP3 || COMP_WIN_Selection == COMP_WIN_Selection_COMP4) + { + /* Disable the window mode of comp3 comp4 */ + COMP_OPAM_DAC -> COMP3_CSR &= ~WINMODE & ~OUTSEL; + COMP_OPAM_DAC -> COMP4_CSR &= ~WINMODE & ~OUTSEL; + } + else if (COMP_WIN_Selection == COMP_WIN_Selection_COMP5 || COMP_WIN_Selection == COMP_WIN_Selection_COMP6) + { + /* Disable the window mode of comp5 comp6 */ + COMP_OPAM_DAC -> COMP5_CSR &= ~WINMODE & ~OUTSEL; + COMP_OPAM_DAC -> COMP6_CSR &= ~WINMODE & ~OUTSEL; + } + } +} + +/** + * @brief Select epwm from HRTIME as trigger of RAMP mode in comp1 and comp 2. + * @note If want to use RAMP function need to enable DAC_Input_sel.DAC_INPUT_SEL_RAMP firstly. + * @param COMP_1_2_Selection: select COMP1 or COMP2. + * This parameter can be : + * @arg COMP_1_2_Selection_COMP1:select COMP1 . + * @arg COMP_1_2_Selection_COMP2:select COMP2. + * @param COMP_RAMP_SEL: Select EPWM as trigger of RAMP source . + * This parameter can be one of the following values: + * COMPx_RAMPSRC_PWM1 : select EPWM1 as RAMP function trigger source + * COMPx_RAMPSRC_PWM2 : select EPWM2 as RAMP function trigger source + * COMPx_RAMPSRC_PWM3 : select EPWM3 as RAMP function trigger source + * COMPx_RAMPSRC_PWM4 : select EPWM4 as RAMP function trigger source + * @retval None + */ +void COMPx_RAMP_EPWM_SEL(uint32_t COMP_1_2_Selection, uint32_t COMP_RAMP_SEL) +{ + assert_param(IS_COMP_1_2_PERIPH(COMP_1_2_Selection)); + assert_param(IS_COMP_RAMPSRC(COMP_RAMP_SEL)); + + if (COMP_1_2_Selection == COMP_1_2_Selection_COMP1) //select COMP1 's RAMP mode + { + if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM1) //select epwm1 as trigger + { + COMP_OPAM_DAC -> COMP1_CSR |= COMPx_RAMPSRC_PWM1; + } + else if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM2) //select epwm2 as trigger + { + COMP_OPAM_DAC -> COMP1_CSR |= COMPx_RAMPSRC_PWM2; + } + else if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM3) //select epwm3 as trigger + { + COMP_OPAM_DAC -> COMP1_CSR |= COMPx_RAMPSRC_PWM3; + } + else if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM4) //select epwm4 as trigger + { + COMP_OPAM_DAC -> COMP1_CSR |= COMPx_RAMPSRC_PWM4; + } + } + else if (COMP_1_2_Selection == COMP_1_2_Selection_COMP2) //select COMP2 's RAMP mode + { + if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM1) //select epwm1 as trigger + { + COMP_OPAM_DAC -> COMP2_CSR |= COMPx_RAMPSRC_PWM1; + } + else if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM2) //select epwm2 as trigger + { + COMP_OPAM_DAC -> COMP2_CSR |= COMPx_RAMPSRC_PWM2; + } + else if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM3) //select epwm3 as trigger + { + COMP_OPAM_DAC -> COMP2_CSR |= COMPx_RAMPSRC_PWM3; + } + else if (COMP_RAMP_SEL == COMPx_RAMPSRC_PWM4) //select epwm4 as trigger + { + COMP_OPAM_DAC -> COMP2_CSR |= COMPx_RAMPSRC_PWM4; + } + } +} + +/** + * @brief Select RAMPLDIS bit to forbid COMP RAMP reset in comp1 and comp 2. + * @note If want to use RAMP function need to enable DAC_Input_sel.DAC_INPUT_SEL_RAMP firstly. + * @param COMP_1_2_Selection: select COMP1 or COMP2. + * This parameter can be : + * @arg COMP_1_2_Selection_COMP1:select COMP1 . + * @arg COMP_1_2_Selection_COMP2:select COMP2. + * @param NewState: new state of the COMP peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void COMPx_RAMP_RMPRLDIS(FunctionalState NewState, uint32_t COMP_1_2_Selection) +{ + assert_param(IS_COMP_1_2_PERIPH(COMP_1_2_Selection)); + + if (COMP_1_2_Selection == COMP_1_2_Selection_COMP1) //select COMP1 + { + if (NewState != DISABLE) + COMP_OPAM_DAC -> COMP1_CSR |= RAMPLDIS; + else + COMP_OPAM_DAC -> COMP1_CSR &= ~RAMPLDIS; + } + else if (COMP_1_2_Selection == COMP_1_2_Selection_COMP2) //select COMP2 + { + if (NewState != DISABLE) + COMP_OPAM_DAC -> COMP2_CSR |= RAMPLDIS; + else + COMP_OPAM_DAC -> COMP2_CSR &= ~RAMPLDIS; + } +} + +/** + * @brief Load RAMPDECVAL_SHADOW and RAMPMAXREF_SHADOW of COMP1 and COMP2. + * @param COMPx_RAMPDECVAL_SHADOW is 16 bit ,x=comp1 or comp2 + * @param COMPx_RAMPMAXREF_SHADOW is 16 bit ,x=comp1 or comp2 + * @param COMP_1_2_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_1_2_Selection_COMP1: COMP1 be selected + * @arg COMP_1_2_Selection_COMP2: COMP2 be selected + * @retval + */ +void COMP_RAMPVAL_SHADOW_LOAD(uint32_t COMP_1_2_Selection, uint16_t COMPx_RAMPDECVAL_SHADOW, uint16_t COMPx_RAMPMAXREF_SHADOW) +{ + /* Check the parameters */ + assert_param(IS_COMP_1_2_PERIPH(COMP_1_2_Selection)); + + if (COMP_1_2_Selection == COMP_1_2_Selection_COMP1) //select comp1 + { + /* load ramp max value*/ + COMP_OPAM_DAC -> COMP1_RAMPMAXREF_SHADOW = COMPx_RAMPMAXREF_SHADOW; + /* load ramp dec value */ + COMP_OPAM_DAC -> COMP1_RAMPDECVAL_SHADOW = COMPx_RAMPDECVAL_SHADOW; + } + else if (COMP_1_2_Selection == COMP_1_2_Selection_COMP2) //select comp2 + { + /* load ramp max value*/ + COMP_OPAM_DAC -> COMP2_RAMPMAXREF_SHADOW = COMPx_RAMPMAXREF_SHADOW; + /* load ramp dec value */ + COMP_OPAM_DAC -> COMP2_RAMPDECVAL_SHADOW = COMPx_RAMPDECVAL_SHADOW; + } + +} + + +/** + * @brief Select qualification number and enable qualification mode in comp1 and comp2. + * @note + * @param NewState: new state of the qualification mode. + * This parameter can be : + * @arg ENABLE: COMP1 or COMP2 enable qualification mode. + * @arg DISABLE: COMP1 or COMP2 disable qualification mode. + * @param COMP_1_2_Selection: select COMP1 or COMP2. + * This parameter can be : + * @arg COMP_1_2_Selection_COMP1:select COMP1. + * @arg COMP_1_2_Selection_COMP2:select COMP2. + * @param COMP_qualsel: Select qualification clk number. + * This parameter can be one of the following values: + * COMPx_QUALSEL_NONE :None select qualification clk number + * COMPx_QUALSEL_1C : select 1 clk as qualification clk number + * COMPx_QUALSEL_2C : select 2 clk as qualification clk number + * COMPx_QUALSEL_3C : select 3 clk as qualification clk number + * COMPx_QUALSEL_4C : select 4 clk as qualification clk number + * COMPx_QUALSEL_5C : select 5 clk as qualification clk number + * COMPx_QUALSEL_6C : select 6 clk as qualification clk number + * COMPx_QUALSEL_7C : select 7 clk as qualification clk number + * COMPx_QUALSEL_8C : select 8 clk as qualification clk number + * COMPx_QUALSEL_9C : select 9 clk as qualification clk number + * COMPx_QUALSEL_10C: select 10 clk as qualification clk number + * COMPx_QUALSEL_11C: select 11 clk as qualification clk number + * COMPx_QUALSEL_12C: select 12 clk as qualification clk number + * COMPx_QUALSEL_13C: select 13 clk as qualification clk number + * COMPx_QUALSEL_14C: select 14 clk as qualification clk number + * COMPx_QUALSEL_15C: select 15 clk as qualification clk number + * COMPx_QUALSEL_16C: select 16 clk as qualification clk number + * COMPx_QUALSEL_17C: select 17 clk as qualification clk number + * COMPx_QUALSEL_18C: select 18 clk as qualification clk number + * COMPx_QUALSEL_18C: select 19 clk as qualification clk number + * COMPx_QUALSEL_20C: select 20 clk as qualification clk number + * COMPx_QUALSEL_21C: select 21 clk as qualification clk number + * COMPx_QUALSEL_22C: select 22 clk as qualification clk number + * COMPx_QUALSEL_23C: select 23 clk as qualification clk number + * COMPx_QUALSEL_24C: select 24 clk as qualification clk number + * COMPx_QUALSEL_25C: select 25 clk as qualification clk number + * COMPx_QUALSEL_26C: select 26 clk as qualification clk number + * COMPx_QUALSEL_27C: select 27 clk as qualification clk number + * COMPx_QUALSEL_28C: select 28 clk as qualification clk number + * COMPx_QUALSEL_29C: select 29 clk as qualification clk number + * COMPx_QUALSEL_30C: select 30 clk as qualification clk number + * COMPx_QUALSEL_31C: select 31 clk as qualification clk number + * @retval None + */ +void COMPx_QUALIFICATION(FunctionalState NewState, uint32_t COMP_1_2_Selection, uint32_t COMP_qualsel) +{ + assert_param(IS_COMP_1_2_PERIPH(COMP_1_2_Selection)); + assert_param(IS_COMP_QUALSER_PERIPH(COMP_qualsel)); + + if (NewState != DISABLE) + { + if (COMP_1_2_Selection == COMP_1_2_Selection_COMP1) //select COMP1 + { + /* enable qualification mode in Comp1 */ + COMP_OPAM_DAC -> COMP1_CSR |= QUALEN ; + /* select qualification number and enable sync bit*/ + COMP_OPAM_DAC -> COMP1_CSR |= COMP_qualsel | SYNCSEL; + } + else if (COMP_1_2_Selection == COMP_1_2_Selection_COMP2) //select COMP2 + { + /* enable qualification mode in Comp1 */ + COMP_OPAM_DAC -> COMP2_CSR |= QUALEN ; + /* select qualification number and enable sync bit */ + COMP_OPAM_DAC -> COMP2_CSR |= COMP_qualsel | SYNCSEL; + } + } + else + { + if (COMP_1_2_Selection == COMP_1_2_Selection_COMP1) //select COMP1 + { + COMP_OPAM_DAC -> COMP1_CSR &= ~COMP_qualsel & ~SYNCSEL & ~QUALEN; + } + else if (COMP_1_2_Selection == COMP_1_2_Selection_COMP2) //select COMP2 + { + COMP_OPAM_DAC -> COMP2_CSR &= ~COMP_qualsel & ~SYNCSEL & ~QUALEN; + } + } +} + +/** + * @brief enable or disable feedback 100K resistor. + * @param NewState: new state of the RAMP mode. + * This parameter can be : + * @arg ENABLE: COMP1 or COMP2 enable feedback resistor . + * @arg DISABLE: COMP1 or COMP2 disable feedback resistor . + * @param COMP_1_2_Selection: select COMP1 or COMP2. + * This parameter can be : + * @arg COMP_1_2_Selection_COMP1:select COMP1. + * @arg COMP_1_2_Selection_COMP2:select COMP2. + * @retval None + */ +void COMPx_Resistor(FunctionalState NewState, uint32_t COMP_1_2_Selection) +{ + assert_param(IS_COMP_1_2_PERIPH(COMP_1_2_Selection)); + + if (NewState != DISABLE) + { + if (COMP_1_2_Selection == COMP_1_2_Selection_COMP1) + { + COMP_OPAM_DAC -> COMP1_CSR |= RSWITCH; //enable resistor of comp1 + } + else if (COMP_1_2_Selection == COMP_1_2_Selection_COMP2) + { + COMP_OPAM_DAC -> COMP2_CSR |= RSWITCH; //enable resistor of comp1 + } + } + else + { + if (COMP_1_2_Selection == COMP_1_2_Selection_COMP1) + { + COMP_OPAM_DAC -> COMP1_CSR &= ~RSWITCH; //disable resistor of comp1 + } + else if (COMP_1_2_Selection == COMP_1_2_Selection_COMP2) + { + COMP_OPAM_DAC -> COMP2_CSR &= ~RSWITCH; //disable resistor of comp1 + } + } +} + + +/** + * @brief Lock the selected comparator (COMP1/COMP2/COMP3/COMP4/COMP5/COMP6) configuration. + * @note Locking the configuration means that all control bits are read-only. + * To unlock the comparator configuration, perform a system reset. + * @param COMP_Selection: selects the comparator to be locked + * This parameter can be a value of the following values: + * @arg COMP_Selection_COMP1: COMP1 configuration is locked. + * @arg COMP_Selection_COMP2: COMP2 configuration is locked. + * @arg COMP_Selection_COMP3: COMP3 configuration is locked. + * @arg COMP_Selection_COMP4: COMP4 configuration is locked. + * @arg COMP_Selection_COMP5: COMP5 configuration is locked. + * @arg COMP_Selection_COMP6: COMP6 configuration is locked. + * @retval None + */ +void COMP_LockConfig(uint32_t COMP_Selection) +{ + /* Check the parameter */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + + if (COMP_Selection == COMP_Selection_COMP1) + COMP_OPAM_DAC -> COMP1_CSR |= COMP_LOCK; //lock COMP1_CSR's bit + + else if (COMP_Selection == COMP_Selection_COMP2) + COMP_OPAM_DAC -> COMP2_CSR |= COMP_LOCK; //lock COMP2_CSR's bit + + else if (COMP_Selection == COMP_Selection_COMP3) + COMP_OPAM_DAC -> COMP3_CSR |= COMP_LOCK; //lock COMP3_CSR's bit + + else if (COMP_Selection == COMP_Selection_COMP4) + COMP_OPAM_DAC -> COMP4_CSR |= COMP_LOCK; //lock COMP4_CSR's bit + + else if (COMP_Selection == COMP_Selection_COMP5) + COMP_OPAM_DAC -> COMP5_CSR |= COMP_LOCK; //lock COMP5_CSR's bit + + else if (COMP_Selection == COMP_Selection_COMP6) + COMP_OPAM_DAC -> COMP6_CSR |= COMP_LOCK; //lock COMP6_CSR's bit +} + + +/** + * @brief Return the output level (high or low) of the selected comparator ,which is behind the comp analog out and ahead of qualification . + * @note The output level NOT depends on the selected polarity. + * @note The polarity is not influence output value: + * - Comparator output is low when the non-inverting input is at a lower + * voltage than the inverting input + * - Comparator output is high when the non-inverting input is at a higher + * voltage than the inverting input + * @param COMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg COMP_Selection_COMP1: COMP1 selected + * @arg COMP_Selection_COMP2: COMP2 selected + * @arg COMP_Selection_COMP3: COMP3 selected + * @arg COMP_Selection_COMP4: COMP4 selected + * @arg COMP_Selection_COMP5: COMP5 selected + * @arg COMP_Selection_COMP6: COMP6 selected + * @retval Returns the selected comparator output level: low or high. + * + */ +uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection) +{ + uint32_t compout = 0x0; + + /* Check the parameters */ + assert_param(IS_COMP_ALL_PERIPH(COMP_Selection)); + + if (COMP_Selection == COMP_Selection_COMP1) + { + /* Check if selected comparator output is high */ + if (((COMP_OPAM_DAC -> COMP1_CSR) & COMPx_CSR_VALUE_Msk) == (uint32_t)VALUE) + { + compout = (uint32_t) COMP_OutputLevel_High >> 30; + } + else + { + compout = (uint32_t) COMP_OutputLevel_Low >> 30; + } + } + else if (COMP_Selection == COMP_Selection_COMP2) + { + /* Check if selected comparator output is high */ + if (((COMP_OPAM_DAC -> COMP2_CSR) & COMPx_CSR_VALUE_Msk) == (uint32_t)VALUE) + { + compout = (uint32_t) COMP_OutputLevel_High >> 30; + } + else + { + compout = (uint32_t) COMP_OutputLevel_Low >> 30; + } + } + else if (COMP_Selection == COMP_Selection_COMP3) + { + /* Check if selected comparator output is high */ + if (((COMP_OPAM_DAC -> COMP3_CSR) & (uint32_t)VALUE) == (uint32_t)VALUE) + { + compout = (uint32_t) COMP_OutputLevel_High >> 30; + } + else + { + compout = (uint32_t) COMP_OutputLevel_Low >> 30; + } + } + else if (COMP_Selection == COMP_Selection_COMP4) + { + /* Check if selected comparator output is high */ + if (((COMP_OPAM_DAC -> COMP4_CSR) & (uint32_t)VALUE) == (uint32_t)VALUE) + { + compout = (uint32_t) COMP_OutputLevel_High >> 30; + } + else + { + compout = (uint32_t) COMP_OutputLevel_Low >> 30; + } + } + else if (COMP_Selection == COMP_Selection_COMP5) + { + /* Check if selected comparator output is high */ + if (((COMP_OPAM_DAC -> COMP5_CSR) & (uint32_t)VALUE) == (uint32_t)VALUE) + { + compout = (uint32_t) COMP_OutputLevel_High >> 30; + } + else + { + compout = (uint32_t) COMP_OutputLevel_Low >> 30; + } + } + else if (COMP_Selection == COMP_Selection_COMP6) + { + /* Check if selected comparator output is high */ + if (((COMP_OPAM_DAC -> COMP6_CSR) & (uint32_t)VALUE) == (uint32_t)VALUE) + { + compout = (uint32_t) COMP_OutputLevel_High >> 30; + } + else + { + compout = (uint32_t) COMP_OutputLevel_Low >> 30; + } + } + /* Return the comparator output level */ + return (uint32_t)(compout); +} + + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_crc.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_crc.c new file mode 100644 index 00000000000..0f488ebc905 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_crc.c @@ -0,0 +1,239 @@ +/** + ****************************************************************************** + * @file ft32f4xx_crc.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of CRC computation unit peripheral: + * + Configuration of the CRC computation unit + * + CRC computation of one/many 32-bit data + * + CRC Independent register (IDR) access + * @version V1.0.0 + * @date 2025-03-26 + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_crc.h" +#include "ft32f4xx_rcc.h" + +/** @defgroup CRC CRC + * @brief CRC module driver + * @{ + */ + +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ + +/** + * @brief Deinitializes CRC peripheral registers to their default reset values. + * @param None + * @retval None + */ +void CRC_DeInit(void) +{ + /* Enable CRC reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1PeriphRst_CRC, ENABLE); + /* Release CRC from reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1PeriphRst_CRC, DISABLE); +} + +/** + * @brief Resets the CRC calculation unit and sets INIT register content in DR register. + * @param None + * @retval None + */ +void CRC_ResetDR(void) +{ + /* Reset CRC generator */ + CRC->CR |= CRC_CR_RESET; +} + +/** + * @brief Selects the reverse operation to be performed on input data. + * @param CRC_ReverseInputData: Specifies the reverse operation on input data. + * This parameter can be: + * @arg CRC_ReverseInputData_No: No reverse operation is performed + * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits + * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits + * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits + * @retval None + */ +void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) +{ + uint32_t tmpcr = 0; + + /* Check the parameter */ + assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); + + /* Get CR register value */ + tmpcr = CRC->CR; + + /* Reset REV_IN bits */ + tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); + /* Set the reverse operation */ + tmpcr |= (uint32_t)CRC_ReverseInputData; + + /* Write to CR register */ + CRC->CR = (uint32_t)tmpcr; +} + +/** + * @brief Enables or disable the reverse operation on output data. + * The reverse operation on output data is performed on 32-bit. + * @param NewState: new state of the reverse operation on output data. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRC_ReverseOutputDataCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable reverse operation on output data */ + CRC->CR |= CRC_CR_REV_OUT; + } + else + { + /* Disable reverse operation on output data */ + CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); + } +} + +/** + * @brief Set control register. + * @param CRC_CRValue: Programmable control register value + * @retval None + */ +void CRC_SetCRegister(uint32_t CRC_CRValue) +{ + CRC->CR = CRC_CRValue; +} + +/** + * @brief Initializes the INIT register. + * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register + * @param CRC_InitValue: Programmable initial CRC value + * @retval None + */ +void CRC_SetINITRegister(uint32_t CRC_InitValue) +{ + CRC->INIT = CRC_InitValue; +} + +/** + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * @param CRC_Data: data word(32-bit) to compute its CRC + * @retval 32-bit CRC + */ +uint32_t CRC_CalcCRC(uint32_t CRC_Data) +{ + CRC->DR = CRC_Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 16-bit CRC of a given 16-bit data. + * @param CRC_Data: data half-word(16-bit) to compute its CRC + * @retval 16-bit CRC + */ +uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data) +{ + *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 8-bit CRC of a given 8-bit data. + * @param CRC_Data: 8-bit data to compute its CRC + * @retval 8-bit CRC + */ +uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data) +{ + *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data; + + return (CRC->DR); +} + +/** + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * @param pBuffer: pointer to the buffer containing the data to be computed + * @param BufferLength: length of the buffer to be computed + * @retval 32-bit CRC + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for (index = 0; index < BufferLength; index++) + { + CRC->DR = pBuffer[index]; + } + return (CRC->DR); +} + +/** + * @brief Returns the current CRC value. + * @param None + * @retval 32-bit CRC + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DR); +} + +/** + * @brief Stores an 8-bit data in the Independent Data(ID) register. + * @param CRC_IDValue: 8-bit value to be stored in the ID register + * @retval None + */ +void CRC_SetIDRegister(uint8_t CRC_IDValue) +{ + CRC->IDR = CRC_IDValue; +} + +/** + * @brief Returns the 8-bit data stored in the Independent Data(ID) register + * @param None + * @retval 8-bit value of the ID register + */ +uint8_t CRC_GetIDRegister(void) +{ + return (uint8_t)(CRC->IDR); +} + +/** + * @brief Returns the 32-bit data in the CRC control register + * @param None + * @retval 32-bit value of the CR register + */ +uint32_t CRC_GetCRegister(void) +{ + return (CRC->CR); +} + +/** + * @brief Returns the 32-bit data in the CRC INIT register + * @param None + * @retval 32-bit value of the INIT register + */ +uint32_t CRC_GetINITRegister(void) +{ + return (CRC->INIT); +} + +/** + * @} + */ + +/** + * @} + */ + + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_crs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_crs.c new file mode 100644 index 00000000000..06f25711666 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_crs.c @@ -0,0 +1,381 @@ +/** + ****************************************************************************** + * @file ft32f4xx_crs.c + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_crs.h" +#include "system_ft32f4xx.h" +#include "ft32f4xx_rcc.h" + + +/** @defgroup CRS + * @brief CRS driver modules + * @{ + */ + +/* CRS Flag Mask */ +#define FLAG_MASK ((uint32_t)0x700) + + +/** + * @brief Deinitializes CRS peripheral registers to their default reset values. + * @param None + * @retval None + */ +void CRS_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE); +} + +/** + * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI48 RC. + * @note This function can be called only when the AUTOTRIMEN bit is reset. + * @param CRS_HSI48CalibrationValue: + * @retval None + */ +void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue) +{ + /* Clear TRIM[5:0] bits */ + CRS->CR &= ~CRS_CR_TRIM; + + /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */ + CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8); + +} + + +/** + * @brief Enables or disables the oscillator clock for frequency error counter. + * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. + * @param NewState: new state of the frequency error counter. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRS_FrequencyErrorCounterCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CRS->CR |= CRS_CR_CEN; + } + else + { + CRS->CR &= ~CRS_CR_CEN; + } +} + +/** + * @brief Enables or disables the automatic hardware adjustement of TRIM bits. + * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. + * @param NewState: new state of the automatic trimming. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRS_AutomaticCalibrationCmd(FunctionalState NewState) +{ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CRS->CR |= CRS_CR_AUTOTRIMEN; + } + else + { + CRS->CR &= ~CRS_CR_AUTOTRIMEN; + } +} + +/** + * @brief Generate the software synchronization event + * @param None + * @retval None + */ +void CRS_SoftwareSynchronizationGenerate(void) +{ + CRS->CR |= CRS_CR_SWSYNC; +} + +/** + * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI48 RC. + * @note This function can be called only when the CEN bit is reset. + * @param CRS_ReloadValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and . + * @retval None + */ +void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue) +{ + + /* Clear RELOAD[15:0] bits */ + CRS->CFGR &= ~CRS_CFGR_RELOAD; + + /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */ + CRS->CFGR |= (uint32_t)CRS_ReloadValue; + +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_ErrorLimitValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and . + * @retval None + */ +void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue) +{ + /* Clear FELIM[7:0] bits */ + CRS->CFGR &= ~CRS_CFGR_FELIM; + + /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */ + CRS->CFGR |= (uint32_t)(CRS_ErrorLimitValue << 16); +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_Prescaler: specifies the HSI calibration trimming value. + * This parameter can be one of the following values: + * @arg CRS_SYNC_Div1: + * @arg CRS_SYNC_Div2: + * @arg CRS_SYNC_Div4: + * @arg CRS_SYNC_Div8: + * @arg CRS_SYNC_Div16: + * @arg CRS_SYNC_Div32: + * @arg CRS_SYNC_Div64: + * @arg CRS_SYNC_Div128: + * @retval None + */ +void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler)); + + /* Clear SYNCDIV[2:0] bits */ + CRS->CFGR &= ~CRS_CFGR_SYNCDIV; + + /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */ + CRS->CFGR |= CRS_Prescaler; +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_Source: . + * This parameter can be one of the following values: + * @arg CRS_SYNCSource_GPIO: + * @arg CRS_SYNCSource_LSE: + * @arg CRS_SYNCSource_USB: + * @retval None + */ +void CRS_SynchronizationSourceConfig(uint32_t CRS_Source) +{ + /* Check the parameters */ + assert_param(IS_CRS_SYNC_SOURCE(CRS_Source)); + + /* Clear SYNCSRC[1:0] bits */ + CRS->CFGR &= ~CRS_CFGR_SYNCSRC; + + /* Set the SYNCSRC[1:0] bits according to CRS_Source value */ + CRS->CFGR |= CRS_Source; +} + +/** + * @brief + * @note This function can be called only when the CEN bit is reset. + * @param CRS_Polarity: . + * This parameter can be one of the following values: + * @arg CRS_SYNCPolarity_Rising: + * @arg CRS_SYNCPolarity_Falling: + * @retval None + */ +void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity) +{ + /* Check the parameters */ + assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity)); + + /* Clear SYNCSPOL bit */ + CRS->CFGR &= ~CRS_CFGR_SYNCPOL; + + /* Set the SYNCSPOL bits according to CRS_Polarity value */ + CRS->CFGR |= CRS_Polarity; +} + +/** + * @brief Returns the Relaod value. + * @param None + * @retval The reload value + */ +uint32_t CRS_GetReloadValue(void) +{ + return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD)); +} + +/** + * @brief Returns the HSI48 Calibration value. + * @param None + * @retval The reload value + */ +uint32_t CRS_GetHSI48CalibrationValue(void) +{ + return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8); +} + +/** + * @brief Returns the frequency error capture. + * @param None + * @retval The frequency error capture value + */ +uint32_t CRS_GetFrequencyErrorValue(void) +{ + return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP)); +} + +/** + * @brief Returns the frequency error direction. + * @param None + * @retval The frequency error direction. The returned value can be one + * of the following values: + * - 0x00: Up counting + * - 0x8000: Down counting + */ +uint32_t CRS_GetFrequencyErrorDirection(void) +{ + return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR)); +} + +/** + * @brief Enables or disables the specified CRS interrupts. + * @param CRS_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg CRS_IT_SYNCOK: + * @arg CRS_IT_SYNCWARN: + * @arg CRS_IT_ERR: + * @arg CRS_IT_ESYNC: + * @param NewState: new state of the specified CRS interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_CRS_IT(CRS_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + CRS->CR |= CRS_IT; + } + else + { + CRS->CR &= ~CRS_IT; + } +} + +/** + * @brief Checks whether the specified CRS flag is set or not. + * @param CRS_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CRS_FLAG_SYNCOK: + * @arg CRS_FLAG_SYNCWARN: + * @arg CRS_FLAG_ERR: + * @arg CRS_FLAG_ESYNC: + * @arg CRS_FLAG_TRIMOVF: + * @arg CRS_FLAG_SYNCERR: + * @arg CRS_FLAG_SYNCMISS: + * @retval The new state of CRS_FLAG (SET or RESET). + */ +FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CRS_FLAG(CRS_FLAG)); + + return ((FlagStatus)(CRS->ISR & CRS_FLAG)); +} + +/** + * @brief Clears the CRS specified FLAG. + * @param CRS_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg CRS_FLAG_SYNCOK: + * @arg CRS_FLAG_SYNCWARN: + * @arg CRS_FLAG_ERR: + * @arg CRS_FLAG_ESYNC: + * @arg CRS_FLAG_TRIMOVF: + * @arg CRS_FLAG_SYNCERR: + * @arg CRS_FLAG_SYNCMISS: + * @retval None + */ +void CRS_ClearFlag(uint32_t CRS_FLAG) +{ + /* Check the parameters */ + assert_param(IS_CRS_FLAG(CRS_FLAG)); + + if ((CRS_FLAG & FLAG_MASK) != 0) + { + CRS->ICR |= CRS_ICR_ERRC; + } + else + { + CRS->ICR |= CRS_FLAG; + } +} + +/** + * @brief Checks whether the specified CRS IT pending bit is set or not. + * @param CRS_IT: specifies the IT pending bit to check. + * This parameter can be one of the following values: + * @arg CRS_IT_SYNCOK: + * @arg CRS_IT_SYNCWARN: + * @arg CRS_IT_ERR: + * @arg CRS_IT_ESYNC: + * @arg CRS_IT_TRIMOVF: + * @arg CRS_IT_SYNCERR: + * @arg CRS_IT_SYNCMISS: + * @retval The new state of CRS_IT (SET or RESET). + */ +ITStatus CRS_GetITStatus(uint32_t CRS_IT) +{ + /* Check the parameters */ + assert_param(IS_CRS_GET_IT(CRS_IT)); + + return ((ITStatus)(CRS->ISR & CRS_IT)); +} + +/** + * @brief Clears the CRS specified IT pending bi. + * @param CRS_FLAG: specifies the IT pending bi to clear. + * This parameter can be one of the following values: + * @arg CRS_IT_SYNCOK: + * @arg CRS_IT_SYNCWARN: + * @arg CRS_IT_ERR: + * @arg CRS_IT_ESYNC: + * @arg CRS_IT_TRIMOVF: + * @arg CRS_IT_SYNCERR: + * @arg CRS_IT_SYNCMISS: + * @retval None + */ +void CRS_ClearITPendingBit(uint32_t CRS_IT) +{ + /* Check the parameters */ + assert_param(IS_CRS_CLEAR_IT(CRS_IT)); + + if ((CRS_IT & FLAG_MASK) != 0) + { + CRS->ICR |= CRS_ICR_ERRC; + } + else + { + CRS->ICR |= CRS_IT; + } +} + + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_dac.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_dac.c new file mode 100644 index 00000000000..e052744637f --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_dac.c @@ -0,0 +1,514 @@ +/** + ****************************************************************************** + * @file ft32f4xx_dac.c + * @author FMD xzhang + * @brief This file provides firmware functions to manage the following + * functionalities of the comparators (DAC1 DAC2 ) peripheral: + * + DAC triangle + * + DAC Noise wave + * @version V1.0.0 + * @data 2025-03-20 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_dac.h" +/* Exported types ------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Types DAC Exported Types + * @{ + + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the DAC. + (+) De-initialize the DAC. +*/ +/* + * @brief Initialize the DAC peripheral according to the specified parameters + * in the DAC_InitStruct and initialize the associated handle. + * @param DAC_1_2_Selection: the selected DAC + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC1 selected + * @arg DAC_CHANNEL_2 : DAC2 selected + * @arg DAC_CHANNEL_D12:DAC1 and DAC2 selected + * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval +*/ +void DAC_Init(uint32_t DAC_1_2_Selection, DAC_InitTypeDef* DAC_InitStruct) +{ + uint16_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + assert_param(IS_DAC_BUFFER(DAC_InitStruct -> DAC_OutputBuffer)); + assert_param(IS_DAC_TRIGGER(DAC_InitStruct -> DAC_trigger)); + + /*!< Configure : DAC_Trigger / DAC_OutputBuffer/DAC_Input_sel/DAC_Output_sel*/ + tmpreg = (uint16_t)((DAC_InitStruct ->DAC_Trigger | DAC_InitStruct -> DAC_OutputBuffer | DAC_InitStruct ->DAC_Input_sel | DAC_InitStruct -> DAC_Output_sel)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) //config DAC1 + { + /*!< Write to DAC_CSR register */ + COMP_OPAM_DAC -> DAC_CR |= (uint32_t) tmpreg; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) //config DAC2 + { + /*!< Write to DAC_CSR register */ + COMP_OPAM_DAC -> DAC_CR |= (uint32_t)(tmpreg << 16); + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) //config DAC1 and DAC2 sametime + { + /*!< Write to DAC_CSR register */ + COMP_OPAM_DAC -> DAC_CR |= (uint32_t)((tmpreg << 16) | tmpreg); + } +} + + +/** + * @brief Deinitializes DAC peripheral registers to their default reset values. + * @note Deinitializes DAC_CR DAC_SR + * @param DAC_1_2_Selection: the selected DAC + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1 : DAC1 selected + * @arg DAC_CHANNEL_2 : DAC2 selected + * @arg DAC_CHANNEL_D12:DAC1 and DAC2 selected + * @retval None + */ +void DAC_DeInit(uint32_t DAC_1_2_Selection) +{ + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + /*!< Write to DAC_CSR register */ + COMP_OPAM_DAC -> DAC_CR &= 0xffff0000; + /*DAC_SR:RC_W1*/ + COMP_OPAM_DAC -> DAC_SR |= DMAUDR1; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + /*!< Write to DAC_CSR register */ + COMP_OPAM_DAC -> DAC_CR &= 0x0000ffff; + /*DAC_SR:RC_W1*/ + COMP_OPAM_DAC -> DAC_SR |= DMAUDR2; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + /*!< Write to DAC_CSR register */ + COMP_OPAM_DAC -> DAC_CR &= 0x00000000; + COMP_OPAM_DAC -> DAC_SR |= DMAUDR1 | DMAUDR2; + } +} +/** + * @brief Enables DAC and starts conversion of channel by soft trriger once. + * the configuration information for the specified DAC. + * @param DAC_1_2_Selection The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_D12:DAC1 and DAC2 selected + * @retval + */ +void DAC_Start(uint32_t DAC_1_2_Selection) +{ + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + + /* Enable the Peripheral */ + if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + COMP_OPAM_DAC -> DAC_CR |= EN1 | EN2; + } + else + { + /*Enable DAC1 or DAC2*/ + COMP_OPAM_DAC -> DAC_CR |= (EN1 << (DAC_1_2_Selection & 0x10UL)) ; + } + //software trriger mode + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + /* Check if software trigger enabled */ + if (((COMP_OPAM_DAC -> DAC_CR) & (TEN1 | DAC_CR_TSEL1_Msk)) == DAC_TRIGGER_SOFTWARE) + { + /* Enable the selected DAC1 software conversion */ + COMP_OPAM_DAC -> DAC_SWTRIGR |= SWTRIGR1; + } + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + /* Check if software trigger enabled */ + if (((COMP_OPAM_DAC -> DAC_CR) & (TEN2 | DAC_CR_TSEL2_Msk)) == (DAC_TRIGGER_SOFTWARE << (DAC_1_2_Selection & 0x10UL))) + { + /* Enable the selected DAC2 software conversion */ + COMP_OPAM_DAC -> DAC_SWTRIGR |= SWTRIGR2; + } + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + /* Check if software trigger enabled */ + if (((COMP_OPAM_DAC -> DAC_CR) & (TEN1 | DAC_CR_TSEL1_Msk | TEN2 | DAC_CR_TSEL2_Msk)) == (DAC_TRIGGER_SOFTWARE | (DAC_TRIGGER_SOFTWARE << 0x10UL))) + { + /* Enable the selected DAC1 DAC2 software conversion */ + COMP_OPAM_DAC -> DAC_SWTRIGR |= SWTRIGR1; + COMP_OPAM_DAC -> DAC_SWTRIGR |= SWTRIGR2; + } + } +} +/** + * @brief Disables DAC and stop conversion of channel. + * the configuration information for the specified DAC. + * @param Channel The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_D12:DAC1 and DAC2 selected + * @retval + */ +void DAC_STOP(uint32_t DAC_1_2_Selection) +{ + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + /* disable the Peripheral */ + COMP_OPAM_DAC -> DAC_CR &= ~EN1; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + /* disable the Peripheral */ + COMP_OPAM_DAC -> DAC_CR &= ~EN2; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + /* disable the Peripheral */ + COMP_OPAM_DAC -> DAC_CR &= (~EN1 & ~EN2); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param DAC_1_2_Selection: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_D12: DAC Channel2 selected + * @param Alignment: Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data :Data to be loaded in the selected data holding register. + * @retval + */ +void DAC_SetValue(uint32_t DAC_1_2_Selection, uint32_t Alignment, uint32_t Data) +{ + + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + assert_param(IS_DAC_ALIGN(Alignment)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) //Data to DAC1 + { + if (Alignment == DAC_ALIGN_12B_R) //Data to DHR12R1 + { + COMP_OPAM_DAC -> DAC_DHR12R1 = Data; + } + else if (Alignment == DAC_ALIGN_12B_L) //Data to DHR12L1 + { + COMP_OPAM_DAC -> DAC_DHR12L1 = Data; + } + else if (Alignment == DAC_ALIGN_8B_R) //Data to DHR8R1 + { + COMP_OPAM_DAC -> DAC_DHR8R1 = Data; + } + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) //Data to DAC2 + { + if (Alignment == DAC_ALIGN_12B_R) //Data to DHR12R2 + { + COMP_OPAM_DAC -> DAC_DHR12R2 = Data; + } + else if (Alignment == DAC_ALIGN_12B_L) //Data to DHR12L2 + { + COMP_OPAM_DAC -> DAC_DHR12L2 = Data; + } + else if (Alignment == DAC_ALIGN_8B_R) //Data to DHR8R2 + { + COMP_OPAM_DAC -> DAC_DHR8R2 = Data; + } + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) //Data to DAC double + { + if (Alignment == DAC_ALIGN_12B_R) //Data to DHR12RD + { + COMP_OPAM_DAC -> DAC_DHR12RD = Data; + } + else if (Alignment == DAC_ALIGN_12B_L) //Data to DHR12LD + { + COMP_OPAM_DAC -> DAC_DHR12LD = Data; + } + else if (Alignment == DAC_ALIGN_8B_R) //Data to DHR8RD + { + COMP_OPAM_DAC -> DAC_DHR8RD = Data; + } + } +} + + +/** + * @brief Return the last data output value of the selected DAC channel. + * @param DAC_1_2_Selection The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t DAC_GetValue(uint32_t DAC_1_2_Selection) +{ + uint32_t result ; + + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + /*delay to read for wait DAC */ + Delay_read(); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + result = COMP_OPAM_DAC -> DAC_DOR1 ; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + result = COMP_OPAM_DAC -> DAC_DOR2 ; + } + /* Returns the DAC channel data output register value */ + return result; +} + + + + +/** + * @brief Enables DAC DMA mode and enable DMA under interrupt. + * @param DAC_1_2_Selection The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_D12:DAC1 and DAC2 selected + * @param NewState: new state of the DAC 's DMA interrupt. + * This parameter can be: ENABLE or DISABLE . + * @retval + */ +void DAC_Start_DMA(uint32_t DAC_1_2_Selection, FunctionalState NewState) +{ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + /* Enable the selected DAC channel1 DMA request */ + COMP_OPAM_DAC -> DAC_CR |= DMAEN1; + + if (NewState != DISABLE) + { + /* Enable the DAC DMA underrun interrupt */ + COMP_OPAM_DAC -> DAC_CR |= DMAUDRIE1; + } + else if (NewState == DISABLE) + { + /* Disable the DAC DMA underrun interrupt */ + COMP_OPAM_DAC -> DAC_CR &= ~DMAUDRIE1; + } + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + /* Enable the selected DAC channel1 DMA request */ + COMP_OPAM_DAC -> DAC_CR |= DMAEN2; + /* Enable the DAC DMA underrun interrupt */ + if (NewState != DISABLE) + { + COMP_OPAM_DAC -> DAC_CR |= DMAUDRIE2; + } + else if (NewState == DISABLE) + { + /* Disable the DAC DMA underrun interrupt */ + COMP_OPAM_DAC -> DAC_CR &= ~DMAUDRIE2; + } + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + COMP_OPAM_DAC -> DAC_CR |= DMAEN1 | DMAEN2; + + if (NewState != DISABLE) + { + COMP_OPAM_DAC -> DAC_CR |= DMAUDRIE1 | DMAUDRIE2; + } + else if (NewState == DISABLE) + { + /* Disable the DAC DMA underrun interrupt */ + COMP_OPAM_DAC -> DAC_CR &= (~DMAUDRIE1) & (~DMAUDRIE2); + } + } +} + + +/** + * @brief Disable DAC DMA mode and disable DMA under interrupt. + * @param DAC_1_2_Selection The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_D12:DAC1 and DAC2 selected + * @retval + */ +void DAC_Stop_DMA(uint32_t DAC_1_2_Selection) +{ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + /* Disable the selected DAC channel1 DMA request */ + COMP_OPAM_DAC -> DAC_CR &= ~DMAEN1; + /* Disable the DAC DMA underrun interrupt */ + COMP_OPAM_DAC -> DAC_CR &= ~DMAUDRIE1; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + /* Disable the selected DAC channel1 DMA request */ + COMP_OPAM_DAC -> DAC_CR &= ~DMAEN2; + /* Disable the DAC DMA underrun interrupt */ + COMP_OPAM_DAC -> DAC_CR &= ~DMAUDRIE2; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + /* Disable the selected DAC channel1 DMA request */ + COMP_OPAM_DAC -> DAC_CR &= ~DMAEN1 & ~DMAEN2; + /* Disable the DAC DMA underrun interrupt */ + COMP_OPAM_DAC -> DAC_CR &= (~DMAUDRIE1) & (~DMAUDRIE2); + } +} + + +/** + * @brief Enable or disable the selected DAC channel wave generation ,DAC_Init and DAC_Start used firstly. + * @param DAC_1_2_Selection The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @arg DAC_CHANNEL_D12:DAC1 and DAC2 selected + * @param Amplitude Select max triangle amplitude. + * This parameter can be one of the following values: + * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 + * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 + * @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7 + * @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15 + * @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31 + * @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63 + * @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127 + * @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255 + * @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511 + * @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023 + * @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047 + * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 + * @retval + */ +void DAC_TriangleWaveGenerate(uint32_t DAC_1_2_Selection, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + /* enable DAC1 triangle */ + COMP_OPAM_DAC -> DAC_CR |= WAVE1_1; + COMP_OPAM_DAC -> DAC_CR |= Amplitude; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + /* enable DAC2 triangle */ + COMP_OPAM_DAC -> DAC_CR |= WAVE2_1; + COMP_OPAM_DAC -> DAC_CR |= Amplitude << (DAC_1_2_Selection & 0x10UL); + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + /* enable DAC1 2 triangle */ + COMP_OPAM_DAC -> DAC_CR |= WAVE1_1 | WAVE2_1; + COMP_OPAM_DAC -> DAC_CR |= ((Amplitude << (DAC_CHANNEL_2 & 0x10UL)) | Amplitude); + } +} + + +/** + * @brief Enable or disable the selected DAC channel wave generation. + * @param DAC_1_2_Selection The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. + * This parameter can be one of the following values: + * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation + * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation + * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation + * @retval + */ +void DAC_NoiseWaveGenerate(uint32_t DAC_1_2_Selection, uint32_t Amplitude) +{ + /* Check the parameters */ + assert_param(IS_DAC_1_2_PERIPH(DAC_1_2_Selection)); + assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); + + if (DAC_1_2_Selection == DAC_CHANNEL_1) + { + /* enable DAC1 noise wave */ + COMP_OPAM_DAC -> DAC_CR |= WAVE1_0; + COMP_OPAM_DAC -> DAC_CR |= Amplitude; + } + else if (DAC_1_2_Selection == DAC_CHANNEL_2) + { + /* enable DAC2 noise wave */ + COMP_OPAM_DAC -> DAC_CR |= WAVE2_0; + COMP_OPAM_DAC -> DAC_CR |= Amplitude << (DAC_1_2_Selection & 0x10UL); + } + else if (DAC_1_2_Selection == DAC_CHANNEL_D12) + { + /* enable DAC1 2 noise wave */ + COMP_OPAM_DAC -> DAC_CR |= WAVE1_0 | WAVE2_0; + COMP_OPAM_DAC -> DAC_CR |= ((Amplitude << (DAC_CHANNEL_2 & 0x10UL)) | Amplitude); + } +} + +/** + * @} + */ +void Delay_read(void) +{ + int m; + for (m = 0; m < 15; m++) + { + __ASM("nop"); + } +} +/** + * @} + */ + +/** +* @} +*/ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_debug.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_debug.c new file mode 100644 index 00000000000..11ce7dc7fc4 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_debug.c @@ -0,0 +1,166 @@ +/** + ****************************************************************************** + * @file ft32f4xx_debug.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Debug MCU (DBGMCU) peripheral: + * + Device and Revision ID management + * + Peripherals Configuration + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_debug.h" + + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + + + +/** + * @brief Returns the device revision identifier. + * @param None + * @retval Device revision identifier + */ +uint32_t DBGMCU_GetREVID(void) +{ + return (DBGMCU->IDCODE >> 16); +} + +/** + * @brief Returns the device identifier. + * @param None + * @retval Device identifier + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return (DBGMCU->IDCODE & IDCODE_DEVID_MASK); +} +/** + * @} + */ + +/** + * @brief Configures low power mode behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @param NewState: new state of the specified low power mode in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->CR |= DBGMCU_Periph; + } + else + { + DBGMCU->CR &= ~DBGMCU_Periph; + } +} +/** + * @} + */ + +/** + * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB1 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted + * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted + * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted + * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted + * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted + * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted + * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted + * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted + * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted + * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped + * when Core is halted. + * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted + * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted + * @arg DBGMCU_I2C1_SMBUS_TIMEOUT_STOP: I2C1 SMBUS timeout mode stopped + * when Core is halted + * @arg DBGMCU_I2C2_SMBUS_TIMEOUT_STOP: I2C2 SMBUS timeout mode stopped + * when Core is halted + * @arg DBGMCU_I2C3_SMBUS_TIMEOUT_STOP: I2C3 SMBUS timeout mode stopped + * when Core is halted + * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted + * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted + * @arg DBGMCU_CAN3_STOP: Debug CAN3 stopped when Core is halted + * @arg DBGMCU_CAN4_STOP: Debug CAN4 stopped when Core is halted + * @param NewState: new state of the specified APB1 peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB1FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB1FZ &= ~DBGMCU_Periph; + } +} +/** + * @} + */ + +/** + * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. + * @param DBGMCU_Periph: specifies the APB2 peripheral. + * This parameter can be any combination of the following values: + * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted + * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted + * @arg DBGMCU_LPTIM_STOP: LPTIM counter stopped when Core is halted + * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted + * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted + * @arg DBGMCU_EPWM1_STOP: EPWM1 counter stopped when Core is halted + * @arg DBGMCU_EPWM2_STOP: EPWM2 counter stopped when Core is halted + * @arg DBGMCU_EPWM3_STOP: EPWM3 counter stopped when Core is halted + * @arg DBGMCU_EPWM4_STOP: EPWM4 counter stopped when Core is halted + * @param NewState: new state of the specified APB2 peripheral in Debug mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + DBGMCU->APB2FZ |= DBGMCU_Periph; + } + else + { + DBGMCU->APB2FZ &= ~DBGMCU_Periph; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_dma.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_dma.c new file mode 100644 index 00000000000..8e2904534c2 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_dma.c @@ -0,0 +1,732 @@ +/** + ****************************************************************************** + * @file ft32f4xx_dma.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Direct Memory Access controller (DMA): + * + Initialization and Configuration + * + Data Counter + * + Interrupts and flags management + * + Software Request + * @version V1.0.0 + * @data 2025-04-15 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_dma.h" +#include "ft32f4xx_rcc.h" +/** @defgroup DMA + * @brief DMA driver modules + * @{ + */ + + +/** + * @brief Initialize the DMA according to the specified + * parameters in the DMA_InitTypeDef and initialize the associated handle. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @retval None + */ +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* Init) +{ + uint32_t tmp_high = 0; + uint32_t tmp_low = 0; + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_DMA_SRC_DST_MASTER_SEL(Init->SrcDstMasterSel)); + assert_param(IS_DMA_TRANS_TYPE_FLOW_CTL(Init->TransferTypeFlowCtl)); + assert_param(IS_DMA_SRC_BURST_TRANS_LENGTH(Init->SrcBurstTransferLength)); + assert_param(IS_DMA_DST_BURST_TRANS_LENGTH(Init->DstBurstTransferLength)); + assert_param(IS_DMA_SRC_ADDR_MODE(Init->SrcAddrMode)); + assert_param(IS_DMA_DST_ADDR_MODE(Init->DstAddrMode)); + assert_param(IS_DMA_SRC_TRANS_WIDTH(Init->SrcTransferWidth)); + assert_param(IS_DMA_DST_TRANS_WIDTH(Init->DstTransferWidth)); + assert_param(IS_DMA_DST_HW_IF(Init->DstHardwareInterface)); + assert_param(IS_DMA_SRC_HW_IF(Init->SrcHardwareInterface)); + assert_param(IS_FUNCTIONAL_STATE(Init->FIFOMode)); + assert_param(IS_FUNCTIONAL_STATE(Init->FlowCtlMode)); + assert_param(IS_FUNCTIONAL_STATE(Init->ReloadDst)); + assert_param(IS_FUNCTIONAL_STATE(Init->ReloadSrc)); + assert_param(IS_DMA_SRC_HS_IF_POL(Init->SrcHsIfPol)); + assert_param(IS_DMA_DST_HS_IF_POL(Init->DstHsIfPol)); + assert_param(IS_DMA_SRC_HS_SEL(Init->SrcHsSel)); + assert_param(IS_DMA_DST_HS_SEL(Init->DstHsSel)); + assert_param(IS_DMA_CHANNEL_POLARITY(Init->Polarity)); + assert_param(IS_DMA_DST_HANDSHAKE_INTERFACE_SEL(Init->DstHsIfPeriphSel)); + assert_param(IS_DMA_SRC_HANDSHAKE_INTERFACE_SEL(Init->SrcHsIfPeriphSel)); + + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + /* Config DMA source address */ + DMAy_Channelx->SAR = (uint64_t)Init->SrcAddress; + + /* Config DMA destination address */ + DMAy_Channelx->DAR = (uint64_t)Init->DstAddress; + + + //tmp_high = (uint32_t)(DMAy_Channelx->CTL >> 32U); + //tmp_low = (uint32_t)(DMAy_Channelx->CTL); + + /* Prepare the DMA Channel configuration */ + tmp_high = (uint32_t)Init->BlockTransSize << 13U; + + tmp_low = ((uint32_t)Init->SrcDstMasterSel | Init->TransferTypeFlowCtl | + Init->SrcBurstTransferLength | Init->DstBurstTransferLength | + Init->SrcAddrMode | Init->DstAddrMode | + Init->SrcTransferWidth | Init->DstTransferWidth) ; + + /* Write to DMA Channel CTL register */ + DMAy_Channelx->CTL = (((uint64_t)tmp_high << 32UL) | (uint64_t)tmp_low); + + + //tmp_high = (uint32_t)(DMAy_Channelx->CFG >> 32U); + //tmp_low = (uint32_t)(DMAy_Channelx->CFG); + tmp_high = 0; + tmp_low = 0; + + /* Prepare the DMA Channel configuration */ + tmp_high |= ((uint32_t)(Init->DstHardwareInterface << 11U) | + (Init->SrcHardwareInterface << 7U)); + + if (Init->FIFOMode == ENABLE) + { + tmp_high |= (uint32_t)(DMA_CFG_FIFO_MODE >> 32U); + } + + if (Init->FlowCtlMode == ENABLE) + { + tmp_high |= (uint32_t)(DMA_CFG_FCMODE >> 32U); + } + + tmp_low |= ((uint32_t)(Init->MaxBurstLength << 20U) | + (Init->SrcHsIfPol << 19U) | + (Init->DstHsIfPol << 18U) | + (Init->SrcHsSel << 11U) | + (Init->DstHsSel << 10U) | + (Init->Polarity << 5U)); + + if (Init->ReloadDst == ENABLE) + { + tmp_low |= (uint32_t)DMA_CFG_RELOAD_DST; + } + + if (Init->ReloadSrc == ENABLE) + { + tmp_low |= (uint32_t)DMA_CFG_RELOAD_SRC; + } + + /* Write to DMA Channel CFG register */ + DMAy_Channelx->CFG = (((uint64_t)tmp_high << 32UL) | (uint64_t)tmp_low); + + + /* Select peripheral request for the handshake interface */ + DMA.BaseAddress->CHSEL |= (uint64_t)((Init->DstHsIfPeriphSel << (Init->DstHardwareInterface * 3UL)) | + (Init->SrcHsIfPeriphSel << (Init->SrcHardwareInterface * 3UL))); +} + + +/** + * @brief Fills each DMA_StructInit member with its default value. + * @param DMA_StructInit: pointer to a DMA_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct) +{ + /*-------------- Reset DMA init structure parameters values ------------------*/ + /* Initialize the DMA source address */ + DMA_InitStruct->SrcAddress = 0U; + + /* Initialize the DMA destination address */ + DMA_InitStruct->DstAddress = 0U; + + /* Initialize the DMA block transfer size */ + DMA_InitStruct->BlockTransSize = 0U; + + /* Initialize the DMA source/destination master select */ + DMA_InitStruct->SrcDstMasterSel = DMA_SRCMASTER1_DSTMASTER1; + + /* Initialize the DMA transfer type and flow control */ + DMA_InitStruct->TransferTypeFlowCtl = DMA_TRANSFERTYPE_FLOWCTL_M2M_DMA; + + /* Initialize the DMA source burst transaction length */ + DMA_InitStruct->SrcBurstTransferLength = DMA_SRC_BURSTTRANSFERLENGTH_1; + + /* Initialize the DMA destination burst transaction length */ + DMA_InitStruct->DstBurstTransferLength = DMA_DST_BURSTTRANSFERLENGTH_1; + + /* Initialize the DMA source address increment */ + DMA_InitStruct->SrcAddrMode = DMA_SRC_ADDRMODE_INC; + + /* Initialize the DMA destination address increment */ + DMA_InitStruct->DstAddrMode = DMA_DST_ADDRMODE_INC; + + /* Initialize the DMA srouce transfer width */ + DMA_InitStruct->SrcTransferWidth = DMA_SRC_TRANSFERWIDTH_8BITS; + + /* Initialize the DMA destination transfer width */ + DMA_InitStruct->DstTransferWidth = DMA_DST_TRANSFERWIDTH_8BITS; + + + /* Initialize the DMA destination hardware interface */ + DMA_InitStruct->DstHardwareInterface = DMA_DST_HARDWARE_INTERFACE_0; + + /* Initialize the DMA source hardware interface */ + DMA_InitStruct->SrcHardwareInterface = DMA_SRC_HARDWARE_INTERFACE_0; + + /* Initialize the DMA FIFO mode */ + DMA_InitStruct->FIFOMode = DISABLE; + + /* Initialize the DMA flow control mode */ + DMA_InitStruct->FlowCtlMode = DISABLE; + + /* Initialize the DMA automatic destination reload */ + DMA_InitStruct->ReloadDst = DISABLE; + + /* Initialize the DMA automatic source reload */ + DMA_InitStruct->ReloadSrc = DISABLE; + + /* Initialize the DMA maximum AMBA burst length */ + DMA_InitStruct->MaxBurstLength = 0U; + + /* Initialize the DMA source handshaking interface polarity */ + DMA_InitStruct->SrcHsIfPol = DMA_SRCHSIFPOL_HIGH; + + /* Initialize the DMA destination handshaking interface polarity */ + DMA_InitStruct->DstHsIfPol = DMA_DSTHSIFPOL_HIGH; + + /* Initialize the DMA source software or handware handshaking */ + DMA_InitStruct->SrcHsSel = DMA_SRCHSSEL_HARDWARE; + + /* Initialize the DMA destination software or handware handshaking */ + DMA_InitStruct->DstHsSel = DMA_DSTHSSEL_HARDWARE; + + /* Initialize the DMA channel polarity */ + DMA_InitStruct->Polarity = DMA_CH_POLARITY_0; + + /* Initialize the destination peripheral request */ + DMA_InitStruct->DstHsIfPeriphSel = DMA_DST_HANDSHAKE_INTERFACE_SEL_0; + + /* Initialize the source peripheral request */ + DMA_InitStruct->SrcHsIfPeriphSel = DMA_SRC_HANDSHAKE_INTERFACE_SEL_0; + +} + + +/** + * @brief DeInitialize the DMA peripheral. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @retval None + */ +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + + if (DMA.BaseAddress == DMA1) + { + /* Enable DMA1 reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1PeriphRst_DMA1, ENABLE); + + /* Release DMA1 from reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1PeriphRst_DMA1, DISABLE); + } + else if (DMA.BaseAddress == DMA2) + { + /* Enable DMA2 reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1PeriphRst_DMA2, ENABLE); + + /* Release DMA2 from reset state */ + RCC_AHB1PeriphResetCmd(RCC_AHB1PeriphRst_DMA2, DISABLE); + } + +} + + +/** + * @brief Return the DMA base address and channel index depending on DMAy_Channelx. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @retval DMA base address and channel index. + */ +DMA_BaseAddressAndChannelIndex CalBaseAddressAndChannelIndex(DMA_Channel_TypeDef* DMAy_Channelx) +{ + DMA_BaseAddressAndChannelIndex DMA; + + /* Compute the channel index */ + if ((uint32_t)(DMAy_Channelx) < (uint32_t)(DMA2_Channel0)) + { + /* DMA1 */ + DMA.ChannelIndex = (((uint32_t)DMAy_Channelx - (uint32_t)DMA1_Channel0) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)); + DMA.BaseAddress = DMA1; + } + else + { + /* DMA2 */ + DMA.ChannelIndex = (((uint32_t)DMAy_Channelx - (uint32_t)DMA2_Channel0) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)); + DMA.BaseAddress = DMA2; + } + + return DMA; +} + + +/** + * @brief Enables or disables the specified DMAy Channelx. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @param NewState New state of the DMAy Channelx. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + if (NewState != DISABLE) + { + /* Enable the Peripheral */ + DMA_ENABLE(DMA.BaseAddress); + /* Enable the DMA Channel */ + DMA_Channel_Cmd(DMAy_Channelx, ENABLE); + } + else + { + /* Disable the DMA Channel */ + DMA_Channel_Cmd(DMAy_Channelx, DISABLE); + /* Disable the Peripheral */ + DMA_DISABLE(DMA.BaseAddress); + } + +} + + +/** + * @brief Returns the number of data units transferred by the current DMAy Channelx. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @retval The number of data units transferred by the current DMAy Channelx. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + + /* Return the number of remaining data units for DMAy Channelx */ + return ((uint16_t)((DMAy_Channelx->CTL) >> 45U)); +} + + +/** + * @brief Enable the specified DMA Channel interrupts. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @param DMA_IT specifies the DMA interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg DMA_IT_TFR Transfer complete interrupt mask + * @arg DMA_IT_BLOCK Block transfer complete interrupt mask + * @arg DMA_IT_SRC Source transfer complete interrupt mask + * @arg DMA_IT_DST Destination transfer complete interrupt mask + * @arg DMA_IT_ERR Transfer error interrupt mask + * @retval None + */ +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_DMA_IT(DMA_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + /* Config channel interrupt mask */ + const uint32_t ch_mask = (1U << (DMA.ChannelIndex)); + const uint32_t ch_en_mask = (0x100U << (DMA.ChannelIndex)); + + /* Config channelx transfer complete interrupt */ + if ((DMA_IT & DMA_IT_TFR) != 0U) + { + (NewState) ? (DMA.BaseAddress->MASKTFR |= (ch_en_mask | ch_mask)) + : (DMA.BaseAddress->MASKTFR &= (ch_en_mask | (~ch_mask))); + } + + /* Config channelx block transfer complete interrupt */ + if ((DMA_IT & DMA_IT_BLOCK) != 0U) + { + (NewState) ? (DMA.BaseAddress->MASKBLOCK |= (ch_en_mask | ch_mask)) + : (DMA.BaseAddress->MASKBLOCK &= (ch_en_mask | (~ch_mask))); + } + + /* Config channelx source transfer complete interrupt */ + if ((DMA_IT & DMA_IT_SRC) != 0U) + { + (NewState) ? (DMA.BaseAddress->MASKSRCTRAN |= (ch_en_mask | ch_mask)) + : (DMA.BaseAddress->MASKSRCTRAN &= (ch_en_mask | (~ch_mask))); + } + + /* Config channelx destination transfer complete interrupt */ + if ((DMA_IT & DMA_IT_DST) != 0U) + { + (NewState) ? (DMA.BaseAddress->MASKDSTTRAN |= (ch_en_mask | ch_mask)) + : (DMA.BaseAddress->MASKDSTTRAN &= (ch_en_mask | (~ch_mask))); + } + + /* Config channelx transfer error interrupt */ + if ((DMA_IT & DMA_IT_ERR) != 0U) + { + (NewState) ? (DMA.BaseAddress->MASKERR |= (ch_en_mask | ch_mask)) + : (DMA.BaseAddress->MASKERR &= (ch_en_mask | (~ch_mask))); + } + + /* Config global interrupt */ + const uint8_t int_en_bit = 0x01; //CTL[0] + if (NewState == ENABLE) + { + /* Enable global interrupt */ + DMAy_Channelx->CTL |= (uint64_t)int_en_bit; + } + else + { + // Check all interrupts are disabled. + if (!(DMA.BaseAddress->MASKTFR & ch_mask) && + !(DMA.BaseAddress->MASKBLOCK & ch_mask) && + !(DMA.BaseAddress->MASKSRCTRAN & ch_mask) && + !(DMA.BaseAddress->MASKDSTTRAN & ch_mask) && + !(DMA.BaseAddress->MASKERR & ch_mask)) + { + /* Disable global interrupt */ + DMAy_Channelx->CTL &= ~(uint64_t)int_en_bit; + } + } +} + + +/** + * @brief Clears the DMA interrupt flags. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @param DMA_IT specifies DMA interrupt flag to clear. + * This parameter can be one of the following values: + * @arg DMA_IT_TFR Transfer complete flag. + * @arg DMA_IT_BLOCK Block transfer complete flag. + * @arg DMA_IT_SRC Source transfer complete flag. + * @arg DMA_IT_DST Destination transfer complete flag. + * @arg DMA_IT_ERR Transfer error flag. + * @retval None + */ +void DMA_ClearFlagStatus(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_DMA_IT(DMA_IT)); + + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + /* Config channel mask */ + const uint32_t ch_mask = (1U << (DMA.ChannelIndex)); + + /* Clear channelx transfer complete interrupt */ + if ((DMA_IT & DMA_IT_TFR) != 0U) + { + DMA.BaseAddress->CLEARTFR = ch_mask; + } + /* Clear channelx block transfer complete interrupt */ + if ((DMA_IT & DMA_IT_BLOCK) != 0U) + { + DMA.BaseAddress->CLEARBLOCK = ch_mask; + } + /* Clear channelx source transfer complete interrupt */ + if ((DMA_IT & DMA_IT_SRC) != 0U) + { + DMA.BaseAddress->CLEARSRCTRAN = ch_mask; + } + /* Clear channelx destination transfer complete interrupt */ + if ((DMA_IT & DMA_IT_DST) != 0U) + { + DMA.BaseAddress->CLEARDSTTRAN = ch_mask; + } + /* Clear channelx transfer error interrupt */ + if ((DMA_IT & DMA_IT_ERR) != 0U) + { + DMA.BaseAddress->CLEARERR = ch_mask; + } +} + + +/** + * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @param DMA_IT specifies the DMA interrupt source to check + * This parameter can be one of the following values: + * @arg DMA_IT_TFR Transfer complete interrupt. + * @arg DMA_IT_BLOCK Block transfer complete interrupt. + * @arg DMA_IT_SRC Source transfer complete interrupt. + * @arg DMA_IT_DST Destination transfer complete interrupt. + * @arg DMA_IT_ERR Transfer error interrupt. + * @retval The new state of DMA_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_IT) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_DMA_IT(DMA_IT)); + + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + /* Config channel mask */ + const uint32_t ch_mask = (1U << (DMA.ChannelIndex)); + + /* Get DMA IT Status register value */ + /* Get channelx transfer complete interrupt status */ + if ((DMA_IT & DMA_IT_TFR) != 0U) + { + tmpreg = DMA.BaseAddress->STATUSTFR; + } + + /* Get channelx block transfer complete interrupt status */ + if ((DMA_IT & DMA_IT_BLOCK) != 0U) + { + tmpreg = DMA.BaseAddress->STATUSBLOCK; + } + + /* Get channelx source transfer complete interrupt status */ + if ((DMA_IT & DMA_IT_SRC) != 0U) + { + tmpreg = DMA.BaseAddress->STATUSSRCTRAN; + } + + /* Get channelx destination transfer complete interrupt status */ + if ((DMA_IT & DMA_IT_DST) != 0U) + { + tmpreg = DMA.BaseAddress->STATUSDSTTRAN; + } + + /* Get channelx transfer error interrupt status */ + if ((DMA_IT & DMA_IT_ERR) != 0U) + { + tmpreg = DMA.BaseAddress->STATUSERR; + } + + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & ch_mask) != (uint32_t)RESET) + { + /* DMA_IT is set */ + bitstatus = SET; + } + else + { + /* DMA_IT is reset */ + bitstatus = RESET; + } + /* Return the DMA_IT status */ + return bitstatus; +} + + +/** + * @brief Checks whether the specified DMAy Channelx flag has occurred or not. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @param DMA_FLAG specifies the DMA flag to check + * This parameter can be one of the following values: + * @arg DMA_IT_TFR Transfer complete flag. + * @arg DMA_IT_BLOCK Block transfer complete flag. + * @arg DMA_IT_SRC Source transfer complete flag. + * @arg DMA_IT_DST Destination transfer complete flag. + * @arg DMA_IT_ERR Transfer error flag. + * @retval The new state of DMA_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(DMA_Channel_TypeDef* DMAy_Channelx, uint8_t DMA_FLAG) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_DMA_FLAG(DMA_FLAG)); + + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + /* Config channel mask */ + const uint32_t ch_mask = (1U << (DMA.ChannelIndex)); + + /* Get DMA IT Status register value */ + /* Get channelx transfer complete interrupt status */ + if ((DMA_FLAG & DMA_FLAG_TFR) != 0U) + { + tmpreg = DMA.BaseAddress->RAWTFR; + } + + /* Get channelx block transfer complete interrupt status */ + if ((DMA_FLAG & DMA_FLAG_BLOCK) != 0U) + { + tmpreg = DMA.BaseAddress->RAWBLOCK; + } + + /* Get channelx source transfer complete interrupt status */ + if ((DMA_FLAG & DMA_FLAG_SRC) != 0U) + { + tmpreg = DMA.BaseAddress->RAWSRCTRAN; + } + + /* Get channelx destination transfer complete interrupt status */ + if ((DMA_FLAG & DMA_FLAG_DST) != 0U) + { + tmpreg = DMA.BaseAddress->RAWDSTTRAN; + } + + /* Get channelx transfer error interrupt status */ + if ((DMA_FLAG & DMA_FLAG_ERR) != 0U) + { + tmpreg = DMA.BaseAddress->RAWERR; + } + + /* Check the status of the specified DMAy interrupt */ + if ((tmpreg & ch_mask) != (uint32_t)RESET) + { + /* DMA_FLAG is set */ + bitstatus = SET; + } + else + { + /* DMA_FLAG is reset */ + bitstatus = RESET; + } + /* Return the DMA_FLAG status */ + return bitstatus; +} + + +/** + * @brief Enable or disable the specified DMA Channel. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @param NewState new state of the specified DMA Channel. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void DMA_Channel_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + /* Config channel mask */ + const uint32_t ch_mask = (1U << (DMA.ChannelIndex)); + const uint32_t ch_en_mask = (0x100U << (DMA.ChannelIndex)); + + if (NewState != DISABLE) + { + DMA.BaseAddress->CHEN |= (ch_en_mask | ch_mask); + DMA.BaseAddress->CHEN &= ~ch_en_mask; + } + else + { + DMA.BaseAddress->CHEN |= ch_en_mask; + DMA.BaseAddress->CHEN &= ~ch_mask; + DMA.BaseAddress->CHEN &= ~ch_en_mask; + } +} + + +/** + * @brief Sets software request. + * @param DMAy_Channelx Where y can be 1 or 2 to select the DMA and x can be 0 to 7 + * for DMAy to select the DMA Channel. + * @param SoftwareRequest The specified software request. + * This parameter can be one of the following values: + * DMA_SW_REQUEST_SRC DMA source software transaction request + * DMA_SW_REQUEST_DST DMA destination software transaction request + * DMA_SW_REQUEST_SRC_SGL DMA source single transaction request + * DMA_SW_REQUEST_DST_SGL DMA destination single transaction request + * DMA_SW_REQUEST_SRC_LST DMA source last transaction request + * DMA_SW_REQUEST_DST_LST DMA destination last transaction request + * @retval None + */ +void DMA_SoftWare_Request(DMA_Channel_TypeDef* DMAy_Channelx, DMA_SoftwareRequestTypeDef SoftwareRequest) +{ + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(DMAy_Channelx)); + assert_param(IS_DMA_SOFTWARE_REQUEST(SoftwareRequest)); + + + /* Calculate the base address and channel index of the DMA */ + DMA_BaseAddressAndChannelIndex DMA = CalBaseAddressAndChannelIndex(DMAy_Channelx); + + /* Config channel mask */ + const uint32_t ch_mask = (1U << (DMA.ChannelIndex)); + const uint32_t ch_en_mask = (0x100U << (DMA.ChannelIndex)); + + /* Config the source software transaction request */ + if (SoftwareRequest == DMA_SW_REQUEST_SRC) + { + DMA.BaseAddress->REQSRC |= (ch_en_mask | ch_mask); + } + + /* Config the destination software transaction request */ + if (SoftwareRequest == DMA_SW_REQUEST_DST) + { + DMA.BaseAddress->REQDST |= (ch_en_mask | ch_mask); + } + + /* Config the source single transaction request */ + if (SoftwareRequest == DMA_SW_REQUEST_SRC_SGL) + { + DMA.BaseAddress->SGLRQSRC |= (ch_en_mask | ch_mask); + } + + /* Config the destination single transaction request */ + if (SoftwareRequest == DMA_SW_REQUEST_DST_SGL) + { + DMA.BaseAddress->SGLRQDST |= (ch_en_mask | ch_mask); + } + + /* Config the source last transaction request */ + if (SoftwareRequest == DMA_SW_REQUEST_SRC_LST) + { + DMA.BaseAddress->LSTSRC |= (ch_en_mask | ch_mask); + } + + /* Config the destination last transaction request */ + if (SoftwareRequest == DMA_SW_REQUEST_DST_LST) + { + DMA.BaseAddress->LSTDST |= (ch_en_mask | ch_mask); + } +} + + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_ecap.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_ecap.c new file mode 100644 index 00000000000..84474a81b30 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_ecap.c @@ -0,0 +1,549 @@ +/** + ****************************************************************************** + * @file ft32f4xx_ecap.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Enhanced Capture (ECAP): + * + Initialization and Configuration + * + ECAP control + * + Data register access + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-04-22 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_ecap.h" +#include "ft32f4xx_rcc.h" + + +/** @defgroup ECAP + * @brief ECAP driver modules + * @{ + */ + + +/** + * @brief Initialize the ECAP according to the specified parameters in the + * ECAP_InitTypeDef and initialize the associated handle. + * @param ECAP_InitStruct pointer to a ECAP_InitTypeDef structure that contains the + * configuration information for the specified ECAP peripheral. + * @retval None + */ +void ECAP_Init(ECAP_InitTypeDef* ECAP_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_ECAP_MODE(ECAP_InitStruct->ECAPMode)); + assert_param(IS_ECAP_EVENT_PRESCALER(ECAP_InitStruct->EventPrescaler)); + assert_param(IS_FUNCTIONAL_STATE(ECAP_InitStruct->CaptureLoad)); + assert_param(IS_FUNCTIONAL_STATE(ECAP_InitStruct->CaptureEvent4Reset)); + assert_param(IS_FUNCTIONAL_STATE(ECAP_InitStruct->CaptureEvent3Reset)); + assert_param(IS_FUNCTIONAL_STATE(ECAP_InitStruct->CaptureEvent2Reset)); + assert_param(IS_FUNCTIONAL_STATE(ECAP_InitStruct->CaptureEvent1Reset)); + assert_param(IS_ECAP_EVENT_POLARITY(ECAP_InitStruct->CaptureEvent4Polarity)); + assert_param(IS_ECAP_EVENT_POLARITY(ECAP_InitStruct->CaptureEvent3Polarity)); + assert_param(IS_ECAP_EVENT_POLARITY(ECAP_InitStruct->CaptureEvent2Polarity)); + assert_param(IS_ECAP_EVENT_POLARITY(ECAP_InitStruct->CaptureEvent1Polarity)); + assert_param(IS_ECAP_APWM_POLARITY(ECAP_InitStruct->APWMPolarity)); + assert_param(IS_FUNCTIONAL_STATE(ECAP_InitStruct->CounterSyncIn)); + assert_param(IS_ECAP_MOD_COUNTER_STOP_WRAP(ECAP_InitStruct->ModCounterStopWrap)); + assert_param(IS_ECAP_MOD_COUNTER_MODE(ECAP_InitStruct->ModCounterMode)); + assert_param(IS_ECAP_COUNTER_VALUE(ECAP_InitStruct->CounterValue)); + assert_param(IS_ECAP_COUNTER_PHASE_VALUE(ECAP_InitStruct->CounterPhaseValue)); + assert_param(IS_ECAP_CAPTURE1_REGISTER_VALUE(ECAP_InitStruct->Capture1RegisterValue)); + assert_param(IS_ECAP_CAPTURE2_REGISTER_VALUE(ECAP_InitStruct->Capture2RegisterValue)); + + /* Config ECAP capture control1 */ + tmpreg = ((uint32_t)(ECAP_InitStruct->EventPrescaler << 9U) | + (ECAP_InitStruct->CaptureEvent4Polarity << 6U) | + (ECAP_InitStruct->CaptureEvent3Polarity << 4U) | + (ECAP_InitStruct->CaptureEvent2Polarity << 2U) | + (ECAP_InitStruct->CaptureEvent1Polarity << 0U)); + + if (ECAP_InitStruct->CaptureLoad == ENABLE) + { + tmpreg |= (uint32_t)ECAP_ECCTL1_CAPLDEN; + } + + if (ECAP_InitStruct->CaptureEvent4Reset == ENABLE) + { + tmpreg |= (uint32_t)ECAP_ECCTL1_CTRRST4; + } + + if (ECAP_InitStruct->CaptureEvent3Reset == ENABLE) + { + tmpreg |= (uint32_t)ECAP_ECCTL1_CTRRST3; + } + + if (ECAP_InitStruct->CaptureEvent2Reset == ENABLE) + { + tmpreg |= (uint32_t)ECAP_ECCTL1_CTRRST2; + } + + if (ECAP_InitStruct->CaptureEvent1Reset == ENABLE) + { + tmpreg |= (uint32_t)ECAP_ECCTL1_CTRRST1; + } + + /* Write to ECAP ECCTL1 */ + ECAP->ECCTL1 = tmpreg; + + + tmpreg = 0; + + /* Config ECAP capture control2 */ + tmpreg = ((uint32_t)(ECAP_InitStruct->ECAPMode) | + (ECAP_InitStruct->ModCounterStopWrap) | + (ECAP_InitStruct->ModCounterMode)); + + //tmpreg &= (uint32_t)~ECAP_ECCTL2_STOP_WRAP; + //tmpreg |= (uint32_t)(ECAP_InitStruct->ModCounterStopWrap); + + if (ECAP_InitStruct->CounterSyncIn == ENABLE) + { + tmpreg |= (uint32_t)ECAP_ECCTL2_SYNCI_EN; + } + + /* Config ECAP APWM mode */ + if (ECAP_InitStruct->ECAPMode == ECAP_MODE_APWM) + { + /* Config APWM output polarity */ + tmpreg |= ((uint32_t)(ECAP_InitStruct->APWMPolarity)); + + /* Config ECAP counter value */ + ECAP->TSCTR = ECAP_InitStruct->CounterValue; + + /* Config ECAP counter phase value */ + ECAP->CTRPHS = ECAP_InitStruct->CounterPhaseValue; + + /* Config ECAP capture 1 register value */ + ECAP->CAP1 = ECAP_InitStruct->Capture1RegisterValue; + + /* Config ECAP capture 2 register value */ + ECAP->CAP2 = ECAP_InitStruct->Capture2RegisterValue; + } + + /* Write to ECAP ECCTL2 */ + ECAP->ECCTL2 = tmpreg; + +} + + +/** + * @brief Fills each ECAP_StructInit member with its default value. + * @param ECAP_StructInit pointer to a ECAP_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void ECAP_StructInit(ECAP_InitTypeDef* ECAP_InitStruct) +{ + /*-------------- Reset ECAP init structure parameters values ------------------*/ + /* Initialize the ECAP mode */ + ECAP_InitStruct->ECAPMode = 0U; + + /* Initialize the prescaler of event filter */ + ECAP_InitStruct->EventPrescaler = 0U; + + /* Initialize the enable loading of CAP1-4 registers on a capture event */ + ECAP_InitStruct->CaptureLoad = DISABLE; + + /* Initialize the counter reset on capture event 4 */ + ECAP_InitStruct->CaptureEvent4Reset = DISABLE; + + /* Initialize the counter reset on capture event 3 */ + ECAP_InitStruct->CaptureEvent3Reset = DISABLE; + + /* Initialize the counter reset on capture event 2 */ + ECAP_InitStruct->CaptureEvent2Reset = DISABLE; + + /* Initialize the counter reset on capture event 1 */ + ECAP_InitStruct->CaptureEvent1Reset = DISABLE; + + /* Initialize the polarity of capture event 4 */ + ECAP_InitStruct->CaptureEvent4Polarity = ECAP_EVENT_POLARITY_RE; + + /* Initialize the polarity of capture event 3 */ + ECAP_InitStruct->CaptureEvent3Polarity = ECAP_EVENT_POLARITY_RE; + + /* Initialize the polarity of capture event 2 */ + ECAP_InitStruct->CaptureEvent2Polarity = ECAP_EVENT_POLARITY_RE; + + /* Initialize the polarity of capture event 1 */ + ECAP_InitStruct->CaptureEvent1Polarity = ECAP_EVENT_POLARITY_RE; + + /* Initialize the polarity of the APWM output */ + ECAP_InitStruct->APWMPolarity = 0U; + + /* Initialize the counter Sync-In */ + ECAP_InitStruct->CounterSyncIn = DISABLE; + + /* Initialize the stop/wrap value of Mod counter */ + ECAP_InitStruct->ModCounterStopWrap = ECAP_STOP_WRAP_EVENT1; + + /* Initialize the mode of Mod counter to continuous mode */ + ECAP_InitStruct->ModCounterMode = ECAP_MOD_COUNTER_CONT; + + /* Initialize the phase value of counter */ + ECAP_InitStruct->CounterPhaseValue = 0U; +} + + +/** + * @brief DeInitialize the ECAP peripheral. + * @retval None + */ +void ECAP_DeInit() +{ + + /* Enable ECAP reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2PeriphRst_ECAP, ENABLE); + + /* Release ECAP from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2PeriphRst_ECAP, DISABLE); + +} + + +/** + * @brief Enables or disables the ECAP counter(TSCTR). + * @param NewState New state of the ECAP counter. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ECAP_Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the ECAP, TSCTR free-running */ + ECAP->ECCTL2 |= (uint32_t)ECAP_ECCTL2_TSCTRSTOP; + } + else + { + /* Disable the ECAP, TSCRT stopped */ + ECAP->ECCTL2 &= (uint32_t)(~ECAP_ECCTL2_TSCTRSTOP); + } +} + + +/** + * @brief Re-Ariming control. + * @Note The re-arm function is valid in one-shot or continuous mode. + * Write 0 : Has no effect; + * Write 1 : Arms the one-shot sequence as follows: + * +Resets the Mod4 counter to zero + * +Unfreezes the Mod4 counter + * +Enables capture register loads + * @retval None + */ +void ECAP_ReArm() +{ + uint32_t tmpreg = 0; + + /* Get the ECCTL2 value */ + tmpreg = ECAP->ECCTL2; + + /* Config the REARM bit of ECCTL2 */ + tmpreg |= (uint32_t)ECAP_ECCTL2_REARM; + + /* Write to ECCTL2 */ + ECAP->ECCTL2 = tmpreg; +} + + +/** + * @brief Software-forced counter(TSCTR) synchronizer. + * This provides the user a method to generate a synchronization pulse + * through software. + * Write 0 : Has no effect; + * Write 1 : Forces a TSCTR shadow load of current ECAP module. + * @retval None + */ +void ECAP_SoftwareForceSync() +{ + uint32_t tmpreg = 0; + + /* Get the ECCTL2 value */ + tmpreg = ECAP->ECCTL2; + + /* Force a TSCTR shadow load */ + tmpreg |= (uint32_t)ECAP_ECCTL2_SWSYNC; + + /* Write to ECCTL2 */ + ECAP->ECCTL2 = tmpreg; +} + + +/** + * @brief Write a value to the specified data register. + * @param ECAP_DATA_REG ECAP data registers. + * @arg ECAP_DATA_REG_TSCTR Counter register + * @arg ECAP_DATA_REG_CTRPHS Counter phase offset register + * @arg ECAP_DATA_REG_CAP1 Capture 1 register + * @arg ECAP_DATA_REG_CAP2 Capture 2 register + * @arg ECAP_DATA_REG_CAP3 Capture 3 register + * @arg ECAP_DATA_REG_CAP4 Capture 4 register + * @param Value The value of data register. + * @retval None + */ +void ECAP_WriteDataRegister(uint8_t ECAP_DATA_REG, uint32_t Value) +{ + /* Check the parameters */ + assert_param(IS_ECAP_DATA_REG(ECAP_DATA_REG)); + + if (ECAP_DATA_REG == ECAP_DATA_REG_TSCTR) + { + /* Write the value to TSCTR */ + ECAP->TSCTR = ((uint32_t)Value); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CTRPHS) + { + /* Write the value to CTRPHS */ + ECAP->CTRPHS = ((uint32_t)Value); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP1) + { + /* Write the value to CAP1 */ + ECAP->CAP1 = ((uint32_t)Value); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP2) + { + /* Write the value to CAP2 */ + ECAP->CAP2 = ((uint32_t)Value); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP3) + { + /* Write the value to CAP3 */ + ECAP->CAP3 = ((uint32_t)Value); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP4) + { + /* Write the value to CAP4 */ + ECAP->CAP4 = ((uint32_t)Value); + } +} + + +/** + * @brief Returns the value of data registers. + * @param ECAP_DATA_REG ECAP data registers. + * @arg ECAP_DATA_REG_TSCTR Counter register + * @arg ECAP_DATA_REG_CTRPHS Counter phase offset register + * @arg ECAP_DATA_REG_CAP1 Capture 1 register + * @arg ECAP_DATA_REG_CAP2 Capture 2 register + * @arg ECAP_DATA_REG_CAP3 Capture 3 register + * @arg ECAP_DATA_REG_CAP4 Capture 4 register + * @retval The value of data registers. + */ +uint32_t ECAP_GetDataRegister(uint8_t ECAP_DATA_REG) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_ECAP_DATA_REG(ECAP_DATA_REG)); + + if (ECAP_DATA_REG == ECAP_DATA_REG_TSCTR) + { + /* Get the value of TSCTR */ + tmpreg = ((uint32_t)(ECAP->TSCTR)); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CTRPHS) + { + /* Get the value of CTRPHS */ + tmpreg = ((uint32_t)(ECAP->CTRPHS)); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP1) + { + /* Get the value of CAP1 */ + tmpreg = ((uint32_t)(ECAP->CAP1)); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP2) + { + /* Get the value of CAP2 */ + tmpreg = ((uint32_t)(ECAP->CAP2)); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP3) + { + /* Get the value of CAP3 */ + tmpreg = ((uint32_t)(ECAP->CAP3)); + } + if (ECAP_DATA_REG == ECAP_DATA_REG_CAP4) + { + /* Get the value of CAP4 */ + tmpreg = ((uint32_t)(ECAP->CAP4)); + } + + /* Return the value of data register */ + return tmpreg; +} + + +/** + * @brief Enable the specified ECAP interrupts. + * @param ECAP_IT specifies the ECAP interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ECAP_IT_CEVT1 Capture event 1 interrupt + * @arg ECAP_IT_CEVT2 Capture event 2 interrupt + * @arg ECAP_IT_CEVT3 Capture event 3 interrupt + * @arg ECAP_IT_CEVT4 Capture event 4 interrupt + * @arg ECAP_IT_CTROVF Counter overflow interrupt + * @arg ECAP_IT_CTRPRD Counter equal period interrupt + * @arg ECAP_IT_CTRCMP Counter equal compare interrupt + * @param NewState new state of the specified ECAP interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void ECAP_ITConfig(uint8_t ECAP_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_ECAP_IT(ECAP_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + if (NewState != DISABLE) + { + /* Enable the selected ECAP interrupts */ + ECAP->ECEINT |= ECAP_IT; + } + else + { + /* Disable the selected ECAP interrupts */ + ECAP->ECEINT &= ~ECAP_IT; + } +} + + +/** + * @brief Clears the ECAP interrupt flags. + * @param ECAP_FLAG specifies the ECAP interrupt flag to clear. + * This parameter can be one of the following values: + * @arg ECAP_FLAG_INT ECAP global interrupt flag + * @arg ECAP_FLAG_CEVT1 Capture event 1 interrupt flag + * @arg ECAP_FLAG_CEVT2 Capture event 2 interrupt flag + * @arg ECAP_FLAG_CEVT3 Capture event 3 interrupt flag + * @arg ECAP_FLAG_CEVT4 Capture event 3 interrupt flag + * @arg ECAP_FLAG_CTROVF Counter overflow interrupt flag + * @arg ECAP_FLAG_CTRPRD Counter equal period interrupt flag + * @arg ECAP_FLAG_CTRCMP Counter equal compare interrupt flag + * @retval None + */ +void ECAP_ClearFlag(uint8_t ECAP_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ECAP_FLAG(ECAP_FLAG)); + + /* Clear the selected ECAP flags */ + ECAP->ECCLR = ECAP_FLAG; +} + + +/** + * @brief Force the specified ECAP interrupt. + * @param ECAP_IT specifies the ECAP interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg ECAP_IT_CEVT1 Capture event 1 interrupt + * @arg ECAP_IT_CEVT2 Capture event 2 interrupt + * @arg ECAP_IT_CEVT3 Capture event 3 interrupt + * @arg ECAP_IT_CEVT4 Capture event 4 interrupt + * @arg ECAP_IT_CTROVF Counter overflow interrupt + * @arg ECAP_IT_CTRPRD Counter equal period interrupt + * @arg ECAP_IT_CTRCMP Counter equal compare interrupt + * @retval None + */ +void ECAP_ITForce(uint8_t ECAP_IT) +{ + /* Check the parameters */ + assert_param(IS_ECAP_IT(ECAP_IT)); + + /* Force the selected ECAP interrupt */ + ECAP->ECFRC = ECAP_IT; +} + +/** + * @brief Checks whether the specified ECAP interrupt has occurred or not. + * @param ECAP_IT specifies the ECAP interrupt sources to check. + * This parameter can be any combination of the following values: + * @arg ECAP_IT_CEVT1 Capture event 1 interrupt + * @arg ECAP_IT_CEVT2 Capture event 2 interrupt + * @arg ECAP_IT_CEVT3 Capture event 3 interrupt + * @arg ECAP_IT_CEVT4 Capture event 4 interrupt + * @arg ECAP_IT_CTROVF Counter overflow interrupt + * @arg ECAP_IT_CTRPRD Counter equal period interrupt + * @arg ECAP_IT_CTRCMP Counter equal compare interrupt + * @retval The new state of ECAP_IT (SET or RESET). + */ +ITStatus ECAP_GetITStatus(uint8_t ECAP_IT) +{ + /* Check the parameters */ + assert_param(IS_ECAP_IT(ECAP_IT)); + + + ITStatus bitstatus = RESET; + + /* Check the status of the specified ECAP interrupt */ + if ((uint32_t)(ECAP->ECEINT & ECAP_IT) != (uint32_t)RESET) + { + /* ECAP_IT is set */ + bitstatus = SET; + } + else + { + /* ECAP_IT is reset */ + bitstatus = RESET; + } + /* Return the ECAP_IT status */ + return bitstatus; +} + + + +/** + * @brief Checks whether the specified ECAP flag has occurred or not. + * @param ECAP_FLAG specifies the ECAP flag to check. + * This parameter can be any combination of the following values: + * @arg ECAP_FLAG_INT ECAP global interrupt flag + * @arg ECAP_FLAG_CEVT1 Capture event 1 interrupt flag + * @arg ECAP_FLAG_CEVT2 Capture event 2 interrupt flag + * @arg ECAP_FLAG_CEVT3 Capture event 3 interrupt flag + * @arg ECAP_FLAG_CEVT4 Capture event 4 interrupt flag + * @arg ECAP_FLAG_CTROVF Counter overflow interrupt flag + * @arg ECAP_FLAG_CTRPRD Counter equal period interrupt flag + * @arg ECAP_FLAG_CTRCMP Counter equal compare interrupt flag + * @retval The new state of ECAP_FLAG (SET or RESET). + */ +FlagStatus ECAP_GetFlagStatus(uint8_t ECAP_FLAG) +{ + /* Check the parameters */ + assert_param(IS_ECAP_FLAG(ECAP_FLAG)); + + + FlagStatus bitstatus = RESET; + + /* Check the status of the specified ECAP interrupt */ + if ((uint32_t)(ECAP->ECFLG & ECAP_FLAG) != (uint32_t)RESET) + { + /* ECAP_FLAG is set */ + bitstatus = SET; + } + else + { + /* ECAP_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ECAP_FLAG status */ + return bitstatus; +} + + + + + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_epwm.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_epwm.c new file mode 100644 index 00000000000..5f840579e71 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_epwm.c @@ -0,0 +1,2027 @@ +/** + ****************************************************************************** + * @file ft32f4xx_epwm.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Enhanced Pulse Width Modulator (EPWM): + * + Initialization and Configuration + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-26 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_epwm.h" +#include "ft32f4xx_rcc.h" + +/** @defgroup EPWM + * @brief EPWM driver modules + * @{ + */ + + + +/** + * @brief When the EALLOW bit is set to 1, write protection function will be disable and + * write operations can be performed on the related registers. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral. + * @retval None + */ +void EALLOW(EPWM_TypeDef* EPWMx) +{ + EPWMx->TBCTL |= EPWM_TBCTL_EALLOW_BITS; +} + +/** + * @brief When the EALLOW bit is set to 0, write protection function will be enabled and + * write operations on the related registers will not be allowed. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral. + * @retval None + */ +void EDIS(EPWM_TypeDef* EPWMx) +{ + EPWMx->TBCTL &= ~EPWM_TBCTL_EALLOW_BITS; +} + + +/** + * @brief Checks whether the specified EPWM TripZone flag is set or not. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral. + * @param TZ_FLAG: specifies the TripZone flag to check. + * This parameter can be one of the following values: + * @arg EPWM_TZ_FLAG_INT : Transmit buffer empty flag. + * @arg EPWM_TZ_FLAG_CBC : Receive buffer not empty flag. + * @arg EPWM_TZ_FLAG_OST : Busy flag. + * @arg EPWM_TZ_FLAG_DCAEVT1 : Overrun flag. + * @arg EPWM_TZ_FLAG_DCAEVT2 : Mode Fault flag. + * @arg EPWM_TZ_FLAG_DCBEVT1 : CRC Error flag. + * @arg EPWM_TZ_FLAG_DCBEVT2 : TI frame format error flag. + * @retval The new state of TZ_FLAG (SET or RESET). + */ +FlagStatus EPWM_TripZone_GetFlagStatus(EPWM_TypeDef* EPWMx, uint16_t TZ_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_EPWM_TZ_GET_FLAG(TZ_FLAG)); + + /* Check the status of the specified EPWM flag */ + if ((EPWMx->TZFLG & TZ_FLAG) != (uint16_t)RESET) + { + /* TZ_FLAG is set */ + bitstatus = SET; + } + else + { + /* TZ_FLAG is reset */ + bitstatus = RESET; + } + /* Return the TZ_FLAG status */ + return bitstatus; +} + +/** + * @brief Checks whether the specified EPWM Event Trigger flag is set or not. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral. + * @param ET_FLAG: specifies the Event Trigger flag to check. + * This parameter can be one of the following values: + * @arg EPWM_ET_FLAG_INT : Transmit buffer empty flag. + * @arg EPWM_ET_FLAG_SOCA : Receive buffer not empty flag. + * @arg EPWM_ET_FLAG_SOCB : Busy flag. + * @retval The new state of ET_FLAG (SET or RESET). + */ +FlagStatus EPWM_EventTrigger_GetFlagStatus(EPWM_TypeDef* EPWMx, uint16_t ET_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_EPWM_ET_GET_FLAG(ET_FLAG)); + + /* Check the status of the specified EPWM flag */ + if ((EPWMx->ETFLG & ET_FLAG) != (uint16_t)RESET) + { + /* ET_FLAG is set */ + bitstatus = SET; + } + else + { + /* ET_FLAG is reset */ + bitstatus = RESET; + } + /* Return the ET_FLAG status */ + return bitstatus; +} + +/** + * @brief Checks whether the specified EPWM Mep Calibration flag is set or not. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral. + * @param MEP_FLAG: specifies the Mep Calibration flag to check. + * This parameter can be one of the following values: + * @arg EPWM_MEP_FLAG_INT : Mep Calibration done flag. + * @retval The new state of MEP_FLAG (SET or RESET). + */ +FlagStatus EPWM_MepCalibration_GetFlagStatus(EPWM_TypeDef* EPWMx, uint16_t MEP_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_EPWM_MEP_GET_FLAG(MEP_FLAG)); + + /* Check the status of the specified EPWM flag */ + if ((EPWMx->MEPFLG & MEP_FLAG) != (uint16_t)RESET) + { + /* MEP_FLAG is set */ + bitstatus = SET; + } + else + { + /* MEP_FLAG is reset */ + bitstatus = RESET; + } + /* Return the MEP_FLAG status */ + return bitstatus; +} + +/** + * @brief Enable MEP SFO when AUTOCONV = 1. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval HRMSTEP value when MEPFLG_MEPFLG = 1. + */ +uint8_t EPWM_enableMEPSFO(EPWM_TypeDef* EPWMx) +{ + EALLOW(EPWMx); + + if (((EPWMx->HRCNFG)&EPWM_HRCNFG_AUTOCONV_BITS) == EPWM_HRCNFG_AUTOCONV_BITS) + { + EPWMx->HRPWR |= EPWM_HRPPWR_MEPSFO_BITS; + + while ((EPWM_MepCalibration_GetFlagStatus(EPWM1, EPWM_MEP_FLAG_INT)) != 1) {}; + + return (EPWMx->HRMSTEP); + } + + EDIS(EPWMx); + return 0; +} + +/** + * @brief Disable MEP SFO. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableMEPSFO(EPWM_TypeDef* EPWMx) +{ + EALLOW(EPWMx); + + EPWMx->HRPWR &= ~EPWM_HRPPWR_MEPSFO_BITS; + + EDIS(EPWMx); +} + + +/** + * @brief Sets the filter value of the TZ1-3 for the trip zone (TZ). + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param FILTER The filter value(0~255). + */ +void EPWM_setTripZoneFilter(EPWM_TypeDef* EPWMx, uint8_t FILTER) +{ + EALLOW(EPWMx); + + EPWMx->TZSEL |= (FILTER << 16); + + EDIS(EPWMx); +} + + + + +/** + * @brief Clears the trip zone (TZ) flag specified + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneFlag The trip zone flag to clear + */ +void EPWM_clearTripZone(EPWM_TypeDef* EPWMx, const EPWM_TripZoneFlag_e tripZoneFlag) +{ + EALLOW(EPWMx); + + EPWMx->TZCLR |= tripZoneFlag; + + EDIS(EPWMx); + +} + +/** + * @brief Decrement the dead band falling edge delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_decrementDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx) +{ + + EPWMx->DBFED--; + +} + +/** + * @brief Decrement the dead band rising edge delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_decrementDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx) +{ + + EPWMx->DBRED--; + +} + +/** + * @brief Disables auto conversion of delay line value + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableAutoConvert(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->HRCNFG &= ~EPWM_HRCNFG_AUTOCONV_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Enables the pulse width modulation (PWM) chopping + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableChopping(EPWM_TypeDef* EPWMx) +{ + + EPWMx->PCCTL = (uint16_t)1; + +} + +/** + * @brief Disables the pulse width modulation (PWM) chopping + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableChopping(EPWM_TypeDef* EPWMx) +{ + + EPWMx->PCCTL &= (~EPWM_PCCTL_CHPEN_BITS); + +} + +/** + * @brief Disables the pulse width modulation (PWM) counter loading from + the phase register + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableCounterLoad(EPWM_TypeDef* EPWMx) +{ + + EPWMx->TBCTL &= (~EPWM_TBCTL_PHSEN_BITS); + +} + +/** + * @brief Disables the pulse width modulation (PWM) deadband + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableDeadBand(EPWM_TypeDef* EPWMx) +{ + + EPWMx->DBCTL = 0; + +} + +/** + * @brief Disables the pulse width modulation (PWM) deadband half cycle + clocking + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableDeadBandHalfCycle(EPWM_TypeDef* EPWMx) +{ + + EPWMx->DBCTL &= (~EPWM_DBCTL_HALFCYCLE_BITS); + +} + +/** + * @brief Disables the pulse width modulation (PWM) digital compare + blanking window + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableDigitalCompareBlankingWindow(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->DCFCTL &= ~EPWM_DCFCTL_BLANKE_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Disables the pulse width modulation (PWM) digital compare + blanking window inversion + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableDigitalCompareBlankingWindowInversion(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->DCFCTL &= ~EPWM_DCFCTL_BLANKINV_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Disables high resolution period control + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableHrPeriod(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->HRPCTL &= ~EPWM_HRPCTL_HRPE_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Disables high resolution phase synchronization + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableHrPhaseSync(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->HRPCTL &= ~EPWM_HRPCTL_TBPHSHRLOADE_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Disables MEP Calibration Off bit + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableMEPCalibrationOff(EPWM_TypeDef* EPWMx) +{ + EALLOW(EPWMx); + + EPWMx->HRPWR &= ~EPWM_HRPPWR_MEPOFF_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Disables the pulse width modulation (PWM) interrupt + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableInt(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETSEL &= (~EPWM_ETSEL_INTEN_BITS); + +} + +/** + * @brief Disables the pulse width modulation (PWM) start of conversion + (SOC) B pulse generation + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableSocAPulse(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETSEL &= (~EPWM_ETSEL_SOCAEN_BITS); + +} + +/** + * @brief Disables the pulse width modulation (PWM) start of conversion + (SOC) B pulse generation + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableSocBPulse(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETSEL &= (~EPWM_ETSEL_SOCBEN_BITS); + +} + +/** + * @brief Disables the pulse width modulation (PWM) trip zones + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_disableTripZones(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->TZSEL = 0; + + EDIS(EPWMx); + +} + +/** + * @brief Disables the pulse width modulation (PWM) trip zones interrupts + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param interruptSource The interrupt source to disable + */ +void EPWM_disableTripZoneInt(EPWM_TypeDef* EPWMx, const EPWM_TripZoneFlag_e interruptSource) +{ + + EALLOW(EPWMx); + + EPWMx->TZEINT &= ~interruptSource; + + EDIS(EPWMx); + +} + +/** + * @brief Disable the pulse width modulation (PWM) trip zone source + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param src The pulse width modulation (PWM) trip zone source + */ +void EPWM_disableTripZoneSrc(EPWM_TypeDef* EPWMx, const EPWM_TripZoneSrc_e src) +{ + + EALLOW(EPWMx); + + EPWMx->TZSEL &= (~src); + + EDIS(EPWMx); + +} + +/** + * @brief Enables auto conversion of delay line value + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableAutoConvert(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->HRCNFG |= EPWM_HRCNFG_AUTOCONV_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Enables the pulse width modulation (PWM) counter loading from + the phase register + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableCounterLoad(EPWM_TypeDef* EPWMx) +{ + + EPWMx->TBCTL |= EPWM_TBCTL_PHSEN_BITS; + +} + +/** + * @brief Enables the pulse width modulation (PWM) deadband half cycle + clocking + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableDeadBandHalfCycle(EPWM_TypeDef* EPWMx) +{ + + EPWMx->DBCTL |= (uint16_t)EPWM_DBCTL_HALFCYCLE_BITS; + +} + +/** + * @brief Enables the pulse width modulation (PWM) digital compare + blanking window + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableDigitalCompareBlankingWindow(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->DCFCTL |= EPWM_DCFCTL_BLANKE_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Enables the pulse width modulation (PWM) digital compare + blanking window inversion + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableDigitalCompareBlankingWindowInversion(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->DCFCTL |= EPWM_DCFCTL_BLANKINV_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Enables high resolution period control + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableHrPeriod(EPWM_TypeDef* EPWMx) +{ + EALLOW(EPWMx); + + EPWMx->HRPCTL |= EPWM_HRPCTL_HRPE_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Enables the pulse width modulation (PWM) interrupt + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableInt(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETSEL |= EPWM_ETSEL_INTEN_BITS; + +} + +/** + * @brief Enables high resolution phase synchronization + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableHrPhaseSync(EPWM_TypeDef* EPWMx) +{ + EALLOW(EPWMx); + + EPWMx->HRPCTL |= EPWM_HRPCTL_TBPHSHRLOADE_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Enables MEP Calibration Off bit + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableMEPCalibrationOff(EPWM_TypeDef* EPWMx) +{ + EALLOW(EPWMx); + + EPWMx->HRPWR |= EPWM_HRPPWR_MEPOFF_BITS; + + EDIS(EPWMx); + +} + +/** + * @brief Enables the pulse width modulation (PWM) start of conversion + (SOC) A pulse generation + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableSocAPulse(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETSEL |= EPWM_ETSEL_SOCAEN_BITS; + +} + +/** + * @brief Enables the pulse width modulation (PWM) start of conversion + (SOC) B pulse generation + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_enableSocBPulse(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETSEL |= (uint16_t)EPWM_ETSEL_SOCBEN_BITS; + +} + +/** + * @brief Enables the pulse width modulation (PWM) trip zones interrupts + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param interruptSource The interrupt source to enable + */ +void EPWM_enableTripZoneInt(EPWM_TypeDef* EPWMx, const EPWM_TripZoneFlag_e interruptSource) +{ + + EALLOW(EPWMx); + + EPWMx->TZEINT |= interruptSource; + + EDIS(EPWMx); + +} + +/** + * @brief Enable the pulse width modulation (PWM) trip zone source + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param src The pulse width modulation (PWM) trip zone source + */ +void EPWM_enableTripZoneSrc(EPWM_TypeDef* EPWMx, const EPWM_TripZoneSrc_e src) +{ + + EALLOW(EPWMx); + + EPWMx->TZSEL |= src; + + EDIS(EPWMx); + +} + +/** + * @brief Gets the pulse width modulation (PWM) deadband falling edge + delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The delay + */ +uint16_t EPWM_getDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx) +{ + + return (EPWMx->DBFED); +} + +/** + * @brief Gets the pulse width modulation (PWM) deadband rising edge delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The delay + */ +uint16_t EPWM_getDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx) +{ + + return (EPWMx->DBRED); +} + +/** + * @brief Gets the pulse width modulation (PWM) interrupt event count + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The interrupt event count + */ +uint16_t EPWM_getIntCount(EPWM_TypeDef* EPWMx) +{ + uint16_t intCount; + + intCount = EPWMx->ETPS & EPWM_ETPS_INTCNT_BITS; + + return (intCount); +} + +/** + * @brief Gets the pulse width modulation (PWM) start of conversion (SOC) + A count + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The SOC A count + */ +uint16_t EPWM_getSocACount(EPWM_TypeDef* EPWMx) +{ + uint16_t intCount; + + intCount = EPWMx->ETPS & EPWM_ETPS_SOCACNT_BITS; + + intCount >>= 10; + + return (intCount); +} + +/** + * @brief Gets the pulse width modulation (PWM) start of conversion (SOC) + B count + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The SOC B count + */ +uint16_t EPWM_getSocBCount(EPWM_TypeDef* EPWMx) +{ + uint16_t intCount; + + intCount = EPWMx->ETPS & (uint16_t)EPWM_ETPS_SOCBCNT_BITS; + + intCount >>= 14; + + return (intCount); +} + + +EPWM_ShadowStatus_e EPWM_getShadowStatus_CmpA(EPWM_TypeDef* EPWMx) +{ + EPWM_ShadowStatus_e status; + + status = (EPWM_ShadowStatus_e)(EPWMx->CMPCTL & (EPWM_CMPCTL_SHDWAFULL_BITS)); + + status >>= 5; + + return (status); +} + + +EPWM_ShadowStatus_e EPWM_getShadowStatus_CmpB(EPWM_TypeDef* EPWMx) +{ + EPWM_ShadowStatus_e status; + + status = (EPWM_ShadowStatus_e)(EPWMx->CMPCTL & (EPWM_CMPCTL_SHDWBFULL_BITS)); + + status >>= 7; + + return (status); +} + +/** + * @brief Set the High Resolution Control Mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param controlMode The control mode HREPWM should use + */ +void EPWM_setHrControlMode(EPWM_TypeDef* EPWMx, const EPWM_HrControlMode_e controlMode) +{ + EALLOW(EPWMx); + + EPWMx->HRCNFG &= ~EPWM_HRCNFG_CTLMODE_BITS; + + EPWMx->HRCNFG |= controlMode; + + EDIS(EPWMx); + +} + +/** + * @brief Set the High Resolution Edge Mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param edgeMode The edge mode HREPWM should use + */ +void EPWM_setHrEdgeMode(EPWM_TypeDef* EPWMx, const EPWM_HrEdgeMode_e edgeMode) +{ + EALLOW(EPWMx); + + EPWMx->HRCNFG &= ~EPWM_HRCNFG_EDGMODE_BITS; + + EPWMx->HRCNFG |= edgeMode; + + EDIS(EPWMx); + +} + +/** + * @brief Set the High Resolution Shadow Load Mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param shadowMode The shadow load mode HREPWM should use + */ +void EPWM_setHrShadowMode(EPWM_TypeDef* EPWMx, const EPWM_HrShadowMode_e shadowMode) +{ + EALLOW(EPWMx); + + EPWMx->HRCNFG &= ~EPWM_HRCNFG_HRLOAD_BITS; + + EPWMx->HRCNFG |= shadowMode; + + EDIS(EPWMx); + +} + +/** + * @brief Increment the dead band falling edge delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_incrementDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx) +{ + EPWMx->DBFED++; + +} + +/** + * @brief Increment the dead band rising edge delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_incrementDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx) +{ + EPWMx->DBRED++; + +} + +/** + * @brief Initializes the pulse width modulation (PWM) object handle + * @param pMemory A pointer to the base address of the EPWM registers + * @param numBytes The number of bytes allocated for the EPWM object, bytes + * @retval The pulse width modulation (PWM) object handle + */ +//EPWM_Handle EPWM_init(void *pMemory, const size_t numBytes) +//{ +// EPWM_TypeDef* EPWMx; +// +// if(numBytes < sizeof(EPWM_TypeDef)) +// { +// return((EPWM_Handle)NULL); +// } +// +// // +// // assign the handle +// // +// +//} + + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM A + when the counter equals CMPA and the counter is decrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntDown_CmpA_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLA &= (~EPWM_AQCTL_CAD_BITS); + + EPWMx->AQCTLA |= (actionQual << 6); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM B + when the counter equals CMPA and the counter is decrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntDown_CmpA_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLB &= (~EPWM_AQCTL_CAD_BITS); + + EPWMx->AQCTLB |= (actionQual << 6); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM A + when the counter equals CMPB and the counter is decrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntDown_CmpB_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLA &= (~EPWM_AQCTL_CBD_BITS); + + EPWMx->AQCTLA |= (actionQual << 10); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM B + when the counter equals CMPB and the counter is decrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntDown_CmpB_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLB &= (~EPWM_AQCTL_CBD_BITS); + + EPWMx->AQCTLB |= (actionQual << 10); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM A + when the counter equals CMPA and the counter is incrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntUp_CmpA_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLA &= (~EPWM_AQCTL_CAU_BITS); + + EPWMx->AQCTLA |= (actionQual << 4); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM B + when the counter equals CMPA and the counter is incrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntUp_CmpA_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLB &= (~EPWM_AQCTL_CAU_BITS); + + EPWMx->AQCTLB |= (actionQual << 4); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM A + when the counter equals CMPB and the counter is incrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntUp_CmpB_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLA &= (~EPWM_AQCTL_CBU_BITS); + + EPWMx->AQCTLA |= (actionQual << 8); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM B + when the counter equals CMPB and the counter is incrementing + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_CntUp_CmpB_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLB &= (~EPWM_AQCTL_CBU_BITS); + + EPWMx->AQCTLB |= (actionQual << 8); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM A + when the counter equals the period + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_Period_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLA &= (~EPWM_AQCTL_PRD_BITS); + + EPWMx->AQCTLA |= (actionQual << 2); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM B + when the counter equals the period + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_Period_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLB &= (~EPWM_AQCTL_PRD_BITS); + + EPWMx->AQCTLB |= (actionQual << 2); + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM A + when the counter equals the zero + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_Zero_PwmA(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLA &= (~EPWM_AQCTL_ZRO_BITS); + + EPWMx->AQCTLA |= actionQual; + +} + +/** + * @brief Sets the pulse width modulation (PWM) object action for EPWM B + when the counter equals the zero + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param actionQual The action qualifier + */ +void EPWM_setActionQual_Zero_PwmB(EPWM_TypeDef* EPWMx, const EPWM_ActionQual_e actionQual) +{ + + EPWMx->AQCTLB &= (~EPWM_AQCTL_ZRO_BITS); + + EPWMx->AQCTLB |= actionQual; + +} + +/** + * @brief Sets the pulse width modulation (PWM) chopping clock frequency + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param clkFreq The clock frequency + */ +void EPWM_setChoppingClkFreq(EPWM_TypeDef* EPWMx, const EPWM_ChoppingClkFreq_e clkFreq) +{ + + EPWMx->PCCTL &= (~EPWM_PCCTL_CHPFREQ_BITS); + + EPWMx->PCCTL |= clkFreq; + +} + +/** + * @brief Sets the pulse width modulation (PWM) chopping clock duty cycle + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param dutyCycle The duty cycle + */ +void EPWM_setChoppingDutyCycle(EPWM_TypeDef* EPWMx, const EPWM_ChoppingDutyCycle_e dutyCycle) +{ + + EPWMx->PCCTL &= (~EPWM_PCCTL_CHPDUTY_BITS); + + EPWMx->PCCTL |= dutyCycle; + +} + +/** + * @brief Sets the pulse width modulation (PWM) chopping clock pulse width + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pulseWidth The pulse width + */ +void EPWM_setChoppingPulseWidth(EPWM_TypeDef* EPWMx, const EPWM_ChoppingPulseWidth_e pulseWidth) +{ + + EPWMx->PCCTL &= (~EPWM_PCCTL_OSHTWTH_BITS); + + EPWMx->PCCTL |= pulseWidth; + +} + +/** + * @brief Sets the pulse width modulation (PWM) high speed clock divisor + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param clkDiv The clock divisor + */ +void EPWM_setHighSpeedClkDiv(EPWM_TypeDef* EPWMx, const EPWM_HspClkDiv_e clkDiv) +{ + + EPWMx->TBCTL &= (~EPWM_TBCTL_HSPCLKDIV_BITS); + + EPWMx->TBCTL |= clkDiv; + +} + +/** + * @brief Sets the pulse width modulation (PWM) clock divisor + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param clkDiv The clock divisor + */ +void EPWM_setClkDiv(EPWM_TypeDef* EPWMx, const EPWM_ClkDiv_e clkDiv) +{ + + EPWMx->TBCTL &= (~EPWM_TBCTL_CLKDIV_BITS); + + EPWMx->TBCTL |= clkDiv; + +} + +/** + * @brief Sets the pulse width modulation (PWM) count + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param count The count + */ +void EPWM_setCount(EPWM_TypeDef* EPWMx, const uint16_t count) +{ + + EPWMx->TBCTR = count; + +} + +/** + * @brief Sets the pulse width modulation (PWM) counter mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param counterMode The count mode + */ +void EPWM_setCounterMode(EPWM_TypeDef* EPWMx, const EPWM_CounterMode_e counterMode) +{ + + EPWMx->TBCTL &= (~EPWM_TBCTL_CTRMODE_BITS); + + EPWMx->TBCTL |= counterMode; + +} + +/** + * @brief Sets the pulse width modulation (PWM) deadband falling edge delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param delay The delay + */ +void EPWM_setDeadBandFallingEdgeDelay(EPWM_TypeDef* EPWMx, const uint16_t delay) +{ + + EPWMx->DBFED |= delay; + +} + +/** + * @brief Sets the pulse width modulation (PWM) deadband input mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param inputMode The input mode + */ +void EPWM_setDeadBandInputMode(EPWM_TypeDef* EPWMx, const EPWM_DeadBandInputMode_e inputMode) +{ + + EPWMx->DBCTL &= (~EPWM_DBCTL_INMODE_BITS); + + EPWMx->DBCTL |= inputMode; + +} + +/** + * @brief Sets the pulse width modulation (PWM) deadband output mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param outputMode The output mode + */ +void EPWM_setDeadBandOutputMode(EPWM_TypeDef* EPWMx, const EPWM_DeadBandOutputMode_e outputMode) +{ + + EPWMx->DBCTL &= (~EPWM_DBCTL_OUTMODE_BITS); + + EPWMx->DBCTL |= outputMode; + +} + +/** + * @brief Sets the pulse width modulation (PWM) deadband polarity + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param polarity The polarity + */ +void EPWM_setDeadBandPolarity(EPWM_TypeDef* EPWMx, const EPWM_DeadBandPolarity_e polarity) +{ + + EPWMx->DBCTL &= (~EPWM_DBCTL_POLSEL_BITS); + + EPWMx->DBCTL |= polarity; + +} + +/** + * @brief Sets the pulse width modulation (PWM) deadband rising edge delay + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param delay The delay + */ +void EPWM_setDeadBandRisingEdgeDelay(EPWM_TypeDef* EPWMx, const uint16_t delay) +{ + + EPWMx->DBRED |= delay; + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare filter + source + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param input The filter's source + */ +void EPWM_setDigitalCompareFilterSource(EPWM_TypeDef* EPWMx, const EPWM_DigitalCompare_FilterSrc_e input) +{ + EALLOW(EPWMx); + + EPWMx->DCFCTL &= ~EPWM_DCFCTL_SRCSEL_BITS; + + EPWMx->DCFCTL |= input; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare blanking + pulse + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pulseSelect The pulse selection + */ +void EPWM_setDigitalCompareBlankingPulse(EPWM_TypeDef* EPWMx, const EPWM_DigitalCompare_PulseSel_e pulseSelect) +{ + EALLOW(EPWMx); + + EPWMx->DCFCTL &= ~EPWM_DCFCTL_PULSESEL_BITS; + + EPWMx->DCFCTL |= pulseSelect << 4; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare filter + offset + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param offset The offset + */ +void EPWM_setDigitalCompareFilterOffset(EPWM_TypeDef* EPWMx, const uint16_t offset) +{ + EPWMx->DCFOFFSET = offset; + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare filter + offset + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param window The window + */ +void EPWM_setDigitalCompareFilterWindow(EPWM_TypeDef* EPWMx, const uint16_t window) +{ + EPWMx->DCFWINDOW = window; + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare input + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param input Comparator input to change + * @param inputSel Input selection for designated input + */ +void EPWM_setDigitalCompareInput(EPWM_TypeDef* EPWMx, const EPWM_DigitalCompare_Input_e input, const EPWM_DigitalCompare_InputSel_e inputSel) +{ + EALLOW(EPWMx); + + EPWMx->DCTRIPSEL &= ~(0x000F << input); + + EPWMx->DCTRIPSEL |= (inputSel << input); + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare A event 1 + source parameters + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param selectFilter Select filter output if true + * @param disableSync Asynchronous if true + * @param enableSoc Enable SOC generation if true + * @param generateSync Generate SYNC if true + */ +void EPWM_setDigitalCompareAEvent1(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync, const uint16_t enableSoc, const uint16_t generateSync) +{ + EALLOW(EPWMx); + + EPWMx->DCACTL &= ~0x000F; + + EPWMx->DCACTL |= selectFilter | (disableSync << 1) | (enableSoc << 2) | + (generateSync << 3); + + EDIS(EPWMx); + +} + + +/** + * @brief Sets the pulse width modulation (PWM) digital compare A event 2 + source parameters + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param selectFilter Select filter output if true + * @param disableSync Asynchronous if true + */ +void EPWM_setDigitalCompareAEvent2(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync) +{ + + EALLOW(EPWMx); + + EPWMx->DCACTL &= ~0x0300; + + EPWMx->DCACTL |= (selectFilter << 8) | (disableSync << 9) ; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare B event 1 + source parameters + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param selectFilter Select filter output if true + * @param disableSync Asynchronous if true + * @param enableSoc Enable SOC generation if true + * @param generateSync Generate SYNC if true + */ +void EPWM_setDigitalCompareBEvent1(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync, const uint16_t enableSoc, const uint16_t generateSync) +{ + + EALLOW(EPWMx); + + EPWMx->DCBCTL &= ~0x000F; + + EPWMx->DCBCTL |= selectFilter | (disableSync << 1) | (enableSoc << 2) | + (generateSync << 3); + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) digital compare B event 2 + source parameters + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param selectFilter Select filter output if true + * @param disableSync Asynchronous if true + */ +void EPWM_setDigitalCompareBEvent2(EPWM_TypeDef* EPWMx, const uint16_t selectFilter, const uint16_t disableSync) +{ + EALLOW(EPWMx); + + EPWMx->DCBCTL &= ~0x0300; + + EPWMx->DCBCTL |= (selectFilter << 8) | (disableSync << 9) ; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) interrupt mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param intMode The interrupt mode + */ +void EPWM_setIntMode(EPWM_TypeDef* EPWMx, const EPWM_IntMode_e intMode) +{ + + EPWMx->ETSEL &= (~EPWM_ETSEL_INTSEL_BITS); + + EPWMx->ETSEL |= intMode; + +} + +/** + * @brief Sets the pulse width modulation (PWM) interrupt period + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param intPeriod The interrupt period + */ +void EPWM_setIntPeriod(EPWM_TypeDef* EPWMx, const EPWM_IntPeriod_e intPeriod) +{ + + EPWMx->ETPS &= (~EPWM_ETPS_INTPRD_BITS); + + EPWMx->ETPS |= intPeriod; + +} + +/** + * @brief Sets the pulse width modulation (PWM) load mode for CMPA + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param loadMode The load mode + */ +void EPWM_setLoadMode_CmpA(EPWM_TypeDef* EPWMx, const EPWM_LoadMode_e loadMode) +{ + + EPWMx->CMPCTL &= (~EPWM_CMPCTL_LOADAMODE_BITS); + + EPWMx->CMPCTL |= loadMode; + +} + +/** + * @brief Sets the pulse width modulation (PWM) load mode for CMPB + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param loadMode The load mode + */ +void EPWM_setLoadMode_CmpB(EPWM_TypeDef* EPWMx, const EPWM_LoadMode_e loadMode) +{ + + EPWMx->CMPCTL &= (~EPWM_CMPCTL_LOADBMODE_BITS); + + EPWMx->CMPCTL |= (loadMode << 2); + +} + +/** + * @brief Sets the pulse width modulation (PWM) period + * Initialize the Time-Base Period Register (TBPRD). These bits determine + * the period of the time-base counter. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param period The period + */ +void EPWM_setPeriod(EPWM_TypeDef* EPWMx, const uint16_t period) +{ + + EPWMx->TBPRD = period; + +} + +/** + * @brief Sets the pulse width modulation (PWM) high resolution period + * Initialize the Time-Base Period Register (TBPRD). These bits determine + * the period of the time-base counter. + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param period The period + */ +void EPWM_setPeriodHr(EPWM_TypeDef* EPWMx, const uint16_t period) +{ + + EALLOW(EPWMx); + + EPWMx->TBPRDHR = period; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) phase + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param phase The phase + */ +void EPWM_setPhase(EPWM_TypeDef* EPWMx, const uint16_t phase) +{ + + EPWMx->TBPHS = phase; + +} + +/** + * @brief Sets the pulse width modulation (PWM) phase direction + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param phaseDir The phase direction + */ +void EPWM_setPhaseDir(EPWM_TypeDef* EPWMx, const EPWM_PhaseDir_e phaseDir) +{ + + EPWMx->TBCTL &= (~EPWM_TBCTL_PHSDIR_BITS); + + EPWMx->TBCTL |= phaseDir; + +} + +/** + * @brief Sets the pulse width modulation (PWM) period load mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param periodLoad The period load mode + */ +void EPWM_setPeriodLoad(EPWM_TypeDef* EPWMx, const EPWM_PeriodLoad_e periodLoad) +{ + + EPWMx->TBCTL &= (~EPWM_TBCTL_PRDLD_BITS); + + EPWMx->TBCTL |= periodLoad; + +} + +/** + * @brief Sets the pulse width modulation (PWM) run mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param runMode The run mode + */ +//void EPWM_setRunMode(EPWM_TypeDef* EPWMx, const EPWM_RunMode_e runMode) +//{ +// +// EPWMx->TBCTL &= (~EPWM_TBCTL_FREESOFT_BITS); +// +// EPWMx->TBCTL |= runMode; +// +//} + +/** + * @brief Sets the pulse width modulation (PWM) start of conversion (SOC) + A interrupt period + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param intPeriod The interrupt period + */ +void EPWM_setSocAPeriod(EPWM_TypeDef* EPWMx, const EPWM_SocPeriod_e intPeriod) +{ + + EPWMx->ETPS &= (~EPWM_ETPS_SOCAPRD_BITS); + + EPWMx->ETPS |= (intPeriod << 8); + +} + +/** + * @brief Sets the pulse width modulation (PWM) start of conversion (SOC) + A interrupt pulse source + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pulseSrc The interrupt pulse source + */ +void EPWM_setSocAPulseSrc(EPWM_TypeDef* EPWMx, const EPWM_SocPulseSrc_e pulseSrc) +{ + + EPWMx->ETSEL &= (~EPWM_ETSEL_SOCASEL_BITS); + + EPWMx->ETSEL |= (pulseSrc << 8); + +} + +/** + * @brief Sets the pulse width modulation (PWM) start of conversion (SOC) + B interrupt period + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param intPeriod The interrupt period + */ +void EPWM_setSocBPeriod(EPWM_TypeDef* EPWMx, const EPWM_SocPeriod_e intPeriod) +{ + + EPWMx->ETPS &= (~EPWM_ETPS_SOCBPRD_BITS); + + EPWMx->ETPS |= (intPeriod << 12); + +} + +/** + * @brief Sets the pulse width modulation (PWM) start of conversion (SOC) + B interrupt pulse source + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pulseSrc The interrupt pulse source + */ +void EPWM_setSocBPulseSrc(EPWM_TypeDef* EPWMx, const EPWM_SocPulseSrc_e pulseSrc) +{ + + EPWMx->ETSEL &= (~EPWM_ETSEL_SOCBSEL_BITS); + + EPWMx->ETSEL |= (pulseSrc << 12); + +} + +/** + * @brief Sets the pulse width modulation (PWM) shadow mode for CMPA + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param shadowMode The shadow mode + */ +void EPWM_setShadowMode_CmpA(EPWM_TypeDef* EPWMx, const EPWM_ShadowMode_e shadowMode) +{ + + EPWMx->CMPCTL &= (~EPWM_CMPCTL_SHDWAMODE_BITS); + + EPWMx->CMPCTL |= (shadowMode << 4); + +} + +/** + * @brief Sets the pulse width modulation (PWM) shadow mode for CMPB + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param shadowMode The shadow mode + */ +void EPWM_setShadowMode_CmpB(EPWM_TypeDef* EPWMx, const EPWM_ShadowMode_e shadowMode) +{ + + EPWMx->CMPCTL &= (~EPWM_CMPCTL_SHDWBMODE_BITS); + + EPWMx->CMPCTL |= (shadowMode << 6); + +} + +/** + * @brief Sets the pulse width modulation (PWM) software sync + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +void EPWM_setSwSync(EPWM_TypeDef* EPWMx) +{ + + EPWMx->TBCTL |= 1 << 6; + +} + +/** + * @brief Force Synchronization + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +inline void EPWM_forceSync(EPWM_TypeDef* EPWMx) +{ + + EPWMx->TBCTL |= EPWM_TBCTL_SWFSYNC_BITS; + +} + + +/** + * @brief Sets the pulse width modulation (PWM) sync mode + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param syncMode The sync mode + */ +void EPWM_setSyncMode(EPWM_TypeDef* EPWMx, const EPWM_SyncMode_e syncMode) +{ + + EPWMx->TBCTL &= (~EPWM_TBCTL_SYNCOSEL_BITS); + + EPWMx->TBCTL |= syncMode; + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone digital compare + event select for Digital Compare Output A Event 1 (DCAEVT1) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneEvent The trip zone digital compare event + */ +void EPWM_setTripZoneDCEventSelect_DCAEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent) +{ + + EALLOW(EPWMx); + + EPWMx->TZDCSEL &= (~EPWM_TZDCSEL_DCAEVT1_BITS); + + EPWMx->TZDCSEL |= tripZoneEvent << 0; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone digital compare + event select for Digital Compare Output A Event 2 (DCAEVT2) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneEvent The trip zone digital compare event + */ +void EPWM_setTripZoneDCEventSelect_DCAEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent) +{ + + EALLOW(EPWMx); + + EPWMx->TZDCSEL &= (~EPWM_TZDCSEL_DCAEVT2_BITS); + + EPWMx->TZDCSEL |= tripZoneEvent << 3; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone digital compare + event select for Digital Compare Output B Event 1 (DCBEVT1) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneEvent The trip zone digital compare event + */ +void EPWM_setTripZoneDCEventSelect_DCBEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent) +{ + + EALLOW(EPWMx); + + EPWMx->TZDCSEL &= (~EPWM_TZDCSEL_DCBEVT1_BITS); + + EPWMx->TZDCSEL |= tripZoneEvent << 6; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone digital compare + event select for Digital Compare Output B Event 2 (DCBEVT2) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneEvent The trip zone digital compare event + */ +void EPWM_setTripZoneDCEventSelect_DCBEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneDCEventSel_e tripZoneEvent) +{ + + EALLOW(EPWMx); + + EPWMx->TZDCSEL &= (~EPWM_TZDCSEL_DCBEVT2_BITS); + + EPWMx->TZDCSEL |= tripZoneEvent << 9; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone state for + Digital Compare Output A Event 1 (DCAEVT1) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneState The trip zone state + */ +void EPWM_setTripZoneState_DCAEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState) +{ + + EALLOW(EPWMx); + + EPWMx->TZCTL &= (~EPWM_TZCTL_DCAEVT1_BITS); + + EPWMx->TZCTL |= tripZoneState << 4; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone state for + Digital Compare Output A Event 2 (DCAEVT1) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneState The trip zone state + */ +void EPWM_setTripZoneState_DCAEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState) +{ + + EALLOW(EPWMx); + + EPWMx->TZCTL &= (~EPWM_TZCTL_DCAEVT2_BITS); + + EPWMx->TZCTL |= tripZoneState << 6; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone state for + Digital Compare Output B Event 1 (DCBEVT1) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneState The trip zone state + */ +void EPWM_setTripZoneState_DCBEVT1(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState) +{ + + EALLOW(EPWMx); + + EPWMx->TZCTL &= (~EPWM_TZCTL_DCBEVT1_BITS); + + EPWMx->TZCTL |= tripZoneState << 8; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone state for + Digital Compare Output B Event 2 (DCBEVT1) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneState The trip zone state + */ +void EPWM_setTripZoneState_DCBEVT2(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState) +{ + + EALLOW(EPWMx); + + EPWMx->TZCTL &= (~EPWM_TZCTL_DCBEVT2_BITS); + + EPWMx->TZCTL |= tripZoneState << 10; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone state for Output + A (TZA) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneState The trip zone state + */ +void EPWM_setTripZoneState_TZA(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState) +{ + + EALLOW(EPWMx); + + EPWMx->TZCTL &= (~EPWM_TZCTL_TZA_BITS); + + EPWMx->TZCTL |= tripZoneState << 0; + + EDIS(EPWMx); + +} + +/** + * @brief Sets the pulse width modulation (PWM) trip zone state for Output + B (TZB) + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param tripZoneState The trip zone state + */ +void EPWM_setTripZoneState_TZB(EPWM_TypeDef* EPWMx, const EPWM_TripZoneState_e tripZoneState) +{ + + EALLOW(EPWMx); + + EPWMx->TZCTL &= (~EPWM_TZCTL_TZB_BITS); + + EPWMx->TZCTL |= tripZoneState << 2; + + EDIS(EPWMx); + +} + + + + + + + +/** + * @brief Clears the Mep Calibration interrupt flag + * @param EPWMx The pulse width modulation (PWM) object handle + */ +inline void EPWM_clearMepFlag(EPWM_TypeDef* EPWMx) +{ + EPWMx->MEPCLR = EPWM_MEP_INT_BITS; +} + + +/** + * @brief Clears the pulse width modulation (PWM) interrupt flag + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +inline void EPWM_clearIntFlag(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETCLR = EPWM_ETCLR_INT_BITS; + +} + + +/** + * @brief Clears the pulse width modulation (PWM) one shot trip + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +inline void EPWM_clearOneShotTrip(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->TZCLR = EPWM_TZCLR_OST_BITS; + + EDIS(EPWMx); + +} + + +/** + * @brief Clears the pulse width modulation (PWM) start of conversion + (SOC) A flag + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +inline void EPWM_clearSocAFlag(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETCLR = EPWM_ETCLR_SOCA_BITS; + +} + + +/** + * @brief Clears the pulse width modulation (PWM) start of conversion + (SOC) B flag + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +inline void EPWM_clearSocBFlag(EPWM_TypeDef* EPWMx) +{ + + EPWMx->ETCLR = EPWM_ETCLR_SOCB_BITS; + +} + + +/** + * @brief Gets the pulse width modulation (PWM) period value + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The pwm period value + */ +inline uint16_t EPWM_getPeriod(EPWM_TypeDef* EPWMx) +{ + + return (EPWMx->TBPRD); +} + + +/** + * @brief Gets the pulse width modulation (PWM) data value from the + Counter Compare A hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The EPWM compare data value + */ +inline uint16_t EPWM_getCmpA(EPWM_TypeDef* EPWMx) +{ + + return (EPWMx->CMPA); +} + + +/** + * @brief Gets the pulse width modulation (PWM) data value from the + Counter Compare A Hr hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The EPWM compare high resolution data value + */ +inline uint16_t EPWM_getCmpAHr(EPWM_TypeDef* EPWMx) +{ + + return (EPWMx->CMPAHR); +} + + +/** + * @brief Gets the pulse width modulation (PWM) data value from the + Counter Compare B hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @retval The EPWM compare data value + */ +inline uint16_t EPWM_getCmpB(EPWM_TypeDef* EPWMx) +{ + + return (EPWMx->CMPB); +} + + +/** + * @brief Sets the pulse width modulation (PWM) one shot trip + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + */ +inline void EPWM_setOneShotTrip(EPWM_TypeDef* EPWMx) +{ + + EALLOW(EPWMx); + + EPWMx->TZFRC |= EPWM_TZFRC_OST_BITS; + + EDIS(EPWMx); + +} + + +/** + * @brief Writes the pulse width modulation (PWM) data value to the + Counter Compare A hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pwmData The EPWM data value + */ +inline void EPWM_write_CmpA(EPWM_TypeDef* EPWMx, const int16_t pwmData) +{ + + int16_t value; + uint16_t period = EPWMx->TBPRD; + int32_t tmp; + + /* Compute the compare A (Q0) from the related duty cycle ratio (Q15) */ + tmp = (int32_t)period * (int32_t)(pwmData); // Q15 = Q0*Q15 + + /* Q0 = (Q15->Q0)/2 + (Q0/2) */ + value = (int16_t)(tmp >> 16) + (int16_t)(period >> 1); + + EPWMx->CMPA = value; + +} + + +/** + * @brief Writes the pulse width modulation (PWM) data value to the + Counter Compare A hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pwmData The EPWM data value + */ +inline void EPWM_setCmpA(EPWM_TypeDef* EPWMx, const uint16_t pwmData) +{ + + EPWMx->CMPA = pwmData; + +} + + +/** + * @brief Writes the pulse width modulation (PWM) data value to the + Counter Compare A Hr hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pwmData The EPWM high resolution data value + */ +inline void EPWM_setCmpAHr(EPWM_TypeDef* EPWMx, const uint16_t pwmData) +{ + + EPWMx->CMPAHR = (pwmData << 8); + +} + + +/** + * @brief Writes the pulse width modulation (PWM) data value to the + Counter Compare B hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pwmData The EPWM data value + */ +inline void EPWM_write_CmpB(EPWM_TypeDef* EPWMx, const int16_t pwmData) +{ + + int16_t value; + uint16_t period = EPWMx->TBPRD; + int32_t tmp; + + /* Compute the compare A (Q0) from the related duty cycle ratio (Q15) */ + tmp = (int32_t)period * (int32_t)(pwmData); // Q15 = Q0*Q15 + + /* Q0 = (Q15->Q0)/2 + (Q0/2) */ + value = (int16_t)(tmp >> 16) + (int16_t)(period >> 1); + + EPWMx->CMPB = value; + +} + + +/** + * @brief Writes the pulse width modulation (PWM) data value to the + Counter Compare B hardware + * @param EPWMx where x can be 1 to 4 to select the EPWM peripheral + * @param pwmData The EPWM data value + */ +inline void EPWM_setCmpB(EPWM_TypeDef* EPWMx, const uint16_t pwmData) +{ + + EPWMx->CMPB = pwmData; + +} + + + + + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_eqep.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_eqep.c new file mode 100644 index 00000000000..a289b669a8a --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_eqep.c @@ -0,0 +1,956 @@ +/** + ****************************************************************************** + * @file ft32f4xx_eqep.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Enhanced Quadrature Encoder Pulse (eQEP): + * + Initialization and Configuration + * + EQEP control + * + Data register access + * + Interrupts and flags management + * @version V1.0.0 + * @date 2025-04-22 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_eqep.h" +#include "ft32f4xx_rcc.h" + + +/** @defgroup EQEP + * @brief EQEP driver modules + * @{ + */ + + +/** + * @brief Initialize the EQEP control according to the specified parameters in the + * EQEP_InitTypeDef and initialize the associated handle. + * @param EQEP_InitStruct pointer to a EQEP_InitTypeDef structure that contains the + * configuration information for the specified EQEP peripheral. + * @retval None + */ +void EQEP_Init(EQEP_InitTypeDef* EQEP_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_EQEP_RESET_SOURCE(EQEP_InitStruct->PosCounterResetSrc)); + assert_param(IS_EQEP_SE_INIT(EQEP_InitStruct->SEInitPosCounter)); + assert_param(IS_EQEP_IE_INIT(EQEP_InitStruct->IEInitPosCounter)); + assert_param(IS_EQEP_SE_LATCH(EQEP_InitStruct->SELatchPosCounter)); + assert_param(IS_EQEP_IE_LATCH(EQEP_InitStruct->IELatchPosCounter)); + assert_param(IS_EQEP_CAPTURELATCH_MODE(EQEP_InitStruct->CaptureLatchMode)); + assert_param(IS_EQEP_POS_COUNTER_VALUE(EQEP_InitStruct->PosCounterValue)); + assert_param(IS_EQEP_POS_COUNTER_INIT_VALUE(EQEP_InitStruct->PosCounterInitValue)); + assert_param(IS_EQEP_POS_COUNTER_MAX_VALUE(EQEP_InitStruct->PosCounterMaxValue)); + assert_param(IS_EQEP_POS_COUNTER_CMP_VALUE(EQEP_InitStruct->PosCounterCmpValue)); + assert_param(IS_EQEP_UNIT_TIMER_PERIOD_VALUE(EQEP_InitStruct->UnitTimerPeriodValue)); + assert_param(IS_EQEP_WDG_TIMER_PERIOD_VALUE(EQEP_InitStruct->WdgTimerPeriodValue)); + + + /* Config EQEP control register */ + tmpreg = (uint32_t)((EQEP_InitStruct->PosCounterResetSrc) | + (EQEP_InitStruct->SEInitPosCounter) | + (EQEP_InitStruct->IEInitPosCounter) | + (EQEP_InitStruct->SELatchPosCounter) | + (EQEP_InitStruct->IELatchPosCounter) | + (EQEP_InitStruct->CaptureLatchMode)); + + /* Write to EQEP QEPCTL register */ + EQEP->QEPCTL = tmpreg; + + /* Write the EQEP position counter register */ + EQEP->QPOSCNT = EQEP_InitStruct->PosCounterValue; + + /* Config the initialization value of the EQEP position counter register */ + EQEP->QPOSINIT = EQEP_InitStruct->PosCounterInitValue; + + /* Config the maximum value of the EQEP position counter register */ + EQEP->QPOSMAX = EQEP_InitStruct->PosCounterMaxValue; + + /* Config the compare value of the EQEP position counter register */ + EQEP->QPOSCMP = EQEP_InitStruct->PosCounterCmpValue; + + /* Config the period value of the EQEP unit timer register */ + EQEP->QUPRD = EQEP_InitStruct->UnitTimerPeriodValue; + + /* Config the period value of the EQEP watch dog timer register */ + EQEP->QWDPRD = EQEP_InitStruct->WdgTimerPeriodValue; + + +} + + +/** + * @brief Initialize the EQEP quadrature decoder unit according to the specified parameters in the + * EQEP_QDUInitStruct. + * @param EQEP_QDUInitStruct pointer to a EQEP_QDUInitTypeDef structure that contains the + * configuration information for the specified EQEP quadrature decoder unit. + * @retval None + */ +void EQEP_QDUInit(EQEP_QDUInitTypeDef* EQEP_QDUInitStruct) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_EQEP_POSCNTSRC_MODE(EQEP_QDUInitStruct->PosCounterSource)); + assert_param(IS_FUNCTIONAL_STATE(EQEP_QDUInitStruct->SyncOutput)); + assert_param(IS_EQEP_SYNC_OUTPUT_PIN(EQEP_QDUInitStruct->SyncOutputPin)); + assert_param(IS_EQEP_EXTERNAL_CLOCK_RATE(EQEP_QDUInitStruct->ExternalClockRate)); + assert_param(IS_FUNCTIONAL_STATE(EQEP_QDUInitStruct->ClockDirSwap)); + assert_param(IS_FUNCTIONAL_STATE(EQEP_QDUInitStruct->IndexGate)); + assert_param(IS_EQEP_QEPA_POLARITY(EQEP_QDUInitStruct->QEPAPolarity)); + assert_param(IS_EQEP_QEPB_POLARITY(EQEP_QDUInitStruct->QEPBPolarity)); + assert_param(IS_EQEP_QEPI_POLARITY(EQEP_QDUInitStruct->QEPIPolarity)); + assert_param(IS_EQEP_QEPS_POLARITY(EQEP_QDUInitStruct->QEPSPolarity)); + + + /* Get the EQEP QEPCTL value */ + tmpreg = EQEP->QDECCTL; + + /* Config EQEP quadrature decoder control register */ + tmpreg &= (uint32_t)~EQEP_QDECCTL_QSRC; + tmpreg |= (uint32_t)(EQEP_QDUInitStruct->PosCounterSource); + + tmpreg |= (uint32_t)((EQEP_QDUInitStruct->ExternalClockRate) | + (EQEP_QDUInitStruct->IndexGate << 9U) | + (EQEP_QDUInitStruct->QEPAPolarity) | + (EQEP_QDUInitStruct->QEPBPolarity) | + (EQEP_QDUInitStruct->QEPIPolarity) | + (EQEP_QDUInitStruct->QEPSPolarity)); + + if (EQEP_QDUInitStruct->SyncOutput == ENABLE) + { + tmpreg |= (uint32_t)(EQEP_QDECCTL_SOEN | + (EQEP_QDUInitStruct->SyncOutputPin)); + } + + if (EQEP_QDUInitStruct->ClockDirSwap == ENABLE) + { + tmpreg |= (uint32_t)EQEP_QDECCTL_SWAP; + } + + if (EQEP_QDUInitStruct->IndexGate == ENABLE) + { + tmpreg |= (uint32_t)EQEP_QDECCTL_IGATE; + } + + /* Write to EQEP QEPCTL register */ + EQEP->QDECCTL = tmpreg; + +} + + +/** + * @brief Initialize the EQEP capture control according to the specified parameters in the + * EQEP_CAPInitStruct. + * @param EQEP_CAPInitStruct pointer to a EQEP_CAPInitTypeDef structure that contains the + * configuration information for the specified EQEP capture unit. + * @retval None + */ +void EQEP_CAPInit(EQEP_CAPInitTypeDef* EQEP_CAPInitStruct) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_EQEP_CLOCKPRESCALER(EQEP_CAPInitStruct->CaptureClockPrescaler)); + assert_param(IS_EQEP_EVENTPRESCALER(EQEP_CAPInitStruct->UnitPosEventPrescaler)); + assert_param(IS_EQEP_CAPTURE_PERIOD_VALUE(EQEP_CAPInitStruct->CapturePeriodValue)); + + + /* Get the EQEP QCAPCTL value */ + tmpreg = EQEP->QCAPCTL; + + /* Config EQEP capture control register */ + tmpreg &= (uint32_t)~EQEP_QCAPCTL_CEN; + tmpreg |= (uint32_t)(EQEP_CAPInitStruct->CaptureClockPrescaler); + tmpreg |= (uint32_t)(EQEP_CAPInitStruct->UnitPosEventPrescaler); + + /* Write to EQEP QCAPCTL register */ + EQEP->QCAPCTL = tmpreg; + + /* Config the period value of the EQEP capture counter register */ + EQEP->QCPRD = EQEP_CAPInitStruct->CapturePeriodValue; + +} + + + +/** + * @brief Initialize the EQEP position compare control according to the specified + * parameters in the EQEP_PosCmpInitStruct. + * @param EQEP_PosCmpInitStruct pointer to a EQEP_PosCmpInitTypeDef structure + * that contains the configuration information for the specified + * EQEP position compare unit. + * @retval None + */ +void EQEP_POSCMPInit(EQEP_PosCmpInitTypeDef* EQEP_PosCmpInitStruct) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(EQEP_PosCmpInitStruct->PosCompareShadow)); + assert_param(IS_EQEP_POSCMP_LOAD(EQEP_PosCmpInitStruct->PosCompareShadowLoad)); + assert_param(IS_EQEP_SYNCOUT_POLARITY(EQEP_PosCmpInitStruct->SyncOutPolarity)); + assert_param(IS_FUNCTIONAL_STATE(EQEP_PosCmpInitStruct->PosCompare)); + assert_param(IS_EQEP_SYNCOUT_PULSE_WIDTH(EQEP_PosCmpInitStruct->SyncOutPulseWidth)); + + + /* Get the EQEP QPOSCTL value */ + tmpreg = EQEP->QPOSCTL; + + /* Config EQEP position compare control register */ + if (EQEP_PosCmpInitStruct->PosCompareShadow == ENABLE) + { + tmpreg |= (uint32_t)EQEP_QPOSCTL_PCSHDW; + } + + tmpreg |= (uint32_t)((EQEP_PosCmpInitStruct->PosCompareShadowLoad) | + (EQEP_PosCmpInitStruct->SyncOutPolarity)); + + if (EQEP_PosCmpInitStruct->PosCompare == ENABLE) + { + tmpreg |= (uint32_t)EQEP_QPOSCTL_PCMPE; + } + + tmpreg |= (uint32_t)(EQEP_PosCmpInitStruct->SyncOutPulseWidth); + + /* Write to EQEP QCAPCTL register */ + EQEP->QPOSCTL = tmpreg; + +} + + +/** + * @brief Fills each EQEP_StructInit member with its default value. + * @param EQEP_InitStruct pointer to a EQEP_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void EQEP_StructInit(EQEP_InitTypeDef* EQEP_InitStruct) +{ + /*---- Reset the parameter values of the EQEP structure ----*/ + /* Initialize the EQEP_PosCounterResetSrc member */ + EQEP_InitStruct->PosCounterResetSrc = 0U; + + /* Initialize the EQEP_SEInitPosCounter member */ + EQEP_InitStruct->SEInitPosCounter = 0U; + + /* Initialize the EQEP_IEInitPosCounter member */ + EQEP_InitStruct->IEInitPosCounter = 0U; + + /* Initialize the EQEP_SELatchPosCounter member */ + EQEP_InitStruct->SELatchPosCounter = 0U; + + /* Initialize the EQEP_IELatchPosCounter member */ + EQEP_InitStruct->IELatchPosCounter = 0U; + + /* Initialize the EQEP_CaptureLatchMode member */ + EQEP_InitStruct->CaptureLatchMode = 0U; + + /* Initialize the EQEP_PosCounterValue member */ + EQEP_InitStruct->PosCounterValue = 0U; + + /* Initialize the EQEP_PosCounterInitValue member */ + EQEP_InitStruct->PosCounterInitValue = 0U; + + /* Initialize the EQEP_PosCounterMaxValue member */ + EQEP_InitStruct->PosCounterMaxValue = 0U; + + /* Initialize the EQEP_PosCounterCmpValue member */ + EQEP_InitStruct->PosCounterCmpValue = 0U; + + /* Initialize the EQEP_UnitTimerPeriodValue member */ + EQEP_InitStruct->UnitTimerPeriodValue = 0U; + + /* Initialize the EQEP_WdgTimerPeriodValue member */ + EQEP_InitStruct->WdgTimerPeriodValue = 0U; + +} + + +/** + * @brief Fills each EQEP_QDUStructInit member with its default value. + * @param EQEP_QDUInitStruct pointer to a EQEP_QDUInitTypeDef structure + * which will be initialized. + * @retval None + */ +void EQEP_QDUStructInit(EQEP_QDUInitTypeDef* EQEP_QDUInitStruct) +{ + /*---- Reset the parameter values of the EQEP quadrature decoder structure ----*/ + /* Initialize the EQEP_PosCounterSource member */ + EQEP_QDUInitStruct->PosCounterSource = 0U; + + /* Initialize the EQEP_SyncOutput member */ + EQEP_QDUInitStruct->SyncOutput = DISABLE; + + /* Initialize the EQEP_SyncOutputPin member */ + EQEP_QDUInitStruct->SyncOutputPin = 0U; + + /* Initialize the EQEP_ExternalClockRate member */ + EQEP_QDUInitStruct->ExternalClockRate = 0U; + + /* Initialize the EQEP_ClockDirSwap member */ + EQEP_QDUInitStruct->ClockDirSwap = DISABLE; + + /* Initialize the EQEP_IndexGate member */ + EQEP_QDUInitStruct->IndexGate = DISABLE; + + /* Initialize the EQEP_QEPAPolarity member */ + EQEP_QDUInitStruct->QEPAPolarity = 0U; + + /* Initialize the EQEP_QEPBPolarity member */ + EQEP_QDUInitStruct->QEPBPolarity = 0U; + + /* Initialize the EQEP_QEPIPolarity member */ + EQEP_QDUInitStruct->QEPIPolarity = 0U; + + /* Initialize the EQEP_QEPSPolarity member */ + EQEP_QDUInitStruct->QEPSPolarity = 0U; + +} + + +/** + * @brief Fills each EQEP_CAPStructInit member with its default value. + * @param EQEP_CAPInitStruct pointer to a EQEP_CAPInitTypeDef structure + * which will be initialized. + * @retval None + */ +void EQEP_CAPStructInit(EQEP_CAPInitTypeDef* EQEP_CAPInitStruct) +{ + /*---- Reset the parameter values of the EQEP capture structure ----*/ + /* Initialize the EQEP_CaptureClockPrescaler member */ + EQEP_CAPInitStruct->CaptureClockPrescaler = 0U; + + /* Initialize the EQEP_UnitPosEventPrescaler member */ + EQEP_CAPInitStruct->UnitPosEventPrescaler = 0U; + + /* Initialize the EQEP_CapturePeriodValue member */ + EQEP_CAPInitStruct->CapturePeriodValue = 0U; + +} + + +/** + * @brief Fills each EQEP_POSCMPStructInit member with its default value. + * @param EQEP_PosCmpInitStruct pointer to a EQEP_PosCmpInitTypeDef structure + * which will be initialized. + * @retval None + */ +void EQEP_POSCMPStructInit(EQEP_PosCmpInitTypeDef* EQEP_PosCmpInitStruct) +{ + /*---- Reset the parameter values of the EQEP position compare structure ----*/ + /* Initialize the EQEP_PosCompareShadow member */ + EQEP_PosCmpInitStruct->PosCompareShadow = DISABLE; + + /* Initialize the EQEP_PosCompareShadowLoad member */ + EQEP_PosCmpInitStruct->PosCompareShadowLoad = 0U; + + /* Initialize the EQEP_SyncOutPolarity member */ + EQEP_PosCmpInitStruct->SyncOutPolarity = 0U; + + /* Initialize the EQEP_PosCompare member */ + EQEP_PosCmpInitStruct->PosCompare = DISABLE; + + /* Initialize the EQEP_SyncOutPulseWidth member */ + EQEP_PosCmpInitStruct->SyncOutPulseWidth = 0U; + +} + + + + + +/** + * @brief DeInitialize the EQEP peripheral. + * @retval None + */ +void EQEP_DeInit() +{ + /* Enable EQEP reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2PeriphRst_EQEP, ENABLE); + + /* Release EQEP from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2PeriphRst_EQEP, DISABLE); + +} + + +/** + * @brief Enables or disables the following EQEP counters. + * @arg Position counter(QPOSCNT) + * @arg Unit timer(QUTMR) + * @arg Watch dog timer(QWDTMR) + * @arg Capture timer(QCTMR) + * @note While resetting the position counter, the internal operating + * flags and read-only registers will also be reset. However, + * the control and configuration registers are not disturbed + * by the software reset. + * @note When QEPCTL.OPEN is disabled, some flags in the QFLG register + * do not get reset or cleared and show the actual state of that flag. + * @param EQEP_SUBMDU_TYPE The data registers of the EQEP. + * This parameter can be one of the following values: + * @arg EQEP_POS_CNT : EQEP position counter. + * @arg EQEP_UNIT_TMR: EQEP unit timer. + * @arg EQEP_WTD_TMR : EQEP watch dog timer. + * @arg EQEP_CAP_TMR : EQEP capture timer. + * @param NewState New state of the EQEP position counter. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void EQEP_Cmd(uint16_t EQEP_SUBMDU_TYPE, FunctionalState NewState) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_EQEP_SUBMDU_TYPE(EQEP_SUBMDU_TYPE)); + + if ((EQEP_SUBMDU_TYPE & EQEP_POS_CNT) != 0U) + { + /* Enable the EQEP position counter, QPOSCNT free-running */ + tmpreg |= (uint32_t)EQEP_QEPCTL_QPEN; + } + if ((EQEP_SUBMDU_TYPE & EQEP_UNIT_TMR) != 0U) + { + /* Enable the EQEP unit timer, QUTMR free-running */ + tmpreg |= (uint32_t)EQEP_QEPCTL_UTE; + } + if ((EQEP_SUBMDU_TYPE & EQEP_WTD_TMR) != 0U) + { + /* Enable the EQEP watch dog timer, QWDTMR free-running */ + tmpreg |= (uint32_t)EQEP_QEPCTL_WDE; + } + if ((EQEP_SUBMDU_TYPE & EQEP_CAP_TMR) != 0U) + { + if (NewState != DISABLE) + { + /* Enable the EQEP capture timer, QCTMR free-running */ + EQEP->QCAPCTL |= (uint32_t)EQEP_QCAPCTL_CEN; + } + else + { + /* Disable the EQEP capture timer, QCTMR reset */ + EQEP->QCAPCTL &= (uint32_t)~EQEP_QCAPCTL_CEN; + } + } + + if (NewState != DISABLE) + { + /* Write to QEPCTL */ + EQEP->QEPCTL |= tmpreg; + } + else + { + /* Write to QEPCTL */ + EQEP->QEPCTL &= ~tmpreg; + } +} + +//void EQEP_Cmd(uint8_t EQEP_SUBMDU_TYPE, FunctionalState NewState) +//{ +// uint32_t tmpreg = 0; +// /* Check the parameters */ +// assert_param(IS_FUNCTIONAL_STATE(NewState)); +// assert_param(IS_EQEP_SUBMDU_TYPE(EQEP_SUBMDU_TYPE)); +// +// if(NewState != DISABLE) +// { +// if((EQEP_SUBMDU_TYPE & EQEP_QPOSCNT) != 0U) +// { +// /* Enable the EQEP position counter, QPOSCNT free-running */ +// tmpreg |= (uint32_t)EQEP_QEPCTL_QPEN; +// } +// if((EQEP_SUBMDU_TYPE & EQEP_QUTMR) != 0U) +// { +// /* Enable the EQEP unit timer, QUTMR free-running */ +// tmpreg |= (uint32_t)EQEP_QEPCTL_UTE; +// } +// if((EQEP_SUBMDU_TYPE & EQEP_QWDTMR) != 0U) +// { +// /* Enable the EQEP watch dog timer, QWDTMR free-running */ +// tmpreg |= (uint32_t)EQEP_QEPCTL_WDE; +// } +// if((EQEP_SUBMDU_TYPE & EQEP_QCTMR) != 0U) +// { +// /* Enable the EQEP capture timer, QCTMR free-running */ +// EQEP->QCAPCTL |= (uint32_t)EQEP_QCAPCTL_CEN; +// } +// +// /* Write to QEPCTL */ +// EQEP->QEPCTL |= tmpreg; +// } +// else +// { +// tmpreg = EQEP->QEPCTL; +// +// if((EQEP_SUBMDU_TYPE & EQEP_QPOSCNT) != 0U) +// { +// /* Disable the EQEP position counter, QPOSCNT reset */ +// tmpreg &= (uint32_t)~EQEP_QEPCTL_QPEN; +// } +// if((EQEP_SUBMDU_TYPE & EQEP_QUTMR) != 0U) +// { +// /* Disable the EQEP unit timer, QUTMR reset */ +// tmpreg &= (uint32_t)~EQEP_QEPCTL_UTE; +// } +// if((EQEP_SUBMDU_TYPE & EQEP_QWDTMR) != 0U) +// { +// /* Disable the EQEP watch dog timer, QWDTMR reset */ +// tmpreg &= (uint32_t)~EQEP_QEPCTL_WDE; +// } +// if((EQEP_SUBMDU_TYPE & EQEP_QCTMR) != 0U) +// { +// /* Disable the EQEP capture timer, QCTMR reset */ +// EQEP->QCAPCTL &= (uint32_t)~EQEP_QCAPCTL_CEN; +// } +// +// /* Write to QEPCTL */ +// EQEP->QEPCTL = tmpreg; +// } +//} + + +/** + * @brief Software initialization position counter. + * @note The SWI bit will not be automatically cleared. It is + * necessary to use this function again and pass the DISABLE + * parameter to clear this bit. + * @param NewState New state of the QEPCTL.SWI. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void EQEP_SoftwareInitPositionCounter(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the QEPCTL.SWI, initialize the position counter */ + EQEP->QEPCTL |= (uint32_t)EQEP_QEPCTL_SWI; + } + else + { + /* Disable the EQEP unit timer, QUTMR reset */ + EQEP->QEPCTL &= (uint32_t)~EQEP_QEPCTL_SWI; + } +} + + + + + +/** + * @brief Write a value to the specified EQEP register. + * @param EQEP_REG_TYPE The data registers of the EQEP. + * This parameter can be one of the following values: + * @arg EQEP_QPOSCNT : EQEP position counter register. + * @arg EQEP_QPOSINIT : EQEP position counter initialization register. + * @arg EQEP_QPOSMAX : EQEP position counter maximum register. + * @arg EQEP_QPOSCMP : EQEP position counter compare register. + * @arg EQEP_QUTMR : EQEP unit timer. + * @arg EQEP_QUPRD : EQEP unit timer period register. + * @arg EQEP_QWDTMR : EQEP watch dog timer. + * @arg EQEP_QWDPRD : EQEP watch dog timer period register. + * @arg EQEP_QCTMR : EQEP capture timer. + * @arg EQEP_QCPRD : EQEP capture timer period register. + * @param Value The values of the specified EQEP registers. + * @retval None + */ +void EQEP_WriteDataRegister(uint16_t EQEP_REG_TYPE, uint32_t Value) +{ + /* Check the parameters */ + assert_param(IS_EQEP_REG_TYPE(EQEP_REG_TYPE)); + + if (EQEP_REG_TYPE == EQEP_QPOSCNT) + { + /* Write the value to QPOSCNT */ + EQEP->QPOSCNT = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QPOSINIT) + { + /* Write the value to QPOSINIT */ + EQEP->QPOSINIT = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QPOSMAX) + { + /* Write the value to QPOSMAX */ + EQEP->QPOSMAX = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QPOSCMP) + { + /* Write the value to QPOSCMP */ + EQEP->QPOSCMP = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QUTMR) + { + /* Write the value to QUTMR */ + EQEP->QUTMR = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QUPRD) + { + /* Write the value to QUPRD */ + EQEP->QUPRD = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QWDTMR) + { + /* Write the value to QWDTMR */ + EQEP->QWDTMR = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QWDPRD) + { + /* Write the value to QWDPRD */ + EQEP->QWDPRD = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QCTMR) + { + /* Write the value to QCTMR */ + EQEP->QCTMR = ((uint32_t)Value); + } + if (EQEP_REG_TYPE == EQEP_QCPRD) + { + /* Write the value to QCPRD */ + EQEP->QCPRD = ((uint32_t)Value); + } +} + + +/** + * @brief Returns the value of the specified EQEP registers. + * @param EQEP_REG_TYPE The data registers of the EQEP. + * This parameter can be one of the following values: + * @arg EQEP_QPOSCNT : EQEP position counter register. + * @arg EQEP_QPOSINIT : EQEP position counter initialization register. + * @arg EQEP_QPOSMAX : EQEP position counter maximum register. + * @arg EQEP_QPOSCMP : EQEP position counter compare register. + * @arg EQEP_QPOSILAT : EQEP index position latch register. + * @arg EQEP_QPOSSLAT : EQEP strobe position latch register. + * @arg EQEP_QPOSLAT : EQEP position latch register. + * @arg EQEP_QUTMR : EQEP unit timer. + * @arg EQEP_QUPRD : EQEP unit timer period register. + * @arg EQEP_QWDTMR : EQEP watch dog timer. + * @arg EQEP_QWDPRD : EQEP watch dog timer period register. + * @arg EQEP_QCTMR : EQEP capture timer. + * @arg EQEP_QCPRD : EQEP capture timer period register. + * @arg EQEP_QCTMRLAT : EQEP capture timer latch register. + * @arg EQEP_QCPRDLAT : EQEP capture timer period latch register. + * @retval The value of the specified EQEP registers. + */ +uint32_t EQEP_GetDataRegister(uint16_t EQEP_REG_TYPE) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_EQEP_REG_TYPE(EQEP_REG_TYPE)); + + + if (EQEP_REG_TYPE == EQEP_QPOSCNT) + { + /* Get the value of QPOSCNT */ + tmpreg = ((uint32_t)(EQEP->QPOSCNT)); + } + if (EQEP_REG_TYPE == EQEP_QPOSINIT) + { + /* Get the value of QPOSINIT */ + tmpreg = ((uint32_t)(EQEP->QPOSINIT)); + } + if (EQEP_REG_TYPE == EQEP_QPOSMAX) + { + /* Get the value of QPOSMAX */ + tmpreg = ((uint32_t)(EQEP->QPOSMAX)); + } + if (EQEP_REG_TYPE == EQEP_QPOSCMP) + { + /* Get the value of QPOSCMP */ + tmpreg = ((uint32_t)(EQEP->QPOSCMP)); + } + if (EQEP_REG_TYPE == EQEP_QPOSILAT) + { + /* Get the value of */ + tmpreg = ((uint32_t)(EQEP->QPOSILAT)); + } + if (EQEP_REG_TYPE == EQEP_QPOSSLAT) + { + /* Get the value of */ + tmpreg = ((uint32_t)(EQEP->QPOSSLAT)); + } + if (EQEP_REG_TYPE == EQEP_QPOSLAT) + { + /* Get the value of */ + tmpreg = ((uint32_t)(EQEP->QPOSLAT)); + } + if (EQEP_REG_TYPE == EQEP_QUTMR) + { + /* Get the value of QUTMR */ + tmpreg = ((uint32_t)(EQEP->QUTMR)); + } + if (EQEP_REG_TYPE == EQEP_QUPRD) + { + /* Get the value of QUPRD */ + tmpreg = ((uint32_t)(EQEP->QUPRD)); + } + if (EQEP_REG_TYPE == EQEP_QWDTMR) + { + /* Get the value of QWDTMR */ + tmpreg = ((uint32_t)(EQEP->QWDTMR)); + } + if (EQEP_REG_TYPE == EQEP_QWDPRD) + { + /* Get the value of QWDPRD */ + tmpreg = ((uint32_t)(EQEP->QWDPRD)); + } + if (EQEP_REG_TYPE == EQEP_QCTMR) + { + /* Get the value of QCTMR */ + tmpreg = ((uint32_t)(EQEP->QCTMR)); + } + if (EQEP_REG_TYPE == EQEP_QCPRD) + { + /* Get the value of QCPRD */ + tmpreg = ((uint32_t)(EQEP->QCPRD)); + } + if (EQEP_REG_TYPE == EQEP_QCTMRLAT) + { + /* Get the value of QCTMRLAT */ + tmpreg = ((uint32_t)(EQEP->QCTMRLAT)); + } + if (EQEP_REG_TYPE == EQEP_QCPRDLAT) + { + /* Get the value of QCPRDLAT */ + tmpreg = ((uint32_t)(EQEP->QCPRDLAT)); + } + + /* Return the value of data register */ + return tmpreg; +} + + +/** + * @brief Enable the specified EQEP interrupts. + * @param EQEP_IT specifies the EQEP interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg EQEP_IT_PCE Position counter error interrupt + * @arg EQEP_IT_PHE Quadrature phase error interrupt + * @arg EQEP_IT_QDC Quadrature direction change interrupt + * @arg EQEP_IT_WTO Watchdog time out interrupt + * @arg EQEP_IT_PCU Position counter underflow interrupt + * @arg EQEP_IT_PCO Position counter overflow interrupt + * @arg EQEP_IT_PCR Position compare ready interrupt + * @arg EQEP_IT_PCM Position compare match interrupt + * @arg EQEP_IT_SEL Strobe event latch interrupt + * @arg EQEP_IT_IEL Index event latch interrupt + * @arg EQEP_IT_UTO Unit time out interrupt + * @param NewState new state of the specified EQEP interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void EQEP_ITConfig(uint16_t EQEP_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_EQEP_IT(EQEP_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + + if (NewState != DISABLE) + { + /* Enable the selected EQEP interrupts */ + EQEP->QEINT |= EQEP_IT; + } + else + { + /* Disable the selected EQEP interrupts */ + EQEP->QEINT &= ~EQEP_IT; + } +} + + +/** + * @brief Clears the EQEP interrupt flags. + * @param EQEP_FLAG specifies the EQEP interrupt flag to clear. + * This parameter can be one of the following values: + * @arg EQEP_FLAG_INT EQEP global interrupt flag + * @arg EQEP_FLAG_PCE Position counter error interrupt flag + * @arg EQEP_FLAG_PHE Quadrature phase error interrupt flag + * @arg EQEP_FLAG_QDC Quadrature direction change interrupt flag + * @arg EQEP_FLAG_WTO Watchdog time out interrupt flag + * @arg EQEP_FLAG_PCU Position counter underflow interrupt flag + * @arg EQEP_FLAG_PCO Position counter overflow interrupt flag + * @arg EQEP_FLAG_PCR Position compare ready interrupt flag + * @arg EQEP_FLAG_PCM Position compare match interrupt flag + * @arg EQEP_FLAG_SEL Strobe event latch interrupt flag + * @arg EQEP_FLAG_IEL Index event latch interrupt flag + * @arg EQEP_FLAG_UTO Unit time out interrupt flag + * @retval None + */ +void EQEP_ClearFlag(uint16_t EQEP_FLAG) +{ + /* Check the parameters */ + assert_param(IS_EQEP_FLAG(EQEP_FLAG)); + + /* Clear the selected EQEP flags */ + EQEP->QCLR = EQEP_FLAG; +} + + +/** + * @brief Force the specified EQEP interrupt. + * @param EQEP_IT specifies the EQEP interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg EQEP_IT_PCE Position counter error interrupt + * @arg EQEP_IT_PHE Quadrature phase error interrupt + * @arg EQEP_IT_QDC Quadrature direction change interrupt + * @arg EQEP_IT_WTO Watchdog time out interrupt + * @arg EQEP_IT_PCU Position counter underflow interrupt + * @arg EQEP_IT_PCO Position counter overflow interrupt + * @arg EQEP_IT_PCR Position compare ready interrupt + * @arg EQEP_IT_PCM Position compare match interrupt + * @arg EQEP_IT_SEL Strobe event latch interrupt + * @arg EQEP_IT_IEL Index event latch interrupt + * @arg EQEP_IT_UTO Unit time out interrupt + * @retval None + */ +void EQEP_ITForce(uint16_t EQEP_IT) +{ + /* Check the parameters */ + assert_param(IS_EQEP_IT(EQEP_IT)); + + /* Force the selected EQEP interrupt */ + EQEP->QFRC = EQEP_IT; +} + + +/** + * @brief Checks whether the specified EQEP interrupt has occurred or not. + * @param EQEP_IT specifies the EQEP interrupt sources to check. + * This parameter can be any combination of the following values: + * @arg EQEP_IT_PCE Position counter error interrupt + * @arg EQEP_IT_PHE Quadrature phase error interrupt + * @arg EQEP_IT_QDC Quadrature direction change interrupt + * @arg EQEP_IT_WTO Watchdog time out interrupt + * @arg EQEP_IT_PCU Position counter underflow interrupt + * @arg EQEP_IT_PCO Position counter overflow interrupt + * @arg EQEP_IT_PCR Position compare ready interrupt + * @arg EQEP_IT_PCM Position compare match interrupt + * @arg EQEP_IT_SEL Strobe event latch interrupt + * @arg EQEP_IT_IEL Index event latch interrupt + * @arg EQEP_IT_UTO Unit time out interrupt + * @retval The new state of EQEP_IT (SET or RESET). + */ +ITStatus EQEP_GetITStatus(uint16_t EQEP_IT) +{ + /* Check the parameters */ + assert_param(IS_EQEP_IT(EQEP_IT)); + + + ITStatus bitstatus = RESET; + + /* Check the status of the specified EQEP interrupt */ + if ((uint32_t)(EQEP->QEINT & EQEP_IT) != (uint32_t)RESET) + { + /* EQEP_IT is set */ + bitstatus = SET; + } + else + { + /* EQEP_IT is reset */ + bitstatus = RESET; + } + /* Return the EQEP_IT status */ + return bitstatus; + +} + + +/** + * @brief Checks whether the specified EQEP flag has occurred or not. + * @param EQEP_FLAG specifies the EQEP flag to check. + * This parameter can be any combination of the following values: + * @arg EQEP_FLAG_INT EQEP global interrupt flag + * @arg EQEP_FLAG_PCE Position counter error interrupt flag + * @arg EQEP_FLAG_PHE Quadrature phase error interrupt flag + * @arg EQEP_FLAG_QDC Quadrature direction change interrupt flag + * @arg EQEP_FLAG_WTO Watchdog time out interrupt flag + * @arg EQEP_FLAG_PCU Position counter underflow interrupt flag + * @arg EQEP_FLAG_PCO Position counter overflow interrupt flag + * @arg EQEP_FLAG_PCR Position compare ready interrupt flag + * @arg EQEP_FLAG_PCM Position compare match interrupt flag + * @arg EQEP_FLAG_SEL Strobe event latch interrupt flag + * @arg EQEP_FLAG_IEL Index event latch interrupt flag + * @arg EQEP_FLAG_UTO Unit time out interrupt flag + * @retval The new state of EQEP_FLAG (SET or RESET). + */ +FlagStatus EQEP_GetFlagStatus(uint16_t EQEP_FLAG) +{ + /* Check the parameters */ + assert_param(IS_EQEP_FLAG(EQEP_FLAG)); + + + FlagStatus bitstatus = RESET; + + /* Check the status of the specified EQEP flag */ + if ((uint32_t)(EQEP->QFLG & EQEP_FLAG) != (uint32_t)RESET) + { + /* EQEP_FLAG is set */ + bitstatus = SET; + } + else + { + /* EQEP_FLAG is reset */ + bitstatus = RESET; + } + /* Return the EQEP_FLAG status */ + return bitstatus; + +} + + +/** + * @brief Checks whether the specified EQEP status has occurred or not. + * @param EQEP_STATUS specifies the EQEP status sources to check. + * This parameter can be any combination of the following values: + * @arg EQEP_STATUS_UPEVNT Unit position event flag + * @arg EQEP_STATUS_FIDF Direction on the first index marker + * @arg EQEP_STATUS_QDF Quadrature direction flag + * @arg EQEP_STATUS_QDLF EQEP direction latch flag + * @arg EQEP_STATUS_COEF Capture overflow error flag + * @arg EQEP_STATUS_CDEF Capture direction error flag + * @arg EQEP_STATUS_FIMF First index marker flag + * @arg EQEP_STATUS_PCEF Position counter error flag + * @retval The new state of EQEP_STATUS (SET or RESET). + */ +FlagStatus EQEP_GetStatus(uint8_t EQEP_STATUS) +{ + /* Check the parameters */ + assert_param(IS_EQEP_STATUS(EQEP_STATUS)); + + + FlagStatus bitstatus = RESET; + + /* Check the status of the specified EQEP status */ + if ((uint32_t)(EQEP->QEPSTS & EQEP_STATUS) != (uint32_t)RESET) + { + /* EQEP_STATUS is set */ + bitstatus = SET; + } + else + { + /* EQEP_STATUS is reset */ + bitstatus = RESET; + } + /* Return the EQEP_STATUS status */ + return bitstatus; + +} + + + + + + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_eth.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_eth.c new file mode 100644 index 00000000000..0bd060e638e --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_eth.c @@ -0,0 +1,2841 @@ +/** + ************************************************************************** + * @file ft32f4xx_eth.c + * @author xcao + * @brief heth module driver + * This file provides firmware functions to manage the following + * functionalities of the Ethernet (heth) peripheral: + * + Initialization and deinitialization functions + * + IO operation :functions + * + Peripheral Control funtions + * + Peripheral State and Errors functions + * + ************************************************************************** + * @attention + * + ************************************************************************** + @verbatim + ========================================================================== + #### How to use this driver + ========================================================================== + [..] + The heth driver can be used as follows: + + (#)Declare a ETH_HandleTypeDef handle structure, for example: + ETH_HandleTypeDef heth; + + (#)Fill parameter of Init structure in heth handle + + (#)Call ETH_Init() API to initialize the Ethernet peripheral (MAC,DMA ...) + + (#)Initialize the heth low level resources through the ETH_MspInit() API: + (##) Enable the Ethernet interface clock using + (+++) RCC_ETHMAC_CLK_ENABLE() + (+++) RCC_ETHTX_CLK_ENABLE() + (+++) RCC_ETHRX_CLK_ENABLE() + + (##) Initialize the related GPIO clocks + (##) Configure Ethernet pinout + (##) Configure Ethernet NVIC interrupt (in Interrupt mode) + + (#) Ethernet data reception is asynchronous, so call the following API + to start the listening mode: + (##) ETH_Start(): + This API starts the MAC and DMA transmission and reception process, + without enabling end of transfer interrupts, in this mode user + has to poll for data reception by calling ETH_ReadData() + (##) ETH_Start_IT(): + This API starts the MAC and DMA transmission and reception process, + end of transfer interrupts are enabled in this mode, + ETH_RxCpltCallback() will be executed when an Ethernet packet is received + + (#) When data is received user can call the following API to get received data: + (##) ETH_ReadData(): Read a received packet + + (#) For transmission path, two APIs are available: + (##) ETH_Transmit(): Transmit an heth frame in blocking mode + (##) ETH_Transmit_IT(): Transmit an heth frame in interrupt mode, + ETH_TxCpltCallback() will be executed when end of transfer occur + + (#) Communication with an external PHY device: + (##) ETH_ReadPHYRegister(): Read a register from an external PHY + (##) ETH_WritePHYRegister(): Write data to an external RHY register + + (#) Configure the Ethernet MAC after heth peripheral initialization + (##) ETH_GetMACConfig(): Get MAC actual configuration into ETH_MACConfigTypeDef + (##) ETH_SetMACConfig(): Set MAC configuration based on ETH_MACConfigTypeDef + + (#) Configure the Ethernet DMA after heth peripheral initialization + (##) ETH_GetDMAConfig(): Get DMA actual configuration into ETH_DMAConfigTypeDef + (##) ETH_SetDMAConfig(): Set DMA configuration based on ETH_DMAConfigTypeDef + + (#) Configure the Ethernet PTP after heth peripheral initialization + (##) Define ETH_USE_PTP to use PTP APIs. + (##) ETH_PTP_GetConfig(): Get PTP actual configuration into ETH_PTP_ConfigTypeDef + (##) ETH_PTP_SetConfig(): Set PTP configuration based on ETH_PTP_ConfigTypeDef + (##) ETH_PTP_GetTime(): Get Seconds and Nanoseconds for the Ethernet PTP registers + (##) ETH_PTP_SetTime(): Set Seconds and Nanoseconds for the Ethernet PTP registers + (##) ETH_PTP_AddTimeOffset(): Add Seconds and Nanoseconds offset for the Ethernet PTP registers + (##) ETH_PTP_InsertTxTimestamp(): Insert Timestamp in transmission + (##) ETH_PTP_GetTxTimestamp(): Get transmission timestamp + (##) ETH_PTP_GetRxTimestamp(): Get reception timestamp + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_eth.h" +#include "ft32f4xx_misc.h" + +//#if defined(eth) + +/** @defgroup eth eth + * @brief eth module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @addtogroup ETH_Private_Constants heth Private Constants + * @{ + */ +#define ETH_MAC_CFG_MASK 0x0FFBFF7FU +#define ETH_MAC_EXTDCFG_MASK 0x3F073FFFU +#define ETH_MAC_PKTFILT_MASK 0x800107FFU +#define ETH_MAC_WTDTO_MASK 0x0000010FU +#define ETH_MAC_TXFLCTL_MASK 0xFFFF00F3U +#define ETH_MAC_RXFLCTL_MASK 0x00000003U +#define ETH_MTL_TXQOPMODE_MASK 0x00000073U +#define ETH_MTL_RXQOPMODE_MASK 0x0000007BU + +#define ETH_DMA_OPMODE_MASK 0x00037A03U +#define ETH_DMA_SYSBUSMODE_MASK 0x0000D001U +#define ETH_DMA_CTL_MASK 0x001D0000U +#define ETH_DMA_TXCTL_MASK 0x007F0011U +#define ETH_DMA_RXCTL_MASK 0x807F7FFFU +#define ETH_MAC_PMTCTLSTU_MASK (ETH_MAC_PMTCTLSTU_PWRDWN | ETH_MAC_PMTCTLSTU_RWKPKTEN | \ + ETH_MAC_PMTCTLSTU_MGKPKTEN | ETH_MAC_PMTCTLSTU_GLBLUCAST | \ + ETH_MAC_PMTCTLSTU_RWKPFE) + +/* Timeout values */ +#define ETH_DMARXNDESCWBF_ERRORS_MASK ((uint32_t) (ETH_DMARXNDESCWBF_DE | ETH_DMARXNDESCWBF_RE | \ + ETH_DMARXNDESCWBF_OE | ETH_DMARXNDESCWBF_RWT |\ + ETH_DMARXNDESCWBF_GP | ETH_DMARXNDESCWBF_CE)) + +#define ETH_PTP_TSCTL_MASK 0x110FFF3FU +#define ETH_PTP_SYSTMSECUPDT 0xFFFFFFFFU +#define ETH_PTP_SYSTMNSECUPDT 0xFFFFFFFFU +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup ETH_Private_Macros heth Private Macros + * @{ + */ +/* Helper macros for TX descriptor handling */ +#define INCR_TX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_TX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_TX_DESC_CNT);}\ + } while (0) + +/* Helper macros for RX descriptor handling */ +#define INCR_RX_DESC_INDEX(inx, offset) do {\ + (inx) += (offset);\ + if ((inx) >= (uint32_t)ETH_RX_DESC_CNT){\ + (inx) = ((inx) - (uint32_t)ETH_RX_DESC_CNT);}\ + } while (0) + + +//#define CLEAR_REG(REG) ((REG) = (0x0)) + +//#define WRITE_REG(REG,VAL) ((REG) = (VAL)) + +//#define READ_REG(REG) ((REG)) + +//#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup ETH_Private_Functions heth Private Functions + * @{ + */ + + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup ETH_Exported_Functions heth Exported Functions + * @{ + */ + +/** @defgroup ETH_Exported_Functions_Group1 Initialization and deinitialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + deinitialize the heth peripheral: + + (+) User must Implement ETH_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO and NVIC ). + + (+) Call the function ETH_Init() to configure the selected device with + the selected configuration: + (++) MAC address + (++) Media interface (MII or RMII) + (++) Rx DMA Descriptors Tab + (++) Tx DMA Descriptors Tab + (++) Length of Rx Buffers + + (+) Call the function ETH_DeInit() to restore the default configuration + of the selected heth peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the Ethernet peripheral registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval uint32_t + */ +uint32_t ETH_Init(ETH_HandleTypeDef *heth) +{ + uint32_t tickstart; + + if (heth->gState == ETH_STATE_RESET) + { + + heth->gState = ETH_STATE_BUSY; + /* Init the low level hardware : GPIO, CLOCK, NVIC. */ + ETH_MspInit(heth); + } + + /* TODO __RCC_SYSCFG_CLK_ENABLE();*/ + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; + if (heth->Init.MediaInterface == ETH_MII_MODE) + { + SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL; + } + else + { + SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL; + } + + /* Ethernet Software reset */ + /* Set the SWR bit: resets all MAC subsystem internal registers and logic */ + /* After reset all the registers holds their respective reset values */ + heth->Instance->ETH_DMA_OPMODE |= ETH_DMA_OPMODE_SWR; + + /* TODO Get tick */ + tickstart = GetTick();//somi + + /* TODO Wait for software reset */ + while (READ_BIT(heth->Instance->ETH_DMA_OPMODE, ETH_DMA_OPMODE_SWR) > 0U) + { + if (((GetTick() - tickstart) > ETH_SWRESET_TIMEOUT)) + { + heth->ErrorCode = ETH_ERROR_TIMEOUT; + heth->gState = ETH_STATE_ERROR; + return ERROR; + } + } + + /*------------------ MAC, MTL and DMA default Configuration ----------------*/ + ETH_MACDMAConfig(heth); + + /* SET DSL to 64 bit */ + heth->Instance->ETH_DMA_CTL |= ETH_DMA_CTL_DSL_64BIT; + + /* Set Receive Buffers Length (must be a multiple of 4) */ + if ((heth->Init.RxBuffLen % 0x4U) != 0x0U) + { + /* Set Error Code */ + heth->ErrorCode = ETH_ERROR_PARAM; + /* Set State as Error */ + heth->gState = ETH_STATE_ERROR; + /* Return Error */ + return HAL_ERROR; + } + else + { + /* Set Receive Buffers Length (must be a multiple of 4) */ + heth->Instance->ETH_DMA_RXCTL = (((heth->Instance->ETH_DMA_RXCTL) & (~(ETH_DMA_RXCTL_RBSZ))) | ((heth->Init.RxBuffLen) << 1)); + } + + /*------------------ DMA Tx Descriptors Configuration ----------------------*/ + ETH_DMATxDescListInit(heth); + + /*------------------ DMA Rx Descriptors Configuration ----------------------*/ + ETH_DMARxDescListInit(heth); + + /*--------------------- ETHERNET MAC Address Configuration ------------------*/ + /* Set MAC addr bits 32 to 47 */ + heth->Instance->ETH_MAC_ADDRH0 = (((uint32_t)(heth->Init.MACAddr[5]) << 8) | (uint32_t)heth->Init.MACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + heth->Instance->ETH_MAC_ADDRL0 = (((uint32_t)(heth->Init.MACAddr[3]) << 24) | ((uint32_t)(heth->Init.MACAddr[2]) << 16) | + ((uint32_t)(heth->Init.MACAddr[1]) << 8) | (uint32_t)heth->Init.MACAddr[0]); + + /* Disable Rx MMC Interrupts */ + heth->Instance->ETH_MMC_RXIRMSK = (ETH_MMC_RXIRMSK_RXCRCERPIM | ETH_MMC_RXIRMSK_RXALGNERPIM | ETH_MMC_RXIRMSK_RXUCGPIM); + /* Disable Tx MMC Interrupts */ + heth->Instance->ETH_MMC_TXIRMSK = (ETH_MMC_TXIRMSK_TXSCOLGPIM | ETH_MMC_TXIRMSK_TXMCOLGPIM); + + heth->ErrorCode = ETH_ERROR_NONE; + heth->gState = ETH_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the heth peripheral. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval uint32_t + */ +uint32_t ETH_DeInit(ETH_HandleTypeDef *heth) +{ + + /* Set the ETH peripheral state to BUSY */ + heth->gState = ETH_STATE_BUSY; + /* De-Init the low level hardware : GPIO, CLOCK, NVIC. */ + ETH_MspDeInit(heth); + /* Set ETH HAL state to Disabled */ + heth->gState = ETH_STATE_RESET; + + return HAL_OK; +} + +/** + * @brief Initializes the heth MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +//__weak void ETH_MspInit(ETH_HandleTypeDef *heth) +void __attribute__((weak)) ETH_MspInit(ETH_HandleTypeDef *heth) +{ + UNUSED(heth); +} + +/** + * @brief DeInitializes heth MSP. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +//__weak void ETH_MspDeInit(ETH_HandleTypeDef *heth) +void __attribute__((weak)) ETH_MspDeInit(ETH_HandleTypeDef *heth) +{ + UNUSED(heth); +} + +/** @defgroup ETH_Exported_Functions_Group2 IO operation functions + * @brief heth Transmit and Receive functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the heth + data transfer. +@endverbatim + * @{ + */ + +/** + * @brief Enables Ethernet MAC and DMA reception and transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval uint32_t + */ +uint32_t ETH_Start(ETH_HandleTypeDef *heth) +{ + if (heth->gState == ETH_STATE_READY) + { + heth->gState = ETH_STATE_BUSY; + + /* Set number of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the MAC transmission and reception*/ + heth->Instance->ETH_MAC_CFG |= (ETH_MAC_CFG_RE | ETH_MAC_CFG_TE); + + /* Set the Flush Transmit FIFO bit */ + heth->Instance->ETH_MTL_TXQOPMODE |= ETH_MTL_TXQOPMODE_FTQ; + + /* Enable the DMA transmission */ + heth->Instance->ETH_DMA_TXCTL |= ETH_DMA_TXCTL_ST; + + /* Enable the DMA reception */ + heth->Instance->ETH_DMA_RXCTL |= ETH_DMA_RXCTL_SR; + + /* Clear Tx and Rx process stopped flags */ + heth->Instance->ETH_DMA_STU |= (ETH_DMA_STU_RPS | ETH_DMA_STU_TPS); + + heth->gState = ETH_STATE_STARTED; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enables Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval uint32_t + */ +uint32_t ETH_Start_IT(ETH_HandleTypeDef *heth) +{ + if (heth->gState == ETH_STATE_READY) + { + heth->gState = ETH_STATE_BUSY; + + /* save IT mode to heth Handle */ + heth->RxDescList.ItMode = 1U; + + /* Set number of descriptors to build */ + heth->RxDescList.RxBuildDescCnt = ETH_RX_DESC_CNT; + + /* Build all descriptors */ + ETH_UpdateDescriptor(heth); + + /* Enable the DMA transmission */ + heth->Instance->ETH_DMA_TXCTL |= ETH_DMA_TXCTL_ST; + + /* Enable the DMA reception */ + heth->Instance->ETH_DMA_RXCTL |= ETH_DMA_RXCTL_SR; + + /* Clear Tx and Rx process stopped flags */ + heth->Instance->ETH_DMA_STU |= (ETH_DMA_STU_RPS | ETH_DMA_STU_TPS); + + /* Set the Flush Transmit FIFO bit */ + heth->Instance->ETH_MTL_TXQOPMODE |= ETH_MTL_TXQOPMODE_FTQ; + + /* Enable the MAC transmission */ + heth->Instance->ETH_MAC_CFG |= ETH_MAC_CFG_TE; + + /* Enable the MAC reception */ + heth->Instance->ETH_MAC_CFG |= ETH_MAC_CFG_RE; + + /* Enable heth DMA interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + heth->Instance->ETH_DMA_INTRENA |= (ETH_DMA_INTREN_NIE | ETH_DMA_INTREN_RIE | ETH_DMA_INTREN_TIE | + ETH_DMA_INTREN_FBEE | ETH_DMA_INTREN_AIE | ETH_DMA_INTREN_RBUE); + + heth->gState = ETH_STATE_STARTED; + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval uint32_t + */ +uint32_t ETH_Stop(ETH_HandleTypeDef *heth) +{ + if (heth->gState == ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = ETH_STATE_BUSY; + + /* Disable the DMA transmission */ + heth->Instance->ETH_DMA_TXCTL &= (~ETH_DMA_TXCTL_ST); + + /* Disable the DMA reception */ + heth->Instance->ETH_DMA_RXCTL &= (~ETH_DMA_RXCTL_SR); + + /* Disable the MAC reception */ + heth->Instance->ETH_MAC_CFG &= (~ETH_MAC_CFG_RE); + + /* Set the Flush Transmit FIFO bit */ + heth->Instance->ETH_MTL_TXQOPMODE |= ETH_MTL_TXQOPMODE_FTQ; + + /* Disable the MAC transmission */ + heth->Instance->ETH_MAC_CFG &= (~ETH_MAC_CFG_TE); + + heth->gState = ETH_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Stop Ethernet MAC and DMA reception/transmission in Interrupt mode + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval uint32_t + */ +uint32_t ETH_Stop_IT(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t descindex; + + if (heth->gState == ETH_STATE_STARTED) + { + /* Set the ETH peripheral state to BUSY */ + heth->gState = ETH_STATE_BUSY; + + /* Disable interrupts: + - Tx complete interrupt + - Rx complete interrupt + - Fatal bus interrupt + */ + heth->Instance->ETH_DMA_INTRENA &= (~(ETH_DMA_INTREN_NIE | ETH_DMA_INTREN_RIE | ETH_DMA_INTREN_TIE | + ETH_DMA_INTREN_FBEE | ETH_DMA_INTREN_AIE | ETH_DMA_INTREN_RBUE)); + + /* Disable the DMA transmission */ + heth->Instance->ETH_DMA_TXCTL &= (~ETH_DMA_TXCTL_ST); + + /* Disable the DMA reception */ + heth->Instance->ETH_DMA_RXCTL &= (~ETH_DMA_RXCTL_SR); + + /* Disable the MAC reception */ + heth->Instance->ETH_MAC_CFG &= (~ETH_MAC_CFG_RE); + + /* Set the Flush Transmit FIFO bit */ + heth->Instance->ETH_MTL_TXQOPMODE |= ETH_MTL_TXQOPMODE_FTQ; + + /* Disable the MAC reception */ + heth->Instance->ETH_MAC_CFG &= (~ETH_MAC_CFG_RE); + + /* Clear IOC bit to all Rx descriptors */ + for (descindex = 0; descindex < (uint32_t)ETH_RX_DESC_CNT; descindex++) + { + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descindex]; + dmarxdesc->DESC3 &= (~ETH_DMARXNDESCRF_IOC); + } + + heth->RxDescList.ItMode = 0U; + + heth->gState = ETH_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in polling mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @param Timeout: timeout value + * @retval uint32_t + */ +uint32_t ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig, uint32_t Timeout) +{ + uint32_t tickstart; + ETH_DMADescTypeDef *dmatxdesc; + + if (pTxConfig == NULL) + { + heth->ErrorCode |= ETH_ERROR_PARAM; + } + + if (heth->gState == ETH_STATE_STARTED) + { + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 0) != ETH_ERROR_NONE) + { + /* Config DMA Tx descriptor by Tx Packet info */ + heth->ErrorCode |= ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + dmatxdesc = (ETH_DMADescTypeDef *)(&heth->TxDescList)->TxDesc[heth->TxDescList.CurTxDesc]; + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + tickstart = GetTick(); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + heth->Instance->ETH_DMA_TXDESCTAILPTR = ((uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + + + /* Wait for data to be transmitted or timeout occurred */ + while ((dmatxdesc->DESC3 & ETH_DMATXNDESCWBF_OWN) != (uint32_t)0U) + { + if ((heth->Instance->ETH_DMA_STU & ETH_DMA_STU_FBE) != (uint32_t)0U) + { + heth->ErrorCode |= ETH_ERROR_DMA; + heth->DMAErrorCode = heth->Instance->ETH_DMA_STU; + return HAL_ERROR; + } + + + /* Check for the Timeout */ + //if (Timeout != MAX_DELAY) + if (Timeout != 0xFFFFFFFFU) + { + if (((GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + heth->ErrorCode |= ETH_ERROR_TIMEOUT; + /* Clear TX descriptor so that we can proceed */ + dmatxdesc->DESC3 = (ETH_DMATXNDESCWBF_FD | ETH_DMATXNDESCWBF_LD); + } + } + } + /* Return function status */ + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Sends an Ethernet Packet in interrupt mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Hold the configuration of packet to be transmitted + * @retval uint32_t + */ +uint32_t ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfigTypeDef *pTxConfig) +{ + if (pTxConfig == NULL) + { + heth->ErrorCode |= ETH_ERROR_PARAM; + //return ERROR; + return HAL_ERROR; + } + + if (heth->gState == ETH_STATE_STARTED) + { + /* Save the packet pointer to release. */ + heth->TxDescList.CurrentPacketAddress = (uint32_t *)pTxConfig->pData; + + /* Config DMA Tx descriptor by Tx Packet info */ + if (ETH_Prepare_Tx_Descriptors(heth, pTxConfig, 1) != ETH_ERROR_NONE) + { + heth->ErrorCode |= ETH_ERROR_BUSY; + return HAL_ERROR; + } + + /* Ensure completion of descriptor preparation before transmission start */ + __DSB(); + + /* Incr current tx desc index */ + INCR_TX_DESC_INDEX(heth->TxDescList.CurTxDesc, 1U); + + /* Start transmission */ + /* issue a poll command to Tx DMA by writing address of next immediate free descriptor */ + heth->Instance->ETH_DMA_TXDESCTAILPTR = ((uint32_t)(heth->TxDescList.TxDesc[heth->TxDescList.CurTxDesc])); + + return HAL_OK; + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Read a received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pAppBuff: Pointer to an application buffer to receive the packet. + * @retval uint32_t + */ +uint32_t ETH_ReadData(ETH_HandleTypeDef *heth, void **pAppBuff) +{ + uint32_t descidx; + ETH_DMADescTypeDef *dmarxdesc; + uint32_t desccnt = 0U; + uint32_t desccntmax; + uint32_t bufflength; + uint8_t rxdataready = 0U; + + if (pAppBuff == NULL) + { + heth->ErrorCode |= ETH_ERROR_PARAM; + return HAL_ERROR; + } + + if (heth->gState != ETH_STATE_STARTED) + { + return HAL_ERROR; + } + + descidx = heth->RxDescList.RxDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccntmax = ETH_RX_DESC_CNT - heth->RxDescList.RxBuildDescCnt; + + /* Check if descriptor is not owned by DMA */ + while ((((dmarxdesc->DESC3)Ð_DMARXNDESCWBF_OWN) == (uint32_t)(0x0U)) && (desccnt < desccntmax) && (rxdataready == 0U)) + { + if (((dmarxdesc->DESC3)Ð_DMARXNDESCWBF_CTXT) != (uint32_t)(0x0U)) + { + /* Get timestamp high */ + heth->RxDescList.TimeStamp.TimeStampHigh = dmarxdesc->DESC1; + /* Get timestamp low */ + heth->RxDescList.TimeStamp.TimeStampLow = dmarxdesc->DESC0; + } + + if ((((dmarxdesc->DESC3)Ð_DMARXNDESCWBF_FD) != (uint32_t)(0x0U)) || (heth->RxDescList.pRxStart != NULL)) + { + /* Check if first descriptor */ + if (((dmarxdesc->DESC3)Ð_DMARXNDESCWBF_FD) != (uint32_t)(0x0U)) + { + heth->RxDescList.RxDescCnt = 0; + heth->RxDescList.RxDataLength = 0; + } + + /* Get the Frame Length of the received packet: substruct 4 bytes of the CRC */ + bufflength = ((dmarxdesc->DESC3) & ETH_DMARXNDESCWBF_PL) - heth->RxDescList.RxDataLength; + + /* Check if last descriptor */ + if (((dmarxdesc->DESC3)Ð_DMARXNDESCWBF_LD) != (uint32_t)(0x0U)) + { + /* Save Last descriptor index */ + heth->RxDescList.pRxLastRxDesc = dmarxdesc->DESC3; + + /* Packet ready */ + rxdataready = 1; + } + + /* Link data */ + WRITE_REG(dmarxdesc->BackupAddr0, dmarxdesc->DESC0); + /* Link callback */ + ETH_RxLinkCallback(&heth->RxDescList.pRxStart, &heth->RxDescList.pRxEnd, + (uint8_t *)dmarxdesc->BackupAddr0, (uint16_t) bufflength); + + heth->RxDescList.RxDescCnt++; + + heth->RxDescList.RxDataLength += bufflength; + + /* Clear buffer pointer */ + dmarxdesc->BackupAddr0 = 0; + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccnt++; + } + + heth->RxDescList.RxBuildDescCnt += desccnt; + if ((heth->RxDescList.RxBuildDescCnt) != 0U) + { + /* Update Descriptors */ + ETH_UpdateDescriptor(heth); + } + + heth->RxDescList.RxDescIdx = descidx; + + if (rxdataready == 1U) + { + /* Return received packet */ + *pAppBuff = heth->RxDescList.pRxStart; + /* Reset first element */ + heth->RxDescList.pRxStart = NULL; + + return HAL_OK; + } + + return HAL_ERROR; +} + +/** + * @brief This function gives back Rx Desc of the last received Packet + * to the DMA, so heth DMA will be able to use these descriptors + * to receive next Packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval void + */ +static void ETH_UpdateDescriptor(ETH_HandleTypeDef *heth) +{ + uint32_t descidx; + uint32_t tailidx; + uint32_t desccount; + ETH_DMADescTypeDef *dmarxdesc; + uint8_t *buff = NULL; + uint8_t allocStatus = 1U; + + descidx = heth->RxDescList.RxBuildDescIdx; + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount = heth->RxDescList.RxBuildDescCnt; + + while ((desccount > 0U) && (allocStatus != 0U)) + { + /* Check if a buffer's attached the descriptor */ + if ((dmarxdesc->BackupAddr0) == 0U) + { + /*Allocate callback*/ + ETH_RxAllocateCallback(&buff); + if (buff == NULL) + { + allocStatus = 0U; + } + else + { + dmarxdesc->BackupAddr0 = (uint32_t)buff; + dmarxdesc->DESC0 = (uint32_t)buff; + } + } + + if (allocStatus != 0U) + { + if (heth->RxDescList.ItMode != 0U) + { + dmarxdesc->DESC3 |= (ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V | ETH_DMARXNDESCRF_IOC); + } + else + { + dmarxdesc->DESC3 |= (ETH_DMARXNDESCRF_OWN | ETH_DMARXNDESCRF_BUF1V); + } + + /* Increment current rx descriptor index */ + INCR_RX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmarxdesc = (ETH_DMADescTypeDef *)heth->RxDescList.RxDesc[descidx]; + desccount--; + } + } + + if (heth->RxDescList.RxBuildDescCnt != desccount) + { + /* Set the tail pointer index */ + tailidx = (descidx + 1U) % ETH_RX_DESC_CNT; + + /* DMB instruction to avoid race condition */ + __DMB(); + + /* Set the Tail pointer address */ + heth->Instance->ETH_DMA_RXDESCTAILPTR |= ((uint32_t)(heth->Init.RxDesc + (tailidx))); + + heth->RxDescList.RxBuildDescIdx = descidx; + heth->RxDescList.RxBuildDescCnt = desccount; + } +} + +/** + * @brief Register the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxAllocateCallback: pointer to function to alloc buffer + * @retval int + */ +uint32_t ETH_RegisterRxAllocateCallback(ETH_HandleTypeDef *heth, + pETH_rxAllocateCallbackTypeDef rxAllocateCallback) +{ + if (rxAllocateCallback == NULL) + { + /* No buffer to save */ + //return ERROR; + return HAL_ERROR; + } + + /* Set function to allocate buffer */ + heth->rxAllocateCallback = rxAllocateCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx alloc callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval void + */ +void ETH_UnRegisterRxAllocateCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxAllocateCallback = ETH_RxAllocateCallback; +} + +/** + * @brief Rx Allocate callback. + * @param buff: pointer to allocated buffer + * @retval None + */ + +/*The definition belowed need to exit at ft32f4xx_def.h file*/ +/*TODO*/ + + +//__weak void ETH_RxAllocateCallback(uint8_t **buff) +void __attribute__((weak)) ETH_RxAllocateCallback(uint8_t **buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_RxAllocateCallback could be implemented in the user file + */ +} + + +/** + * @brief Rx Link callback. + * @param pStart: pointer to packet start + * @param pEnd: pointer to packet end + * @param buff: pointer to received data + * @param Length: received data length + * @retval None + */ +//__weak void ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +void __attribute__((weak)) ETH_RxLinkCallback(void **pStart, void **pEnd, uint8_t *buff, uint16_t Length) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(pStart); + UNUSED(pEnd); + UNUSED(buff); + UNUSED(Length); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_RxLinkCallback could be implemented in the user file + */ +} + +/** + * @brief Set the Rx link data function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param rxLinkCallback: pointer to function to link data + * @retval int + */ +uint32_t ETH_RegisterRxLinkCallback(ETH_HandleTypeDef *heth, pETH_rxLinkCallbackTypeDef rxLinkCallback) +{ + if (rxLinkCallback == NULL) + { + /* No buffer to save */ + //return ERROR; + return HAL_ERROR; + } + + /* Set function to link data */ + heth->rxLinkCallback = rxLinkCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Rx link callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval void + */ +void ETH_UnRegisterRxLinkCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->rxLinkCallback = ETH_RxLinkCallback; +} + +/** + * @brief Get the error state of the last received packet. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pErrorCode: pointer to uint32_t to hold the error code + * @retval void + */ +void ETH_GetRxDataErrorCode(const ETH_HandleTypeDef *heth, uint32_t *pErrorCode) +{ + /* Get error bits. */ + *pErrorCode = ((heth->RxDescList.pRxLastRxDesc) & ETH_DMARXNDESCWBF_ERRORS_MASK); +} + +/** + * @brief Set the Tx free function. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txFreeCallback: pointer to function to release the packet + * @retval int + */ +uint32_t ETH_RegisterTxFreeCallback(ETH_HandleTypeDef *heth, pETH_txFreeCallbackTypeDef txFreeCallback) +{ + if (txFreeCallback == NULL) + { + /* No buffer to save */ + //return ERROR; + return HAL_ERROR; + } + + /* Set function to free transmmitted packet */ + heth->txFreeCallback = txFreeCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx free callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval void + */ +void ETH_UnRegisterTxFreeCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txFreeCallback = ETH_TxFreeCallback; + + //return OK; +} + +/** + * @brief Tx Free callback. + * @param buff: pointer to buffer to free + * @retval None + */ +//__weak void ETH_TxFreeCallback(uint32_t *buff) +void __attribute__((weak)) ETH_TxFreeCallback(uint32_t *buff) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_TxFreeCallback could be implemented in the user file + */ +} + +/** + * @brief Release transmitted Tx packets. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval void + */ +void ETH_ReleaseTxPacket(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t numOfBuf = dmatxdesclist->BuffersInUse; + uint32_t idx = dmatxdesclist->releaseIndex; + uint8_t pktTxStatus = 1U; + uint8_t pktInUse; +#ifdef ETH_USE_PTP + ETH_TimeStampTypeDef *timestamp = &heth->TxTimestamp; +#endif /* ETH_USE_PTP */ + + /* Loop through buffers in use. */ + while ((numOfBuf != 0U) && (pktTxStatus != 0U)) + { + pktInUse = 1U; + numOfBuf--; + /* If no packet, just examine the next packet. */ + if (dmatxdesclist->PacketAddress[idx] == NULL) + { + /* No packet in use, skip to next. */ + INCR_TX_DESC_INDEX(idx, 1U); + pktInUse = 0U; + } + + if (pktInUse != 0U) + { + /* Determine if the packet has been transmitted. */ + if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCRF_OWN) == 0U) + { +#ifdef ETH_USE_PTP + /* Disable Ptp transmission */ + heth->Init.TxDesc[idx].DESC3 &= (~(0x40000000U)); + + if ((heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_LD) + && (heth->Init.TxDesc[idx].DESC3 & ETH_DMATXNDESCWBF_TTSS)) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->Init.TxDesc[idx].DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->Init.TxDesc[idx].DESC1; + } + else + { + timestamp->TimeStampHigh = timestamp->TimeStampLow = UINT32_MAX; + } + + /* Handle Ptp */ + if (timestamp->TimeStampHigh != UINT32_MAX && timestamp->TimeStampLow != UINT32_MAX) + { + ETH_TxPtpCallback(dmatxdesclist->PacketAddress[idx], timestamp); + } + +#endif /* ETH_USE_PTP */ + + /* Release the packet. */ + ETH_TxFreeCallback(dmatxdesclist->PacketAddress[idx]); + + /* Clear the entry in the in-use array. */ + dmatxdesclist->PacketAddress[idx] = NULL; + + /* Update the transmit relesae index and number of buffers in use. */ + INCR_TX_DESC_INDEX(idx, 1U); + dmatxdesclist->BuffersInUse = numOfBuf; + dmatxdesclist->releaseIndex = idx; + } + else + { + /* Get out of the loop! */ + pktTxStatus = 0U; + } + } + } + //return HAL_OK; +} + +#ifdef ETH_USE_PTP +/** + * @brief Set the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval int + */ +uint32_t ETH_PTP_SetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + uint32_t tmpTSCR; + ETH_TimeTypeDef time; + + if (ptpconfig == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + tmpTSCR = ptpconfig->Timestamp | + ((uint32_t)ptpconfig->TimestampUpdate << ETH_PTP_TSCTL_TSUPDT_Pos) | + ((uint32_t)ptpconfig->TimestampAll << ETH_PTP_TSCTL_TSENALL_Pos) | + ((uint32_t)ptpconfig->TimestampRolloverMode << ETH_PTP_TSCTL_TSCTRLSSR_Pos) | + ((uint32_t)ptpconfig->TimestampV2 << ETH_PTP_TSCTL_TSVER2ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEthernet << ETH_PTP_TSCTL_TSIPENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv6 << ETH_PTP_TSCTL_TSIPV6ENA_Pos) | + ((uint32_t)ptpconfig->TimestampIPv4 << ETH_PTP_TSCTL_TSIPV4ENA_Pos) | + ((uint32_t)ptpconfig->TimestampEvent << ETH_PTP_TSCTL_TSEVNTENA_Pos) | + ((uint32_t)ptpconfig->TimestampMaster << ETH_PTP_TSCTL_TSENMACADDR_Pos) | + ((uint32_t)ptpconfig->TimestampSnapshots << ETH_PTP_TSCTL_SNAPTYPSEL_Pos) | + ((uint32_t)ptpconfig->TimestampFilter << ETH_PTP_TSCTL_TSENMACADDR_Pos) | + ((uint32_t)ptpconfig->TimestampChecksumCorrection << ETH_PTP_TSCTL_CSC_Pos) | + ((uint32_t)ptpconfig->TimestampStatusMode << ETH_PTP_TSCTL_TXTSSISM_Pos); + + /* Write to PTP_TSCTL */ + heth->Instance->ETH_PTP_TSCTL = (((heth->Instance->ETH_PTP_TSCTL) & ((~ETH_PTP_TSCTL_MASK))) | (tmpTSCR)); + + /* Enable Timestamp */ + heth->Instance->ETH_PTP_TSCTL |= ETH_PTP_TSCTL_TSENA; + heth->Instance->ETH_PTP_SUBSECINR = (ptpconfig->TimestampSubsecondInc); + heth->Instance->ETH_PTP_TSADD = ptpconfig->TimestampAddend; + + /* Enable Timestamp */ + if (ptpconfig->TimestampAddendUpdate == ENABLE) + { + heth->Instance->ETH_PTP_TSCTL |= ETH_PTP_TSCTL_TSADDREG; + while (((heth->Instance->ETH_PTP_TSCTL)Ð_PTP_TSCTL_TSADDREG) != 0) + { + + } + } + + /* Ptp Init */ + heth->Instance->ETH_PTP_TSCTL |= ETH_PTP_TSCTL_TSINIT; + + /* Set PTP Configuration done */ + heth->IsPtpConfigured = ETH_PTP_CONFIGURED; + + /* Set Seconds */ + time.Seconds = heth->Instance->ETH_PTP_SYSTMSEC; + + /* Set NanoSeconds */ + time.NanoSeconds = heth->Instance->ETH_PTP_SYSTMNSEC; + + ETH_PTP_SetTime(heth, &time); + + return HAL_OK; +} + +/** + * @brief Get the Ethernet PTP configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ptpconfig: pointer to a ETH_PTP_ConfigTypeDef structure that contains + * the configuration information for PTP + * @retval int + */ + +uint32_t ETH_PTP_GetConfig(ETH_HandleTypeDef *heth, ETH_PTP_ConfigTypeDef *ptpconfig) +{ + if (ptpconfig == NULL) + { + //return ERROR; + return HAL_ERROR; + } + ptpconfig->Timestamp = ((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSENA); + + ptpconfig->TimestampUpdate = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSCFUPDT)\ + >> ETH_PTP_TSCTL_TSCFUPDT_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampAll = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSENALL)\ + >> ETH_PTP_TSCTL_TSENALL_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampRolloverMode = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSCTRLSSR)\ + >> ETH_PTP_TSCTL_TSCTRLSSR_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampV2 = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSVER2ENA)\ + >> ETH_PTP_TSCTL_TSVER2ENA_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampEthernet = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSIPENA)\ + >> ETH_PTP_TSCTL_TSIPENA_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampIPv6 = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSIPV6ENA)\ + >> ETH_PTP_TSCTL_TSIPV6ENA_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampIPv4 = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSIPV4ENA)\ + >> ETH_PTP_TSCTL_TSIPV4ENA_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampEvent = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSEVNTENA)\ + >> ETH_PTP_TSCTL_TSEVNTENA_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampMaster = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSMSTRENA)\ + >> ETH_PTP_TSCTL_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampSnapshots = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSMSTRENA)\ + >> ETH_PTP_TSCTL_TSMSTRENA_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampFilter = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TSENMACADDR)\ + >> ETH_PTP_TSCTL_TSENMACADDR_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampChecksumCorrection = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_CSC)\ + >> ETH_PTP_TSCTL_CSC_Pos) > 0U) ? ENABLE : DISABLE; + + ptpconfig->TimestampStatusMode = ((((heth->Instance->ETH_PTP_TSCTL) & ETH_PTP_TSCTL_TXTSSISM)\ + >> ETH_PTP_TSCTL_TXTSSISM_Pos) > 0U) ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Set Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param time: pointer to a ETH_TimeTypeDef structure that contains + * time to set + * @retval int + */ +uint32_t ETH_PTP_SetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == ETH_PTP_CONFIGURED) + { + /* Set Seconds */ + heth->Instance->ETH_PTP_SYSTMSECUPDT = time->Seconds; + + /* Set NanoSeconds */ + heth->Instance->ETH_PTP_SYSTMNSECUPDT = time->NanoSeconds; + + /* the system time is updated */ + heth->Instance->ETH_PTP_TSCTL = ETH_PTP_TSCTL_TSUPDT; + } + else + { + /* Return function status */ + //return ERROR; + return HAL_ERROR; + } +} + +/** + * @brief Get Seconds and Nanoseconds for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param time: pointer to a ETH_TimeTypeDef structure that contains + * time to get + * @retval int + */ +uint32_t ETH_PTP_GetTime(ETH_HandleTypeDef *heth, ETH_TimeTypeDef *time) +{ + if (heth->IsPtpConfigured == ETH_PTP_CONFIGURED) + { + /* Get Seconds */ + time->Seconds = heth->Instance->ETH_PTP_SYSTMSEC; + /* Get NanoSeconds */ + time->NanoSeconds = heth->Instance->ETH_PTP_SYSTMNSEC; + } + else + { + /* Return function status */ + //return ERROR; + return HAL_ERROR; + } +} + +/** + * @brief Update time for the Ethernet PTP registers. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timeoffset: pointer to a ETH_PtpUpdateTypeDef structure that contains + * the time update information + * @retval int + */ +uint32_t ETH_PTP_AddTimeOffset(ETH_HandleTypeDef *heth, ETH_PtpUpdateTypeDef ptpoffsettype, + ETH_TimeTypeDef *timeoffset) +{ + if (heth->IsPtpConfigured == ETH_PTP_CONFIGURED) + { + if (ptpoffsettype == ETH_PTP_NEGATIVE_UPDATE) + { + /* Set Seconds update */ + heth->Instance->ETH_PTP_SYSTMSECUPDT = ETH_MACSTSUR_VALUE - timeoffset->Seconds + 1U; + + if (((heth->Instance->ETH_PTP_TSCTL)Ð_PTP_TSCTL_TSCTRLSSR) == ETH_PTP_TSCTL_TSCTRLSSR) + { + /* Set nanoSeconds update */ + heth->Instance->ETH_PTP_SYSTMNSECUPDT = ETH_MACSTNUR_VALUE - timeoffset->NanoSeconds; + } + else + { + /* Set nanoSeconds update */ + heth->Instance->ETH_PTP_SYSTMNSECUPDT = ETH_MACSTSUR_VALUE - timeoffset->NanoSeconds + 1U; + } + } + else + { + /* Set Seconds update */ + heth->Instance->ETH_PTP_SYSTMSECUPDT = timeoffset->Seconds; + /* Set nanoSeconds update */ + heth->Instance->ETH_PTP_SYSTMNSECUPDT = timeoffset->NanoSeconds; + } + + heth->Instance->ETH_PTP_TSCTL |= ETH_PTP_TSCTL_TSUPDT; + + return HAL_OK; + } + else + { + /* Return function status */ + //return ERROR; + return HAL_ERROR; + } +} + +/** + * @brief Insert Timestamp in transmission. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval int + */ +uint32_t ETH_PTP_InsertTxTimestamp(ETH_HandleTypeDef *heth) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + if (heth->IsPtpConfigured == ETH_PTP_CONFIGURED) + { + /* Enable Time Stamp transmission */ + dmatxdesc->DESC2 |= ETH_DMATXNDESCRF_TTSE; + + return HAL_OK; + } + else + { + /* Return function status */ + // return ERROR; + return HAL_ERROR; + } +} + +/** + * @brief Get transmission timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * transmission timestamp + * @retval int + */ +uint32_t ETH_PTP_GetTxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t idx = dmatxdesclist->releaseIndex; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[idx]; + + if (heth->IsPtpConfigured == ETH_PTP_CONFIGURED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = dmatxdesc->DESC0; + /* Get timestamp high */ + timestamp->TimeStampHigh = dmatxdesc->DESC1; + + return HAL_OK; + } + else + { + /* Return function status */ + //return ERROR; + return HAL_ERROR; + } +} + +/** + * @brief Get receive timestamp. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param timestamp: pointer to ETH_TIMESTAMPTypeDef structure that contains + * receive timestamp + * @retval int + */ +uint32_t ETH_PTP_GetRxTimestamp(ETH_HandleTypeDef *heth, ETH_TimeStampTypeDef *timestamp) +{ + if (heth->IsPtpConfigured == ETH_PTP_CONFIGURED) + { + /* Get timestamp low */ + timestamp->TimeStampLow = heth->RxDescList.TimeStamp.TimeStampLow; + /* Get timestamp high */ + timestamp->TimeStampHigh = heth->RxDescList.TimeStamp.TimeStampHigh; + + return HAL_OK; + } + else + { + /* Return function status */ + //return ERROR; + return HAL_ERROR; + } +} + +/** + * @brief Register the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param txPtpCallback: Function to handle Ptp transmission + * @retval int + */ +uint32_t ETH_RegisterTxPtpCallback(ETH_HandleTypeDef *heth, pETH_txPtpCallbackTypeDef txPtpCallback) +{ + if (txPtpCallback == NULL) + { + /* No buffer to save */ + //return ERROR; + return HAL_ERROR; + } + /* Set Function to handle Tx Ptp */ + heth->txPtpCallback = txPtpCallback; + + return HAL_OK; +} + +/** + * @brief Unregister the Tx Ptp callback. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval int + */ +uint32_t ETH_UnRegisterTxPtpCallback(ETH_HandleTypeDef *heth) +{ + /* Set function to allocate buffer */ + heth->txPtpCallback = ETH_TxPtpCallback; + + //return OK; + return HAL_OK; +} + +/** + * @brief Tx Ptp callback. + * @param buff: pointer to application buffer + * @param timestamp: pointer to ETH_TimeStampTypeDef structure that contains + * transmission timestamp + * @retval None + */ +//__weak void ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +void __attribute__((weak)) ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(buff); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_TxPtpCallback could be implemented in the user file + */ +} +#endif /* ETH_USE_PTP */ + +/** + * @brief This function handles heth interrupt request. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval void + */ +void ETH_IRQHandler(ETH_HandleTypeDef *heth) +{ + uint32_t mac_flag = (heth->Instance->ETH_MAC_IRSTU); + uint32_t dma_flag = (heth->Instance->ETH_DMA_STU); + uint32_t dma_itsource = (heth->Instance->ETH_DMA_INTRENA); + uint32_t exti_flag = (EXTI->PR); + + /* Packet received */ + if (((dma_flag & ETH_DMA_STU_RI) != 0U) && ((dma_itsource & ETH_DMA_INTREN_RIE) != 0U)) + { + /* Clear the heth DMA Rx IT pending bits */ + heth->Instance->ETH_DMA_STU = (ETH_DMA_STU_RI | ETH_DMA_STU_NIS); + /* Receive complete callback */ + ETH_RxCpltCallback(heth); + } + + /* Packet transmitted */ + if (((dma_flag & ETH_DMA_STU_TI) != 0U) && ((dma_itsource & ETH_DMA_INTREN_TIE) != 0U)) + { + /* Clear the heth DMA Tx IT pending bits */ + heth->Instance->ETH_DMA_STU = (ETH_DMA_STU_TI | ETH_DMA_STU_NIS); + + ETH_TxCpltCallback(heth); + } + + /* heth DMA Error */ + if (((dma_flag & ETH_DMA_STU_AIS) != 0U) && ((dma_itsource & ETH_DMA_INTREN_AIE) != 0U)) + { + heth->ErrorCode |= ETH_ERROR_DMA; + /* if fatal bus error occurred */ + if ((dma_flag & ETH_DMA_STU_FBE) != 0U) + { + /* Get DMA error code */ + heth->DMAErrorCode = ((heth->Instance->ETH_DMA_STU) & (ETH_DMA_STU_FBE | ETH_DMA_STU_TPS | ETH_DMA_STU_RPS)); + + /* Disable all interrupts */ + __ETH_DMA_DISABLE_IT(heth, ETH_DMA_INTREN_NIE | ETH_DMA_INTREN_AIE); + + /* Set state to ERROR */ + heth->gState = ETH_STATE_ERROR; + } + else + { + /* Get DMA error status */ + heth->DMAErrorCode = ((heth->Instance->ETH_DMA_STU) & (ETH_DMA_STU_CDE | ETH_DMA_STU_ETI | ETH_DMA_STU_RWT | + ETH_DMA_STU_RBU | ETH_DMA_STU_AIS)); + + /* Clear the interrupt summary flag */ + __ETH_DMA_CLEAR_IT(heth, (ETH_DMA_STU_CDE | ETH_DMA_STU_ETI | ETH_DMA_STU_RWT | + ETH_DMA_STU_RBU | ETH_DMA_STU_AIS)); + } + + /* Ethernet DMA Error callback */ + ETH_ErrorCallback(heth); + } + + /* heth MAC Error IT */ + if (((mac_flag & ETH_MAC_IREN_RXSTSIE) == ETH_MAC_IREN_RXSTSIE) || \ + ((mac_flag & ETH_MAC_IREN_TXSTSIE) == ETH_MAC_IREN_TXSTSIE)) + { + heth->ErrorCode |= ETH_ERROR_MAC; + + /* Get MAC Rx Tx status and clear Status register pending bit */ + heth->MACErrorCode = (heth->Instance->ETH_MAC_RXTXSTU); + + heth->gState = ETH_STATE_ERROR; + + /* Ethernet Error callback */ + ETH_ErrorCallback(heth); + + heth->MACErrorCode = (uint32_t)(0x0U); + } + + /* heth PMT IT */ + if ((mac_flag & ETH_MAC_PMT_IT) != 0U) + { + /* Get MAC Wake-up source and clear the status register pending bit */ + heth->MACWakeUpEvent = ((heth->Instance->ETH_MAC_PMTCTLSTU) & (ETH_MAC_PMTCTLSTU_RWKPRCVD | ETH_MAC_PMTCTLSTU_MGKPRCVD)); + + /* Ethernet PMT callback */ + ETH_PMTCallback(heth); + + heth->MACWakeUpEvent = (uint32_t)(0x0U); + } + + /* check heth WAKEUP exti flag */ + if ((exti_flag & ETH_WAKEUP_EXTI_LINE) != 0U) + { + /* Clear heth WAKEUP Exti pending bit */ + __ETH_WAKEUP_EXTI_CLEAR_FLAG(ETH_WAKEUP_EXTI_LINE); + + /* heth WAKEUP callback */ + ETH_WakeUpCallback(heth); + } +} + + +/** + * @brief Tx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +//__weak void ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +void __attribute__((weak)) ETH_TxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_TxCpltCallback could be implemented in the user file + */ +} + +/** + * @brief Rx Transfer completed callbacks. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +//__weak void ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +void __attribute__((weak)) ETH_RxCpltCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_RxCpltCallback could be implemented in the user file + */ +} + +/** +* @brief Ethernet transfer error callbacks +* @param heth: pointer to a ETH_HandleTypeDef structure that contains +* the configuration information for ETHERNET module +* @retval None +*/ +//__weak void ETH_ErrorCallback(ETH_HandleTypeDef *heth) +void __attribute__((weak)) ETH_ErrorCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_ErrorCallback could be implemented in the user file + */ +} + +/** + * @brief Ethernet Power Management module IT callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +//__weak void ETH_PMTCallback(ETH_HandleTypeDef *heth) +void __attribute__((weak)) ETH_PMTCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_PMTCallback could be implemented in the user file + */ +} + +/** + * @brief heth WAKEUP interrupt callback + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +//__weak void ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +void __attribute__((weak)) ETH_WakeUpCallback(ETH_HandleTypeDef *heth) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(heth); + /* NOTE : This function Should not be modified, when the callback is needed, + the ETH_WakeUpCallback could be implemented in the user file + */ +} + +/** + * @brief Read a PHY register + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param pRegValue: parameter to hold read value + * @retval int + */ +uint32_t ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t *pRegValue) +{ + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (((heth->Instance->ETH_MAC_MDIOADDR)Ð_MAC_MDIOADDR_GB) != (uint32_t)(0x0U)) + { + //return ERROR; + return HAL_ERROR; + } + + /* Get the MAC_MDIOADDR value */ + tmpreg = heth->Instance->ETH_MAC_MDIOADDR; + + /* Prepare the MDIO Address Register value + - Set the PHY device address + - Set the PHY register address + - Set the read mode + - Set the MII Busy bit */ + + MODIFY_REG(tmpreg, ETH_MAC_MDIOADDR_PA, (PHYAddr << 21)); + MODIFY_REG(tmpreg, ETH_MAC_MDIOADDR_RDA, (PHYReg << 16)); + MODIFY_REG(tmpreg, ETH_MAC_MDIOADDR_GOC, ETH_MAC_MDIOADDR_GOC_RD); + tmpreg |= ETH_MAC_MDIOADDR_GB; + + /* Write the result value into the MII Address register */ + WRITE_REG(heth->Instance->ETH_MAC_MDIOADDR, tmpreg); + + /*TODO*/ + tickstart = GetTick(); + + /* Wait for the Busy flag */ + while (((heth->Instance->ETH_MAC_MDIOADDR)Ð_MAC_MDIOADDR_GB) > 0U) + { + if (((GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + { + return ERROR; + } + } + + /* Get ETH_MAC_MDIODATA value */ + WRITE_REG(*pRegValue, (uint16_t)heth->Instance->ETH_MAC_MDIODATA); + + return HAL_OK; +} + +/** + * @brief Writes to a PHY register. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param PHYAddr: PHY port address, must be a value from 0 to 31 + * @param PHYReg: PHY register address, must be a value from 0 to 31 + * @param RegValue: the value to write + * @retval void + */ +uint32_t ETH_WritePHYRegister(const ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, + uint32_t RegValue) +{ + uint32_t tickstart; + uint32_t tmpreg; + + /* Check for the Busy flag */ + if (((heth->Instance->ETH_MAC_MDIOADDR)Ð_MAC_MDIOADDR_GB) != (uint32_t)(0x0U)) + { + return HAL_ERROR; + } + + /* Get the ETH_MAC_MDIOADDR value */ + WRITE_REG(tmpreg, heth->Instance->ETH_MAC_MDIOADDR); + + /* Prepare the MDIO Address Register value + - Set the PHY device address + - Set the PHY register address + - Set the write mode + - Set the MII Busy bit */ + MODIFY_REG(tmpreg, ETH_MAC_MDIOADDR_PA, (PHYAddr << 21)); + MODIFY_REG(tmpreg, ETH_MAC_MDIOADDR_RDA, (PHYReg << 16)); + MODIFY_REG(tmpreg, ETH_MAC_MDIOADDR_GOC, ETH_MAC_MDIOADDR_GOC_WR); + tmpreg |= ETH_MAC_MDIOADDR_GB; + + /* Give the value to the MII data register */ + WRITE_REG(heth->Instance->ETH_MAC_MDIODATA, (uint16_t)RegValue); + + /* Write the result value into the MII Address register */ + WRITE_REG(heth->Instance->ETH_MAC_MDIOADDR, tmpreg); + + /*TODO*/ + //tickstart = GetTick(); + + /* Wait for the Busy flag */ + while (((heth->Instance->ETH_MAC_MDIOADDR)Ð_MAC_MDIOADDR_GB) > 0U) + { + // if (((GetTick() - tickstart) > ETH_MDIO_BUS_TIMEOUT)) + // { + // return ERROR; + // } + } + + return HAL_OK; +} +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group3 Peripheral Control functions + * @brief heth control functions + * +@verbatim + ============================================================================== + ##### Peripheral Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control the heth + peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Get the configuration of the MAC and MTL subsystems. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param macconf: pointer to a ETH_MACConfigTypeDef structure that will hold + * the configuration of the MAC. + * @retval int + */ +uint32_t ETH_GetMACConfig(const ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + /* Get MAC parameters */ + macconf->PreambleLength = ((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_PRELEN); + macconf->DeferralCheck = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_DC) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->BackOffLimit = ((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_BL); + macconf->RetryTransmission = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_DR) >> 8) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseDuringTransmit = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_DCRS) >> 9) == 0U) ? ENABLE : DISABLE; + macconf->ReceiveOwn = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_DO) >> 10) == 0U) ? ENABLE : DISABLE; + macconf->CarrierSenseBeforeTransmit = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_ECRSFD) >> 11) > 0U) ? ENABLE : DISABLE; + macconf->LoopbackMode = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_LM) >> 12) > 0U) ? ENABLE : DISABLE; + macconf->DuplexMode = ((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_DM); + macconf->Speed = ((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_FES); + macconf->JumboPacket = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_JE) >> 16) > 0U) ? ENABLE : DISABLE; + macconf->Jabber = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_JD) >> 17) > 0U) ? ENABLE : DISABLE; + macconf->Watchdog = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_WD) >> 19) > 0U) ? ENABLE : DISABLE; + macconf->AutomaticPadCRCStrip = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_ACS) >> 20) > 0U) ? ENABLE : DISABLE; + macconf->CRCStripTypePacket = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_CST) >> 21) > 0U) ? ENABLE : DISABLE; + macconf->Support2KPacket = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_S2KP) >> 22) > 0U) ? ENABLE : DISABLE; + macconf->GiantPacketSizeLimitControl = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_GPSLCE) >> 23) > 0U) ? ENABLE : DISABLE; + macconf->InterPacketGapVal = ((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_IPG); + macconf->ChecksumOffload = ((((heth->Instance->ETH_MAC_CFG)Ð_MAC_CFG_IPC) >> 27) > 0U) ? ENABLE : DISABLE; + + macconf->GiantPacketSizeLimit = ((heth->Instance->ETH_MAC_EXTDCFG)Ð_MAC_EXTDCFG_GPSL); + macconf->CRCCheckingRxPackets = ((((heth->Instance->ETH_MAC_EXTDCFG)Ð_MAC_EXTDCFG_DCRCC) >> 16) > 0U) ? ENABLE : DISABLE; + macconf->SlowProtocolDetect = ((((heth->Instance->ETH_MAC_EXTDCFG)Ð_MAC_EXTDCFG_SPEN) >> 17) > 0U) ? ENABLE : DISABLE; + macconf->UnicastSlowProtocolPacketDetect = ((((heth->Instance->ETH_MAC_EXTDCFG)Ð_MAC_EXTDCFG_USP) >> 18) > 0U) ? ENABLE : DISABLE; + macconf->ExtendedInterPacketGap = ((((heth->Instance->ETH_MAC_EXTDCFG)Ð_MAC_EXTDCFG_EIPGEN) >> 24) > 0U) ? ENABLE : DISABLE; + macconf->ExtendedInterPacketGapVal = (((heth->Instance->ETH_MAC_EXTDCFG)Ð_MAC_EXTDCFG_EIPG) >> 25); + + macconf->ProgrammableWatchdog = ((((heth->Instance->ETH_MAC_WTDTO)Ð_MAC_WTDTO_PWE) >> 8) > 0U) ? ENABLE : DISABLE; + macconf->WatchdogTimeout = ((heth->Instance->ETH_MAC_WTDTO)Ð_MAC_WTDTO_WTO); + + macconf->TransmitFlowControl = ((((heth->Instance->ETH_MAC_TXFLCTL)Ð_MAC_TXFLCTL_TFE) >> 1) > 0U) ? ENABLE : DISABLE; + macconf->ZeroQuantaPause = ((((heth->Instance->ETH_MAC_TXFLCTL)Ð_MAC_TXFLCTL_DZPQ) >> 7) == 0U) ? ENABLE : DISABLE; + macconf->PauseLowThreshold = ((heth->Instance->ETH_MAC_TXFLCTL)Ð_MAC_TXFLCTL_PLT); + macconf->PauseTime = (((heth->Instance->ETH_MAC_TXFLCTL)Ð_MAC_TXFLCTL_PT) >> 16); + + macconf->ReceiveFlowControl = (((heth->Instance->ETH_MAC_RXFLCTL)Ð_MAC_RXFLCTL_RFE) > 0U) ? ENABLE : DISABLE; + macconf->UnicastPausePacketDetect = ((((heth->Instance->ETH_MAC_RXFLCTL)Ð_MAC_RXFLCTL_UP) >> 1) > 0U) ? ENABLE : DISABLE; + + macconf->TransmitQueueMode = ((heth->Instance->ETH_MTL_TXQOPMODE) & (ETH_MTL_TXQOPMDDE_TTC | ETH_MTL_TXQOPMDDE_TSF)); + + macconf->ReceiveQueueMode = ((heth->Instance->ETH_MTL_RXQOPMODE) & (ETH_MTL_RXQOPMODE_RTC | ETH_MTL_RXQ0OPMD_RSF)); + macconf->ForwardRxUndersizedGoodPacket = ((((heth->Instance->ETH_MTL_RXQOPMODE)Ð_MTL_RXQOPMODE_FUP) >> 3) > 0U) ? ENABLE : DISABLE; + macconf->ForwardRxErrorPacket = ((((heth->Instance->ETH_MTL_RXQOPMODE)Ð_MTL_RXQOPMODE_FEP) >> 4) > 0U) ? ENABLE : DISABLE; + macconf->DropTCPIPChecksumErrorPacket = ((((heth->Instance->ETH_MTL_RXQOPMODE)Ð_MTL_RXQOPMODE_DIS_TCP_EF) >> 6) > 0U) ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Get the configuration of the DMA. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param dmaconf: pointer to a ETH_DMAConfigTypeDef structure that will hold + * the configuration of the heth DMA. + * @retval int + */ +uint32_t ETH_GetDMAConfig(const ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf) +{ + if (dmaconf == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + dmaconf->AddressAlignedBeats = ((((heth->Instance->ETH_DMA_SYSBUSMODE)Ð_DMA_SYSBMODE_AAL) >> 12) > 0U) ? ENABLE : DISABLE; + dmaconf->BurstMode = ((heth->Instance->ETH_DMA_SYSBUSMODE) & (ETH_DMA_SYSBMODE_FB | ETH_DMA_SYSBMODE_MB)); + dmaconf->RebuildINCRxBurst = ((((heth->Instance->ETH_DMA_SYSBUSMODE)Ð_DMA_SYSBMODE_RB) >> 15) > 0U) ? ENABLE : DISABLE; + + dmaconf->DMAArbitration = ((heth->Instance->ETH_DMA_OPMODE) & (ETH_DMA_OPMODE_TXPR | ETH_DMA_OPMODE_PR | ETH_DMA_OPMODE_DA)); + + dmaconf->PBLx8Mode = ((((heth->Instance->ETH_DMA_CTL)Ð_DMA_CTL_8PBL) >> 16) > 0U) ? ENABLE : DISABLE; + + dmaconf->FlushRxPacket = ((((heth->Instance->ETH_DMA_RXCTL)Ð_DMA_CH0RXCTL_RPF) >> 31) > 0U) ? ENABLE : DISABLE; + dmaconf->RxDMABurstLength = ((heth->Instance->ETH_DMA_RXCTL)Ð_DMA_RXCTL_RPBL); + + dmaconf->SecondPacketOperate = ((((heth->Instance->ETH_DMA_TXCTL)Ð_DMA_CH0TXCTL_OSF) >> 4) > 0U) ? ENABLE : DISABLE; + dmaconf->TxDMABurstLength = ((heth->Instance->ETH_DMA_TXCTL)Ð_DMA_TXCTL_TPBL); + + return HAL_OK; +} + +/** + * @brief Configures the Clock range of heth MDIO interface. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +void ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth) +{ + uint32_t hclk; + uint32_t tmpreg; + uint32_t tmpreg1 = 0; + + uint32_t pllp = 2; + uint32_t pllsource = 0; + uint32_t pllm = 2; + uint32_t pllvco = 0; + + /* Get the ETHERNET MAC_MDIOADDR value */ + tmpreg = (heth->Instance)->ETH_MAC_MDIOADDR; + + /* Clear CSR Clock Range bits */ + tmpreg &= ~ETH_MAC_MDIOADDR_CR; + + /* Get hclk frequency value */ + //hclk = RCC_GetHCLKFreq(); + + /*TODO*/ + tmpreg1 = RCC->CFGR & RCC_CFGR_SWS; + switch (tmpreg1) + { + case 0x00: + hclk = 16000000; + break; + case 0x04: + hclk = 25000000; + break; + case 0x08: + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 14; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /*HSE used as PLL clock source*/ + pllvco = (25000000U / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /*HSI used as PLL clock source*/ + pllvco = (16000000U / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> 17) + 1) * 2; + hclk = pllvco / pllp; + } + + + /* Set CR bits depending on hclk value */ + if (hclk < 35000000U) + { + /* CSR Clock Range between 20-35 MHz */ + tmpreg |= (uint32_t)ETH_MAC_MDIOADDR_CR_DIV16; + } + else if (hclk < 60000000U) + { + /* CSR Clock Range between 35-60 MHz */ + tmpreg |= (uint32_t)ETH_MAC_MDIOADDR_CR_DIV26; + } + else if (hclk < 100000000U) + { + /* CSR Clock Range between 60-100 MHz */ + tmpreg |= (uint32_t)ETH_MAC_MDIOADDR_CR_DIV42; + } + else if (hclk < 150000000U) + { + /* CSR Clock Range between 100-150 MHz */ + tmpreg |= (uint32_t)ETH_MAC_MDIOADDR_CR_DIV62; + } + else + { + /* CSR Clock Range between 150-250 MHz */ + tmpreg |= (uint32_t)ETH_MAC_MDIOADDR_CR_DIV102; + } + + /* Configure the CSR Clock Range */ + (heth->Instance)-> ETH_MAC_MDIOADDR = (uint32_t)tmpreg; +} + +/** + * @brief Set the heth MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that contains + * the configuration of the heth MAC filters. + * @retval int + */ +uint32_t ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, const ETH_MACFilterConfigTypeDef *pFilterConfig) +{ + uint32_t filterconfig; + + if (pFilterConfig == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + filterconfig = ((uint32_t)pFilterConfig->PromiscuousMode | + ((uint32_t)pFilterConfig->HashUnicast << 1) | + ((uint32_t)pFilterConfig->HashMulticast << 2) | + ((uint32_t)pFilterConfig->DestAddrInverseFiltering << 3) | + ((uint32_t)pFilterConfig->PassAllMulticast << 4) | + ((uint32_t)((pFilterConfig->BroadcastFilter == DISABLE) ? 1U : 0U) << 5) | + ((uint32_t)pFilterConfig->SrcAddrInverseFiltering << 8) | + ((uint32_t)pFilterConfig->SrcAddrFiltering << 9) | + ((uint32_t)pFilterConfig->HachOrPerfectFilter << 10) | + ((uint32_t)pFilterConfig->ReceiveAllMode << 31) | + pFilterConfig->ControlPacketsFilter); + + MODIFY_REG(heth->Instance->ETH_MAC_PKTFILT, ETH_MAC_PKTFILT_MASK, filterconfig); + + return HAL_OK; +} + +/** + * @brief Get the heth MAC (L2) Filters configuration. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilterConfig: pointer to a ETH_MACFilterConfigTypeDef structure that will hold + * the configuration of the heth MAC filters. + * @retval int + */ +uint32_t ETH_GetMACFilterConfig(const ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig) +{ + if (pFilterConfig == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + pFilterConfig->PromiscuousMode = (((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_PR) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashUnicast = ((((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_HUC) >> 1) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HashMulticast = ((((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_HMC) >> 2) > 0U) ? ENABLE : DISABLE; + pFilterConfig->DestAddrInverseFiltering = ((((heth->Instance->ETH_MAC_PKTFILT)& + ETH_MAC_PKTFILT_DAIF) >> 3) > 0U) ? ENABLE : DISABLE; + pFilterConfig->PassAllMulticast = ((((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_PM) >> 4) > 0U) ? ENABLE : DISABLE; + pFilterConfig->BroadcastFilter = ((((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_DBF) >> 5) == 0U) ? ENABLE : DISABLE; + pFilterConfig->ControlPacketsFilter = ((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_PCF); + pFilterConfig->SrcAddrInverseFiltering = ((((heth->Instance->ETH_MAC_PKTFILT)& + ETH_MAC_PKTFILT_SAIF) >> 8) > 0U) ? ENABLE : DISABLE; + pFilterConfig->SrcAddrFiltering = ((((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_SAF) >> 9) > 0U) ? ENABLE : DISABLE; + pFilterConfig->HachOrPerfectFilter = ((((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_HPF) >> 10) > 0U) + ? ENABLE : DISABLE; + pFilterConfig->ReceiveAllMode = ((((heth->Instance->ETH_MAC_PKTFILT)Ð_MAC_PKTFILT_RA) >> 31) > 0U) ? ENABLE : DISABLE; + + return HAL_OK; +} + +/** + * @brief Set the source MAC Address to be matched. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param AddrNbr: The MAC address to configure + * This parameter must be a value of the following: + * ETH_MAC_ADDRESS1 + * ETH_MAC_ADDRESS2 + * ETH_MAC_ADDRESS3 + * @param pMACAddr: Pointer to MAC address buffer data (6 bytes) + * @retval int + */ +uint32_t ETH_SetSourceMACAddrMatch(const ETH_HandleTypeDef *heth, uint32_t AddrNbr, + const uint8_t *pMACAddr) +{ + uint32_t macaddrlr; + uint32_t macaddrhr; + + if (pMACAddr == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + /* Get mac addr high reg offset */ + macaddrhr = ((uint32_t) & (heth->Instance->ETH_MAC_ADDRH0) + AddrNbr); + /* Get mac addr low reg offset */ + macaddrlr = ((uint32_t) & (heth->Instance->ETH_MAC_ADDRL0) + AddrNbr); + + /* Set MAC addr bits 32 to 47 */ + (*(__IO uint32_t *)macaddrhr) = (((uint32_t)(pMACAddr[5]) << 8) | (uint32_t)pMACAddr[4]); + /* Set MAC addr bits 0 to 31 */ + (*(__IO uint32_t *)macaddrlr) = (((uint32_t)(pMACAddr[3]) << 24) | ((uint32_t)(pMACAddr[2]) << 16) | + ((uint32_t)(pMACAddr[1]) << 8) | (uint32_t)pMACAddr[0]); + + /* Enable address and set source address bit */ + (*(__IO uint32_t *)macaddrhr) |= (ETH_MAC_ADDRH_SA | ETH_MAC_ADDRH_AE); + + return HAL_OK; +} + +/** + * @brief Set the heth Hash Table Value. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pHashTable: pointer to a table of two 32 bit values, that contains + * the 64 bits of the hash table. + * @retval int + */ +uint32_t ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable) +{ + if (pHashTable == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + heth->Instance->ETH_MAC_HASHTB0 = pHashTable[0]; + heth->Instance->ETH_MAC_HASHTB1 = pHashTable[1]; + + //return OK; + return HAL_OK; +} + +/** + * @brief Set the VLAN Identifier for Rx packets + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param ComparisonBits: 12 or 16 bit comparison mode + must be a value of @ref ETH_VLAN_Tag_Comparison + * @param VLANIdentifier: VLAN Identifier value + * @retval None + */ +void ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier) +{ + if (ComparisonBits == ETH_VLANTAGCOMPARISON_16BIT) + { + MODIFY_REG(heth->Instance->ETH_MAC_VLANT, ETH_MAC_VLANT_VL, VLANIdentifier); + (heth->Instance->ETH_MAC_VLANT) &= (~ETH_MAC_VLANT_ETV); + } + else + { + MODIFY_REG(heth->Instance->ETH_MAC_VLANT, ETH_MAC_VLANT_VL_VID, VLANIdentifier); + //SET_BIT(heth->Instance->ETH_MAC_VLANT, ETH_MAC_VLANT_ETV); + heth->Instance->ETH_MAC_VLANT |= ETH_MAC_VLANT_ETV; + } +} + +/** + * @brief Enters the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pPowerDownConfig: a pointer to ETH_PowerDownConfigTypeDef structure + * that contains the Power Down configuration + * @retval None. + */ +void ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, const ETH_PowerDownConfigTypeDef *pPowerDownConfig) +{ + uint32_t powerdownconfig; + + powerdownconfig = (((uint32_t)pPowerDownConfig->MagicPacket << 1) | + ((uint32_t)pPowerDownConfig->WakeUpPacket << 2) | + ((uint32_t)pPowerDownConfig->GlobalUnicast << 9) | + ((uint32_t)pPowerDownConfig->WakeUpForward << 10) | + ETH_MAC_PMTCTLSTU_PWRDWN); + + /* Enable PMT interrupt */ + __ETH_MAC_ENABLE_IT(heth, ETH_MAC_IREN_PMTIE); + + MODIFY_REG(heth->Instance->ETH_MAC_PMTCTLSTU, ETH_MAC_PMTCTLSTU_MASK, powerdownconfig); +} + +/** + * @brief Exits from the Power down mode. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None. + */ +void ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth) +{ + /* clear wake up sources */ + heth->Instance->ETH_MAC_PMTCTLSTU &= (~(ETH_MAC_PMTCTLSTU_RWKPKTEN | ETH_MAC_PMTCTLSTU_MGKPKTEN | ETH_MAC_PMTCTLSTU_GLBLUCAST | + ETH_MAC_PMTCTLSTU_RWKPFE)); + + if (((heth->Instance->ETH_MAC_PMTCTLSTU) & (ETH_MAC_PMTCTLSTU_PWRDWN)) != ((uint32_t)0x0U)) + { + /* Exit power down mode */ + (heth->Instance->ETH_MAC_PMTCTLSTU) &= (~(ETH_MAC_PMTCTLSTU_PWRDWN)); + } + + /* Disable PMT interrupt */ + __ETH_MAC_DISABLE_IT(heth, ETH_MAC_IREN_PMTIE); +} + +/** + * @brief Set the WakeUp filter. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pFilter: pointer to filter registers values + * @param Count: number of filter registers, must be from 1 to 8. + * @retval int. + */ +uint32_t ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count) +{ + uint32_t regindex; + + if (pFilter == NULL) + { + //return ERROR; + return HAL_ERROR; + } + + /* Reset Filter Pointer */ + (heth->Instance->ETH_MAC_PMTCTLSTU) |= (ETH_MAC_PMTCTLSTU_RWKFILTRST); + + /* Wake up packet filter config */ + for (regindex = 0; regindex < Count; regindex++) + { + /* Write filter regs */ + ((heth->Instance->ETH_MAC_RWKPKTFILT) &= (pFilter[regindex])); + } + + //return OK; + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup ETH_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief heth State and Errors functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Errors functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to return the State of + heth communication process, return Peripheral Errors occurred during communication + process + + +@endverbatim + * @{ + */ + +/** + * @brief Returns the heth state. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval HAL state + */ +uint32_t ETH_GetState(const ETH_HandleTypeDef *heth) +{ + return heth->gState; +} + +/** + * @brief Returns the heth error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval heth Error Code + */ +uint32_t ETH_GetError(const ETH_HandleTypeDef *heth) +{ + //return heth->ErrorCode; + return heth->ErrorCode; +} + +/** + * @brief Returns the heth DMA error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval heth DMA Error Code + */ +uint32_t ETH_GetDMAError(const ETH_HandleTypeDef *heth) +{ + return heth->DMAErrorCode; +} + +/** + * @brief Returns the heth MAC error code + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval heth MAC Error Code + */ +uint32_t ETH_GetMACError(const ETH_HandleTypeDef *heth) +{ + return heth->MACErrorCode; +} + +/** + * @brief Returns the heth MAC WakeUp event source + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval heth MAC WakeUp event source + */ +uint32_t ETH_GetMACWakeUpSource(const ETH_HandleTypeDef *heth) +{ + return heth->MACWakeUpEvent; +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup ETH_Private_Functions heth Private Functions + * @{ + */ +uint32_t ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf) +{ + if (macconf == NULL) + { + return HAL_ERROR; + } + else + { + HAL_ETH_SetMACConfig(heth, macconf); + + return HAL_OK; + } + +} +static void HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, const ETH_MACConfigTypeDef *macconf) +{ + uint32_t macregval; + + /*------------------------ ETH_MAC_CFG Configuration --------------------*/ + macregval = (macconf->InterPacketGapVal | + ((uint32_t)macconf->ChecksumOffload << 27) | + ((uint32_t)macconf->GiantPacketSizeLimitControl << 23) | + ((uint32_t)macconf->Support2KPacket << 22) | + ((uint32_t)macconf->CRCStripTypePacket << 21) | + ((uint32_t)macconf->AutomaticPadCRCStrip << 20) | + ((uint32_t)((macconf->Watchdog == DISABLE) ? 1U : 0U) << 19) | + ((uint32_t)((macconf->Jabber == DISABLE) ? 1U : 0U) << 17) | + ((uint32_t)macconf->JumboPacket << 16) | + macconf->Speed | + macconf->DuplexMode | + ((uint32_t)macconf->LoopbackMode << 12) | + ((uint32_t)macconf->CarrierSenseBeforeTransmit << 11) | + ((uint32_t)((macconf->ReceiveOwn == DISABLE) ? 1U : 0U) << 10) | + ((uint32_t)((macconf->CarrierSenseDuringTransmit == DISABLE) ? 1U : 0U) << 9) | + ((uint32_t)((macconf->RetryTransmission == DISABLE) ? 1U : 0U) << 8) | + macconf->BackOffLimit | + ((uint32_t)macconf->DeferralCheck << 4) | + macconf->PreambleLength); + + /* Write to ETH_MAC_CFG */ + MODIFY_REG(heth->Instance->ETH_MAC_CFG, ETH_MAC_CFG_MASK, macregval); + + /*------------------------ ETH_MAC_EXTDCFG Configuration --------------------*/ + macregval = ((macconf->ExtendedInterPacketGapVal << 25) | + ((uint32_t)macconf->ExtendedInterPacketGap << 24) | + ((uint32_t)macconf->UnicastSlowProtocolPacketDetect << 18) | + ((uint32_t)macconf->SlowProtocolDetect << 17) | + ((uint32_t)((macconf->CRCCheckingRxPackets == DISABLE) ? 1U : 0U) << 16) | + macconf->GiantPacketSizeLimit); + + /* Write to ETH_MAC_EXTDCFG */ + MODIFY_REG(heth->Instance->ETH_MAC_EXTDCFG, ETH_MAC_EXTDCFG_MASK, macregval); + + /*------------------------ ETH_MAC_WTDTO Configuration --------------------*/ + macregval = (((uint32_t)macconf->ProgrammableWatchdog << 8) | + macconf->WatchdogTimeout); + + /* Write to ETH_MAC_WTDTO */ + MODIFY_REG(heth->Instance->ETH_MAC_WTDTO, ETH_MAC_WTDTO_MASK, macregval); + + /*------------------------ ETH_MAC_TXFLCTL Configuration --------------------*/ + macregval = (((uint32_t)macconf->TransmitFlowControl << 1) | + macconf->PauseLowThreshold | + ((uint32_t)((macconf->ZeroQuantaPause == DISABLE) ? 1U : 0U) << 7) | + (macconf->PauseTime << 16)); + + /* Write to ETH_MAC_TXFLCTL */ + MODIFY_REG(heth->Instance->ETH_MAC_TXFLCTL, ETH_MAC_TXFLCTL_MASK, macregval); + + /*------------------------ ETH_MAC_RXFLCTL Configuration --------------------*/ + macregval = ((uint32_t)macconf->ReceiveFlowControl | + ((uint32_t)macconf->UnicastPausePacketDetect << 1)); + + /* Write to ETH_MAC_RXFLCTL */ + MODIFY_REG(heth->Instance->ETH_MAC_RXFLCTL, ETH_MAC_RXFLCTL_MASK, macregval); + + /*------------------------ ETH_MTL_TXQOPMODE Configuration --------------------*/ + /* Write to ETH_MTL_TXQOPMODE */ + MODIFY_REG(heth->Instance->ETH_MTL_TXQOPMODE, ETH_MTL_TXQOPMODE_MASK, macconf->TransmitQueueMode); + + /*------------------------ ETH_MTL_RXQOPMODE Configuration --------------------*/ + macregval = (macconf->ReceiveQueueMode | + ((uint32_t)((macconf->DropTCPIPChecksumErrorPacket == DISABLE) ? 1U : 0U) << 6) | + ((uint32_t)macconf->ForwardRxErrorPacket << 4) | + ((uint32_t)macconf->ForwardRxUndersizedGoodPacket << 3)); + + /* Write to ETH_MTL_RXQOPMODE */ + MODIFY_REG(heth->Instance->ETH_MTL_RXQOPMODE, ETH_MTL_RXQOPMODE_MASK, macregval); +} + + +static void ETH_SetDMAConfig(ETH_HandleTypeDef *heth, const ETH_DMAConfigTypeDef *dmaconf) +{ + uint32_t dmaregval; + + /*------------------------ETH_DMA_OPMODE Configuration --------------------*/ + MODIFY_REG(heth->Instance->ETH_DMA_OPMODE, ETH_DMA_OPMODE_MASK, dmaconf->DMAArbitration); + + /*------------------------ETH_DMA_SYSBUSMODE_MASK Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->AddressAlignedBeats << 12) | + dmaconf->BurstMode | + ((uint32_t)dmaconf->RebuildINCRxBurst << 15)); + + MODIFY_REG(heth->Instance->ETH_DMA_SYSBUSMODE, ETH_DMA_SYSBUSMODE_MASK, dmaregval); + + /*------------------------ ETH_DMA_CTL Configuration --------------------*/ + dmaregval = ((uint32_t)dmaconf->PBLx8Mode << 16) ; + + MODIFY_REG(heth->Instance->ETH_DMA_CTL, ETH_DMA_CTL_MASK, dmaregval); + + /*------------------------ ETH_DMA_TXCTL Configuration --------------------*/ + dmaregval = (dmaconf->TxDMABurstLength | ((uint32_t)dmaconf->SecondPacketOperate << 4)); + + MODIFY_REG(heth->Instance->ETH_DMA_TXCTL, ETH_DMA_TXCTL_MASK, dmaregval); + + /*------------------------ ETH_DMA_RXCTL Configuration --------------------*/ + dmaregval = (((uint32_t)dmaconf->FlushRxPacket << 31) | dmaconf->RxDMABurstLength); + + /* Write to ETH_DMA_RXCTL */ + MODIFY_REG(heth->Instance->ETH_DMA_RXCTL, ETH_DMA_RXCTL_MASK, dmaregval); +} + +/** + * @brief Configures Ethernet MAC and DMA with default parameters. + * called by ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval none + */ +static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth) +{ + ETH_MACConfigTypeDef macDefaultConf; + ETH_DMAConfigTypeDef dmaDefaultConf; + + /*--------------- ETHERNET MAC registers default Configuration --------------*/ + macDefaultConf.AutomaticPadCRCStrip = ENABLE; + macDefaultConf.BackOffLimit = ETH_BACKOFFLIMIT_10; + macDefaultConf.CarrierSenseBeforeTransmit = DISABLE; + macDefaultConf.CarrierSenseDuringTransmit = ENABLE; + macDefaultConf.ChecksumOffload = ENABLE; + macDefaultConf.CRCCheckingRxPackets = ENABLE; + macDefaultConf.CRCStripTypePacket = ENABLE; + macDefaultConf.DeferralCheck = DISABLE; + macDefaultConf.DropTCPIPChecksumErrorPacket = ENABLE; + macDefaultConf.DuplexMode = ETH_FULLDUPLEX_MODE; + macDefaultConf.ExtendedInterPacketGap = DISABLE; + macDefaultConf.ExtendedInterPacketGapVal = 0x0U; + macDefaultConf.ForwardRxErrorPacket = DISABLE; + macDefaultConf.ForwardRxUndersizedGoodPacket = DISABLE; + macDefaultConf.GiantPacketSizeLimit = 0x618U; + macDefaultConf.GiantPacketSizeLimitControl = DISABLE; + macDefaultConf.InterPacketGapVal = ETH_INTERPACKETGAP_96BIT; + macDefaultConf.Jabber = ENABLE; + macDefaultConf.JumboPacket = DISABLE; + macDefaultConf.LoopbackMode = DISABLE; + macDefaultConf.PauseLowThreshold = ETH_PAUSELOWTHRESHOLD_MINUS_4; + macDefaultConf.PauseTime = 0x0U; + macDefaultConf.PreambleLength = ETH_PREAMBLELENGTH_7; + macDefaultConf.ProgrammableWatchdog = DISABLE; + macDefaultConf.ReceiveFlowControl = DISABLE; + macDefaultConf.ReceiveOwn = ENABLE; + macDefaultConf.ReceiveQueueMode = ETH_RECEIVESTOREFORWARD; + macDefaultConf.RetryTransmission = ENABLE; + macDefaultConf.SlowProtocolDetect = DISABLE; + macDefaultConf.Speed = ETH_SPEED_100M; + macDefaultConf.Support2KPacket = DISABLE; + macDefaultConf.TransmitQueueMode = ETH_TRANSMITSTOREFORWARD; + macDefaultConf.TransmitFlowControl = DISABLE; + macDefaultConf.UnicastPausePacketDetect = DISABLE; + macDefaultConf.UnicastSlowProtocolPacketDetect = DISABLE; + macDefaultConf.Watchdog = ENABLE; + macDefaultConf.WatchdogTimeout = ETH_WATCHDOGTIMEOUT_2KB; + macDefaultConf.ZeroQuantaPause = ENABLE; + + /* MAC default configuration */ + ETH_SetMACConfig(heth, &macDefaultConf); + + /*--------------- ETHERNET DMA registers default Configuration --------------*/ + dmaDefaultConf.AddressAlignedBeats = ENABLE; + dmaDefaultConf.BurstMode = ETH_BURSTLENGTH_FIXED; + dmaDefaultConf.DMAArbitration = ETH_DMAARBITRATION_RX1_TX1; + dmaDefaultConf.FlushRxPacket = DISABLE; + dmaDefaultConf.PBLx8Mode = DISABLE; + dmaDefaultConf.RebuildINCRxBurst = DISABLE; + dmaDefaultConf.RxDMABurstLength = ETH_RXDMABURSTLENGTH_32BEAT; + dmaDefaultConf.SecondPacketOperate = DISABLE; + dmaDefaultConf.TxDMABurstLength = ETH_TXDMABURSTLENGTH_32BEAT; + + /* DMA default configuration */ + ETH_SetDMAConfig(heth, &dmaDefaultConf); +} + +/** + * @brief Initializes the DMA Tx descriptors. + * called by ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMATxDescListInit(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmatxdesc; + uint32_t i; + + /* Fill each DMATxDesc descriptor with the right values */ + for (i = 0; i < (uint32_t)ETH_TX_DESC_CNT; i++) + { + dmatxdesc = heth->Init.TxDesc + i; + + WRITE_REG(dmatxdesc->DESC0, 0x0U); + WRITE_REG(dmatxdesc->DESC1, 0x0U); + WRITE_REG(dmatxdesc->DESC2, 0x0U); + WRITE_REG(dmatxdesc->DESC3, 0x0U); + + WRITE_REG(heth->TxDescList.TxDesc[i], (uint32_t)dmatxdesc); + + /*TODO*/ + //printf("TxDescList TxDesc[%d] addr = %p\n",i,heth->TxDescList.TxDesc[i]); + } + + heth->TxDescList.CurTxDesc = 0; + + /* Set Transmit Descriptor Ring Length */ + WRITE_REG(heth->Instance->ETH_DMA_TXDESCRINGLEN, (ETH_TX_DESC_CNT - 1U)); + + /* Set Transmit Descriptor List Address */ + WRITE_REG(heth->Instance->ETH_DMA_TXDESCLSTADDR, (uint32_t) heth->Init.TxDesc); + + /* Set Transmit Descriptor Tail pointer */ + WRITE_REG(heth->Instance->ETH_DMA_TXDESCTAILPTR, (uint32_t) heth->Init.TxDesc); +} + +/** + * @brief Initializes the DMA Rx descriptors in chain mode. + * called by ETH_Init() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @retval None + */ +static void ETH_DMARxDescListInit(ETH_HandleTypeDef *heth) +{ + ETH_DMADescTypeDef *dmarxdesc; + uint32_t i; + + for (i = 0; i < (uint32_t)ETH_RX_DESC_CNT; i++) + { + dmarxdesc = heth->Init.RxDesc + i; + + WRITE_REG(dmarxdesc->DESC0, 0x0U); + WRITE_REG(dmarxdesc->DESC1, 0x0U); + WRITE_REG(dmarxdesc->DESC2, 0x0U); + WRITE_REG(dmarxdesc->DESC3, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr0, 0x0U); + WRITE_REG(dmarxdesc->BackupAddr1, 0x0U); + + /* Set Rx descritors addresses */ + WRITE_REG(heth->RxDescList.RxDesc[i], (uint32_t)dmarxdesc); + + /*TODO*/ + //printf("RxDescList RxDesc[%d] addr = %p\n",i,heth->RxDescList.RxDesc[i]); + } + + WRITE_REG(heth->RxDescList.RxDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxDescCnt, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescIdx, 0U); + WRITE_REG(heth->RxDescList.RxBuildDescCnt, 0U); + WRITE_REG(heth->RxDescList.ItMode, 0U); + + /* Set Receive Descriptor Ring Length */ + WRITE_REG(heth->Instance->ETH_DMA_RXCTL2, ((uint32_t)(ETH_RX_DESC_CNT - 1U))); + + /* Set Receive Descriptor List Address */ + WRITE_REG(heth->Instance->ETH_DMA_RXDESCLSTADDR, (uint32_t) heth->Init.RxDesc); + + /* Set Receive Descriptor Tail pointer Address */ + WRITE_REG(heth->Instance->ETH_DMA_RXDESCTAILPTR, ((uint32_t)(heth->Init.RxDesc + (uint32_t)(ETH_RX_DESC_CNT - 1U)))); +} + +/** + * @brief Prepare Tx DMA descriptor before transmission. + * called by ETH_Transmit and ETH_Transmit_IT() API. + * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * the configuration information for ETHERNET module + * @param pTxConfig: Tx packet configuration + * @param ItMode: Enable or disable Tx EOT interrept + * @retval Status + */ +static uint32_t ETH_Prepare_Tx_Descriptors(ETH_HandleTypeDef *heth, const ETH_TxPacketConfigTypeDef *pTxConfig, + uint32_t ItMode) +{ + ETH_TxDescListTypeDef *dmatxdesclist = &heth->TxDescList; + uint32_t descidx = dmatxdesclist->CurTxDesc; + uint32_t firstdescidx = dmatxdesclist->CurTxDesc; + uint32_t idx; + uint32_t descnbr = 0; + ETH_DMADescTypeDef *dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + ETH_BufferTypeDef *txbuffer = pTxConfig->TxBuffer; + + /*TODO*/ + //printf("Prepare TxDESC[%d],addr=%p\n",descidx,dmatxdesclist->TxDesc[descidx]); + //printf("ETH Buffer addr = %p\n",*txbuffer); + + uint32_t bd_count = 0; + uint32_t primask_bit; + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((((dmatxdesc->DESC3)Ð_DMATXNDESCWBF_OWN) == ETH_DMATXNDESCWBF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + return ETH_ERROR_BUSY; + } + + + + /***************************************************************************/ + /***************** Normal descriptors configuration *****************/ + /***************************************************************************/ + descnbr += 1U; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + + //if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + if ((((pTxConfig->Attributes)Ð_TX_PACKETS_FEATURES_CSUM)) != (uint32_t)(0x0U)) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + } + + //if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)RESET) + if (((pTxConfig->Attributes)Ð_TX_PACKETS_FEATURES_CRCPAD) != (uint32_t)(0x0U)) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CPC, pTxConfig->CRCPadCtrl); + } + //} + + if (((pTxConfig->Attributes)Ð_TX_PACKETS_FEATURES_VLANTAG) != (uint32_t)(0x0U)) + { + /* Set Vlan Tag control */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_VTIR, pTxConfig->VlanCtrl); + } + + if (txbuffer->next != NULL) + { + txbuffer = txbuffer->next; + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0U); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + } + //if (((pTxConfig->Attributes)Ð_TX_PACKETS_FEATURES_TSO) != (uint32_t)(0x0U)) + //{ + // /* Set TCP Header length */ + // MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_THL, (pTxConfig->TCPHeaderLen << 19)); + // /* Set TCP payload length */ + // MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + // /* Set TCP Segmentation Enabled bit */ + // dmatxdesc->DESC3 |= ETH_DMATXNDESCRF_TSE; + //} + //else + //{ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + + /* Mark it as First Descriptor */ + //SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + dmatxdesc->DESC3 |= ETH_DMATXNDESCRF_FD; + /* Mark it as NORMAL descriptor */ + //CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + dmatxdesc->DESC3 &= (~(ETH_DMATXNDESCRF_CTXT)); + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* set OWN bit of FIRST descriptor */ + //SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + dmatxdesc->DESC3 |= ETH_DMATXNDESCRF_OWN; + + /* If source address insertion/replacement is enabled for this packet */ + if (((pTxConfig->Attributes)Ð_TX_PACKETS_FEATURES_SAIC) != (uint32_t)(0x0U)) + { + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_SAIC, pTxConfig->SrcAddrCtrl); + } + + /* only if the packet is split into more than one descriptors > 1 */ + while (txbuffer->next != NULL) + { + /* Clear the LD bit of previous descriptor */ + //CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + dmatxdesc->DESC3 &= (~(ETH_DMATXNDESCRF_LD)); + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* Clear the FD bit of new Descriptor */ + //CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FD); + dmatxdesc->DESC3 &= (~(ETH_DMATXNDESCRF_FD)); + + /* Current Tx Descriptor Owned by DMA: cannot be used by the application */ + if ((((dmatxdesc->DESC3)Ð_DMATXNDESCRF_OWN) == ETH_DMATXNDESCRF_OWN) + || (dmatxdesclist->PacketAddress[descidx] != NULL)) + { + descidx = firstdescidx; + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + + /* clear previous desc own bit */ + for (idx = 0; idx < descnbr; idx ++) + { + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + + //CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + dmatxdesc->DESC3 &= (~(ETH_DMATXNDESCRF_OWN)); + + /* Increment current tx descriptor index */ + INCR_TX_DESC_INDEX(descidx, 1U); + /* Get current descriptor address */ + dmatxdesc = (ETH_DMADescTypeDef *)dmatxdesclist->TxDesc[descidx]; + } + + return ETH_ERROR_BUSY; + } + + descnbr += 1U; + + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + + /* Set header or buffer 1 address */ + WRITE_REG(dmatxdesc->DESC0, (uint32_t)txbuffer->buffer); + /* Set header or buffer 1 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B1L, txbuffer->len); + + if (txbuffer->next != NULL) + { + /* Get the next Tx buffer in the list */ + txbuffer = txbuffer->next; + /* Set buffer 2 address */ + WRITE_REG(dmatxdesc->DESC1, (uint32_t)txbuffer->buffer); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, (txbuffer->len << 16)); + } + else + { + WRITE_REG(dmatxdesc->DESC1, 0x0U); + /* Set buffer 2 Length */ + MODIFY_REG(dmatxdesc->DESC2, ETH_DMATXNDESCRF_B2L, 0x0U); + } + + //if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)RESET) + //if (((pTxConfig->Attributes) & ETH_TX_PACKETS_FEATURES_TSO) != (uint32_t)(0x0U)) + //{ + // /* Set TCP payload length */ + // MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TPL, pTxConfig->PayloadLen); + // /* Set TCP Segmentation Enabled bit */ + // //SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_TSE); + // dmatxdesc->DESC3 |= ETH_DMATXNDESCRF_TSE; + //} + //else + //{ + /* Set the packet length */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_FL, pTxConfig->Length); + + //if (READ_BIT(pTxConfig->Attributes, ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)RESET) + if (((pTxConfig->Attributes) & ETH_TX_PACKETS_FEATURES_CSUM) != (uint32_t)(0x0U)) + { + /* Checksum Insertion Control */ + MODIFY_REG(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CIC, pTxConfig->ChecksumCtrl); + } + //} + + bd_count += 1U; + + /* Ensure rest of descriptor is written to RAM before the OWN bit */ + __DMB(); + /* Set Own bit */ + //SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_OWN); + dmatxdesc->DESC3 |= ETH_DMATXNDESCRF_OWN; + /* Mark it as NORMAL descriptor */ + //CLEAR_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_CTXT); + dmatxdesc->DESC3 &= (~(ETH_DMATXNDESCRF_CTXT)); + } + + //if (ItMode != ((uint32_t)RESET)) + if (ItMode != ((uint32_t)(0x0U))) + { + /* Set Interrupt on completion bit */ + //SET_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + dmatxdesc->DESC2 |= ETH_DMATXNDESCRF_IOC; + } + else + { + /* Clear Interrupt on completion bit */ + //CLEAR_BIT(dmatxdesc->DESC2, ETH_DMATXNDESCRF_IOC); + dmatxdesc->DESC2 &= (~(ETH_DMATXNDESCRF_IOC)); + } + + /* Mark it as LAST descriptor */ + //SET_BIT(dmatxdesc->DESC3, ETH_DMATXNDESCRF_LD); + dmatxdesc->DESC3 |= ETH_DMATXNDESCRF_LD; + /* Save the current packet address to expose it to the application */ + dmatxdesclist->PacketAddress[descidx] = dmatxdesclist->CurrentPacketAddress; + + dmatxdesclist->CurTxDesc = descidx; + + /* Enter critical section */ + primask_bit = __get_PRIMASK(); + __set_PRIMASK(1); + + dmatxdesclist->BuffersInUse += bd_count + 1U; + + /* Exit critical section: restore previous priority mask */ + __set_PRIMASK(primask_bit); + + /* Return function status */ + return ETH_ERROR_NONE; +} + +/** + * @} + */ + +/** + * @} + */ + +//#endif /* heth */ + +/** + * @} + */ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_exti.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_exti.c new file mode 100644 index 00000000000..c3c2d5daf86 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_exti.c @@ -0,0 +1,211 @@ +/** + ****************************************************************************** + * @file ft32f4xx_exti.c + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_exti.h" + + + +/** @defgroup EXTI + * @brief EXTI driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + + +/** + * @brief Deinitializes the EXTI peripheral registers to their default reset + * values. + * @param None + * @retval None + */ +void EXTI_DeInit(void) +{ + EXTI->IMR = 0x60000000; + EXTI->EMR = 0x00000000; + EXTI->RTSR = 0x00000000; + EXTI->FTSR = 0x00000000; + EXTI->SWIER = 0x00000000; + EXTI->PR = 0x00000000; +} + + +/** + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that + * contains the configuration information for the EXTI peripheral. + * @retval None + */ +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); + assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); + assert_param(IS_GET_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); + + tmp = (uint32_t)EXTI_BASE; + + if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + /* Clear EXTI line configuration */ + EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; + + tmp += EXTI_InitStruct->EXTI_Mode; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; + + /* Select the trigger for the selected interrupts */ + if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + + *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + + /* Disable the selected external lines */ + *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + + +/** + * @brief Fills each EXTI_InitStruct member with its reset value. + * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + + +/** + * @brief Generates a Software interrupt on selected EXTI line. + * @param EXTI_Line: specifies the EXTI line on which the software interrupt + * will be generated. + * This parameter can be any combination of EXTI_Linex where x can be (0..28). + * Line29(LPTIM)&Line30(LPUART) are don't have flag status. + * @retval None + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + EXTI->SWIER |= EXTI_Line; +} + + +/** + * @brief Checks whether the specified EXTI line flag is set or not. + * @param EXTI_Line: specifies the EXTI line flag to check. + * This parameter can be EXTI_Linex where x can be (0..28). + * Line29(LPTIM)&Line30(LPUART) are don't have flag status. + * @retval The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + + +/** + * @brief Clears the EXTI's line pending flags. + * @param EXTI_Line: specifies the EXTI lines flags to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..28). + * @retval None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + + +/** + * @brief Checks whether the specified EXTI line is asserted or not. + * @param EXTI_Line: specifies the EXTI line to check. + * This parameter can be EXTI_Linex where x can be (0..28). + * @retval The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + + +/** + * @brief Clears the EXTI's line pending bits. + * @param EXTI_Line: specifies the EXTI lines to clear. + * This parameter can be any combination of EXTI_Linex where x can be (0..28). + * @retval None + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + /* Check the parameters */ + assert_param(IS_GET_EXTI_LINE(EXTI_Line)); + + EXTI->PR = EXTI_Line; +} + + + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_fdcan.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_fdcan.c new file mode 100644 index 00000000000..aa973233394 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_fdcan.c @@ -0,0 +1,2449 @@ +/** + ****************************************************************************** + * @file ft32f4xx_fdcan.c + * @author FMD AE + * @brief FDCAN module driver. + * This file provides firmware functions to manage the following + * functionalities of the Flexible DataRate Controller Area Network + * (FDCAN) peripheral:: + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Configuration and Control functions + * + Peripheral State and Error functions + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-06 + * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Initialize the FDCAN peripheral using FDCAN_Init function. + (++) FDCAN_Init + (++) FDCAN_DeInit + (#) If needed , configure the reception filters and optional features using + the following configuration functions: + (++) FDCAN_ConfigFilter + (++) FDCAN_ConfigRxFifoOverwrite + (++) FDCAN_ConfigTimestampLocation + (++) FDCAN_EnableTimestampCounter + (++) FDCAN_ConfigTxDelayCompensation + (++) FDCAN_EnableTxDelayCompensation + (++) FDCAN_EnableISOMode + (++) FDCAN_DisableISOMode + + (#) If needed , configure the TxBuffer and get RxBuffer and other value using + the following configuration functions: + (++) FDCAN_ConfigTxBuffer + (++) FDCAN_GetRxBuffer + (++) FDCAN_GetArbLostCap + (++) FDCAN_GetErrorCnt + + (#) Start the FDCAN module using FDCAN_Start function. At this level + the node is active on the bus: it can send and receive messages. + + (#) The following Tx control functions can only be called when the FDCAN + module is started: + (++) FDCAN_AddMessageToTxPTB + (++) FDCAN_AddMessageToTxSTBFifoQ + (++) FDCAN_AbortTxRequest + + (#) After having submitted a Tx request in Tx Fifo or Queue, it is possible to + get STB Tx buffer status if used STB for transmission thanks to + FDCAN_GetSecondaryBufferStatus API. + It is then possible to abort transmission from STB which has been requested + but not started yet using FDCAN_AbortTxRequest API. + + (#) When a message is received into the FDCAN message RAM, it can be + retrieved using the FDCAN_GetRxMessage function. + + (#) Calling the FDCAN_Stop function stops the FDCAN module by entering + it to initialization mode and re-enabling access to configuration + registers through the configuration functions listed here above. + + (#) All other control functions can be called any time after initialization + phase, no matter if the FDCAN module is started or stopped. + + *** Polling mode operation *** + ============================== + [..] + (#) Reception and transmission states can be monitored via the following + functions: + (++) HAL_FDCAN_GetRxFifoFillStatus + (++) FDCAN_GetSecondaryBufferStatus + + *** Interrupt mode operation *** + ================================ + [..] + (#) There are one interrupt line for each FDCAN: line 0. + By default, all interrupts are assigned to line 0. + + (#) Notifications are activated using FDCAN_ActivateNotification + function. Then, the process can be controlled through one of the + available user callbacks: CANx_Handler. + + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_fdcan.h" +#include "ft32f4xx_rcc.h" + + +/** + * @brief Calculate each RAM block start address and size + * @param hfdcan pointer to an FDCAN_HandleTypeDef structure that contains + * the configuration information for the specified FDCAN. + * @retval none + */ +//static void FDCAN_CalcultateBlockBaseAddresses(FDCAN_TypeDef* fdcan) //zhujia +//{ +//} + +//arbitration need handle process how or just leave function head file? + +/* ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize and configure the FDCAN. + (+) De-initialize the FDCAN. + (+) Enter FDCAN peripheral in power down mode. +*/ +/** + * @brief Initializes the FDCAN peripheral according to the specified + * parameters in the FDCAN_InitTypeDef structure. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param fdcanInit: specifies the fdcan initial config value + * @arg FrameFormat: Specifies the FDCAN frame format + * The value of FrameFormat: FDCAN_FRAME_CLASSIC + * FDCAN_FRAME_FD_NO_BRS + * FDCAN_FRAME_FD_BRS + * @arg AutoPrimaryRetransmission: Enable or disable the automatic retransmission mode for PTB + * The value of AutoPrimaryRetransmission: ENABLE + * DISABLE + * @arg AutoSecondaryRetransmission: Enable or disable the automatic retransmission mode for STB + * The value of AutoSecondaryRetransmission: ENABLE + * DISABLE + * @arg TTCANMode: Enable or disable the Time Trigger CAN + * The value of TTCANMode: ENABLE + * DISABLE + * @arg FDCANSACK: Specifies the Self-ACKnowledge in External LoopBack mode + * The value of FDCANSACK: FDCAN_NO_SACK + * FDCAN_SACK + * @arg ReceiveBufferStoreAllFrames: Specifies the receive buffer stores all frames or normal frames + * The value of ReceiveBufferStoreAllFrames: FDCAN_RBUF_STORE_NORMAL_OPERATION + * FDCAN_RBUF_STORE_ALL_DATA_FRAMES + * CAN_S_SEG_UNIT_SET: Config the follow parameter in this register: + * @arg NominalPrescaler: Specifies the value by which the oscillator frequency + * is divided for generating the nominal bit time quanta + * The value of NominalPrescaler: 1 and 255 + * @arg NominalSyncJumpWidth: Specifies the maximum number of time quanta the FDCAN hardware + * is allowed to lengthen or shorten a bit to performresynchronization + * The value of NominalSyncJumpWidth: 2 and 127 + * @arg NominalTimeSeg1: Specifies the number of time quanta in Bit Segment 1 + * The value of NominalTimeSeg1: 3 and 255 + * @arg NominalTimeSeg2: Specifies the number of time quanta in Bit Segment 2 + * The value of NominalTimeSeg2: 2 and 127 + * CAN_F_SEG_UNIT_SET: Config the follow parameter in this register: + * @arg DataPrescaler: Specifies the value by which the oscillator frequency + * is divided for generating the data bit time quanta + * The value of DataPrescaler: 1 and 255 + * @arg DataSyncJumpWidth: Specifies the maximum number of time quanta the FDCAN hardware + * is allowed to lengthen or shorten a data bit to perform resynchronization + * The value of DataSyncJumpWidth: 2 and 15 + * @arg DataTimeSeg1: Specifies the number of time quanta in Data Bit Segment 1 + * The value of DataTimeSeg1: 3 and 31 + * @arg DataTimeSeg2: Specifies the number of time quanta in Data Bit Segment 2 + * The value of DataTimeSeg2: 2 and 15 + * @arg TimeTriggerPrescaler: Specifies the value by which bit time is divided for time trigger timer + * The value of TimeTriggerPrescaler: FDCAN_TIME_TRIGGER_PRESCALER_1 + * FDCAN_TIME_TRIGGER_PRESCALER_2 + * FDCAN_TIME_TRIGGER_PRESCALER_4 + * FDCAN_TIME_TRIGGER_PRESCALER_8 + * @arg TimeTriggerType: Specifies the kind of trigger in Time Trigger mode CAN_TRIG_CFG[TTYPE] + * The value of TimeTriggerType: FDCAN_TTCAN_IMMEDIATE_TRIG + * FDCAN_TTCAN_TIME_TRIG + * FDCAN_TTCAN_SINGLE_SHOT_TRIG + * FDCAN_TTCAN_TRANSMIT_START_TRIG + * FDCAN_TTCAN_TRANSMIT_STOP_TRIG + * @arg TransmitEnableWindow: Specifies the ticks of transmit enable window CAN_TRIG_CFG[TEW] + * The value of TransmitEnableWindow: 0 and 15 + * @arg TriggerTime: Specifies the cycle time for a trigger CAN_TRIG_CFG[TT_TRIG] + * The value of TriggerTime: 0 and 255 + * @arg WatchTriggerTime: Specifies the cycle time for a watch trigger CAN_TRANS_INT_STAT[TT_WTRIG] + * The value of WatchTriggerTime: 0 and 255 + * @retval None. + */ + +void FDCAN_Init(FDCAN_TypeDef* fdcan, FDCAN_InitTypeDef* fdcanInit) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan));/*Check fdcan ?= FDCAN1/2/3/4*/ + + /* Check Init parameters */ + assert_param(IS_FDCAN_FRAME_FORMAT(fdcanInit->FrameFormat)); + assert_param(IS_FUNCTIONAL_STATE(fdcanInit->AutoPrimaryRetransmission)); + assert_param(IS_FUNCTIONAL_STATE(fdcanInit->AutoSecondaryRetransmission)); + assert_param(IS_FDCAN_FDCANSACK(fdcanInit->FDCANSACK)); + assert_param(IS_FDCAN_RBUF_STORE_ALL(fdcanInit->ReceiveBufferStoreAllFrames)); + assert_param(IS_FDCAN_NOMINAL_PRESCALER(fdcanInit->NominalPrescaler)); + assert_param(IS_FDCAN_NOMINAL_SJW(fdcanInit->NominalSyncJumpWidth)); + assert_param(IS_FDCAN_NOMANAL_SEG1(fdcanInit->NominalTimeSeg1)); + assert_param(IS_FDCAN_NOMANAL_SEG2(fdcanInit->NominalTimeSeg2)); + assert_param(IS_FDCAN_DATA_PRESCALER(fdcanInit->DataPrescaler)); + assert_param(IS_FDCAN_DATA_SJW(fdcanInit->DataSyncJumpWidth)); + assert_param(IS_FDCAN_DATA_SEG1(fdcanInit->DataTimeSeg1)); + assert_param(IS_FDCAN_DATA_SEG2(fdcanInit->DataTimeSeg2)); + + if (fdcanInit->TTCANMode == ENABLE) /*The TTCAN is set*/ + { + assert_param(IS_FDCAN_TTCAN_PRESCALER(fdcanInit->TimeTriggerPrescaler)); + assert_param(IS_FDCAN_TTCAN_TYPE(fdcanInit->TimeTriggerType)); + assert_param(IS_FDCAN_TTCAN_TR_EN_WIN(fdcanInit->TransmitEnableWindow)); + assert_param(IS_FDCAN_TTCAN_TRIGGER_TIME(fdcanInit->TriggerTime)); + assert_param(IS_FDCAN_TTCAN_WATCH_TIME(fdcanInit->WatchTriggerTime)); + + /* Set the value by which bit time is divided for time trigger timer */ + fdcan->CAN_INT_FLAG2 |= fdcanInit->TimeTriggerPrescaler; + + uint32_t CAN_TRG_CFG_VALUE; + CAN_TRG_CFG_VALUE = fdcan->CAN_TRIG_CFG; + CAN_TRG_CFG_VALUE = (CAN_TRG_CFG_VALUE & ~CAN_TRIG_CFG_TTPTR); + /* Set the cycle time for a trigger */ + /* Set the kind of trigger in Time Trigger mode */ + /* Set the ticks of transmit enable window */ + fdcan->CAN_TRIG_CFG |= ((fdcanInit->TriggerTime << 16U) | + fdcanInit->TimeTriggerType | + (fdcanInit->TransmitEnableWindow << 12U) | + CAN_TRG_CFG_VALUE) ; + } + + if (fdcanInit->WatchTriggerTime != DISABLE) + { + /* Set the cycle time for a watch trigger */ + uint32_t CAN_TRANS_INT_STAT_VALUE; + CAN_TRANS_INT_STAT_VALUE = fdcan->CAN_TRANS_INT_STAT ; + CAN_TRANS_INT_STAT_VALUE = (CAN_TRANS_INT_STAT_VALUE & ~CAN_TRANS_INT_STAT_WTRIG); + fdcan->CAN_TRANS_INT_STAT = (CAN_TRANS_INT_STAT_VALUE | fdcanInit->WatchTriggerTime); + } + + /* Set the nominal bit timing register */ + fdcan->CAN_S_SEG_UNIT_SET = (((fdcanInit->NominalPrescaler) << 24U) | + ((fdcanInit->NominalSyncJumpWidth) << 16U) | + ((fdcanInit->NominalTimeSeg2) << 8U) | + ((fdcanInit->NominalTimeSeg1) << 0U)); + + /* If FD operation with BRS is selected, set the data bit timing register */ + fdcan->CAN_F_SEG_UNIT_SET = (((fdcanInit->DataPrescaler) << 24U) | + ((fdcanInit->DataSyncJumpWidth) << 16U) | + ((fdcanInit->DataTimeSeg2) << 8U) | + ((fdcanInit->DataTimeSeg1) << 0U)); + + /* If FD_CAN AutoPrimaryRetransmission is ENABLE */ + if (fdcanInit->AutoPrimaryRetransmission == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_TPSS; + } + + /* If FD_CAN AutoSecondaryRetransmission is ENABLE */ + if (fdcanInit->AutoSecondaryRetransmission == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_TSSS; + } + + if (fdcanInit->FDCANSACK == FDCAN_SACK) + { + /* Set FD_CAN Self_Acknowledg */ + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_SACK; + } + + if (fdcanInit->ReceiveBufferStoreAllFrames == ENABLE) + { + /* Set FD_CAN receive buffer stores all frames */ + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_RBALL; + } +} +/** + * @brief Deinitializes the CANx peripheral registers to their default + * reset values. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @retval None + */ + +void FDCAN_DeInit(FDCAN_TypeDef* fdcan) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (fdcan == FDCAN1) + { + /* Enable CAN1 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN1, ENABLE); + /* Release CAN1 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN1, DISABLE); + } + + if (fdcan == FDCAN2) + { + /* Enable CAN2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN2, ENABLE); + /* Release CAN2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN2, DISABLE); + } + + if (fdcan == FDCAN3) + { + /* Enable CAN3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN3, ENABLE); + /* Release CAN3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN3, DISABLE); + } + + if (fdcan == FDCAN4) + { + /* Enable CAN4 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN4, ENABLE); + /* Release CAN4 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1PeriphRst_CAN4, DISABLE); + } +} + +/** + * @brief config can_ctrl in reset or run mode. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_Reset(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_RESET; + } + else + { + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_RESET; + } +} + +/** + * @brief config can_ctrl mode. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param Mode: Specifies the FDCAN mode + * This parameter can be any combination of the following values: + * @arg FDCAN_MODE_NORMAL + * @arg FDCAN_MODE_LOM + * @arg FDCAN_MODE_INTERNAL_LOOPBACK + * @arg FDCAN_MODE_EXTERNAL_LOOPBACK + * @retval None + */ +void FDCAN_ConfigMode(FDCAN_TypeDef* fdcan, uint32_t Mode) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_MODE(Mode)); + + /* Set FD_CAN Mode */ + fdcan->CAN_CMD_CTRL |= Mode; +} + + + +/** + * @brief config can_ctrl in reset or run mode. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param ReceiveBufferAlmostFullWarningLimit: Specifies the limit value of recevie buffer almost full + * The value of ReceiveBufferAlmostFullWarningLimit: 1 and 6 + * @retval None + */ +void FDCAN_SetRxBufAFWL(FDCAN_TypeDef* fdcan, uint32_t ReceiveBufferAlmostFullWarningLimit) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_RBUF_AF_LIMIT(ReceiveBufferAlmostFullWarningLimit)); + + /* get can int flag1 value */ + uint32_t can_int_flag1_value; + can_int_flag1_value = fdcan->CAN_INT_FLAG1; + + /* clear can int flag in this reg*/ + can_int_flag1_value = can_int_flag1_value & CAN_INT_FLAG1_MASK; + /* clear afwl value */ + can_int_flag1_value = can_int_flag1_value & ~CAN_INT_FLAG1_AFWL; + fdcan->CAN_INT_FLAG1 = (can_int_flag1_value | (ReceiveBufferAlmostFullWarningLimit << 28U)); +} + +/** + * @brief config can_ctrl in reset or run mode. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param ProgrammableErrorWarningLimit: Specifies the limit value of programmable error warning + * The value of ProgrammableErrorWarningLimit: 0 and 15 + * @retval None + */ + +void FDCAN_SetEWL(FDCAN_TypeDef* fdcan, uint32_t ProgrammableErrorWarningLimit) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_PROG_ERROR_WARN_LIMIT(ProgrammableErrorWarningLimit)); + + /* get can int flag1 value */ + uint32_t can_int_flag1_value; + can_int_flag1_value = fdcan->CAN_INT_FLAG1; + + /* clear can int flag in this reg*/ + can_int_flag1_value = can_int_flag1_value & CAN_INT_FLAG1_MASK; + /* clear ewl value */ + can_int_flag1_value = can_int_flag1_value & ~CAN_INT_FLAG1_EWL; + + /* Config ewl value */ + fdcan->CAN_INT_FLAG1 = (can_int_flag1_value | (ProgrammableErrorWarningLimit << 24U)); +} + +/** + * @brief config can_ctrl in reset or run mode. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param TransBufferSelect: Selects the trransmit buffer + * This parameter can be any combination of the following values: + * @arg FDCAN_SELECT_PTB + * @arg FDCAN_SELECT_STB + * @retval None + */ +void FDCAN_TransBufferSelect(FDCAN_TypeDef* fdcan, uint32_t TransBufferSelect) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_BUF_SEL(TransBufferSelect)); + if (TransBufferSelect == FDCAN_SELECT_STB) + { + /* Set FD_CAN TransBufferSelect is STB */ + fdcan->CAN_CMD_CTRL |= FDCAN_SELECT_STB; + } + else if (TransBufferSelect == FDCAN_SELECT_PTB) + { + /* Set FD_CAN TransBufferSelect is PTB */ + fdcan->CAN_CMD_CTRL &= ~FDCAN_SELECT_STB; + } +} + +/** + * @brief Select TTCAN trans buffer mode + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_TTCANTransBufferMode(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_TTTBM; + } + else + { + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_TTTBM; + } +} + + +/** + * @brief Start PTB trans + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_PTBTrans(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_TPE; + } + else + { + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_TPE; + } +} + +/** + * @brief Abort PTB trans + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_PTBAbort(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_TPA; + } + else + { + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_TPA; + } +} + +/** + * @brief Start STB trans + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param STBFifoPriorityMode the STB transmit fifo or priority Mode selection + * This parameter can be any combination of the following values: + * @arg FDCAN_STB_FIFO: stb in fifo mode + * @arg FDCAN_STB_PRIORITY: stb in priority mode + * @retval None + */ +void FDCAN_TransSTBMode(FDCAN_TypeDef* fdcan, uint32_t STBFifoPriorityMode) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_STB_FP_MODE(STBFifoPriorityMode)); + + /* Set FD_CAN STB transmit is fifo or priority */ + fdcan->CAN_CMD_CTRL |= STBFifoPriorityMode; + +} + +/** + * @brief Start STB trans + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param STBTransmitOneAllMode:Specifies the STB transmit one frame or all frame Mode selection + * @arg FDCAN_STB_NO_TRANSMIT + * @arg FDCAN_STB_NO_TRANSMIT_ONE + * @arg FDCAN_STB_NO_TRANSMIT_ALL + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_STBTrans(FDCAN_TypeDef* fdcan, uint32_t STBTransmitOneAllMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_STB_OA_MODE(STBTransmitOneAllMode)); + + uint32_t can_cmd_ctrl_value; + can_cmd_ctrl_value = fdcan->CAN_CMD_CTRL; + /* clr tsnext value */ + can_cmd_ctrl_value = (can_cmd_ctrl_value & (~CAN_CMD_CTRL_TSNEXT)); + + if (NewState == ENABLE) + { + /* Set FD_CAN STB transmit is one or all and don't set tsnext */ + fdcan->CAN_CMD_CTRL = (can_cmd_ctrl_value | STBTransmitOneAllMode); + } + else + { + fdcan->CAN_CMD_CTRL = (can_cmd_ctrl_value & (~STBTransmitOneAllMode)); + } +} + +/** + * @brief Abort STB trans + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_STBAbort(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_TSA; + } + else + { + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_TSA; + } +} + +/** + * @brief Get arbitration lost position + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @retval None + */ +uint8_t FDCAN_GetArbLostPosition(FDCAN_TypeDef* fdcan) +{ + uint8_t temp; + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + temp = ((fdcan->CAN_ERR_CNT) & CAN_ERR_CNT_ALC); + + return temp; +} + +/** + * @brief Get kind of error + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @retval None + */ +uint8_t FDCAN_GetKindOfError(FDCAN_TypeDef* fdcan) +{ + uint8_t temp; + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + temp = (((fdcan->CAN_ERR_CNT) & CAN_ERR_CNT_KOER) >> 5U); + + return temp; +} + +/** + * @brief Release RxBuffer + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_RxBufRelease(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_RREL; + } + else + { + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_RREL; + } +} + +/** + * @brief Enable CAN standby + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_StandbyMode(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_STBY; + } + else + { + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_STBY; + } +} + +/** + * @brief Enable CAN standby + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param FDCAN_ReceiveBufferOverflow_Mode: specifies the ROM value. + * This parameter can be any combination of the following values: + * @arg FDCAN_RECEIVE_OVERFLOW_OVERWRITTEN: ROM=0,The oldest message will be overwritten + * @arg FDCAN_RECEIVE_OVERFLOW_DISCARD: ROM=1,The new message will not be stored + * @retval None + */ +void FDCAN_RbufOverFlowMode(FDCAN_TypeDef* fdcan, uint32_t FDCAN_ReceiveBufferOverflow_Mode) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_RECEIVE_BUFFER_OVERFLOW_MODE(FDCAN_ReceiveBufferOverflow_Mode)); + + fdcan->CAN_CMD_CTRL |= FDCAN_ReceiveBufferOverflow_Mode; +} + + +/** @defgroup FDCAN_Exported_Functions_Group2 Configuration functions + * @brief FDCAN Configuration functions. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) FDCAN_ConfigFilter : Configure the FDCAN reception filters + (+) FDCAN_ConfigRxFifoOverwrite : Configure the Rx FIFO operation mode + (+) FDCAN_ConfigTimestampLocation : Configure the timestamp Location in SOF or EOF + (+) FDCAN_EnableTimestampCounter : Enable or Disable the timestamp counter + (+) FDCAN_ConfigTxDelayCompensation : Configure the transmitter delay compensation + (+) FDCAN_EnableTxDelayCompensation : Enable or Disable the transmitter delay compensation + (+) FDCAN_EnableISOMode : Enable ISO 11898-1 protocol mode + (+) FDCAN_DisableISOMode : Disable ISO 11898-1 protocol mode + +@endverbatim + * @{ + */ + +/** + * @brief Configure the FDCAN reception filter according to the specified + * parameters in the FDCAN_FilterTypeDef structure. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param sFilterConfig pointer to an FDCAN_FilterTypeDef structure that + * contains the filter configuration information + * This parameter can be any combination of the following values: + * @arg FilterAddress: Specifies the filter which will be initialized + * The value of FilterAddress: 0 and 15 + * @arg SelectAcceptanceMask: Enable or disable the filter mask + * The value of SelectAcceptanceMask: ENABLE + * DISABLE + * @arg FilterAcceptanceCODE: Specifies the filter identification + * The value of FilterAcceptanceCODE: 0 and 0x7FF for standard frames + * 0 and 0x1FFFFFFF for extended frames + * @arg FilterAcceptanceMASK: Specifies the filter acceptance mask + * 1: acceptance check for these bis of receive ID with AC_CODE disable + * 0: acceptance check for these bis of receive ID with AC_CODE enable + * The value of FilterAcceptanceMASK: 0 and 0x7FF for standard frames + * 0 and 0x1FFFFFFF for extended frames + * @arg FilterAcceptanceMaskIDECheck: Specifies the filter acceptance mask IDE bit check enable + * The value of FilterAcceptanceMaskIDECheck: FDCAN_ACCEP_MASK_AIDE_DISABLE + * FDCAN_ACCEP_MASK_AIDE_ENABLE + * @arg FilterAcceptanceMaskIDE: Specifies the filter acceptance mask IDE bit value + * The value of FilterAcceptanceMaskIDE: FDCAN_ACCEP_MASK_IDE_STANDARD + * FDCAN_ACCEP_MASK_IDE_EXTENDED + * @retval HAL status + */ + +void FDCAN_ConfigFilter(FDCAN_TypeDef* fdcan, FDCAN_FilterTypeDef* sFilterConfig) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_FILTER_ADDR(sFilterConfig->FilterAddress)); + assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->SelectAcceptanceMask)); + assert_param(IS_FDCAN_FILTER_ACODE(sFilterConfig->FilterAcceptanceCODE)); + assert_param(IS_FDCAN_FILTER_AMASK(sFilterConfig->FilterAcceptanceMASK)); + assert_param(IS_FDCAN_FILTER_AMASK_IDEE(sFilterConfig->FilterAcceptanceMaskIDECheck)); + assert_param(IS_FDCAN_FILTER_AMASK_IDE(sFilterConfig->FilterAcceptanceMaskIDE)); + + uint32_t CAN_FILTER_CTRL_VALUE; + /* GET CAN_FILTER_CTRL_VALUE */ + CAN_FILTER_CTRL_VALUE = fdcan->CAN_FILTER_CTRL; + /* CLR ACFADR BUT REMAIN OTHERS BITS*/ + CAN_FILTER_CTRL_VALUE = (CAN_FILTER_CTRL_VALUE & ~CAN_FILTER_CTRL_ACFADR); + /* CLR SELMASK */ + CAN_FILTER_CTRL_VALUE = (CAN_FILTER_CTRL_VALUE & ~CAN_FILTER_CTRL_SELMASK); + /* Set filter address, choose which filter be set */ + fdcan->CAN_FILTER_CTRL = (CAN_FILTER_CTRL_VALUE | sFilterConfig->FilterAddress); + + /* Set acceptance code */ + fdcan->CAN_ACF = (sFilterConfig->FilterAcceptanceCODE); + + /* If select acceptance mask, set mask value */ + if (sFilterConfig->SelectAcceptanceMask == ENABLE) + { + /* Select MASK, CAN_ACF Point to AMASK */ + fdcan->CAN_FILTER_CTRL |= CAN_FILTER_CTRL_SELMASK; + + /* Set mask value, 0 and 0x7FF for standard frames, 0 and 0x1FFFFFFF for extended frames */ + fdcan->CAN_ACF = (sFilterConfig->FilterAcceptanceMASK); + } + + /* If FilterAcceptanceMaskIDECheck is 0 AIDEE=0, Accept Filter accepts both standard and extended frames*/ + /* If FilterAcceptanceMaskIDECheck is 1 AIDEE=1, set FilterAcceptanceMaskIDE(accepts standard or extended frames)*/ + if (sFilterConfig->FilterAcceptanceMaskIDECheck == FDCAN_ACCEP_MASK_AIDE_ENABLE) + { + /* Set AIDEE, If AIDEE=1, Accept Filter accepts standard and extended frames decided by AIDE*/ + fdcan->CAN_ACF |= CAN_ACF_AIDEE; + + /* Set AIDE, If AIDEE=1,AIDE=0, only accept standard frames */ + /* Set AIDE, If AIDEE=1,AIDE=1, only accept extended frames */ + if (sFilterConfig->FilterAcceptanceMaskIDE == FDCAN_ACCEP_MASK_IDE_EXTENDED) + { + fdcan->CAN_ACF |= CAN_ACF_AIDE; + } + else if (sFilterConfig->FilterAcceptanceMaskIDE == FDCAN_ACCEP_MASK_IDE_STANDARD) + { + fdcan->CAN_ACF &= ~CAN_ACF_AIDE; + } + } +} + +/** + * @brief Configure the FDCAN reception filter according to the specified + * parameters in the FDCAN_FilterTypeDef structure. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param FDCAN_ACE: specifies the filter. + * This parameter can be any combination of the following values: + * @arg FDCAN_CAN_FILTER0: choose filter0 + * @arg FDCAN_CAN_FILTER1: choose filter1 + * @arg FDCAN_CAN_FILTER2: choose filter2 + * @arg FDCAN_CAN_FILTER3: choose filter3 + * @arg FDCAN_CAN_FILTER4: choose filter4 + * @arg FDCAN_CAN_FILTER5: choose filter5 + * @arg FDCAN_CAN_FILTER6: choose filter6 + * @arg FDCAN_CAN_FILTER7: choose filter7 + * @arg FDCAN_CAN_FILTER8: choose filter8 + * @arg FDCAN_CAN_FILTER9: choose filter9 + * @arg FDCAN_CAN_FILTER10: choose filter10 + * @arg FDCAN_CAN_FILTER11: choose filter11 + * @arg FDCAN_CAN_FILTER12: choose filter12 + * @arg FDCAN_CAN_FILTER13: choose filter13 + * @arg FDCAN_CAN_FILTER14: choose filter14 + * @arg FDCAN_CAN_FILTER15: choose filter15 + * @arg FDCAN_CAN_FILTER_ALL: choose all filter + * @param NewState: new state of the specified instance's TxDelay. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_EnableFilter(FDCAN_TypeDef* fdcan, uint32_t FDCAN_ACE, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_FILTER_ACE(FDCAN_ACE)); + + /* Set the Fdcan Filter NewState */ + if (NewState == ENABLE) + { + fdcan->CAN_FILTER_CTRL |= FDCAN_ACE; + } + else + { + fdcan->CAN_FILTER_CTRL &= ~FDCAN_ACE; + } +} + +/** + * @brief Select the Receive Buffer accept mode while full. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param FdcanRbOverMode: specifies the ROM. + * This parameter can be any combination of the following values: + * @arg FDCAN_RECEIVE_OVERFLOW_OVERWRITTEN: the new message will be writen in receive buffer + * @arg FDCAN_RECEIVE_OVERFLOW_DISCARD: the new message will not be written + * @retval None + */ +void FDCAN_ConfigRxFifoOverwrite(FDCAN_TypeDef* fdcan, uint32_t FdcanRbOverMode) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_RBUF_OVERFLOW_MODE(FdcanRbOverMode)); + + /* Set the Receive Buffer write mode while it's full */ + fdcan->CAN_CMD_CTRL |= FdcanRbOverMode; +} + + +/** + * @brief Select the Fdcan TimeStamp location. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param FdcanTimeStampLocation: specifies the TimeStamp Location. + * This parameter can be any combination of the following values: + * @arg FDCAN_TIMESTAMP_SOF: the TimeStamp in SOF + * @arg FDCAN_TIMESTAMP_EOF: the TimeStamp in EOF + * @retval None + */ +void FDCAN_ConfigTimestampLocation(FDCAN_TypeDef* fdcan, uint32_t FdcanTimeStampLocation) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_TIME_STAMP_LOCATION(FdcanTimeStampLocation)); + + /* Set the Fdcan TimeStamp Location SOF or EOF*/ + fdcan->CAN_FILTER_CTRL |= FdcanTimeStampLocation; +} + +/** + * @brief Enable or Disable the Fdcan TimeStamp. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's timestamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_EnableTimestampCounter(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Set the Fdcan TimeStamp NewState */ + if (NewState == ENABLE) + { + fdcan->CAN_FILTER_CTRL |= FDCAN_TIMESTAMP_ENABLE; + } + else + { + fdcan->CAN_FILTER_CTRL &= ~FDCAN_TIMESTAMP_ENABLE; + /* wait timestamp disable success */ + while ((fdcan->CAN_FILTER_CTRL & FDCAN_TIMESTAMP_DISABLE) == FDCAN_TIMESTAMP_DISABLE); + } +} + +/** + * @brief Config the txdelay value. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param FdcanTxDelayValue: specifies the TXDelay value. + * This parameter can be the range of 0~0x7F + * @retval None + */ +void FDCAN_ConfigTxDelayCompensation(FDCAN_TypeDef* fdcan, uint32_t FdcanTxDelayValue) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_TXDELAY_VALUE(FdcanTxDelayValue)); + + /* Set the Fdcan TimeStamp Location */ + fdcan->CAN_ERR_CNT |= (FdcanTxDelayValue << 8U); +} + +/** + * @brief Enable or Disable the txdelay. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param NewState: new state of the specified instance's TxDelay. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FDCAN_EnableTxDelayCompensation(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Set the Fdcan TxDelay NewState*/ + if (NewState == ENABLE) + { + fdcan->CAN_ERR_CNT |= FDCAN_TXDELAY_ENABLE; + } + else + { + fdcan->CAN_ERR_CNT &= ~FDCAN_TXDELAY_ENABLE; + /* wait txdelay disable success */ + while ((fdcan->CAN_ERR_CNT & FDCAN_TXDELAY_DISABLE) == FDCAN_TXDELAY_DISABLE); + } +} + +/** + * @brief Enable ISO 11898-1 protocol mode. + * CAN FD frame format is according to ISO 11898-1 standard. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @retval None + */ +void FDCAN_EnableISOMode(FDCAN_TypeDef* fdcan) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Enable ISO mode */ + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_FD_ISO; + +} + +/** + * @brief Disable ISO 11898-1 protocol mode. + * CAN FD frame format is according to Bosch CAN FD specification. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @retval None + */ +void FDCAN_DisableISOMode(FDCAN_TypeDef* fdcan) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Disable ISO mode */ + fdcan->CAN_CMD_CTRL &= ~CAN_CMD_CTRL_FD_ISO; + + /* Wait ISO bit clear */ + while ((fdcan->CAN_CMD_CTRL & CAN_CMD_CTRL_FD_ISO) == CAN_CMD_CTRL_FD_ISO); +} + + +/** @defgroup FDCAN_Exported_Functions_Group3 Configuration TxBuffer And Get RxBuffer + * @brief FDCAN Configuration TxBuffer And Get RxBuffer. + * +@verbatim + ============================================================================== + ##### Configuration functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) FDCAN_ConfigTxBuffer: Configure the FDCAN TxBuffer + (+) FDCAN_GetRxBuffer: Get the FDCAN RxBuffer + (+) FDCAN_GetArbLostCap: Get the FDCAN ArbitrationLostCapture + (+) FDCAN_GetErrorCnt: Get the FDCAN ErrorCounter TECNT, RECNT and KOER + (+) FDCAN_ConfigTsnext: Set TSNEXT and Clear by hardware + + @endverbatim + * @{ + */ + +/** + * @brief Config TxBuffer. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param TxHeader: specifies the TxBuffer config. + * @arg Identifier: Specifies the identifier + * The value of Identifier: 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + * 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + * @arg IdType: Specifies the identifier type for the transmitted message + * The value of IdType: FDCAN_STANDARD_ID + * FDCAN_EXTENDED_ID + * @arg TxFrameType: Specifies the frame type of the transmitted message + * The value of TxFrameType: FDCAN_DATA_FRAME + * FDCAN_REMOTE_FRAME + * @arg DataLength: Specifies the data length of the transmitted frame + * The value of DataLength: FDCAN_DLC_BYTES_0 + * FDCAN_DLC_BYTES_1 + * FDCAN_DLC_BYTES_2 + * FDCAN_DLC_BYTES_3 + * FDCAN_DLC_BYTES_4 + * FDCAN_DLC_BYTES_5 + * FDCAN_DLC_BYTES_6 + * FDCAN_DLC_BYTES_7 + * FDCAN_DLC_BYTES_8 + * FDCAN_DLC_BYTES_12 + * FDCAN_DLC_BYTES_16 + * FDCAN_DLC_BYTES_20 + * FDCAN_DLC_BYTES_24 + * FDCAN_DLC_BYTES_32 + * FDCAN_DLC_BYTES_48 + * FDCAN_DLC_BYTES_64 + * @arg BitRateSwitch: Specifies whether the Tx frame is transmitted with or without bit rate switching + * The value of BitRateSwitch: FDCAN_BRS_OFF + * FDCAN_BRS_ON + * @arg FDFormat: Specifies whether the Tx frame is transmitted in classic or FD format + * The value of FDFormat: FDCAN_CLASSIC_CAN + * FDCAN_FD_CAN + * @arg TTSEN: Specifies the enable if transmit Time-Stamp in CiA 603 + * The value of TTSEN: FDCAN_TTS_DISABLE + * FDCAN_TTS_ENABLE + * @retval None + */ +void FDCAN_ConfigTxBuffer(FDCAN_TypeDef* fdcan, FDCAN_TxHeaderTypeDef* TxHeader, uint8_t message_data[16][4]) +{ + uint32_t i; + + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_ID(TxHeader->Identifier)); + assert_param(IS_FDCAN_IDTYPE(TxHeader->IdType)); + assert_param(IS_FDCAN_FRAME_TYPE(TxHeader->TxFrameType)); + assert_param(IS_FDCAN_TYPE(TxHeader->FDFormat)); + assert_param(IS_FDCAN_BRS(TxHeader->BitRateSwitch)); + assert_param(IS_FDCAN_DATA_LENGTH(TxHeader->DataLength)); + assert_param(IS_FDCAN_TTS_STATE(TxHeader->TTSEN)); + + /* Config frame ID and TTSEN */ + fdcan->CAN_TRANSMIT_BUFFER0 = (TxHeader->Identifier | + TxHeader->TTSEN); + + /* Config IDE RTR FDF BRS and DLC*/ + fdcan->CAN_TRANSMIT_BUFFER1 = (TxHeader->IdType | /* Config id type */ + TxHeader->TxFrameType | /* Config frame type */ + TxHeader->FDFormat | /* Config fdcan format */ + TxHeader->BitRateSwitch | /* Config fdcan bit rate switch */ + TxHeader->DataLength); /* Config date length */ + + if (TxHeader->TxFrameType == FDCAN_DATA_FRAME) + { + if (TxHeader->DataLength == FDCAN_DLC_BYTES_1) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_2) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) | + (message_data[0][1] << 8) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_3) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) | + (message_data[0][1] << 8) | + (message_data[0][2] << 16) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_4) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) | + (message_data[0][1] << 8) | + (message_data[0][2] << 16) | + (message_data[0][3] << 24) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_5) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) | + (message_data[0][1] << 8) | + (message_data[0][2] << 16) | + (message_data[0][3] << 24) ; + + fdcan->CAN_TRANSMIT_BUFFER[1] = (message_data[1][0]) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_6) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) | + (message_data[0][1] << 8) | + (message_data[0][2] << 16) | + (message_data[0][3] << 24) ; + + fdcan->CAN_TRANSMIT_BUFFER[1] = (message_data[1][0]) | + (message_data[1][1] << 8) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_7) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) | + (message_data[0][1] << 8) | + (message_data[0][2] << 16) | + (message_data[0][3] << 24) ; + + fdcan->CAN_TRANSMIT_BUFFER[1] = (message_data[1][0]) | + (message_data[1][1] << 8) | + (message_data[1][2] << 16) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_8) + { + fdcan->CAN_TRANSMIT_BUFFER[0] = (message_data[0][0]) | + (message_data[0][1] << 8) | + (message_data[0][2] << 16) | + (message_data[0][3] << 24) ; + + fdcan->CAN_TRANSMIT_BUFFER[1] = (message_data[1][0]) | + (message_data[1][1] << 8) | + (message_data[1][2] << 16) | + (message_data[1][3] << 24) ; + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_12) + { + if (TxHeader->FDFormat != FDCAN_FD_CAN) + { + for (i = 0; i < 2; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + else + { + for (i = 0; i < 3; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_16) + { + if (TxHeader->FDFormat != FDCAN_FD_CAN) + { + for (i = 0; i < 2; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + else + { + for (i = 0; i < 4; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_20) + { + if (TxHeader->FDFormat != FDCAN_FD_CAN) + { + for (i = 0; i < 2; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + else + { + for (i = 0; i < 5; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_24) + { + if (TxHeader->FDFormat != FDCAN_FD_CAN) + { + for (i = 0; i < 2; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + else + { + for (i = 0; i < 6; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_32) + { + if (TxHeader->FDFormat != FDCAN_FD_CAN) + { + for (i = 0; i < 2; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + else + { + for (i = 0; i < 8; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_48) + { + if (TxHeader->FDFormat != FDCAN_FD_CAN) + { + for (i = 0; i < 2; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + else + { + for (i = 0; i < 11; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + } + if (TxHeader->DataLength == FDCAN_DLC_BYTES_64) + { + if (TxHeader->FDFormat != FDCAN_FD_CAN) + { + for (i = 0; i < 2; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + else + { + for (i = 0; i < 16; i++) + { + fdcan->CAN_TRANSMIT_BUFFER[i] = (message_data[i][0]) | + (message_data[i][1] << 8) | + (message_data[i][2] << 16) | + (message_data[i][3] << 24) ; + } + } + } + } +} + + +/** + * @brief Get RxBuffer. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param RxHeader: specifies the RxBuffer Value. + * This parameter can be any combination of the following values: + * @arg Identifier: Specifies the identifier + * The value of Identifier: 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID + * 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID + * @arg IdType: Specifies the identifier type of the received message + * The value of IdType: FDCAN_STANDARD_ID + * FDCAN_EXTENDED_ID + * @arg RxFrameType: Specifies the the received message frame type + * The value of RxFrameType: FDCAN_DATA_FRAME + * FDCAN_REMOTE_FRAME + * @arg DataLength: pecifies the received frame length + * The value of DataLength: FDCAN_DLC_BYTES_0 + * FDCAN_DLC_BYTES_1 + * FDCAN_DLC_BYTES_2 + * FDCAN_DLC_BYTES_3 + * FDCAN_DLC_BYTES_4 + * FDCAN_DLC_BYTES_5 + * FDCAN_DLC_BYTES_6 + * FDCAN_DLC_BYTES_7 + * FDCAN_DLC_BYTES_8 + * FDCAN_DLC_BYTES_12 + * FDCAN_DLC_BYTES_16 + * FDCAN_DLC_BYTES_20 + * FDCAN_DLC_BYTES_24 + * FDCAN_DLC_BYTES_32 + * FDCAN_DLC_BYTES_48 + * FDCAN_DLC_BYTES_64 + * @arg ErrorStateIndicator: Specifies the error state indicator + * The value of ErrorStateIndicator: FDCAN_ESI_ACTIVE + * FDCAN_ESI_PASSIVE + * @arg BitRateSwitch: Specifies whether the Rx frame is received with or without bit rate switching + * The value of BitRateSwitch: FDCAN_BRS_OFF + * FDCAN_BRS_ON + * @arg FDFormat: Specifies whether the Rx frame is received in classic or FD format + * The value of FDFormat: FDCAN_CLASSIC_CAN + * FDCAN_FD_CAN + * @arg RxKOER: Specifies the kind of ERROR of receive frames + * The value of RxKOER: FDCAN_NO_ERROR + * FDCAN_BIT_ERROR + * FDCAN_FORM_ERROR + * FDCAN_STUFF_ERROR + * FDCAN_ACK_ERROR + * FDCAN_CRC_ERROR + * FDCAN_OTHER_ERROR + * FDCAN_NOT_USED + * @arg CycleTime: Specifies the time-stamp cycle time only in TTCAN mode + * The value of CycleTime: This parameter must be a number between 0 and 0xFFFF + * @retval None + */ +void FDCAN_GetRxBuffer(FDCAN_TypeDef* fdcan, FDCAN_RxHeaderTypeDef* RxHeader, uint8_t message_data[16][4]) +{ + uint32_t i; + uint32_t j; + + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Get ID type */ + RxHeader->IdType = (fdcan->CAN_RECEIVE_BUFFER1 & FDCAN_EXTENDED_ID); + + /* Get ID value */ + RxHeader->Identifier = fdcan->CAN_RECEIVE_BUFFER0; + + /* Get Rx frame type */ + RxHeader->RxFrameType = (fdcan->CAN_RECEIVE_BUFFER1 & FDCAN_REMOTE_FRAME); + + /* Get FDCAN format */ + RxHeader->FDFormat = (fdcan->CAN_RECEIVE_BUFFER1 & FDCAN_FD_CAN); + + /* Get the error state indicator */ + RxHeader->ErrorStateIndicator = (fdcan->CAN_RECEIVE_BUFFER0 & FDCAN_ESI_PASSIVE); + + /* Get whether the Rx frame is received with or without bit rate switching*/ + RxHeader->BitRateSwitch = (fdcan->CAN_RECEIVE_BUFFER1 & FDCAN_BRS_ON); + + /* Get the kind of ERROR of receive frames */ + RxHeader->RxKOER = ((fdcan->CAN_RECEIVE_BUFFER1 & 0x0000E000) >> 13U); + + /* Get the time-stamp cycle time only in TTCAN mode */ + if ((fdcan->CAN_FILTER_CTRL & FDCAN_TIMESTAMP_ENABLE) == FDCAN_TIMESTAMP_ENABLE) + { + RxHeader->CycleTime = ((fdcan->CAN_RECEIVE_BUFFER1 & 0xffff0000) >> 16U); + } + + /* Get RX date length */ + RxHeader->DataLength = (fdcan->CAN_RECEIVE_BUFFER1 & FDCAN_DLC_BYTES_64); + + /* Only data frame can read rxbuf data */ + if (RxHeader->RxFrameType == FDCAN_DATA_FRAME) + { + /*Get Rx date value*/ + if (RxHeader->DataLength == FDCAN_DLC_BYTES_1) + { + uint32_t rbuf_data0_value; + rbuf_data0_value = fdcan->CAN_RECEIVE_BUFFER[0]; + message_data[0][0] = (rbuf_data0_value & 0x000000ff); + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_2) + { + uint32_t rbuf_data0_value; + rbuf_data0_value = fdcan->CAN_RECEIVE_BUFFER[0]; + message_data[0][0] = (rbuf_data0_value & 0x000000ff); + message_data[0][1] = ((rbuf_data0_value & 0x0000ff00) >> 8U); + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_3) + { + uint32_t rbuf_data0_value; + rbuf_data0_value = fdcan->CAN_RECEIVE_BUFFER[0]; + message_data[0][0] = (rbuf_data0_value & 0x000000ff); + message_data[0][1] = ((rbuf_data0_value & 0x0000ff00) >> 8U); + message_data[0][2] = ((rbuf_data0_value & 0x00ff0000) >> 16U); + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_4) + { + uint32_t rbuf_data0_value; + rbuf_data0_value = fdcan->CAN_RECEIVE_BUFFER[0]; + message_data[0][0] = (rbuf_data0_value & 0x000000ff); + message_data[0][1] = ((rbuf_data0_value & 0x0000ff00) >> 8U); + message_data[0][2] = ((rbuf_data0_value & 0x00ff0000) >> 16U); + message_data[0][3] = ((rbuf_data0_value & 0xff000000) >> 24U); + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_5) + { + uint32_t rbuf_data0_value; + uint32_t rbuf_data1_value; + rbuf_data0_value = fdcan->CAN_RECEIVE_BUFFER[0]; + rbuf_data1_value = fdcan->CAN_RECEIVE_BUFFER[1]; + message_data[0][0] = (rbuf_data0_value & 0x000000ff); + message_data[0][1] = ((rbuf_data0_value & 0x0000ff00) >> 8U); + message_data[0][2] = ((rbuf_data0_value & 0x00ff0000) >> 16U); + message_data[0][3] = ((rbuf_data0_value & 0xff000000) >> 24U); + + message_data[1][0] = (rbuf_data1_value & 0x000000ff); + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_6) + { + uint32_t rbuf_data0_value; + uint32_t rbuf_data1_value; + rbuf_data0_value = fdcan->CAN_RECEIVE_BUFFER[0]; + rbuf_data1_value = fdcan->CAN_RECEIVE_BUFFER[1]; + message_data[0][0] = (rbuf_data0_value & 0x000000ff); + message_data[0][1] = ((rbuf_data0_value & 0x0000ff00) >> 8U); + message_data[0][2] = ((rbuf_data0_value & 0x00ff0000) >> 16U); + message_data[0][3] = ((rbuf_data0_value & 0xff000000) >> 24U); + + message_data[1][0] = (rbuf_data1_value & 0x000000ff); + message_data[1][1] = ((rbuf_data1_value & 0x0000ff00) >> 8U); + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_7) + { + uint32_t rbuf_data0_value; + uint32_t rbuf_data1_value; + rbuf_data0_value = fdcan->CAN_RECEIVE_BUFFER[0]; + rbuf_data1_value = fdcan->CAN_RECEIVE_BUFFER[1]; + message_data[0][0] = (rbuf_data0_value & 0x000000ff); + message_data[0][1] = ((rbuf_data0_value & 0x0000ff00) >> 8U); + message_data[0][2] = ((rbuf_data0_value & 0x00ff0000) >> 16U); + message_data[0][3] = ((rbuf_data0_value & 0xff000000) >> 24U); + + message_data[1][0] = (rbuf_data1_value & 0x000000ff); + message_data[1][1] = ((rbuf_data1_value & 0x0000ff00) >> 8U); + message_data[1][2] = ((rbuf_data1_value & 0x00ff0000) >> 16U); + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_8) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_12) + { + if (RxHeader->FDFormat == FDCAN_CLASSIC_CAN) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + else + { + uint32_t message_data_one[3]; + for (i = 0; i < 3; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 3; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_16) + { + if (RxHeader->FDFormat == FDCAN_CLASSIC_CAN) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + else + { + uint32_t message_data_one[4]; + for (i = 0; i < 4; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 4; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_20) + { + if (RxHeader->FDFormat == FDCAN_CLASSIC_CAN) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + else + { + uint32_t message_data_one[5]; + for (i = 0; i < 5; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 5; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_24) + { + if (RxHeader->FDFormat == FDCAN_CLASSIC_CAN) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + else + { + uint32_t message_data_one[6]; + for (i = 0; i < 6; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 6; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_32) + { + if (RxHeader->FDFormat == FDCAN_CLASSIC_CAN) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + else + { + uint32_t message_data_one[8]; + for (i = 0; i < 8; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 8; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_48) + { + if (RxHeader->FDFormat == FDCAN_CLASSIC_CAN) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + else + { + uint32_t message_data_one[12]; + for (i = 0; i < 12; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 12; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + } + if (RxHeader->DataLength == FDCAN_DLC_BYTES_64) + { + if (RxHeader->FDFormat == FDCAN_CLASSIC_CAN) + { + uint32_t message_data_one[2]; + for (i = 0; i < 2; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 2; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + else + { + uint32_t message_data_one[16]; + for (i = 0; i < 16; i++) + { + message_data_one[i] = fdcan->CAN_RECEIVE_BUFFER[i]; + } + for (j = 0; j < 16; j++) + { + message_data[j][0] = (message_data_one[j] & 0x000000ff); + message_data[j][1] = ((message_data_one[j] & 0x0000ff00) >> 8U); + message_data[j][2] = ((message_data_one[j] & 0x00ff0000) >> 16U); + message_data[j][3] = ((message_data_one[j] & 0xff000000) >> 24U); + } + } + } + } +} + +/** + * @brief Get Arbitration Lost Capture Value. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param ArbLostCap: specifies the ALC value. + * This parameter can be any combination of the following values: + * @arg ArbitrationLostCapture:Specifies the bit position in the frame where the arbitration has been lost + * The value of ArbitrationLostCapture: This parameter must be a number between 0 and 31 + * @retval None + */ +void FDCAN_GetArbLostCap(FDCAN_TypeDef* fdcan, FDCAN_ArbitrationLostCaptureTypeDef* ArbLostCap) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Get ALC value */ + ArbLostCap->ArbitrationLostCapture = fdcan->CAN_ERR_CNT; +} + +/** + * @brief Get TECNT, RECNT and KOER. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param ErrorCnt: specifies the TECNT, RECNT and KOER value. + * This parameter can be any combination of the following values: + * @arg TxErrorCnt: Specifies the Transmit Error Counter Value + * The value of TxErrorCnt: This parameter can be a number between 0 and 255 + * @arg RxErrorCnt: Specifies the Receive Error Counter Value + * The value of RxErrorCnt: This parameter can be a number between 0 and 255 + * @arg KOER: Specifies the kind of Error + * The value of KOER: FDCAN_NO_ERROR + * FDCAN_BIT_ERROR + * FDCAN_FORM_ERROR + * FDCAN_STUFF_ERROR + * FDCAN_ACK_ERROR + * FDCAN_CRC_ERROR + * FDCAN_OTHER_ERROR + * FDCAN_NOT_USED + * @retval None + */ +void FDCAN_GetErrorCnt(FDCAN_TypeDef* fdcan, FDCAN_ErrorCountersTypeDef* ErrorCnt) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Get TECNT, RECNT and KOER */ + ErrorCnt->TxErrorCnt = ((fdcan->CAN_ERR_CNT & 0xff000000) >> 24U); + ErrorCnt->RxErrorCnt = ((fdcan->CAN_ERR_CNT & 0x00ff0000) >> 16U); + ErrorCnt->KOER = ((fdcan->CAN_ERR_CNT & 0x000000E0) >> 5U); +} + +/** + * @brief Get TECNT, RECNT and KOER. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @retval None + */ +void FDCAN_ConfigTsnext(FDCAN_TypeDef* fdcan) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + /* Set TSNEXT */ + fdcan->CAN_CMD_CTRL |= CAN_CMD_CTRL_TSNEXT; + + /* Wait TSNEXT be clear by hardware */ + while ((fdcan->CAN_CMD_CTRL & CAN_CMD_CTRL_TSNEXT) == CAN_CMD_CTRL_TSNEXT); +} + +/** + * @brief Get TECNT, RECNT and KOER. + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @retval None + */ +void FDCAN_ConfigInitialOffset(FDCAN_TypeDef* fdcan) +{ + /* Check the parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (fdcan == FDCAN1) + { + fdcan->CAN_INIT_CFG_OFFSET = 0x000; + } + + if (fdcan == FDCAN2) + { + fdcan->CAN_INIT_CFG_OFFSET = 0x0F4; + } + + if (fdcan == FDCAN3) + { + fdcan->CAN_INIT_CFG_OFFSET = 0x1E8; + } + + if (fdcan == FDCAN4) + { + fdcan->CAN_INIT_CFG_OFFSET = 0x2DC; + } +} + +/** @defgroup FDCAN_Exported_Functions_Group4 Interrupts management + * @brief Interrupts management + * +@verbatim + ============================================================================== + ##### Interrupts management ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) FDCAN_ActivateNotification : Enable interrupts + (+) FDCAN_DeactivateNotification : Disable interrupts + +@endverbatim + * @{ + */ + +/** + * @brief Enable interrupts. + * @param fdcan pointer to an FDCAN_TypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param FDCAN_INT_REG: specifies the int in which reg. + * This parameter can be one of the following values: + * FDCAN_INT_REG_FLAG1: int in CAN_INT_FLAG1 + * FDCAN_INT_REG_FLAG2: int in CAN_INT_FLAG2 + * @param ActiveITs indicates which interrupts will be enabled. + * This parameter can be any combination of the following values: + * FDCAN_IT_RECEIVE: Receive interrupt enable + * FDCAN_IT_RBUF_OVERRUN: Receive buffer overrun interrupt enable + * FDCAN_IT_RBUF_FULL: Receive buffer full interupt enable + * FDCAN_IT_RB_ALMOST_FULL: Receive buffer almost full interupt enable + * FDCAN_IT_TRANSMISSION_PRIMARY : Transmission primary successfully interupt enable + * FDCAN_IT_TRANSMISSION_SECONDARY: Transmission secondary successfully interupt enable + * FDCAN_IT_ERROR: Error interupt enable + * FDCAN_IT_ERROR_PASSIVE: Node is error passive interupt enable + * FDCAN_IT_ARBITRATION_LOST: Lost arbitration interupt enable + * FDCAN_IT_BUS_ERROR: Bus error interupt enable + * FDCAN_IT_TIME_TRIGGER: Time Trigger interupt enable + * FDCAN_IT_WATCH_TRIGGER: Watch Trigger interupt enable + * @retval None. + */ +void FDCAN_ActivateNotification(FDCAN_TypeDef* fdcan, uint32_t FDCAN_INT_REG, uint32_t ActiveITs) +{ + + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_IT(ActiveITs)); + assert_param(IS_FDCAN_INT_REG(FDCAN_INT_REG)); + + + if (FDCAN_INT_REG == FDCAN_INT_REG_FLAG1) + { + /* get can int enable value */ + uint32_t can_int_flag1_value; + can_int_flag1_value = fdcan->CAN_INT_FLAG1; + + /* clear can int flag in this reg*/ + can_int_flag1_value = can_int_flag1_value & CAN_INT_FLAG1_MASK; + + /* Enable choosed Interrupt */ + fdcan->CAN_INT_FLAG1 = can_int_flag1_value | ActiveITs; + } + + if (FDCAN_INT_REG == FDCAN_INT_REG_FLAG2) + { + /* Enable Interrupt */ + fdcan->CAN_INT_FLAG2 |= ActiveITs; + } +} + +/** + * @brief Disable interrupts. + * @param fdcan pointer to an FDCAN_TypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param FDCAN_INT_REG: specifies the int in which reg. + * This parameter can be one of the following values: + * FDCAN_INT_REG_FLAG1: int in CAN_INT_FLAG1 + * FDCAN_INT_REG_FLAG2: int in CAN_INT_FLAG2 + * @param InactiveITs indicates which interrupts will be disabled. + * This parameter can be any combination of @arg FDCAN_Interrupts: + * FDCAN_IT_RECEIVE: Receive interrupt enable + * FDCAN_IT_RBUF_OVERRUN: Receive buffer overrun interrupt enable + * FDCAN_IT_RBUF_FULL: Receive buffer full interupt enable + * FDCAN_IT_RB_ALMOST_FULL: Receive buffer almost full interupt enable + * FDCAN_IT_TRANSMISSION_PRIMARY : Transmission primary successfully interupt enable + * FDCAN_IT_TRANSMISSION_SECONDARY: Transmission secondary successfully interupt enable + * FDCAN_IT_ERROR: Error interupt enable + * FDCAN_IT_ERROR_PASSIVE: Node is error passive interupt enable + * FDCAN_IT_ARBITRATION_LOST: Lost arbitration interupt enable + * FDCAN_IT_BUS_ERROR: Bus error interupt enable + * FDCAN_IT_TIME_TRIGGER: Time Trigger interupt enable + * FDCAN_IT_WATCH_TRIGGER: Watch Trigger interupt enable + * @retval None. + */ +void FDCAN_DeactivateNotification(FDCAN_TypeDef* fdcan, uint32_t FDCAN_INT_REG, uint32_t InactiveITs) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_IT(InactiveITs)); + assert_param(IS_FDCAN_INT_REG(FDCAN_INT_REG)); + + if (FDCAN_INT_REG == FDCAN_INT_REG_FLAG1) + { + /* get can int enable value */ + uint32_t can_int_flag1_value; + can_int_flag1_value = fdcan->CAN_INT_FLAG1; + + /* clear can int flag in this reg*/ + can_int_flag1_value = can_int_flag1_value & CAN_INT_FLAG1_MASK; + + /* disable choosed int enable bit */ + fdcan->CAN_INT_FLAG1 = (can_int_flag1_value & (~InactiveITs)); + + if (((InactiveITs & FDCAN_IT_RECEIVE) != 0U) || ((InactiveITs & FDCAN_IT_RBUF_OVERRUN) != 0U) || \ + ((InactiveITs & FDCAN_IT_RBUF_FULL) != 0U) || ((InactiveITs & FDCAN_IT_RB_ALMOST_FULL) != 0U) || \ + ((InactiveITs & FDCAN_IT_TRANSMISSION_PRIMARY) != 0U) || ((InactiveITs & FDCAN_IT_TRANSMISSION_SECONDARY) != 0U) || \ + ((InactiveITs & FDCAN_IT_ERROR) != 0U) || ((InactiveITs & FDCAN_IT_ERROR_PASSIVE) != 0U) || \ + ((InactiveITs & FDCAN_IT_ARBITRATION_LOST) != 0U) || ((InactiveITs & FDCAN_IT_BUS_ERROR) != 0U)) + { + /* Wait choosed Interrupts are disabled */ + while ((fdcan->CAN_INT_FLAG1 & InactiveITs) == InactiveITs); + + } + + } + + if (FDCAN_INT_REG == FDCAN_INT_REG_FLAG2) + { + fdcan->CAN_INT_FLAG2 &= ~InactiveITs; + + /* Check which interrupts are enabled before */ + if (((InactiveITs & FDCAN_IT_TIME_TRIGGER) != 0U) || ((InactiveITs & FDCAN_IT_WATCH_TRIGGER) != 0U)) + { + /* Wait choosed Interrupts are disabled */ + while ((fdcan->CAN_INT_FLAG2 & InactiveITs) == InactiveITs); + } + } + +} +/** + * @} + */ + +/** + * @brief get single bit STAT status. + * @param fdcan pointer to an FDCAN_TypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param FDCAN_FLAG_REG: specifies the flag in which reg. + * This parameter can be one of the following values: + * FDCAN_FLAG_REG_CMD: flag in CAN_CMD_CTRL + * FDCAN_FLAG_REG_FLAG1: flag in CAN_INT_FLAG1 + * FDCAN_FLAG_REG_FLAG2: flag in CAN_INT_FLAG2 + * @param FDCAN_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * FDCAN_FLAG_ROV: receive buffer overflow + * FDCAN_FLAG_RACTIVE: receiving + * FDCAN_FLAG_TACTIVE: transmiting + * FDCAN_FLAG_EPIF: passive error interrupt flag + * FDCAN_FLAG_ALIF: arbit lose interrupt flag + * FDCAN_FLAG_BEIF: bus error interrupt flag + * FDCAN_FLAG_RIF: receive interrupr flag + * FDCAN_FLAG_ROIF: receive overflow interrupt flag + * FDCAN_FLAG_RFIF: receive full interrupt flag + * FDCAN_FLAG_RAFIF: receive almost full interrupr flag + * FDCAN_FLAG_TPIF: transmit primary interrupt flag + * FDCAN_FLAG_TSIF: transmit secondry interrupt flag + * FDCAN_FLAG_EIF: error interrupt flag + * FDCAN_FLAG_AIF: abort interrupr flag + * FDCAN_FLAG_WTIF: watch dog trig interrupt flag + * FDCAN_FLAG_TEIF: timer trig error interrupt flag + * FDCAN_FLAG_TTIF: timer trig interrupt flag + * @retval None. + */ +FlagStatus FDCAN_GetFlagStatus(FDCAN_TypeDef* fdcan, uint32_t FDCAN_FLAG_REG, uint32_t FDCAN_FLAG) +{ + FlagStatus bitstatus = RESET; + assert_param(IS_FDCAN_FLAG(FDCAN_FLAG)); + assert_param(IS_FDCAN_FLAG_REG(FDCAN_FLAG_REG)); + + if (FDCAN_FLAG_REG == FDCAN_FLAG_REG_CMD) + { + if ((fdcan->CAN_CMD_CTRL & FDCAN_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + if (FDCAN_FLAG_REG == FDCAN_FLAG_REG_FLAG1) + { + if ((fdcan->CAN_INT_FLAG1 & FDCAN_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + if (FDCAN_FLAG_REG == FDCAN_FLAG_REG_FLAG2) + { + if ((fdcan->CAN_INT_FLAG2 & FDCAN_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief get single bit STAT status. + * @param fdcan pointer to an FDCAN_TypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param FDCAN_FLAG_REG: specifies the flag in which reg. + * This parameter can be one of the following values: + * FDCAN_FLAG_REG_FLAG1: flag in CAN_INT_FLAG1 + * FDCAN_FLAG_REG_FLAG2: flag in CAN_INT_FLAG2 + * @param FDCAN_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * FDCAN_FLAG_EPIF: passive error interrupt flag + * FDCAN_FLAG_ALIF: arbit lose interrupt flag + * FDCAN_FLAG_BEIF: bus error interrupt flag + * FDCAN_FLAG_RIF: receive interrupr flag + * FDCAN_FLAG_ROIF: receive overflow interrupt flag + * FDCAN_FLAG_RFIF: receive full interrupt flag + * FDCAN_FLAG_RAFIF: receive almost full interrupr flag + * FDCAN_FLAG_TPIF: transmit primary interrupt flag + * FDCAN_FLAG_TSIF: transmit secondry interrupt flag + * FDCAN_FLAG_EIF: error interrupt flag + * FDCAN_FLAG_AIF: abort interrupr flag + * FDCAN_FLAG_WTIF: watch dog trig interrupt flag + * FDCAN_FLAG_TEIF: timer trig error interrupt flag + * FDCAN_FLAG_TTIF: timer trig interrupt flag + * FDCAN_FLAG_RTIF_ALL: can_rtif all flag + * @retval None. + */ +void FDCAN_ClearInterruptFlag(FDCAN_TypeDef* fdcan, uint32_t FDCAN_FLAG_REG, uint32_t FDCAN_FLAG) +{ + assert_param(IS_FDCAN_FLAG(FDCAN_FLAG)); + assert_param(IS_FDCAN_FLAG_REG(FDCAN_FLAG_REG)); + + if (FDCAN_FLAG_REG == FDCAN_FLAG_REG_FLAG1) + { + /* get can int enable value */ + uint32_t can_int_flag1_value; + can_int_flag1_value = fdcan->CAN_INT_FLAG1; + + /* clear can int flag in this reg*/ + can_int_flag1_value = can_int_flag1_value & CAN_INT_FLAG1_MASK; + + fdcan->CAN_INT_FLAG1 = (can_int_flag1_value | FDCAN_FLAG); + } + else if (FDCAN_FLAG_REG == FDCAN_FLAG_REG_FLAG2) + { + fdcan->CAN_INT_FLAG2 |= FDCAN_FLAG; + } +} + +/** + * @brief get dual bits STAT status. + * @param fdcan pointer to an FDCAN_TypeDef structure that contains + * the configuration information for the specified FDCAN. + * @param FDCAN_BUF_TYPE: specifies the buffer status. + * This parameter can be one of the following values: + * @arg FDCAN_TRANS_BUFFER_STAT: Transmission Secondary buffer Status + * @arg FDCAN_RECEIVE_BUFFER_STAT: Receive buffer status + * + * @retval None. + */ +int FDCAN_GetFifoStatus(FDCAN_TypeDef* fdcan, uint32_t FDCAN_BUF_TYPE) +{ + int dual_bitstatus = Empty; + + if (FDCAN_BUF_TYPE == FDCAN_TRANS_BUFFER_STAT) + { + if (((fdcan->CAN_CMD_CTRL & FDCAN_TBUF_FULL) >> 16) == 0x0) + { + dual_bitstatus = Empty; + } + else if (((fdcan->CAN_CMD_CTRL & FDCAN_TBUF_FULL) >> 16) == 0x1) + { + dual_bitstatus = Less_HalfFull; + } + else if (((fdcan->CAN_CMD_CTRL & FDCAN_TBUF_FULL) >> 16) == 0x2) + { + dual_bitstatus = More_HalfFull; + } + else if (((fdcan->CAN_CMD_CTRL & FDCAN_TBUF_FULL) >> 16) == 0x3) + { + dual_bitstatus = Full; + } + } + else if (FDCAN_BUF_TYPE == FDCAN_RECEIVE_BUFFER_STAT) + { + if (((fdcan->CAN_CMD_CTRL & FDCAN_RBUF_FULL) >> 24) == 0x0) + { + dual_bitstatus = Empty; + } + else if (((fdcan->CAN_CMD_CTRL & FDCAN_RBUF_FULL) >> 24) == 0x1) + { + dual_bitstatus = Less_HalfFull; + } + else if (((fdcan->CAN_CMD_CTRL & FDCAN_RBUF_FULL) >> 24) == 0x2) + { + dual_bitstatus = More_HalfFull; + } + else if (((fdcan->CAN_CMD_CTRL & FDCAN_RBUF_FULL) >> 24) == 0x3) + { + dual_bitstatus = Full; + } + } + return dual_bitstatus; +} + + +/** + * @brief Set reference message + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param FDCAN_REF_MSG_IDE:ref_msg id type + * This parameter can be any combination of the following values: + * @arg FDCAN_REF_MSG_STD:standard id + * @arg FDCAN_REF_MSG_EXT:externed id + * @param FDCAN_REF_MSG_ID:reference id value + * @retval None + */ + +void FDCAN_RefMessageSet(FDCAN_TypeDef* fdcan, uint32_t FDCAN_REF_MSG_IDE, uint32_t FDCAN_REF_MSG_ID) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_REF_MSG_IDTYPE(FDCAN_REF_MSG_IDE)); + assert_param(IS_FDCAN_REF_MSG_ID_VALUE(FDCAN_REF_MSG_ID)); + + fdcan->CAN_REF_MSG = (FDCAN_REF_MSG_IDE | FDCAN_REF_MSG_ID); +} + +/** + * @brief Set reference message + * @param fdcan: specifies the instance. + * This parameter can be any combination of the following values: + * @arg FDCAN1: the instance is can1 + * @arg FDCAN2: the instance is can2 + * @arg FDCAN3: the instance is can3 + * @arg FDCAN4: the instance is can4 + * @param FDCAN_TBPTR:point tbuf ptb or stb + * @retval None + */ + +void FDCAN_TbufSoltPoint(FDCAN_TypeDef* fdcan, uint32_t FDCAN_TBPTR) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_TBPTR_VALUE(FDCAN_TBPTR)); + + /* CLR OLD TBPTR VALUE */ + uint32_t CAN_INT_FLAG2_VALUE; + CAN_INT_FLAG2_VALUE = fdcan->CAN_INT_FLAG2; + CAN_INT_FLAG2_VALUE = (CAN_INT_FLAG2_VALUE & ~CAN_INT_FLAG2_TBPTR); + /* SET NEW TBPTR VALUE */ + fdcan->CAN_INT_FLAG2 = ((FDCAN_TBPTR << 16U) | CAN_INT_FLAG2_VALUE); +} + +void FDCAN_TransmitSoltPoint(FDCAN_TypeDef* fdcan, uint32_t FDCAN_TTPTR) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_TTPTR_VALUE(FDCAN_TTPTR)); + + /* CLR OLD TTPTR VALUE */ + uint32_t CAN_TRG_CFG_VALUE; + CAN_TRG_CFG_VALUE = fdcan->CAN_TRIG_CFG; + CAN_TRG_CFG_VALUE = (CAN_TRG_CFG_VALUE & ~CAN_TRIG_CFG_TTPTR); + CAN_TRG_CFG_VALUE = (CAN_TRG_CFG_VALUE & ~0xFFFF0000); + /* SET NEW TTPTR VALUE */ + fdcan->CAN_TRIG_CFG = (FDCAN_TTPTR | CAN_TRG_CFG_VALUE); +} + + +void FDCAN_SetTbufSoltEmpty(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_INT_FLAG2 |= CAN_INT_FLAG2_TBE; + while ((fdcan->CAN_INT_FLAG2 & CAN_INT_FLAG2_TBE) == CAN_INT_FLAG2_TBE); + } + else if (NewState == DISABLE) + { + fdcan->CAN_INT_FLAG2 &= ~CAN_INT_FLAG2_TBE; + } +} + +void FDCAN_SetTbufSoltFull(FDCAN_TypeDef* fdcan, FunctionalState NewState) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + fdcan->CAN_INT_FLAG2 |= CAN_INT_FLAG2_TBF; + while ((fdcan->CAN_INT_FLAG2 & CAN_INT_FLAG2_TBF) == CAN_INT_FLAG2_TBF); + } + else if (NewState == DISABLE) + { + fdcan->CAN_INT_FLAG2 &= ~CAN_INT_FLAG2_TBF; + } +} + +void FDCAN_TimeTrigEnable(FDCAN_TypeDef* fdcan, FunctionalState NewState)/* Function used enbale tten*/ +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + /* Set the Time_Triger Enable */ + fdcan->CAN_INT_FLAG2 |= CAN_INT_FLAG2_TTEN; + } + else if (NewState == DISABLE) + { + /* clr the Time_Triger Enable */ + fdcan->CAN_INT_FLAG2 &= ~CAN_INT_FLAG2_TTEN; + } +} +/** + * @param FDCAN_TIMEPOS:time stamp position + * This parameter can be any combination of the following values: + * @arg FDCAN_TIMEPOS_SOF:time stamp position in sof + * @arg FDCAN_TIMEPOS_EOF:time stamp position in eof +*/ +void FDCAN_TimeStampPosition(FDCAN_TypeDef* fdcan, uint32_t FDCAN_TIMEPOS)/* Function used set timepos*/ +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + assert_param(IS_FDCAN_TIME_POS(FDCAN_TIMEPOS)); + + if (FDCAN_TIMEPOS == FDCAN_TIMEPOS_SOF) + { + /* Set the Time_Stamp Position in SOF */ + fdcan->CAN_FILTER_CTRL &= ~CAN_FILTER_CTRL_TIMEPOS; + } + else if (FDCAN_TIMEPOS == FDCAN_TIMEPOS_EOF) + { + /* Set the Time_Stamp Position in EOF */ + fdcan->CAN_FILTER_CTRL |= FDCAN_TIMEPOS_EOF; + } +} + +void FDCAN_TimeStampEnable(FDCAN_TypeDef* fdcan, FunctionalState NewState)/* Function used enbale timestamp*/ +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + if (NewState == ENABLE) + { + /* Set the Time_Stamp Enable */ + fdcan->CAN_FILTER_CTRL |= CAN_FILTER_CTRL_TIMEEN; + } + else if (NewState == DISABLE) + { + /* Clr the Time_Stamp Enable */ + fdcan->CAN_FILTER_CTRL &= ~CAN_FILTER_CTRL_TIMEEN; + } +} + +void FDCAN_GetCanTransmisionTs(FDCAN_TypeDef* fdcan, uint32_t can_transmission_ts[2]) +{ + /* Check function parameters */ + assert_param(IS_FDCAN_ALL_INSTANCE(fdcan)); + + uint32_t i; + for (i = 0; i < 2; i++) + { + can_transmission_ts[i] = fdcan->CAN_TRANSMISION_TS[i]; + } + +} + + +/** + * @} + */ + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_flash.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_flash.c new file mode 100644 index 00000000000..b6b1f61f3f0 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_flash.c @@ -0,0 +1,900 @@ +/** + ****************************************************************************** + * @file ft32f4xx_flash.c + * @author FMD xzhang + * @brief This file provides firmware functions to manage the following + * functionalities of the FLASH peripheral: + * - FLASH Interface configuration + * - FLASH Memory Programming + * - Option Bytes Programming + * - Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-13 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_flash.h" + +/** + * @brief Sets the code latency value. + * @param FLASH_Latency: specifies the FLASH Latency value. + * This parameter can be one of the following values: + * @arg FLASH_Latency_0: FLASH 0 Latency cycle + * @arg FLASH_Latency_1: FLASH 1 Latency cycle + * @arg FLASH_Latency_2: FLASH 2 Latency cycle + * @arg FLASH_Latency_3: FLASH 3 Latency cycle + * @arg FLASH_Latency_4: FLASH 4 Latency cycle + * @arg FLASH_Latency_5: FLASH 5 Latency cycle + * @arg FLASH_Latency_6: FLASH 6 Latency cycle + * @arg FLASH_Latency_7: FLASH 7 Latency cycle + * @retval None + */ +void FLASH_SetLatency(uint32_t FLASH_Latency) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_FLASH_LATENCY(FLASH_Latency)); + + /* Read the RDC register */ + tmpreg = FLASH->RDC; + + /* Sets the Latency value */ + tmpreg &= (uint32_t)(~((uint32_t)FLASH_RDC_LATENCY)); + tmpreg |= FLASH_Latency; + + /* Write the RDC register */ + FLASH->RDC = tmpreg; +} + +/** + * @brief Enables or disables the Prefetch Buffer. + * @param NewState: new state of the FLASH prefetch buffer. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_PrefetchBufferCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + FLASH->RDC |= FLASH_RDC_PRFTBE ; + } + else + { + FLASH->RDC &= ~FLASH_RDC_PRFTBE; + } +} + +/** + * @brief Checks whether the FLASH Prefetch Buffer status is set or not. + * @param None + * @retval FLASH Prefetch Buffer Status (SET or RESET). + */ +FlagStatus FLASH_GetPrefetchBufferStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((FLASH->RDC & FLASH_RDC_PRFTBS) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */ + return bitstatus; +} + +/** + * @brief UnLocks the Program memory access. + * @param None + * @retval None + */ +void FLASH_Unlock(void) +{ + unsigned int read_data; + do + { + read_data = FLASH->FR ; + } + while ((read_data & FLASH_FR_BSY) != 0); + /*KEYR write key1 0x45670123 key2 0xCDEF89AB*/ + if ((FLASH->WRC & FLASH_WRC_LOCK) != 0) + { + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + } +} +/** + * @brief Locks the Program memory access. + * @param None + * @retval None + */ +void FLASH_Lock(void) +{ + /* Set the LOCK Bit to lock the FLASH control register and program memory access */ + FLASH->WRC |= FLASH_WRC_LOCK; +} + + +/** + * @brief Erases a specified page in program memory. + * @note To correctly run this function, the FLASH_Unlock() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param page_num: The page number in program memory to be erased. + * @param erase_size: The size of erase : + * This parameter can be: + * @arg ERASE_SIZE_0:Erase size is 512B (default value) + * @arg ERASE_SIZE_1: Erase size is 2KB + * @arg ERASE_SIZE_2: Erase size is 16KB + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of 512 bytes). + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t page_num, uint32_t erase_size) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t erase_page_num; + + /* Check the parameters */ + assert_param(IS_FLASH_ERASE_PAGE_NUM(page_num)); + assert_param(IS_ERASE_SIZE(erase_size)); + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to erase the page */ + /*PNB in bit6-15 of WRC reg*/ + erase_page_num = (page_num << 6); + /*clear status flag*/ + FLASH->FR |= FLASH_FR_CLEAR; + /*clear page number*/ + FLASH->WRC &= (~FLASH_WRC_PNB); + /*Active page Erase function*/ + FLASH->WRC |= FLASH_WRC_PER; + /*select erase size*/ + FLASH->WRC |= erase_size; + /*Page ERASE ERASE start*/ + FLASH->WRC |= (erase_page_num) | FLASH_WRC_STRT; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + /*clear FLASH_WRC_PER & FLASH_WRC_STRT*/ + FLASH->WRC &= (~FLASH_WRC_STRT) & (~FLASH_WRC_PER); + + } + + FLASH_PrefetchBufferCmd(ENABLE); + /* Return the Erase Status */ + return status; +} + + +/** + * @brief Erases all FLASH pages. + * @note To correctly run this function, the FLASH_Unlock() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param None + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + + /* If the previous operation is completed, proceed to erase the page */ + /*clear status flag; clear page numbe; ERASE start*/ + FLASH->FR |= FLASH_FR_CLEAR; + FLASH->WRC |= FLASH_WRC_MER | FLASH_WRC_STRT; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + /*clear FLASH_WRC_MER & FLASH_WRC_STRT*/ + FLASH->WRC &= (~FLASH_WRC_MER) & (~FLASH_WRC_STRT); + + } + + FLASH_PrefetchBufferCmd(ENABLE); + + return status; +} + +/** + * @brief Programs 4 word continued at a specified address. + * @note To correctly run this function, the FLASH_Unlock() FLASH_ErasePage() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed,address is the first address of Data0 + * @param Datax: specifies the 4 data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data3, uint32_t Data2, uint32_t Data1, uint32_t Data0) +{ + /*clear status flag*/ + FLASH->FR |= FLASH_FR_CLEAR; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + //enable function of program firstly + FLASH->WRC |= FLASH_WRC_PG; + + /* proceed to program the data3 */ + *(__IO uint32_t*)Address = (uint32_t)Data0; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new word */ + *(__IO uint32_t*)(Address + 0x4) = (uint32_t) Data1; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + if (status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new word */ + *(__IO uint32_t*)(Address + 0x8) = (uint32_t) Data2; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + /* If the previous operation is completed, proceed to program the new word */ + *(__IO uint32_t*)(Address + 0xc) = (uint32_t) Data3; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PG Bit */ + FLASH->WRC &= ~FLASH_WRC_PG; + } + } + } + + } + else + { + /* Disable the PG Bit */ + FLASH->WRC &= ~FLASH_WRC_PG; + } + FLASH_PrefetchBufferCmd(ENABLE); + + return status; +} + + +/** + * @brief Programs a word at a specified address. + * @note To correctly run this function, the FLASH_Unlock() FLASH_ErasePage() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed + * @param Data0: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_Program_oneWord(uint32_t Address, uint32_t Data0) +{ + /*clear status flag*/ + FLASH->FR |= FLASH_FR_CLEAR; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + //enable function of program firstly + FLASH->WRC |= FLASH_WRC_PG; + + /* proceed to program the data3 */ + *(__IO uint32_t*)Address = (uint32_t)Data0; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + /* Disable the PG Bit */ + FLASH->WRC &= ~FLASH_WRC_PG; + } + else + { + /* Disable the PG Bit */ + FLASH->WRC &= ~FLASH_WRC_PG; + } + + FLASH_PrefetchBufferCmd(ENABLE); + return status; +} +/** + * @brief Programs a half word at a specified address. + * @note To correctly run this function, the FLASH_Unlock() FLASH_ErasePage() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed,address is the first address of Datax. + * @param Datax: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_Program_HalfWord(uint32_t Address, uint16_t Data0) +{ + /*clear status flag*/ + FLASH->FR |= FLASH_FR_CLEAR; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + //enable function of program + FLASH->WRC |= FLASH_WRC_PG; + /* proceed to program the data0 */ + *(__IO uint16_t*)Address = (uint16_t)Data0; + + while ((FLASH->FR & FLASH_FR_BSY) != 0); + + /* Disable the PG Bit */ + FLASH->WRC &= ~FLASH_WRC_PG; + } + else + { + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + + FLASH_PrefetchBufferCmd(ENABLE); + return status; +} + + +/** + * @brief Programs 1 Byte at a specified address. + * @note To correctly run this function, the FLASH_Unlock() FLASH_ErasePage() function must be called before. + * @note Call the FLASH_Lock() to disable the flash memory access (recommended + * to protect the FLASH memory against possible unwanted operation) + * @param Address: specifies the address to be programmed,address is the first address of Datax. + * @param Datax: specifies the data to be programmed. + * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_Program_Byte(uint32_t Address, uint8_t Data0) +{ + /*clear status flag*/ + FLASH->FR |= FLASH_FR_CLEAR; + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status == FLASH_COMPLETE) + { + /*enable function of program*/ + FLASH->WRC |= FLASH_WRC_PG; + + /*proceed to program the data3 */ + *(__IO uint8_t*)Address = (uint8_t)Data0; + + while ((FLASH->FR & FLASH_FR_BSY) != 0); + + /* Disable the PG Bit */ + FLASH->WRC &= ~FLASH_WRC_PG; + } + else + { + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + } + + FLASH_PrefetchBufferCmd(ENABLE); + return status; +} + +/** + * @brief Unlocks the option bytes block access. + * @param None + * @retval None + */ +void FLASH_OPBC_Unlock(void) +{ + unsigned int read_data; + + do + { + read_data = FLASH->FR ; + } + /*flash is not busy now*/ + while ((read_data & FLASH_FR_BSY) != 0); + + /*option byte is unlock*/ + if ((FLASH->OPBC & FLASH_OPBC_OPTLOCK) != 0) + { + /* Unlocking the option bytes block access */ + FLASH->OPTKEYR = FLASH_OPTKEY1; + FLASH->OPTKEYR = FLASH_OPTKEY2; + } +} + +/** + * @brief Locks the option bytes block access. + * @param None + * @retval None + */ +void FLASH_OPBC_Lock(void) +{ + /* Set the OPTLOCK Bit to lock the option bytes block access */ + FLASH->OPBC |= FLASH_OPBC_OPTLOCK; +} + + +/** + * @brief Write protects the desired pages + * @note To correctly run this function, the FLASH_OPBC_Unlock() function must be called before. + * @note Call the FLASH_OPBC_lock() to disable the flash control register access and the option after FLASH_OPBC_Unlock + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param WRPR_WRP: specifies the address of the pages to be write protected. + * This parameter can be: + * @arg WRP_PAGE0_31 to WRP_PAGE992_1023 + * @arg WRP_AllPAGES + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WRPR_EnableWRP(uint32_t WRPR_WRP) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check the parameters */ + assert_param(IS_WRPR_WRP(WRPR_WRP)); + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + if (status == FLASH_COMPLETE) + { + FLASH->WRPR = WRPR_WRP; + FLASH->OPBC |= FLASH_OPBC_OPTSTRT;//update OPBC reg value + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTSTART Bit */ + FLASH->OPBC &= ~FLASH_OPBC_OPTSTRT; + } + } + + FLASH_PrefetchBufferCmd(ENABLE); + return status; +} + + +/** + * @brief Enables or disables the read out protection. + * @note To correctly run this function, the FLASH_OPBC_Unlock() function must be called before. + * @note Call the FLASH_OPBC_lock() to disable the flash control register access and the option after FLASH_OPBC_Unlock + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param FLASH_ReadProtection_Level: specifies the read protection level. + * This parameter can be: + * @arg OPBC_RDP_Level_0: Read protection 0 of the memory + * @arg OPBC_RDP_Level_1: Read protection 1 of the memory + * @arg OPBC_RDP_Level_2: Read protection 2 of the memory (Be CAREFUL !! to use protection 2) + * @note When enabling OPBC_RDP level 2 it's no more possible to go back to level 1 or 0 + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OPBC_RDPConfig(uint8_t OPBC_RDP) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OPBC_RDP(OPBC_RDP)); + + uint32_t opbc_data; + opbc_data = (FLASH->OPBC); + opbc_data &= ~(0xff << 8); + opbc_data |= (OPBC_RDP << 8); + + FLASH_PrefetchBufferCmd(DISABLE); + + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + if (status == FLASH_COMPLETE) + { + FLASH->OPBC = opbc_data | FLASH_OPBC_OPTSTRT ; + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + if (status != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTSTART Bit */ + FLASH->OPBC &= ~FLASH_OPBC_OPTSTRT; + } + } + + FLASH_PrefetchBufferCmd(ENABLE); + return status; +} + + +/** + * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + * @note To correctly run this function, the FLASH_OPBC_Unlock() function must be called before. + * @note Call the FLASH_OPBC_lock() to disable the flash control register access and the optio after FLASH_OPBC_Unlock + * bytes (recommended to protect the FLASH memory against possible unwanted operation) + * @param OPBC_IWDG: Selects the WDG mode + * This parameter can be one of the following values: + * @arg OPBC_IWDG_SW: Software WDG selected 1 + * @arg OPBC_IWDG_HW: Hardware WDG selected 0 + * @param OPBC_STOP: Reset event when entering STOP mode. + * This parameter can be one of the following values: + * @arg OPBC_STOP_NoRST: No reset generated when entering in STOP + * @arg OPBC_STOP_RST: Reset generated when entering in STOP + * @param OPBC_STDBY: Reset event when entering Standby mode. + * This parameter can be one of the following values: + * @arg OPBC_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OPBC_STDBY_RST: Reset generated when entering in STANDBY + * @retval FLASH Status: The returned value can be: + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_OPBC_UserConfig(uint8_t OPBC_IWDG, uint8_t OPBC_STOP, uint8_t OPBC_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OPBC_IWDG_SOURCE(OPBC_IWDG)); + assert_param(IS_OPBC_STOP_SOURCE(OPBC_STOP)); + assert_param(IS_OPBC_STDBY_SOURCE(OPBC_STDBY)); + + FLASH_PrefetchBufferCmd(DISABLE); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + uint32_t opbc_data; + opbc_data = (FLASH->OPBC); + opbc_data &= ~(0xff); + opbc_data |= OPBC_IWDG | OPBC_STOP | OPBC_STDBY; + + + if (status == FLASH_COMPLETE) + { + FLASH->OPBC = (opbc_data | FLASH_OPBC_OPTSTRT); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTPG Bit */ + FLASH->OPBC &= ~FLASH_OPBC_OPTSTRT; + } + } + + FLASH_PrefetchBufferCmd(ENABLE); + /* Return the Option Byte program Status */ + return status; +} + + +/** + * @brief Set the BOR Level. + * @note To correctly run this function, the FLASH_OPBC_Unlock() function must be called before. + * @param BORR_Level specifies the Option Bytes posedge threshold voltage Level. + * This parameter can be one of the following values: + * @arg OPBC_BORR_LEVEL0: Supply threshold voltage 2.1v + * @arg OPBC_BORR_LEVEL1: Supply threshold voltage 2.3v + * @arg OPBC_BORR_LEVEL2: Supply threshold voltage 2.6v + * @arg OPBC_BORR_LEVEL3: Supply threshold voltage 2.9v + * @param BORF_Level specifies the Option Bytes negedge threshold voltage Level. + * This parameter can be one of the following values: * + * @arg OPBC_BORF_LEVEL0: Supply threshold voltage 2.0v + * @arg OPBC_BORF_LEVEL1: Supply threshold voltage 2.2v + * @arg OPBC_BORF_LEVEL2: Supply threshold voltage 2.5v + * @arg OPBC_BORF_LEVEL3: Supply threshold voltage 2.8v + * @param NewState: new state of the configed undervoltage reset :BOR_EN. + * This parameter can be: ENABLE or DISABLE. + * @retval HAL Status + */ +FLASH_Status FLASH_OPBC_BOR_LevelConfig(uint32_t BORR_Level, uint32_t BORF_Level, FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + + /* Check the parameters */ + assert_param(IS_OPBC_BORR_LEVEL(BORR_Level)); + assert_param(IS_OPBC_BORF_LEVEL(BORR_Level)); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + FLASH_PrefetchBufferCmd(DISABLE); + + uint32_t opbc_data; + opbc_data = (FLASH->OPBC); + opbc_data &= ~(0xff << 16); + opbc_data |= BORR_Level | BORF_Level; + + + if (NewState != DISABLE) + { + if (status == FLASH_COMPLETE) + { + /*enable configed undervoltage reset,config BOR Level,Wait for last operation to be completed*/ + FLASH->OPBC = FLASH_OPBC_BOR_EN | opbc_data | FLASH_OPBC_OPTSTRT; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + + if (status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTSTRT Bit */ + FLASH->OPBC &= ~FLASH_OPBC_OPTSTRT; + } + } + } + else + { + /*disable configed undervoltage reset*/ + FLASH->OPBC &= ~FLASH_OPBC_BOR_EN; + /*update OPBC reg value*/ + FLASH->OPBC = opbc_data | FLASH_OPBC_OPTSTRT; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT); + if (status != FLASH_TIMEOUT) + { + /* If the program operation is completed, disable the OPTSTRT Bit */ + FLASH->OPBC &= ~FLASH_OPBC_OPTSTRT; + } + } + + FLASH_PrefetchBufferCmd(ENABLE); + /* Return the Option Byte program Status */ + return status; +} + + + +/** + * @brief Clears the FLASH's pending flags. + * @param FLASH_FLAG: specifies the FLASH flags to clear. + * This parameter can be any combination of the following values: + * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Programming flag + * @arg FLASH_FLAG_PGSERR:FLASH Programming sequence error flag + * @arg FLASH_FLAG_OPBERR:user option and factory are not load correctly flag + * @note Can not clear FLASH_FLAG_BSY flag + * @retval None + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + /* Check the parameters */ + assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG)); + + /* Clear the flags( RC_W1 )*/ + FLASH->FR |= FLASH_FLAG; +} + + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param FLASH_FLAG: specifies the FLASH flag to check. + * This parameter can be one of the following values: + * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag + * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_EOP: FLASH End of Programming flag + * @arg FLASH_FLAG_PGSERR:FLASH Programming sequence error flag + * @arg FLASH_FLAG_OPBERR:user option and factory are not load correctly flag + * @retval The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG)); + + if ((FLASH->FR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the new state of FLASH_FLAG (SET or RESET) */ + return bitstatus; +} + + +/** + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value + */ +uint32_t FLASH_OPBC_GetWRP(void) +{ + /* Return the FLASH write protection Register value */ + return (uint32_t)(FLASH->WRPR); +} + + +/** + * @brief Checks whether the FLASH Read out Protection Status is set or not. + * @param None + * @retval FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_OPBC_GetRDP(void) +{ + FlagStatus readstatus = RESET; + uint32_t Temp = ((FLASH -> OPBC) & FLASH_OPBC_RDP_Msk); + if (Temp == (OPBC_RDP_Level_1 << 8) || Temp == (OPBC_RDP_Level_2 << 8)) + { + readstatus = SET; + } + else + { + readstatus = RESET; + } + return readstatus; +} + + +/** + * @brief Enables or disables the specified FLASH interrupts. + * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or + * disabled. + * This parameter can be any combination of the following values: + * @arg FLASH_IT_EOP: FLASH end of programming Interrupt + * @arg FLASH_IT_ERR: FLASH Error Interrupt + * @param NewState: new state of the flash Interrupt + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FLASH_IT(FLASH_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the interrupt sources */ + FLASH->WRC |= FLASH_IT; + } + else + { + /* Disable the interrupt sources */ + FLASH->WRC &= ~(uint32_t)FLASH_IT; + } +} + + +/** + * @brief Returns the FLASH Status. + * @param None + * @retval FLASH Status: The returned value can be: + * FLASH_BUSY, FLASH_ERROR_PROGRAM,FLASH_ERROR_PGSERR, FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status FLASHstatus = FLASH_COMPLETE; + + if ((FLASH->FR & (uint32_t)FLASH_FLAG_BSY) != (uint32_t)0x00) + { + FLASHstatus = FLASH_BUSY; + } + else + { + if ((FLASH->FR & (uint32_t)FLASH_FLAG_WRPERR) != (uint32_t)0x00) + { + FLASHstatus = FLASH_ERROR_WRP; + } + else + { + if ((FLASH->FR & (uint32_t)(FLASH_FLAG_PGERR)) != (uint32_t)0x00) + { + FLASHstatus = FLASH_ERROR_PROGRAM; + } + else + { + if ((FLASH->FR & (uint32_t)(FLASH_FLAG_PGSERR)) != (uint32_t)0x00) + { + FLASHstatus = FLASH_ERROR_PGSERR; + } + else + { + FLASHstatus = FLASH_COMPLETE; + } + } + } + } + /* Return the FLASH Status */ + return FLASHstatus; +} + + +/** + * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur. + * @param Timeout: FLASH programming Timeout + * @retval FLASH Status: The returned value can be: FLASH_BUSY, + * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + /* Check for the FLASH Status */ + status = FLASH_GetStatus(); + + /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ + while ((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetStatus(); + Timeout--; + } + + if (Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + /* Return the operation status */ + return status; +} + +/** + * @} + */ + +/** + * @} + */ + +/** +* @} +*/ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_fmc.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_fmc.c new file mode 100644 index 00000000000..fe822663ad6 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_fmc.c @@ -0,0 +1,1251 @@ +/** + ****************************************************************************** + * @file ft32f4xx__fmc.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Flexible Memory Controller (FMC) peripheral + * memories: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * @version V1.0.0 + * @date 2025-04-16 + ****************************************************************************** + @verbatim + ============================================================================== + ##### FMC peripheral features ##### + ============================================================================== + [..] The Flexible memory controller (FMC) includes following memory controllers: + (+) The NOR/PSRAM memory controller + (+) The NAND memory controller + (+) The Synchronous DRAM (SDRAM) controller + + [..] The FMC functional block makes the interface with synchronous and asynchronous static + memories, SDRAM memories. Its main purposes are: + (+) to translate AHB transactions into the appropriate external device protocol + (+) to meet the access time requirements of the external memory devices + + [..] All external memories share the addresses, data and control signals with the controller. + Each external device is accessed by means of a unique Chip Select. The FMC performs + only one access at a time to an external device. + The main features of the FMC controller are the following: + (+) Interface with static-memory mapped devices including: + (++) Static random access memory (SRAM) + (++) Read-only memory (ROM) + (++) NOR Flash memory/OneNAND Flash memory + (++) PSRAM (4 memory banks) + (++) Two banks of NAND Flash memory with ECC hardware to check up to 8 Kbytes of + data + (+) Interface with synchronous DRAM (SDRAM) memories + (+) Independent Chip Select control for each memory bank + (+) Independent configuration for each memory bank + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_fmc.h" + +/** @defgroup + * @brief FMC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ + +/** @defgroup FMC_Private_Constants FMC Private Constants + * @{ + */ + +/* ----------------------- FMC registers bit mask --------------------------- */ + +#if defined(FMC_Bank1) +/* --- BCR Register ---*/ +/* BCR register clear mask */ + +/* --- BTR Register ---*/ +/* BTR register clear mask */ +#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\ + FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\ + FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\ + FMC_BTR1_ACCMOD)) + +/* --- BWTR Register ---*/ +/* BWTR register clear mask */ +#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\ + FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\ + FMC_BWTR1_ACCMOD)) +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank3) || defined(FMC_Bank2_3) +/* --- PCR Register ---*/ +/* PCR register clear mask */ +#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \ + FMC_PCR2_PTYP | FMC_PCR2_PWID | \ + FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \ + FMC_PCR2_TAR | FMC_PCR2_ECCPS)) +/* --- PMEM Register ---*/ +/* PMEM register clear mask */ +#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\ + FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2)) + +/* --- PATT Register ---*/ +/* PATT register clear mask */ +#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\ + FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2)) + +#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) +/* --- SDCR Register ---*/ +/* SDCR register clear mask */ +#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \ + FMC_SDCR1_MWID | FMC_SDCR1_NB | \ + FMC_SDCR1_CAS | FMC_SDCR1_WP | \ + FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \ + FMC_SDCR1_RPIPE)) + +/* --- SDTR Register ---*/ +/* SDTR register clear mask */ +#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \ + FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \ + FMC_SDTR1_TWR | FMC_SDTR1_TRP | \ + FMC_SDTR1_TRCD)) +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup FMC_Exported_Functions FMC Exported Functions + * @{ + */ + +#if defined(FMC_Bank1) + +/** @defgroup FMC_Exported_Functions_NORSRAM FMC NOR SRAM Exported Functions + * @brief NORSRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use NORSRAM device driver ##### + ============================================================================== + + [..] + This driver contains a set of APIs to interface with the FMC NORSRAM banks in order + to run the NORSRAM external devices. + + (+) FMC NORSRAM bank reset using the function FMC_NORSRAM_DeInit() + (+) FMC NORSRAM bank control configuration using the function FMC_NORSRAM_Init() + (+) FMC NORSRAM bank timing configuration using the function FMC_NORSRAM_Timing_Init() + (+) FMC NORSRAM bank extended timing configuration using the function + FMC_NORSRAM_Extended_Timing_Init() + (+) FMC NORSRAM bank enable/disable write operation using the functions + FMC_NORSRAM_WriteOperation_Enable()/FMC_NORSRAM_WriteOperation_Disable() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_NORSRAM_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * + @verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NORSRAM interface + (+) De-initialize the FMC NORSRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the FMC_NORSRAM device according to the specified + * control parameters in the FMC_NORSRAM_InitTypeDef + * @param Device Pointer to NORSRAM device instance + * This paramater can be FMC_NORSRAM_DEVICE + * @param Init Pointer to NORSRAM Initialization structure + * @retval None + */ +void FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init) +{ + uint32_t flashaccess; + uint32_t btcr_reg; + uint32_t mask; + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); + assert_param(IS_FMC_MUX(Init->DataAddressMux)); + assert_param(IS_FMC_MEMORY(Init->MemoryType)); + assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); + assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); + assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); + assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); + assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); + assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); + assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); + assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); + assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); + assert_param(IS_FMC_PAGESIZE(Init->PageSize)); + + /* Disable NORSRAM Device */ + __FMC_NORSRAM_DISABLE(Device, Init->NSBank); + + /* Set NORSRAM device control parameters */ + if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE; + } + else + { + flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE; + } + + btcr_reg = (flashaccess | \ + Init->DataAddressMux | \ + Init->MemoryType | \ + Init->MemoryDataWidth | \ + Init->BurstAccessMode | \ + Init->WaitSignalPolarity | \ + Init->WaitSignalActive | \ + Init->WriteOperation | \ + Init->WaitSignal | \ + Init->ExtendedMode | \ + Init->AsynchronousWait | \ + Init->WriteBurst); + + btcr_reg |= Init->ContinuousClock; + btcr_reg |= Init->PageSize; + + mask = (FMC_BCR1_MBKEN | + FMC_BCR1_MUXEN | + FMC_BCR1_MTYP | + FMC_BCR1_MWID | + FMC_BCR1_FACCEN | + FMC_BCR1_BURSTEN | + FMC_BCR1_WAITPOL | + FMC_BCR1_WAITCFG | + FMC_BCR1_WREN | + FMC_BCR1_WAITEN | + FMC_BCR1_EXTMOD | + FMC_BCR1_ASYNCWAIT | + FMC_BCR1_CBURSTRW); + + mask |= FMC_BCR1_CCLKEN; + mask |= FMC_BCR1_CPSIZE; + + tmpreg = Device->BTCR[Init->NSBank]; + tmpreg &= (uint32_t)~((uint32_t)mask); + tmpreg |= btcr_reg; + + Device->BTCR[Init->NSBank] = tmpreg; + + /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */ + if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1)) + { + tmpreg = Device->BTCR[FMC_NORSRAM_BANK1]; + tmpreg &= (uint32_t)~((uint32_t)FMC_BCR1_CCLKEN); + tmpreg |= Init->ContinuousClock; + + Device->BTCR[FMC_NORSRAM_BANK1] = tmpreg; + } +} + +/** + * @brief DeInitialize the FMC_NORSRAM peripheral + * @param Device Pointer to NORSRAM device instance + * This paramater can be FMC_NORSRAM_DEVICE + * @param ExDevice Pointer to NORSRAM extended mode device instance + * This paramater can be FMC_NORSRAM_EXTENDED_DEVICE + * @param Bank NORSRAM bank number + * This paramater can be one of the following values: + * @arg FMC_NORSRAM_BANK1 + * @arg FMC_NORSRAM_BANK2 + * @arg FMC_NORSRAM_BANK3 + * @arg FMC_NORSRAM_BANK4 + * @retval None + */ +void FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable the FMC_NORSRAM device */ + __FMC_NORSRAM_DISABLE(Device, Bank); + + /* De-initialize the FMC_NORSRAM device */ + /* FMC_NORSRAM_BANK1 */ + if (Bank == FMC_NORSRAM_BANK1) + { + Device->BTCR[Bank] = 0x000030DBU; + } + /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */ + else + { + Device->BTCR[Bank] = 0x000030D2U; + } + + Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; + ExDevice->BWTR[Bank] = 0x0FFFFFFFU; +} + +/** + * @brief Initialize the FMC_NORSRAM Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * This paramater can be FMC_NORSRAM_DEVICE + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * This paramater can be one of the following values: + * @arg FMC_NORSRAM_BANK1 + * @arg FMC_NORSRAM_BANK2 + * @arg FMC_NORSRAM_BANK3 + * @arg FMC_NORSRAM_BANK4 + * @retval None + */ +void FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpr; + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); + assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set FMC_NORSRAM device timing parameters */ + tmpreg = Device->BTCR[Bank + 1U]; + tmpreg &= (uint32_t)~((uint32_t)BTR_CLEAR_MASK); + tmpreg |= (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) | + (((Timing->BusTurnAroundDuration) - 1U) << FMC_BTR1_BUSTURN_Pos) | + (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) | + (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) | + (Timing->AccessMode)); + + Device->BTCR[Bank + 1U] = tmpreg; + + /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ + if ((Device->BTCR[FMC_NORSRAM_BANK1] & FMC_BCR1_CCLKEN) != 0U) + { + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos)); + tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); + + tmpreg = Device->BTCR[FMC_NORSRAM_BANK1 + 1U]; + tmpreg &= (uint32_t)~((uint32_t)FMC_BTR1_CLKDIV); + tmpreg |= tmpr; + + Device->BTCR[FMC_NORSRAM_BANK1 + 1U] = tmpreg; + } +} + +/** + * @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified + * parameters in the FMC_NORSRAM_TimingTypeDef + * @param Device Pointer to NORSRAM device instance + * This paramater can be FMC_NORSRAM_EXTENDED_DEVICE + * @param Timing Pointer to NORSRAM Timing structure + * @param Bank NORSRAM bank number + * This paramater can be one of the following values: + * @arg FMC_NORSRAM_BANK1 + * @arg FMC_NORSRAM_BANK2 + * @arg FMC_NORSRAM_BANK3 + * @arg FMC_NORSRAM_BANK4 + * @param ExtendedMode FMC Extended Mode + * This parameter can be one of the following values: + * @arg FMC_EXTENDED_MODE_DISABLE + * @arg FMC_EXTENDED_MODE_ENABLE + * @retval None + */ +void FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, + FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + uint32_t ExtendedMode) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE) + { + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); + assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); + assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); + assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); + assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); + assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Set NORSRAM device timing register for write configuration, if extended mode is used */ + tmpreg = Device->BWTR[Bank]; + tmpreg &= (uint32_t)~((uint32_t)BWTR_CLEAR_MASK); + tmpreg |= (Timing->AddressSetupTime | + ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | + ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | + Timing->AccessMode | + (((Timing->BusTurnAroundDuration) - 1U) << FMC_BTR1_BUSTURN_Pos)); + + Device->BWTR[Bank] = tmpreg; + } + else + { + Device->BWTR[Bank] = 0x0FFFFFFFU; + } + +} +/** + * @} + */ + +/** @addtogroup FMC_NORSRAM_Private_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NORSRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NORSRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * This paramater can be FMC_NORSRAM_DEVICE + * @param Bank NORSRAM bank number + * This paramater can be one of the following values: + * @arg FMC_NORSRAM_BANK1 + * @arg FMC_NORSRAM_BANK2 + * @arg FMC_NORSRAM_BANK3 + * @arg FMC_NORSRAM_BANK4 + * @retval None + */ +void FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Enable write operation */ + Device->BTCR[Bank] |= FMC_WRITE_OPERATION_ENABLE; +} + +/** + * @brief Disables dynamically FMC_NORSRAM write operation. + * @param Device Pointer to NORSRAM device instance + * This paramater can be FMC_NORSRAM_DEVICE + * @param Bank NORSRAM bank number + * This paramater can be one of the following values: + * @arg FMC_NORSRAM_BANK1 + * @arg FMC_NORSRAM_BANK2 + * @arg FMC_NORSRAM_BANK3 + * @arg FMC_NORSRAM_BANK4 + * @retval None + */ +void FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NORSRAM_DEVICE(Device)); + assert_param(IS_FMC_NORSRAM_BANK(Bank)); + + /* Disable write operation */ + Device->BTCR[Bank] &= (uint32_t)~((uint32_t)FMC_WRITE_OPERATION_ENABLE); +} + +/** + * @} + */ + +/** + * @} + */ +#endif /* FMC_Bank1 */ + +#if defined(FMC_Bank2_3) + +/** @defgroup FMC_Exported_Functions_NAND FMC NAND Exported Functions + * @brief NAND Controller functions + * + @verbatim + ============================================================================== + ##### How to use NAND device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC NAND banks in order + to run the NAND external devices. + + (+) FMC NAND bank reset using the function FMC_NAND_DeInit() + (+) FMC NAND bank control configuration using the function FMC_NAND_Init() + (+) FMC NAND bank common space timing configuration using the function + FMC_NAND_CommonSpace_Timing_Init() + (+) FMC NAND bank attribute space timing configuration using the function + FMC_NAND_AttributeSpace_Timing_Init() + (+) FMC NAND bank enable/disable ECC correction feature using the functions + FMC_NAND_ECC_Enable()/FMC_NAND_ECC_Disable() + (+) FMC NAND bank get ECC correction code using the function FMC_NAND_GetECC() + +@endverbatim + * @{ + */ + +/** @defgroup FMC_NAND_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC NAND interface + (+) De-initialize the FMC NAND interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_NAND device according to the specified + * control parameters in the FMC_NAND_HandleTypeDef + * @param Device Pointer to NAND device instance + * This paramater can be FMC_NAND_DEVICE + * @param Init Pointer to NAND Initialization structure + * @retval None + */ +void FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Init->NandBank)); + assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); + assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); + assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); + assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); + assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); + + /* Set NAND device control parameters */ + if (Init->NandBank == FMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + tmpreg = Device->PCR2; + tmpreg &= (uint32_t)~((uint32_t)PCR_CLEAR_MASK); + tmpreg |= (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + (((Init->TCLRSetupTime) - 0x1U) << FMC_PCR2_TCLR_Pos) | + (((Init->TARSetupTime) - 0x1U) << FMC_PCR2_TAR_Pos)); + + Device->PCR2 = tmpreg; + } + else + { + /* NAND bank 3 registers configuration */ + tmpreg = Device->PCR3; + tmpreg &= (uint32_t)~((uint32_t)PCR_CLEAR_MASK); + tmpreg |= (Init->Waitfeature | + FMC_PCR_MEMORY_TYPE_NAND | + Init->MemoryDataWidth | + Init->EccComputation | + Init->ECCPageSize | + (((Init->TCLRSetupTime) - 0x1U) << FMC_PCR3_TCLR_Pos) | + (((Init->TARSetupTime) - 0x1U) << FMC_PCR3_TAR_Pos)); + + Device->PCR3 = tmpreg; + } +} + +/** + * @brief Initializes the FMC_NAND Common space Timing according to the specified + * parameters in the FMC_NAND_TimingTypeDef + * @param Device Pointer to NAND device instance + * This paramater can be FMC_NAND_DEVICE + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * This paramater can be one of the following values: + * @arg FMC_NAND_BANK2 + * @arg FMC_NAND_BANK3 + * @retval None + */ +void FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Set FMC_NAND device timing parameters */ + if (Bank == FMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + tmpreg = Device->PMEM2; + tmpreg &= (uint32_t)~((uint32_t)PMEM_CLEAR_MASK); + tmpreg |= (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)); + + Device->PMEM2 = tmpreg; + } + else + { + /* NAND bank 3 registers configuration */ + tmpreg = Device->PMEM3; + tmpreg &= (uint32_t)~((uint32_t)PMEM_CLEAR_MASK); + tmpreg |= (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM3_MEMWAIT3_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM3_MEMHOLD3_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM3_MEMHIZ3_Pos)); + + Device->PMEM3 = tmpreg; + } +} + +/** + * @brief Initializes the FMC_NAND Attribute space Timing according to the specified + * parameters in the FMC_NAND_TimingTypeDef + * @param Device Pointer to NAND device instance + * This paramater can be FMC_NAND_DEVICE + * @param Timing Pointer to NAND timing structure + * @param Bank NAND bank number + * This paramater can be one of the following values: + * @arg FMC_NAND_BANK2 + * @arg FMC_NAND_BANK3 + * @retval None + */ +void FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, + FMC_NAND_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); + assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); + assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); + assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Set FMC_NAND device timing parameters */ + if (Bank == FMC_NAND_BANK2) + { + /* NAND bank 2 registers configuration */ + tmpreg = Device->PATT2; + tmpreg &= (uint32_t)((uint32_t)PATT_CLEAR_MASK); + tmpreg |= (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)); + + Device->PATT2 = tmpreg; + } + else + { + /* NAND bank 3 registers configuration */ + tmpreg = Device->PATT3; + tmpreg &= (uint32_t)((uint32_t)PATT_CLEAR_MASK); + tmpreg |= (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT3_ATTWAIT3_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT3_ATTHOLD3_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT3_ATTHIZ3_Pos)); + + Device->PATT3 = tmpreg; + } +} + +/** + * @brief DeInitializes the FMC_NAND device + * @param Device Pointer to NAND device instance + * This paramater can be FMC_NAND_DEVICE + * @param Bank NAND bank number + * This paramater can be one of the following values: + * @arg FMC_NAND_BANK2 + * @arg FMC_NAND_BANK3 + * @retval None + */ +void FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable the NAND Bank */ + __FMC_NAND_DISABLE(Device, Bank); + + /* De-initialize the NAND Bank */ + if (Bank == FMC_NAND_BANK2) + { + /* Set the FMC_NAND_BANK2 registers to their reset values */ + Device->PCR2 = 0x00000018U; + Device->SR2 = 0x00000040U; + Device->PMEM2 = 0xFCFCFCFCU; + Device->PATT2 = 0xFCFCFCFCU; + } + /* FMC_Bank3_NAND */ + else + { + /* Set the FMC_NAND_BANK3 registers to their reset values */ + Device->PCR3 = 0x00000018U; + Device->SR3 = 0x00000040U; + Device->PMEM3 = 0xFCFCFCFCU; + Device->PATT3 = 0xFCFCFCFCU; + } +} + +/** + * @} + */ + +/** @defgroup FMC_NAND_Group2 Peripheral Control functions + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_NAND Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC NAND interface. + +@endverbatim + * @{ + */ + + +/** + * @brief Enables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * This paramater can be FMC_NAND_DEVICE + * @param Bank NAND bank number + * This paramater can be one of the following values: + * @arg FMC_NAND_BANK2 + * @arg FMC_NAND_BANK3 + * @retval None + */ +void FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Enable ECC feature */ + if (Bank == FMC_NAND_BANK2) + { + Device->PCR2 |= FMC_PCR2_ECCEN; + } + else + { + Device->PCR3 |= FMC_PCR3_ECCEN; + } +} + + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * This paramater can be FMC_NAND_DEVICE + * @param Bank NAND bank number + * This paramater can be one of the following values: + * @arg FMC_NAND_BANK2 + * @arg FMC_NAND_BANK3 + * @retval None + */ +void FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Disable ECC feature */ + if (Bank == FMC_NAND_BANK2) + { + Device->PCR2 &= (uint32_t)~((uint32_t)FMC_PCR2_ECCEN); + } + else + { + Device->PCR3 &= (uint32_t)~((uint32_t)FMC_PCR3_ECCEN); + } +} + +/** + * @brief Disables dynamically FMC_NAND ECC feature. + * @param Device Pointer to NAND device instance + * This paramater can be FMC_NAND_DEVICE + * @param ECCval Pointer to ECC value + * @param Bank NAND bank number + * This paramater can be one of the following values: + * @arg FMC_NAND_BANK2 + * @arg FMC_NAND_BANK3 + * @param Timeout Timeout wait value + * @retval None + */ +void FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_NAND_DEVICE(Device)); + assert_param(IS_FMC_NAND_BANK(Bank)); + + /* Wait until FIFO is empty */ + while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) + { + } + + if (Bank == FMC_NAND_BANK2) + { + /* Get the ECCR2 register value */ + *ECCval = (uint32_t)Device->ECCR2; + } + else + { + /* Get the ECCR3 register value */ + *ECCval = (uint32_t)Device->ECCR3; + } +} + +/** + * @} + */ +#endif /* FMC_Bank2_3 */ + +#if defined(FMC_Bank5_6) + +/** @defgroup FMC_SDRAM + * @brief SDRAM Controller functions + * + @verbatim + ============================================================================== + ##### How to use SDRAM device driver ##### + ============================================================================== + [..] + This driver contains a set of APIs to interface with the FMC SDRAM banks in order + to run the SDRAM external devices. + + (+) FMC SDRAM bank reset using the function FMC_SDRAM_DeInit() + (+) FMC SDRAM bank control configuration using the function FMC_SDRAM_Init() + (+) FMC SDRAM bank timing configuration using the function FMC_SDRAM_Timing_Init() + (+) FMC SDRAM bank enable/disable write operation using the functions + FMC_SDRAM_WriteOperation_Enable()/FMC_SDRAM_WriteOperation_Disable() + (+) FMC SDRAM bank send command using the function FMC_SDRAM_SendCommand() + +@endverbatim + * @{ + */ + +/** @addtogroup FMC_SDRAM_Private_Functions_Group1 + * @brief Initialization and Configuration functions + * +@verbatim + ============================================================================== + ##### Initialization and de_initialization functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the FMC SDRAM interface + (+) De-initialize the FMC SDRAM interface + (+) Configure the FMC clock and associated GPIOs + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the FMC_SDRAM device according to the specified + * control parameters in the FMC_SDRAM_InitTypeDef + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param Init Pointer to SDRAM Initialization structure + * @retval None + */ +void FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); + assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); + assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); + assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); + assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); + assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); + assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); + assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); + assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); + assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); + + /* Set SDRAM bank configuration parameters */ + if (Init->SDBank == FMC_SDRAM_BANK1) + { + tmpreg = Device->SDCR[FMC_SDRAM_BANK1]; + tmpreg &= (uint32_t)~((uint32_t)SDCR_CLEAR_MASK); + tmpreg |= (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection | + Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay); + + Device->SDCR[FMC_SDRAM_BANK1] = tmpreg; + } + else /* FMC_Bank2_SDRAM */ + { + tmpreg = Device->SDCR[FMC_SDRAM_BANK1]; + tmpreg &= (uint32_t)~((uint32_t)(FMC_SDCR1_SDCLK | + FMC_SDCR1_RBURST | + FMC_SDCR1_RPIPE)); + tmpreg |= (Init->SDClockPeriod | + Init->ReadBurst | + Init->ReadPipeDelay); + + Device->SDCR[FMC_SDRAM_BANK1] = tmpreg; + + tmpreg = Device->SDCR[FMC_SDRAM_BANK2]; + tmpreg &= (uint32_t)~((uint32_t)SDCR_CLEAR_MASK); + tmpreg |= (Init->ColumnBitsNumber | + Init->RowBitsNumber | + Init->MemoryDataWidth | + Init->InternalBankNumber | + Init->CASLatency | + Init->WriteProtection); + + Device->SDCR[FMC_SDRAM_BANK2] = tmpreg; + } +} + + +/** + * @brief Initializes the FMC_SDRAM device timing according to the specified + * parameters in the FMC_SDRAM_TimingTypeDef + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param Timing Pointer to SDRAM Timing structure + * @param Bank SDRAM bank number + * This paramater can be one of the following values: + * @arg FMC_SDRAM_BANK1 + * @arg FMC_SDRAM_BANK2 + * @retval None + */ +void FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); + assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); + assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); + assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); + assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); + assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); + assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Set SDRAM device timing parameters */ + if (Bank == FMC_SDRAM_BANK1) + { + tmpreg = Device->SDTR[FMC_SDRAM_BANK1]; + tmpreg &= (uint32_t)~((uint32_t)SDTR_CLEAR_MASK); + tmpreg |= (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)); + + Device->SDTR[FMC_SDRAM_BANK1] = tmpreg; + } + else /* FMC_Bank2_SDRAM */ + { + tmpreg = Device->SDTR[FMC_SDRAM_BANK1]; + tmpreg &= (uint32_t)~((uint32_t)(FMC_SDTR1_TRC | + FMC_SDTR1_TRP)); + tmpreg |= ((((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | + (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); + + Device->SDTR[FMC_SDRAM_BANK1] = tmpreg; + + tmpreg = Device->SDTR[FMC_SDRAM_BANK2]; + tmpreg &= (uint32_t)~((uint32_t)SDTR_CLEAR_MASK); + tmpreg |= (((Timing->LoadToActiveDelay) - 1U) | + (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | + (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | + (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | + (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)); + + Device->SDTR[FMC_SDRAM_BANK2] = tmpreg; + } +} + +/** + * @brief DeInitializes the FMC_SDRAM peripheral + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param Bank SDRAM bank number + * This paramater can be one of the following values: + * @arg FMC_SDRAM_BANK1 + * @arg FMC_SDRAM_BANK2 + * @retval None + */ +void FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* De-initialize the SDRAM device */ + Device->SDCR[Bank] = 0x000002D0U; + Device->SDTR[Bank] = 0x0FFFFFFFU; + Device->SDCMR = 0x00000000U; + Device->SDRTR = 0x00000000U; + Device->SDSR = 0x00000000U; +} + +/** + * @} + */ + +/** @addtogroup FMC_SDRAMPrivate_Functions_Group2 + * @brief management functions + * +@verbatim + ============================================================================== + ##### FMC_SDRAM Control functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to control dynamically + the FMC SDRAM interface. + +@endverbatim + * @{ + */ + +/** + * @brief Enables dynamically FMC_SDRAM write protection. + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param Bank SDRAM bank number + * This paramater can be one of the following values: + * @arg FMC_SDRAM_BANK1 + * @arg FMC_SDRAM_BANK2 + * @retval None + */ +void FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Enable write protection */ + Device->SDCR[Bank] |= FMC_SDRAM_WRITE_PROTECTION_ENABLE; +} + +/** + * @brief Disables dynamically FMC_SDRAM write protection. + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param Bank SDRAM bank number + * This paramater can be one of the following values: + * @arg FMC_SDRAM_BANK1 + * @arg FMC_SDRAM_BANK2 + * @retval None + */ +void FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Disable write protection */ + Device->SDCR[Bank] &= (uint32_t)~((uint32_t)FMC_SDRAM_WRITE_PROTECTION_ENABLE); +} + +/** + * @brief Send Command to the FMC SDRAM bank + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param Command Pointer to SDRAM command structure + * @param Timing Pointer to SDRAM Timing structure + * @param Timeout Timeout wait value + * @retval None + */ +void FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, + FMC_SDRAM_CommandTypeDef *Command) +{ + uint32_t tmpreg; + uint32_t tickstart = 0U; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode)); + assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber)); + assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition)); + + /* Set command register */ + tmpreg = Device->SDCMR; + tmpreg &= (uint32_t)~((uint32_t)(FMC_SDCMR_MODE | + FMC_SDCMR_CTB2 | + FMC_SDCMR_CTB1 | + FMC_SDCMR_NRFS | + FMC_SDCMR_MRD)); + tmpreg |= ((Command->CommandMode) | + (Command->CommandTarget) | + (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) | + ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)); + + Device->SDCMR = tmpreg; + + /* wait until command is send */ + while ((Device->SDSR & FMC_SDSR_BUSY) != 0U) + { + } +} + +/** + * @brief Program the SDRAM Memory Refresh rate. + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param RefreshRate The SDRAM refresh rate value. + * @retval None + */ +void FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_REFRESH_RATE(RefreshRate)); + + /* Set the refresh rate in command register */ + tmpreg = Device->SDRTR; + tmpreg &= (uint32_t)~((uint32_t)FMC_SDRTR_COUNT); + tmpreg |= (RefreshRate << FMC_SDRTR_COUNT_Pos); + + Device->SDRTR = tmpreg; +} + +/** + * @brief Set the Number of consecutive SDRAM Memory auto Refresh commands. + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param AutoRefreshNumber Specifies the auto Refresh number. + * @retval None + */ +void FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, + uint32_t AutoRefreshNumber) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber)); + + /* Set the Auto-refresh number in command register */ + tmpreg = Device->SDCMR; + tmpreg &= (uint32_t)~((uint32_t)FMC_SDCMR_NRFS); + tmpreg |= ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos); + + Device->SDCMR = tmpreg; +} + +/** + * @brief Returns the indicated FMC SDRAM bank mode status. + * @param Device Pointer to SDRAM device instance + * This paramater can be FMC_SDRAM_DEVICE + * @param Bank SDRAM bank number + * This paramater can be one of the following values: + * @arg FMC_SDRAM_BANK1 + * @arg FMC_SDRAM_BANK2 + * @retval The FMC SDRAM bank mode status, could be on of the following values: + * FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or + * FMC_SDRAM_POWER_DOWN_MODE. + */ +uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) +{ + uint32_t tmpreg; + + /* Check the parameters */ + assert_param(IS_FMC_SDRAM_DEVICE(Device)); + assert_param(IS_FMC_SDRAM_BANK(Bank)); + + /* Get the corresponding bank mode */ + if (Bank == FMC_SDRAM_BANK1) + { + tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); + } + else + { + tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); + } + + /* Return the mode status */ + return tmpreg; +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* FMC_Bank5_6 */ + +/** + * @} + */ + +/** + * @} + */ +/** + * @} + */ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_gpio.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_gpio.c new file mode 100644 index 00000000000..4471271373f --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_gpio.c @@ -0,0 +1,395 @@ +/** + ****************************************************************************** + * @file ft32f4xx_gpio.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the GPIO peripheral: + * + Initialization and Configuration functions + * + GPIO Read and Write functions + * + GPIO Alternate functions configuration functions + * @version V1.0.0 + * @date 2025-03-27 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_gpio.h" +#include "ft32f4xx_rcc.h" + +/** + * @brief Deinitializes the GPIOx peripheral registers to their default reset + * values. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @retval None + */ +void GPIO_DeInit(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + if (GPIOx == GPIOA) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE); + } + else if (GPIOx == GPIOB) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE); + } + else if (GPIOx == GPIOC) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE); + } + else if (GPIOx == GPIOD) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE); + } + else if (GPIOx == GPIOE) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE); + } + else if (GPIOx == GPIOH) + { + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE); + RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE); + } +} + +/** + * @brief Initializes the GPIOx peripheral according to the specified + * parameters in the GPIO_InitStruct. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct) +{ + uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin)); + assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode)); + assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd)); + + /*-------------------------- Configure the port pins -----------------------*/ + /*-- GPIO Mode Configuration --*/ + for (pinpos = 0x00; pinpos < 0x10; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + + /* Get the port pins position */ + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if (currentpin == pos) + { + if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF)) + { + /* Check Speed mode parameters */ + assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed)); + + /* Speed mode configuration */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEEDR0 << (pinpos * 2)); + GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2)); + + /* Check Output mode parameters */ + assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType)); + + /* Output mode configuration */ + GPIOx->OTYPER &= ~((GPIO_OTYPER_OT0) << ((uint16_t)pinpos)); + GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos)); + } + + GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2)); + + GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2)); + + /* Pull-up Pull down resistor configuration */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2)); + GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2)); + } + } +} + +/** + * @brief Fills each GPIO_InitStruct member with its default value. + * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will + * be initialized. + * @retval None + */ +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_0; + GPIO_InitStruct->GPIO_OType = GPIO_OType_PP; + GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL; +} + +/** + * @brief Locks GPIO Pins configuration registers. + * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, + * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. + * @note The configuration of the locked GPIO pins can no longer be modified + * until the next device reset. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * @note This parameter can be GPIO_Pin_x where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0,1) for GPIOH. + * @retval None + */ +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + __IO uint32_t tmp = 0x00010000; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + tmp |= GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Reset LCKK bit */ + GPIOx->LCKR = GPIO_Pin; + /* Set LCKK bit */ + GPIOx->LCKR = tmp; + /* Read LCKK bit */ + tmp = GPIOx->LCKR; + /* Read LCKK bit */ + tmp = GPIOx->LCKR; +} +/** + * @} + */ + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + + * @param GPIO_Pin: specifies the port bit to read. + * @note This parameter can be GPIO_Pin_x where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0,1) for GPIOH. + * @retval The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified input port pin. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @note This parameter can be GPIO_Pin_x where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0,1) for GPIOH. + * @retval The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->IDR); +} + +/** + * @brief Reads the specified output data port bit. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: Specifies the port bit to read. + * @note This parameter can be GPIO_Pin_x where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0,1) for GPIOH. + * @retval The output port pin value. + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + + if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + return bitstatus; +} + +/** + * @brief Reads the specified GPIO output data port. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @retval GPIO output data port value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + return ((uint16_t)GPIOx->ODR); +} + +/** + * @brief Sets the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * @note This parameter can be GPIO_Pin_x where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..1) for GPIOH. + * @retval None + */ +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = GPIO_Pin; +} + +/** + * @brief Clears the selected data port bits. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bits to be written. + * @note This parameter can be GPIO_Pin_x where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..1) for GPIOH. + * @retval None + */ +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; +} + +/** + * @brief Sets or clears the selected data port bit. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_Pin: specifies the port bit to be written. + * @note This parameter can be GPIO_Pin_x where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0,1) for GPIOH. + * @param BitVal: specifies the value to be written to the selected bit. + * This parameter can be one of the BitAction enumeration values: + * @arg Bit_RESET: to clear the port pin + * @arg Bit_SET: to set the port pin + * @retval None + */ +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GET_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_BIT_ACTION(BitVal)); + + if (BitVal != Bit_RESET) + { + GPIOx->BSRR = GPIO_Pin; + } + else + { + GPIOx->BSRR = (uint32_t)GPIO_Pin << 16U; + } +} + +/** + * @brief Writes data to the specified GPIO data port. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param PortVal: specifies the value to be written to the port output data register. + * @retval None + */ +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal) +{ + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + + GPIOx->ODR = PortVal; +} + +/** + * @} + */ + + +/** + * @brief Set GPIO port for alternate function. + * @param GPIOx: where x can be (A, B, C, D, E or H) to select the GPIO peripheral. + * @param GPIO_PinSource: specifies the pin for the Alternate function. + * This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE + * and (0..12) for GPIOC. + * @param GPIO_AF: selects the pin to used as Alternate function. + * This parameter can be one of the following value: + * @arg GPIO_AF_0: SYS + * @arg GPIO_AF_1: TIM1/2, LPTIM + * @arg GPIO_AF_2: TIM3/4/5 + * @arg GPIO_AF_3: TIM8/9/10/11, CRS + * @arg GPIO_AF_4: I2C1/2/3, SPI3, I2S3 + * @arg GPIO_AF_5: SPI1/2, I2S2 + * @arg GPIO_AF_6: SPI3, I2S2, SDIO + * @arg GPIO_AF_7: USART1/2/3, UART7 + * @arg GPIO_AF_8: UART4/5, LPUART, USART6, COMP1/2/3/4/5/6 + * @arg GPIO_AF_9: CAN1/2/3/4, TIM12/13/14 + * @arg GPIO_AF_10: OTG_FS, QUADSPI + * @arg GPIO_AF_11: ETH, + * @arg GPIO_AF_12: OTH_HS, FMC + * @arg GPIO_AF_13: SSI, SPDIF + * @arg GPIO_AF_14: EPWM, EQEP, ECAP + * @arg GPIO_AF_15: EVENTOUT + * @note The pin should already been configured in Alternate Function mode(AF) + * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF + * @note Refer to the Alternate function mapping table in the device datasheet + * for the detailed mapping of the system and peripherals'alternate + * function I/O pins. + * @retval None + */ +void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF) +{ + uint32_t temp = 0x00; + uint32_t temp_2 = 0x00; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_PERIPH(GPIOx)); + assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource)); + assert_param(IS_GPIO_AF(GPIO_AF)); + + temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)); + GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)(0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07)) * 4)); + temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp; + GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE*******************/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_hcd_fs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_hcd_fs.c new file mode 100644 index 00000000000..955f7ab8d4c --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_hcd_fs.c @@ -0,0 +1,1173 @@ +/** + ****************************************************************************** + * @file ft32f4xx_hcd_fs.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * @version V1.0.0 + * @data 2025-05-28 + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a HCD_FS_HandleTypeDef handle structure, for example: + HCD_FS_HandleTypeDef hhcd; + + (#)Fill parameters of Init structure in HCD handle + + (#)Call HCD_FS_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Initialize the HCD low level resources through the HCD_FS_MspInit() API: + (##) Enable the HCD/USB Low Level interface clock using the following macros + (##) Initialize the related GPIO clocks + (##) Configure HCD pin-out + (##) Configure HCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HCD_FS_Start(); + + @endverbatim + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "ft32f4xx_hcd_fs.h" + + +#ifdef HCD_FS_MODULE_ENABLED +#if defined (USB_OTG_FS) + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +static void HCD_FS_EP0_IRQHandler(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num); +static void HCD_FS_RXEP_IRQHandler(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num, uint8_t epnum); +static void HCD_FS_TXEP_IRQHandler(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num, uint8_t epnum); + +/* Exported functions --------------------------------------------------------*/ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef HCD_FS_Init(HCD_FS_HandleTypeDef *hhcd) +{ + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return USB_FS_ERROR; + } + + if (hhcd->State == HCD_FS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = USB_FS_UNLOCKED; + + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HCD_FS_MspInit(hhcd); + } + + hhcd->State = HCD_FS_STATE_BUSY; + + /* Disable the Interrupts */ + USB_FS_SetUSBInt(0U); + + /* Init the Core (common init.) */ + if (USB_FS_CoreInit() != USB_FS_OK) + { + hhcd->State = HCD_FS_STATE_ERROR; + return USB_FS_ERROR; + } + + /* Init Host */ + if (USB_FS_HostInit(hhcd->Init) != USB_FS_OK) + { + hhcd->State = HCD_FS_STATE_ERROR; + return USB_FS_ERROR; + } + + hhcd->State = HCD_FS_STATE_READY; + hhcd->cur_ep = 0U; + + return USB_FS_OK; +} + +/** + * @brief Initialize a host endpoint. + * @param hhcd HCD handle + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * @retval USB_FS status + */ +USB_FS_StatusTypeDef HCD_FS_EP_Init(HCD_FS_HandleTypeDef *hhcd, + uint8_t ep_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + USB_FS_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint8_t ep_dir; + uint8_t interval; + + __USB_FS_LOCK(hhcd); + hhcd->cur_ep = ep_num; + + hhcd->ep[ep_num].dev_addr = dev_address; + hhcd->ep[ep_num].ep_type = ep_type; + hhcd->ep[ep_num].ep_num = ep_num; + hhcd->ep[ep_num].epnum = epnum & 0xFU; + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->ep[ep_num].ep_is_in = 1U; + } + else + { + hhcd->ep[ep_num].ep_is_in = 0U; + } + + ep_dir = hhcd->ep[ep_num].ep_is_in; + interval = hhcd->ep[ep_num].interval; + HostCoreSpeed = USB_FS_GetSpeed(); + + hhcd->ep[ep_num].speed = speed; + hhcd->ep[ep_num].max_packet = (uint16_t)mps; + + status = USB_FS_HEP_Init(epnum, + dev_address, + ep_type, + interval, + mps); + __USB_FS_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef HCD_FS_DeInit(HCD_FS_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return USB_FS_ERROR; + } + + hhcd->State = HCD_FS_STATE_BUSY; + + USB_FS_SetUSBInt(0U); + + hhcd->State = HCD_FS_STATE_RESET; + hhcd->cur_ep = 0U; + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HCD_FS_MspDeInit(hhcd); + + return USB_FS_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_MspInit(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_MspInit could be implemented in the user file + */ + + +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_MspDeInit(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_MspDeInit could be implemented in the user file + */ + +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ep_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum endpoint number + * @param direction endpoint number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + */ + +void HCD_FS_EP_SubmitRequest(HCD_FS_HandleTypeDef *hhcd, + uint8_t ep_num, uint8_t direction, + uint8_t ep_type, uint8_t token, + uint8_t *pbuff, uint16_t length, + uint8_t ctl_state) +{ + hhcd->cur_ep = ep_num; + hhcd->ep[ep_num].ep_is_in = direction; + hhcd->ep[ep_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->ep[ep_num].data_pid = EP_PID_SETUP; + } + else + { + hhcd->ep[ep_num].data_pid = EP_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if (token == 1U) /* out send data */ + { + if (direction == 0U) + { + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->ep[ep_num].toggle_out = 1U; + } + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->ep[ep_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->ep[ep_num].data_pid = EP_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->ep[ep_num].data_pid = EP_PID_DATA1; + } + } + else + { + /*...*/ + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->ep[ep_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->ep[ep_num].data_pid = EP_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->ep[ep_num].data_pid = EP_PID_DATA1; + } + } + else + { + if (hhcd->ep[ep_num].toggle_in == 0U) + { + hhcd->ep[ep_num].data_pid = EP_PID_DATA0; + } + else + { + hhcd->ep[ep_num].data_pid = EP_PID_DATA1; + } + } + break; + + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->ep[ep_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->ep[ep_num].data_pid = EP_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->ep[ep_num].data_pid = EP_PID_DATA1; + } + } + else + { + if (hhcd->ep[ep_num].toggle_in == 0U) + { + hhcd->ep[ep_num].data_pid = EP_PID_DATA0; + } + else + { + hhcd->ep[ep_num].data_pid = EP_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->ep[ep_num].data_pid = EP_PID_DATA0; + break; + + default: + break; + } + + hhcd->ep[ep_num].xfer_buff = pbuff; + hhcd->ep[ep_num].xfer_len = length; + hhcd->ep[ep_num].XferSize = 0U; + hhcd->ep[ep_num].urb_state = URB_IDLE; + hhcd->ep[ep_num].xfer_count = 0U; + hhcd->ep[ep_num].ep_num = ep_num; + hhcd->ep[ep_num].state = EP_IDLE; + if (ep_num <= 1U) + { + USB_FS_HEP0_StartXfer(&hhcd->ep[ep_num], ctl_state); + } + else + { + USB_FS_HEP_StartXfer(&hhcd->ep[ep_num]); + } +} + + + +//void HCD_FS_ResetCore(HCD_FS_CoreTypeDef *cP, uint8_t state) +//{ +// HCD_FS_EPTypeDef *eP; +// HCD_FS_CoreTypeDef *cP; +// +// cP->Resetting = 1U; +// cP->OTGState = 0U; +// +// /* Clear all pending Device Interrupts */ +// USB_FS_ClrEPInt(void); +// USB_FS->INTRTX1E = 0U; +// USB_FS->INTRRX1E = 0U; +// +// USB_FS_ClrUSBInt(void); +// USB_FS->INTRUSBE = 0U; +// +// USB_FS_SetAddress(0U); /* clear host address reg */ +// +// USB_FS_RstEP0Regs(void); +// for (i = 0; i < cP->NumEPDefs; i++) +// { +// eP = cP->EPA + i; +// USB_FS_RstEPRegs(eP->BltEP); +// HCD_FS_RstEPVars(eP); +// } +// USB_FS_SetUSBInt((~OTG_FS_INTRUSBE_SOFINTE)); +// USB_FS_SetEPInt(cP->IntEMask); +// USB_FS_ClrUSBInt(void); +// USB_FS_ClrEPInt(void); +// +// +//DBGVAR(DRCDBG_ENUM, "\n\r*ES*=", TRACE_B(state)); +// eP = cP->EPA; +//// MGC_SWOP_Setup(&cP->EP0Setup); /* order bytes for USB output */ +// cP->EP0State = state; +// if (!USB_Submit_URB(cP->EP0URB)) /* 0 on return is good to go */ +// return; +// MGC_Reset_DRC_Core(CRST_ENUM_FAILED, cP->CoreID);/* endpoints get reset*/ +// return; +//} +// +// +// +///* +// * MGC_Reset_EP_IO_Vars used to reset the soft I/O state variables for a +// * DRC endpoint object. +// */ +//void HCD_FS_RstEPVars(HCD_FS_EPTypeDef *eP) +//{ +// eP->IOState = 0; /* TX, no status phase is default */ +// +// if(eP->BltEP) +// { +// eP->URBP = (struct urb *)NULL; +// } +// eP->MaxEPSize = eP->FIFOSize; /* until negotiated differently */ +// eP->FifoRemain = 0; +// eP->BytesRequested = 0; +// eP->BytesProcessed = 0; +// eP->DRCInterval = 0; +// eP->intr_flag = 0; +// eP->TgtEP = 0; +// eP->Allocated = 0; +// eP->LastPacket = 0; +// eP->URBRestart = 0; +// eP->Halted = 0; +// +//} /* MGC_Reset_EP_IO_Vars */ + + + + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HCD_FS_IRQHandler(HCD_FS_HandleTypeDef *hhcd) +{ + uint32_t i; + uint8_t tx_int; + uint8_t rx_int; + uint32_t reg_int; + + reg_int = USB_FS_ReadInterrupts(); + + tx_int = ((reg_int >> 8) & 0xFU); + rx_int = ((reg_int >> 16) & 0xFU); + + /* Ensure that we are in host mode */ + if ((USB_FS_GetMode() & USB_OTG_MODE_HOST) == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (reg_int == 0U) + { + return; + } + + /* Handle vbus error Interrupts */ + if ((reg_int & OTG_FS_INTRUSB_VERRINT) == OTG_FS_INTRUSB_VERRINT) + { + HCD_FS_VBusErr_Callback(hhcd); + } + + /* Handle session request Interrupts */ + if ((reg_int & OTG_FS_INTRUSB_SREQINT) == OTG_FS_INTRUSB_SREQINT) + { + HCD_FS_Session_Callback(hhcd); + } + + /* Handle Host Disconnect Interrupts */ + if ((reg_int & OTG_FS_INTRUSB_DISCINT) == OTG_FS_INTRUSB_DISCINT) + { + /* Handle Host Port Disconnect Interrupt */ + HCD_FS_Disconnect_Callback(hhcd); + } + + /* Handle Host Connect Interrupts */ + if ((reg_int & OTG_FS_INTRUSB_CONNINT) == OTG_FS_INTRUSB_CONNINT) + { + /* Handle Host Port Connect Interrupt */ + HCD_FS_Connect_Callback(hhcd); + } + + /* Handle Host SOF Interrupt */ + if ((reg_int & OTG_FS_INTRUSB_SOFINT) == OTG_FS_INTRUSB_SOFINT) + { + HCD_FS_SOF_Callback(hhcd); + } + /* Handle Host babble Interrupt */ + if ((reg_int & OTG_FS_INTRUSB_BABBINT) == OTG_FS_INTRUSB_BABBINT) + { + HCD_FS_Babble_Callback(hhcd); + } + /* Handle resume Interrupt */ + if ((reg_int & OTG_FS_INTRUSB_RESINT) == OTG_FS_INTRUSB_RESINT) + { + HCD_FS_Resume_Callback(hhcd); + } + + if ((tx_int & OTG_FS_INTRTX1_EP0INF) == OTG_FS_INTRTX1_EP0INF) + { + (void)USB_FS_IndexSel(0U); + HCD_FS_EP0_IRQHandler(hhcd, hhcd->cur_ep); + } + + /* Handle Tx endpoint Interrupt */ + for (i = 1U; i < hhcd->Init.endpoints; i++) + { + if (((tx_int >> i) & 0x01U) != 0U) + { + (void)USB_FS_IndexSel((uint8_t)i); + HCD_FS_TXEP_IRQHandler(hhcd, hhcd->cur_ep, (uint8_t)i); + } + } + + /* Handle Rx endpoint Interrupt */ + for (i = 1U; i < hhcd->Init.endpoints; i++) + { + if (((rx_int >> i) & 0x01U) != 0U) + { + (void)USB_FS_IndexSel((uint8_t)i); + HCD_FS_RXEP_IRQHandler(hhcd, hhcd->cur_ep, (uint8_t)i); + } + } + } +} + + +/** + * @brief Handles HCD Wakeup interrupt request. + * @param hhcd HCD handle + * @retval status + */ +void HCD_FS_WKUP_IRQHandler(HCD_FS_HandleTypeDef *hhcd) +{ + UNUSED(hhcd); +} + + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_SOF_Callback(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_VBusErr_Callback(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_Session_Callback(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_Babble_Callback(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_Resume_Callback(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_SOF_Callback could be implemented in the user file + */ +} + + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_Connect_Callback(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_FS_Disconnect_Callback(HCD_FS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +void __attribute__((weak)) HCD_FS_EP_NotifyURBChange_Callback(HCD_FS_HandleTypeDef *hhcd, uint8_t epnum, HCD_FS_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(epnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_FS_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef HCD_FS_Start(HCD_FS_HandleTypeDef *hhcd) +{ + __USB_FS_LOCK(hhcd); + /* Enable port power */ + USB_FS_DrvSess(1U); + + /* Enable connect interrupt */ + USB_FS_SetUSBInt(OTG_FS_INTRUSBE_CONNINTE | OTG_FS_INTRUSBE_SOFINTE | OTG_FS_INTRUSBE_BABBINTE | OTG_FS_INTRUSBE_DISCINTE | OTG_FS_INTRUSBE_RESINTE); + __USB_FS_UNLOCK(hhcd); + + return USB_FS_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval USB_FS status + */ + +USB_FS_StatusTypeDef HCD_FS_Stop(HCD_FS_HandleTypeDef *hhcd) +{ + __USB_FS_LOCK(hhcd); + USB_FS_DrvSess(0U); + __USB_FS_UNLOCK(hhcd); + + return USB_FS_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval none + */ +void HCD_FS_ResetPort(void) +{ + USB_FS_ResetPort(); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HCD state + */ +HCD_FS_StateTypeDef HCD_FS_GetState(HCD_FS_HandleTypeDef *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param epnum endpoint number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_ERROR/ + * URB_STALL + */ +HCD_FS_URBStateTypeDef HCD_FS_EP_GetURBState(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num) +{ + return hhcd->ep[ep_num].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param epnum endpoint number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HCD_FS_EP_GetXferCount(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num) +{ + return hhcd->ep[ep_num].xfer_count; +} + +/** + * @brief Return the current endpoint pipe. + * @param hhcd HCD handle + * @param epnum endpoint number. + * This parameter can be a value from 1 to 15 + * @retval host transfer pieps + */ +uint32_t HCD_FS_GetCurrEp(HCD_FS_HandleTypeDef *hhcd) +{ + return hhcd->cur_ep; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param epnum endpoint number. + * This parameter can be a value from 1 to 15 + * @retval host endpoint state + * This parameter can be one of these values: + * EP_IDLE/ + * EP_XFRC/ + * EP_HALTED/ + * EP_NAK/ + * EP_STALL/ + * EP_XACTERR/ + * EP_BBLERR/ + * EP_DATATGLERR + */ +HCD_FS_EPStateTypeDef HCD_FS_EP_GetState(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num) +{ + return hhcd->ep[ep_num].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HCD_FS_GetCurrentFrame(void) +{ + return (USB_FS_GetCurrentFrame()); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HCD_FS_GetCurrentSpeed(void) +{ + return (USB_FS_GetSpeed()); +} + + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ + +/** + * @brief Handle Host endpoint0 interrupt requests. + * @param hhcd HCD handle + * @param epnum endpoint number. + * This parameter can be 0 + * @retval none + */ +static void HCD_FS_EP0_IRQHandler(HCD_FS_HandleTypeDef *hhcd, uint8_t epnum) +{ + uint8_t tmpreg; + uint8_t bytecount; + + tmpreg = USB_FS->CSR0; + + if ((tmpreg & OTG_FS_CSR0_NAKTMO) == OTG_FS_CSR0_NAKTMO) + { + hhcd->ep[epnum].ErrCnt = 0U; + hhcd->ep[epnum].state = EP_NAK; + if (hhcd->ep[epnum].ep_is_in == 0U) + { + USB_FS_FlushEp0Fifo(); /* flush fifo to halt transcation*/ + } + else + { + USB_FS->CSR0 &= (~OTG_FS_CSR0_REQPKT); /* clear reqpkt halt transcation */ + } + USB_FS->CSR0 &= (~OTG_FS_CSR0_NAKTMO); + } + else if ((tmpreg & OTG_FS_CSR0_RXSTALL) == OTG_FS_CSR0_RXSTALL) + { + hhcd->ep[epnum].state = EP_STALL; + hhcd->ep[epnum].urb_state = URB_STALL; + if ( hhcd->ep[epnum].ep_is_in == 0U) + { + USB_FS_FlushEp0Fifo(); /* flush fifo to halt transcation*/ + } + else + { + USB_FS->CSR0 &= (~OTG_FS_CSR0_REQPKT); /* clear reqpkt halt transcation */ + } + USB_FS->CSR0 &= (~OTG_FS_CSR0_RXSTALL); + HCD_FS_EP_NotifyURBChange_Callback(hhcd, epnum, hhcd->ep[epnum].urb_state); + } + else if ((tmpreg & OTG_FS_CSR0_ERR) == OTG_FS_CSR0_ERR) + { + hhcd->ep[epnum].state = EP_XACTERR; + hhcd->ep[epnum].urb_state = URB_ERROR; + if ( hhcd->ep[epnum].ep_is_in == 0U) + { + USB_FS_FlushEp0Fifo(); /* flush fifo to halt transcation*/ + } + else + { + USB_FS->CSR0 &= (~OTG_FS_CSR0_REQPKT); /* clear reqpkt halt transcation */ + } + USB_FS->CSR0 &= (~OTG_FS_CSR0_RXSTALL); + HCD_FS_EP_NotifyURBChange_Callback(hhcd, epnum, hhcd->ep[epnum].urb_state); + } + + else if ((tmpreg & OTG_FS_CSR0_RXPKTRDY) == OTG_FS_CSR0_RXPKTRDY) + { + bytecount = USB_FS_Read_Count0(); + hhcd->ep[epnum].toggle_in ^= 1U; + hhcd->ep[epnum].xfer_count = bytecount; + hhcd->ep[epnum].XferSize = hhcd->ep[epnum].XferSize + bytecount ; + hhcd->ep[epnum].ErrCnt = 0U; + if ((bytecount > 0U) && (hhcd->ep[epnum].xfer_buff != (void *)0)) + { + USB_FS_FIFORead(hhcd->ep[epnum].xfer_buff, 0U, bytecount); + } + if (bytecount == 0U) + { + hhcd->ep[epnum].state = EP_XFRC; + hhcd->ep[epnum].urb_state = URB_DONE; + } + else if (bytecount < 0x40) + { + hhcd->ep[epnum].state = EP_XFRC; + hhcd->ep[epnum].urb_state = URB_DONE; + } + else if (hhcd->ep[epnum].XferSize == hhcd->ep[epnum].xfer_len) + { + // if (hhcd->ep[epnum].xfer_len >= 0x40U) + if (bytecount == 0x40U) + { + USB_FS_HEP0_StartXfer(&hhcd->ep[epnum], CTRL_DATA); + } + else + { + hhcd->ep[epnum].state = EP_XFRC; + hhcd->ep[epnum].urb_state = URB_DONE; + } + } + else + { + USB_FS_HEP0_StartXfer(&hhcd->ep[epnum], CTRL_DATA); + } + HCD_FS_EP_NotifyURBChange_Callback(hhcd, epnum, hhcd->ep[epnum].urb_state); + } + else + { + hhcd->ep[epnum].ErrCnt = 0U; + hhcd->ep[epnum].toggle_out ^= 1U; + hhcd->ep[epnum].state = EP_XFRC; + hhcd->ep[epnum].urb_state = URB_DONE; + HCD_FS_EP_NotifyURBChange_Callback(hhcd, epnum, hhcd->ep[epnum].urb_state); + } +} + +/** + * @brief Handle Host endpoint RX interrupt requests. + * @param hhcd HCD handle + * @param epnum endpoint number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_FS_RXEP_IRQHandler(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num, uint8_t epnum) +{ + uint8_t tmpreg; + uint16_t bytecount; + uint32_t maxpacket; + uint16_t fifo_size; + + tmpreg = USB_FS->RXCSR1; + maxpacket = (USB_FS->RXMAXP) << 3U; + + if ((tmpreg & OTG_FS_RXCSR1_NAKTMO) == OTG_FS_RXCSR1_NAKTMO) + { + hhcd->ep[ep_num].ErrCnt = 0U; + if ( hhcd->ep[epnum].ep_type == EP_TYPE_ISOC) + { + hhcd->ep[ep_num].state = EP_XACTERR; + USB_FS_FlushRxFifo(epnum); /* flush fifo to halt transcation*/ + } + else + { + hhcd->ep[ep_num].state = EP_NAK; + } + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_REQPKT); /* clear reqpkt halt transcation */ + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_NAKTMO); + } + else if ((tmpreg & OTG_FS_RXCSR1_RXSTALL) == OTG_FS_RXCSR1_RXSTALL) + { + hhcd->ep[ep_num].state = EP_STALL; + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_REQPKT); /* clear reqpkt halt transcation */ + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_RXSTALL); + } + else if ((tmpreg & OTG_FS_RXCSR1_ERR) == OTG_FS_RXCSR1_ERR) + { + hhcd->ep[ep_num].state = EP_XACTERR; + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_REQPKT); /* clear reqpkt halt transcation */ + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_RXSTALL); + } + else if ((tmpreg & OTG_FS_RXCSR1_RXPKTRDY) == OTG_FS_RXCSR1_RXPKTRDY) + { + bytecount = USB_FS_Read_RxCount(); + hhcd->ep[ep_num].state = EP_XFRC; + hhcd->ep[ep_num].ErrCnt = 0U; + hhcd->ep[ep_num].toggle_in ^= 1U; + hhcd->ep[ep_num].xfer_count = bytecount; + if ((bytecount > 0U) && (hhcd->ep[ep_num].xfer_buff != (void *)0)) + { + USB_FS_FIFORead(hhcd->ep[ep_num].xfer_buff, epnum, bytecount); + } + if (bytecount == 0U) + { + hhcd->ep[ep_num].state = EP_XFRC; + hhcd->ep[ep_num].urb_state = URB_DONE; + HCD_FS_EP_NotifyURBChange_Callback(hhcd, ep_num, hhcd->ep[ep_num].urb_state); + } + else if (hhcd->ep[ep_num].XferSize == hhcd->ep[ep_num].xfer_len) + { + if (bytecount == maxpacket) + { + USB_FS->RXCSR1 |= OTG_FS_RXCSR1_REQPKT; + } + else + { + hhcd->ep[ep_num].state = EP_XFRC; + hhcd->ep[ep_num].urb_state = URB_DONE; + HCD_FS_EP_NotifyURBChange_Callback(hhcd, epnum, hhcd->ep[ep_num].urb_state); + } + } + else + { + hhcd->ep[ep_num].xfer_len = hhcd->ep[ep_num].xfer_len - maxpacket; + hhcd->ep[ep_num].toggle_out ^= 1U; + USB_FS_HEP_StartXfer(&hhcd->ep[epnum]); + } + USB_FS->RXCSR1 &= ~OTG_FS_RXCSR1_RXPKTRDY; + } + else + { + /*...*/ + } +} + +/** + * @brief Handle Host endpoint TX interrupt requests. + * @param hhcd HCD handle + * @param epnum endpoint number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_FS_TXEP_IRQHandler(HCD_FS_HandleTypeDef *hhcd, uint8_t ep_num, uint8_t epnum) +{ + uint8_t tmpreg; + uint32_t maxpacket; + uint16_t fifo_size; + + tmpreg = USB_FS->TXCSR1; + maxpacket = (USB_FS->TXMAXP) << 3U; + + if ((tmpreg & OTG_FS_TXCSR1_NAKTMO) == OTG_FS_TXCSR1_NAKTMO) + { + hhcd->ep[ep_num].ErrCnt = 0U; + hhcd->ep[ep_num].state = EP_NAK; + (void)USB_FS_FlushTxFifo(epnum); + (void)USB_FS_FlushTxFifo(epnum); /* flush txfifo to halt transcation */ + USB_FS->TXCSR1 &= (~OTG_FS_TXCSR1_NAKTMO); + } + else if ((tmpreg & OTG_FS_TXCSR1_RXSTALL) == OTG_FS_TXCSR1_RXSTALL) + { + hhcd->ep[ep_num].state = EP_STALL; + (void)USB_FS_FlushTxFifo(epnum); + (void)USB_FS_FlushTxFifo(epnum); /* flush txfifo to halt transcation */ + USB_FS->TXCSR1 &= (~OTG_FS_TXCSR1_RXSTALL); + } + else if ((tmpreg & OTG_FS_TXCSR1_ERR) == OTG_FS_TXCSR1_ERR) + { + hhcd->ep[ep_num].state = EP_XACTERR; + (void)USB_FS_FlushTxFifo(epnum); + (void)USB_FS_FlushTxFifo(epnum); /* flush txfifo to halt transcation */ + USB_FS->TXCSR1 &= (~OTG_FS_TXCSR1_RXSTALL); + } + else + { + hhcd->ep[ep_num].ErrCnt = 0U; + if (hhcd->ep[ep_num].xfer_len == hhcd->ep[ep_num].XferSize) + { + if (hhcd->ep[ep_num].xfer_len == maxpacket) + { + hhcd->ep[ep_num].toggle_out ^= 1U; + USB_FS->TXCSR1 = OTG_FS_TXCSR1_TXPKTRDY; + } + else + { + hhcd->ep[ep_num].state = EP_XFRC; + hhcd->ep[ep_num].toggle_out ^= 1U; + hhcd->ep[ep_num].urb_state = URB_DONE; + HCD_FS_EP_NotifyURBChange_Callback(hhcd, ep_num, hhcd->ep[ep_num].urb_state); + } + } + else + { + hhcd->ep[ep_num].xfer_len = hhcd->ep[ep_num].xfer_len - maxpacket; + hhcd->ep[ep_num].toggle_out ^= 1U; + USB_FS_HEP_StartXfer(&hhcd->ep[epnum]); + } + } +} + +/** + * @} + */ + + +#endif /* defined (USB_OTG_FS) */ +#endif /* HCD_FS_MODULE_ENABLED */ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_hcd_hs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_hcd_hs.c new file mode 100644 index 00000000000..59ec4f01b57 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_hcd_hs.c @@ -0,0 +1,1573 @@ +/** + ****************************************************************************** + * @file ft32f4xx_hcd_hs.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * @version V1.0.0 + * @data 2025-03-26 + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a HCD_HS_HandleTypeDef handle structure, for example: + HCD_HS_HandleTypeDef hhcd; + + (#)Fill parameters of Init structure in HCD handle + + (#)Call HCD_HS_Init() API to initialize the HCD peripheral (Core, Host core, ...) + + (#)Initialize the HCD low level resources through the HCD_HS_MspInit() API: + (##) Enable the HCD/USB Low Level interface clock using the following macros + (##) Initialize the related GPIO clocks + (##) Configure HCD pin-out + (##) Configure HCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the HCD Driver: + (##) hhcd.pData = phost; + + (#)Enable HCD transmission and reception: + (##) HCD_HS_Start(); + + @endverbatim + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "ft32f4xx_hcd_hs.h" +#include "ft32f4xx_rcc.h" + + +/** @addtogroup FT32F4xx_DRIVER + * @{ + */ + +#ifdef HCD_MODULE_ENABLED +#if defined (USB_OTG_HS) +/** @defgroup HCD_HS HCD + * @brief HCD HS module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup HCD_HS_Private_Functions HCD Private Functions + * @{ + */ +static void HCD_HS_HC_IN_IRQHandler(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HS_HC_OUT_IRQHandler(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum); +static void HCD_HS_RXQLVL_IRQHandler(HCD_HS_HandleTypeDef *hhcd); +static void HCD_HS_Port_IRQHandler(HCD_HS_HandleTypeDef *hhcd); +/** + * @{ + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup HCD_HS_Exported_Functions HCD Exported Functions + * @{ + */ + +/** @defgroup HCD_HS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the host driver. + * @param hhcd HCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef HCD_HS_Init(HCD_HS_HandleTypeDef *hhcd) +{ + + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return USB_HS_ERROR; + } + + if (hhcd->State == HCD_HS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hhcd->Lock = USB_HS_UNLOCKED; + + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HCD_HS_MspInit(hhcd); + } + + hhcd->State = HCD_HS_STATE_BUSY; + + /* Disable the Interrupts */ + __HCD_HS_DISABLE(); + + /* Init the Core (common init.) */ + if (USB_HS_CoreInit(hhcd->Init) != USB_HS_OK) + { + hhcd->State = HCD_HS_STATE_ERROR; + return USB_HS_ERROR; + } + + /* Init Host */ + if (USB_HS_HostInit(hhcd->Init) != USB_HS_OK) + { + hhcd->State = HCD_HS_STATE_ERROR; + return USB_HS_ERROR; + } + + hhcd->State = HCD_HS_STATE_READY; + + return USB_HS_OK; +} + +/** + * @brief Initialize a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number. + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed. + * This parameter can be one of these values: + * HCD_DEVICE_SPEED_HIGH: high speed mode, + * HCD_DEVICE_SPEED_FULL: Full speed mode, + * HCD_DEVICE_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type, + * EP_TYPE_ISOC: Isochronous type, + * EP_TYPE_BULK: Bulk type, + * EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size. + * This parameter can be a value from 0 to32K + * @retval USB_HS status + */ +USB_HS_StatusTypeDef HCD_HS_HC_Init(HCD_HS_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, + uint16_t mps) +{ + USB_HS_StatusTypeDef status; + uint32_t HostCoreSpeed; + uint32_t HCcharMps = mps; + + __USB_HS_LOCK(hhcd); + hhcd->hc[ch_num].do_ping = 0U; + hhcd->hc[ch_num].dev_addr = dev_address; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].ep_type = ep_type; + hhcd->hc[ch_num].ep_num = epnum & 0x7FU; + + HCD_HS_HC_ClearHubInfo(hhcd, ch_num); + + if ((epnum & 0x80U) == 0x80U) + { + hhcd->hc[ch_num].ep_is_in = 1U; + } + else + { + hhcd->hc[ch_num].ep_is_in = 0U; + } + + HostCoreSpeed = USB_HS_GetHostSpeed(); + + if (ep_type == EP_TYPE_ISOC) + { + /* FS device plugged to HS HUB */ + if ((speed == HCD_DEVICE_SPEED_FULL) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + if (HCcharMps > ISO_SPLT_MPS) + { + /* ISO Max Packet Size for Split mode */ + HCcharMps = ISO_SPLT_MPS; + } + } + } + + hhcd->hc[ch_num].speed = speed; + hhcd->hc[ch_num].max_packet = (uint16_t)HCcharMps; + + status = USB_HS_HC_Init(ch_num, + epnum, + dev_address, + speed, + ep_type, + (uint16_t)HCcharMps); + __USB_HS_UNLOCK(hhcd); + + return status; +} + +/** + * @brief Halt a host channel. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval USB_HS status + */ +USB_HS_StatusTypeDef HCD_HS_HC_Halt(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num) +{ + USB_HS_StatusTypeDef status = USB_HS_OK; + + __USB_HS_LOCK(hhcd); + (void)USB_HS_HC_Halt(ch_num); + __USB_HS_UNLOCK(hhcd); + + return status; +} + +/** + * @brief DeInitialize the host driver. + * @param hhcd HCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef HCD_HS_DeInit(HCD_HS_HandleTypeDef *hhcd) +{ + /* Check the HCD handle allocation */ + if (hhcd == NULL) + { + return USB_HS_ERROR; + } + + hhcd->State = HCD_HS_STATE_BUSY; + + __HCD_HS_DISABLE(); + + hhcd->State = HCD_HS_STATE_RESET; + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + HCD_HS_MspDeInit(hhcd); + + return USB_HS_OK; +} + +/** + * @brief Initialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_HS_MspInit(HCD_HS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_MspInit could be implemented in the user file + */ + + +} + +/** + * @brief DeInitialize the HCD MSP. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_HS_MspDeInit(HCD_HS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_MspDeInit could be implemented in the user file + */ + +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group2 Input and Output operation functions + * @brief HCD IO operation functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USB Host Data + Transfer + +@endverbatim + * @{ + */ + +/** + * @brief Submit a new URB for processing. + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param direction Channel number. + * This parameter can be one of these values: + * 0 : Output / 1 : Input + * @param ep_type Endpoint Type. + * This parameter can be one of these values: + * EP_TYPE_CTRL: Control type/ + * EP_TYPE_ISOC: Isochronous type/ + * EP_TYPE_BULK: Bulk type/ + * EP_TYPE_INTR: Interrupt type/ + * @param token Endpoint Type. + * This parameter can be one of these values: + * 0: HC_PID_SETUP / 1: HC_PID_DATA1 + * @param pbuff pointer to URB data + * @param length Length of URB data + * @param do_ping activate do ping protocol (for high speed only). + * This parameter can be one of these values: + * 0 : do ping inactive / 1 : do ping active + */ +void HCD_HS_HC_SubmitRequest(HCD_HS_HandleTypeDef *hhcd, + uint8_t ch_num, + uint8_t direction, + uint8_t ep_type, + uint8_t token, + uint8_t *pbuff, + uint16_t length, + uint8_t do_ping) +{ + hhcd->hc[ch_num].ep_is_in = direction; + hhcd->hc[ch_num].ep_type = ep_type; + + if (token == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_SETUP; + hhcd->hc[ch_num].do_ping = do_ping; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + + /* Manage Data Toggle */ + switch (ep_type) + { + case EP_TYPE_CTRL: + if (token == 1U) /* out send data */ + { + if (direction == 0U) + { + if (length == 0U) + { + /* For Status OUT stage, Length==0, Status Out PID = 1 */ + hhcd->hc[ch_num].toggle_out = 1U; + } + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].do_ssplit == 1U) + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + } + } + break; + + case EP_TYPE_BULK: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + + break; + + case EP_TYPE_INTR: + if (direction == 0U) + { + /* Set the Data Toggle bit as per the Flag */ + if (hhcd->hc[ch_num].toggle_out == 0U) + { + /* Put the PID 0 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + /* Put the PID 1 */ + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + else + { + if (hhcd->hc[ch_num].toggle_in == 0U) + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + } + else + { + hhcd->hc[ch_num].data_pid = HC_PID_DATA1; + } + } + break; + + case EP_TYPE_ISOC: + hhcd->hc[ch_num].data_pid = HC_PID_DATA0; + break; + + default: + break; + } + + hhcd->hc[ch_num].xfer_buff = pbuff; + hhcd->hc[ch_num].xfer_len = length; + hhcd->hc[ch_num].urb_state = URB_IDLE; + hhcd->hc[ch_num].xfer_count = 0U; + hhcd->hc[ch_num].ch_num = ch_num; + hhcd->hc[ch_num].state = HC_IDLE; + + USB_HS_HC_StartXfer(&hhcd->hc[ch_num], (uint8_t)hhcd->Init.dma_enable); +} + +/** + * @brief Handle HCD interrupt request. + * @param hhcd HCD handle + * @retval None + */ +void HCD_HS_IRQHandler(HCD_HS_HandleTypeDef *hhcd) +{ + uint32_t i; + uint32_t interrupt; + + /* Ensure that we are in device mode */ + if (USB_HS_GetMode() == USB_OTG_MODE_HOST) + { + /* Avoid spurious interrupt */ + if (__HCD_HS_IS_INVALID_INTERRUPT()) + { + return; + } + + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_IPXFR_INCOMPISOOUT)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_IPXFR_INCOMPISOOUT); + } + + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_IISOIXFR)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_IISOIXFR); + } + + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_PTXFE)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_PTXFE); + } + + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_MMIS)) + { + /* Incorrect mode, acknowledge the interrupt */ + __HCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_MMIS); + } + + /* Handle Host Disconnect Interrupts */ + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_DISCINT)) + { + __HCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_DISCINT); + + if ((USB_HS_HPRT0 & OTG_HS_HPRT_PCSTS) == 0U) + { + /* Handle Host Port Disconnect Interrupt */ + HCD_HS_Disconnect_Callback(hhcd); + + } + } + + /* Handle Host Port Interrupts */ + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_HPRTINT)) + { + HCD_HS_Port_IRQHandler(hhcd); + } + + /* Handle Host SOF Interrupt */ + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_SOF)) + { + HCD_HS_SOF_Callback(hhcd); + + __HCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_SOF); + } + + /* Handle Host channel Interrupt */ + if (__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_HCINT)) + { + interrupt = USB_HS_HC_ReadInterrupt(); + for (i = 0U; i < hhcd->Init.Host_channels; i++) + { + if ((interrupt & (1UL << (i & 0xFU))) != 0U) + { + if ((USB_HS_HC(i)->HCCHAR & OTG_HS_HCCHAR_EPDIR) == OTG_HS_HCCHAR_EPDIR) + { + HCD_HS_HC_IN_IRQHandler(hhcd, (uint8_t)i); + } + else + { + HCD_HS_HC_OUT_IRQHandler(hhcd, (uint8_t)i); + } + } + } + __HCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_HCINT); + } + + /* Handle Rx Queue Level Interrupts */ + if ((__HCD_HS_GET_FLAG(OTG_HS_GINTSTS_RXFLVL)) != 0U) + { + USB_HS_MASK_INTERRUPT(OTG_HS_GINTSTS_RXFLVL); + + HCD_HS_RXQLVL_IRQHandler(hhcd); + + USB_HS_UNMASK_INTERRUPT(OTG_HS_GINTSTS_RXFLVL); + } + } +} + + +/** + * @brief Handles HCD Wakeup interrupt request. + * @param hhcd HCD handle + * @retval status + */ +void HCD_HS_WKUP_IRQHandler(HCD_HS_HandleTypeDef *hhcd) +{ + UNUSED(hhcd); +} + + +/** + * @brief SOF callback. + * @param hhcd HCD handle + * @retval None + */ +__attribute__((weak)) void HCD_HS_SOF_Callback(HCD_HS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_SOF_Callback could be implemented in the user file + */ +} + +/** + * @brief Connection Event callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_HS_Connect_Callback(HCD_HS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_Connect_Callback could be implemented in the user file + */ +} + +/** + * @brief Disconnection Event callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_HS_Disconnect_Callback(HCD_HS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Enabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_HS_PortEnabled_Callback(HCD_HS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_Disconnect_Callback could be implemented in the user file + */ +} + +/** + * @brief Port Disabled Event callback. + * @param hhcd HCD handle + * @retval None + */ +void __attribute__((weak)) HCD_HS_PortDisabled_Callback(HCD_HS_HandleTypeDef *hhcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_Disconnect_Callback could be implemented in the user file + */ +} + + +/** + * @brief Notify URB state change callback. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @param urb_state: + * This parameter can be one of these values: + * URB_IDLE/ + * URB_DONE/ + * URB_NOTREADY/ + * URB_NYET/ + * URB_ERROR/ + * URB_STALL/ + * @retval None + */ +void __attribute__((weak)) HCD_HS_HC_NotifyURBChange_Callback(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum, HCD_HS_URBStateTypeDef urb_state) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hhcd); + UNUSED(chnum); + UNUSED(urb_state); + + /* NOTE : This function should not be modified, when the callback is needed, + the HCD_HS_HC_NotifyURBChange_Callback could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions + * @brief Management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the HCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the host driver. + * @param hhcd HCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef HCD_HS_Start(HCD_HS_HandleTypeDef *hhcd) +{ + __USB_HS_LOCK(hhcd); + /* Enable port power */ + USB_HS_DriveVbus(1U); + + /* Enable global interrupt */ + __HCD_HS_ENABLE(); + __USB_HS_UNLOCK(hhcd); + + return USB_HS_OK; +} + +/** + * @brief Stop the host driver. + * @param hhcd HCD handle + * @retval USB_HS status + */ + +USB_HS_StatusTypeDef HCD_HS_Stop(HCD_HS_HandleTypeDef *hhcd) +{ + __USB_HS_LOCK(hhcd); + (void)USB_HS_StopHost(); + __USB_HS_UNLOCK(hhcd); + + return USB_HS_OK; +} + +/** + * @brief Reset the host port. + * @param hhcd HCD handle + * @retval none + */ +void HCD_HS_ResetPort(void) +{ + USB_HS_ResetPort(); +} + +/** + * @} + */ + +/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the HCD handle state. + * @param hhcd HCD handle + * @retval HCD state + */ +HCD_HS_StateTypeDef HCD_HS_GetState(HCD_HS_HandleTypeDef *hhcd) +{ + return hhcd->State; +} + +/** + * @brief Return URB state for a channel. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval URB state. + * This parameter can be one of these values: + * URB_IDLE + * URB_DONE + * URB_NOTREADY + * URB_NYET + * URB_ERROR + * URB_STALL + */ +HCD_HS_URBStateTypeDef HCD_HS_HC_GetURBState(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].urb_state; +} + + +/** + * @brief Return the last host transfer size. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval last transfer size in byte + */ +uint32_t HCD_HS_HC_GetXferCount(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].xfer_count; +} + +/** + * @brief Return the Host Channel state. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval Host channel state + * This parameter can be one of these values: + * HC_IDLE/ + * HC_XFRC/ + * HC_HALTED/ + * HC_NYET/ + * HC_NAK/ + * HC_STALL/ + * HC_XACTERR/ + * HC_BBLERR/ + * HC_DATATGLERR + */ +HCD_HS_HCStateTypeDef HCD_HS_HC_GetState(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum) +{ + return hhcd->hc[chnum].state; +} + +/** + * @brief Return the current Host frame number. + * @param hhcd HCD handle + * @retval Current Host frame number + */ +uint32_t HCD_HS_GetCurrentFrame() +{ + return (USB_HS_GetCurrentFrame()); +} + +/** + * @brief Return the Host enumeration speed. + * @param hhcd HCD handle + * @retval Enumeration speed + */ +uint32_t HCD_HS_GetCurrentSpeed() +{ + return (USB_HS_GetHostSpeed()); +} + +/** + * @brief Set host channel Hub information + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @param addr Hub address + * @param PortNbr Hub port number + * @retval none + */ +void HCD_HS_HC_SetHubInfo(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num, uint8_t addr, uint8_t PortNbr) +{ + uint32_t HostCoreSpeed = USB_HS_GetHostSpeed(); + + /* LS/FS device plugged to HS HUB */ + if ((hhcd->hc[ch_num].speed != HCD_DEVICE_SPEED_HIGH) && (HostCoreSpeed == HPRT0_PRTSPD_HIGH_SPEED)) + { + hhcd->hc[ch_num].do_ssplit = 1U; + + if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL) && (hhcd->hc[ch_num].ep_is_in != 0U)) + { + hhcd->hc[ch_num].toggle_in = 1U; + } + } + + hhcd->hc[ch_num].hub_addr = addr; + hhcd->hc[ch_num].hub_port_nbr = PortNbr; + +} + +/** + * @brief Clear host channel Hub information + * @param hhcd HCD handle + * @param ch_num Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +void HCD_HS_HC_ClearHubInfo(HCD_HS_HandleTypeDef *hhcd, uint8_t ch_num) +{ + + hhcd->hc[ch_num].do_ssplit = 0U; + hhcd->hc[ch_num].do_csplit = 0U; + hhcd->hc[ch_num].hub_addr = 0U; + hhcd->hc[ch_num].hub_port_nbr = 0U; + +} + + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup HCD_Private_Functions + * @{ + */ +/** + * @brief Handle Host Channel IN interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HS_HC_IN_IRQHandler(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum) +{ + uint32_t tmpreg; + + if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_AHBERR)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_BBERR)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_BBERR); + hhcd->hc[chnum].state = HC_BBLERR; + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_STALL)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_DTERR)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_DTERR); + hhcd->hc[chnum].state = HC_DATATGLERR; + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_TXERR)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_TXERR); + hhcd->hc[chnum].state = HC_XACTERR; + USB_HS_HC_Halt(chnum); + } + else + { + /* ... */ + } + + if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_FRMOR)) + { + USB_HS_HC_Halt(chnum); + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_FRMOR); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_XFRC)) + { + /* clear any pending ACK IT */ + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_ACK); + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HCD_HS_CLEAR_HC_CSPLT(chnum); + } + + if (hhcd->Init.dma_enable != 0U) + { + hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].XferSize - (USB_HS_HC(chnum)->HCTSIZ & OTG_HS_HCTSIZ_XFRSIZ); + } + + hhcd->hc[chnum].state = HC_XFRC; + hhcd->hc[chnum].ErrCnt = 0U; + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_XFRC); + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + USB_HS_HC_Halt(chnum); + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_NAK); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_INTR) || + (hhcd->hc[chnum].ep_type == EP_TYPE_ISOC)) + { + USB_HS_HC(chnum)->HCCHAR |= OTG_HS_HCCHAR_ODDFRM; + hhcd->hc[chnum].urb_state = URB_DONE; + + HCD_HS_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + } + + else + { + /* ... */ + } + + if (hhcd->Init.dma_enable == 1U) + { + if ((((hhcd->hc[chnum].xfer_count + hhcd->hc[chnum].max_packet -1U) / hhcd->hc[chnum].max_packet) & 1U) != 0U) + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_ACK)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_ACK); + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 1U; + hhcd->hc[chnum].state = HC_ACK; + + USB_HS_HC_Halt(chnum); + } + } + + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_CHH)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + if (hhcd->hc[chnum].do_ssplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + hhcd->hc[chnum].ep_ss_schedule = 0U; + __HCD_HS_CLEAR_HC_CSPLT(chnum); + } + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + if (hhcd->hc[chnum].do_csplit == 1U) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].NyetErrCnt++; + if (hhcd->hc[chnum].NyetErrCnt > 2U) + { + hhcd->hc[chnum].NyetErrCnt = 0U; + hhcd->hc[chnum].do_csplit = 0U; + + if (hhcd->hc[chnum].ErrCnt < 3U) + { + hhcd->hc[chnum].ep_ss_schedule = 1U; + } + __HCD_HS_CLEAR_HC_CSPLT(chnum); + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Set Complete split and re-active the channel */ + USB_HS_HC(chnum)->HCSPLT |= OTG_HS_HCSPLT_COMPLSPLT; + USB_HS_HC(chnum)->HCINTMSK |= OTG_HS_HCINTMSK_NYETM; + USB_HS_HC(chnum)->HCINTMSK &= ~OTG_HS_HCINTMSK_ACKM; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + } + } + } + + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + /* re-activate the channel */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + } + } + else if (hhcd->hc[chnum].state == HC_BBLERR) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + if (hhcd->hc[chnum].state == HC_HALTED) + { + return; + } + } + + HCD_HS_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + } + + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_NAK)) + { + if (hhcd->hc[chnum].ep_type == EP_TYPE_INTR) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + USB_HS_HC_Halt(chnum); + } + else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL) || + (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + if ((hhcd->Init.dma_enable == 0U) || (hhcd->hc[chnum].do_csplit == 1U)) + { + hhcd->hc[chnum].state = HC_NAK; + USB_HS_HC_Halt(chnum); + } + } + else + { + /*...*/ + } + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HCD_HS_CLEAR_HC_CSPLT(chnum); + __HCD_HS_UNMASK_ACK_HC_INT(chnum); + } + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_NAK); + } + else + { + /*...*/ + } + +} + +/** + * @brief Handle Host Channel OUT interrupt requests. + * @param hhcd HCD handle + * @param chnum Channel number. + * This parameter can be a value from 1 to 15 + * @retval none + */ +static void HCD_HS_HC_OUT_IRQHandler(HCD_HS_HandleTypeDef *hhcd, uint8_t chnum) +{ + uint32_t tmpreg; + uint32_t num_packets; + + if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_AHBERR)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_AHBERR); + hhcd->hc[chnum].state = HC_XACTERR; + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_ACK)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_ACK); + if (hhcd->hc[chnum].do_ping == 1U) + { + hhcd->hc[chnum].do_ping = 0U; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + hhcd->hc[chnum].state = HC_ACK; + USB_HS_HC_Halt(chnum); + } + + if ((hhcd->hc[chnum].do_ssplit == 1U) && (hhcd->hc[chnum].do_csplit == 0U)) + { + if (hhcd->hc[chnum].ep_type != EP_TYPE_ISOC) + { + hhcd->hc[chnum].do_csplit = 1U; + } + hhcd->hc[chnum].state = HC_ACK; + USB_HS_HC_Halt(chnum); + + /* reset error_count */ + hhcd->hc[chnum].ErrCnt = 0U; + } + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_FRMOR)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_FRMOR); + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_XFRC)) + { + hhcd->hc[chnum].ErrCnt = 0U; + + /* transaction completed with NYET state, update do ping state */ + if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_NYET)) + { + hhcd->hc[chnum].do_ping = 1U; + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_NYET); + } + if (hhcd->hc[chnum].do_csplit != 0U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HCD_HS_CLEAR_HC_CSPLT(chnum); + } + + /* clear any pending IT */ + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_XFRC); + hhcd->hc[chnum].state = HC_XFRC; + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_NYET)) + { + hhcd->hc[chnum].state = HC_NYET; + + if (hhcd->hc[chnum].do_ssplit == 0U) + { + hhcd->hc[chnum].do_ping = 1U; + } + + hhcd->hc[chnum].ErrCnt = 0U; + USB_HS_HC_Halt(chnum); + /* clear any pending IT */ + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_NYET); + } + + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_STALL)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_STALL); + hhcd->hc[chnum].state = HC_STALL; + USB_HS_HC_Halt(chnum); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_NAK)) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].state = HC_NAK; + + if (hhcd->hc[chnum].do_ping == 0U) + { + if (hhcd->hc[chnum].speed == HCD_DEVICE_SPEED_HIGH) + { + hhcd->hc[chnum].do_ping = 1U; + } + } + + USB_HS_HC_Halt(chnum); + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_NAK); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_TXERR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].state = HC_XACTERR; + USB_HS_HC_Halt(chnum); + } + else + { + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].urb_state = URB_ERROR; + + HCD_HS_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + /* Re-activate the channel */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + } + } + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_TXERR); + } + + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_DTERR)) + { + hhcd->hc[chnum].state = HC_DATATGLERR; + USB_HS_HC_Halt(chnum); + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_DTERR); + } + else if (__HCD_HS_GET_CH_FLAG(chnum, OTG_HS_HCINT_CHH)) + { + __HCD_HS_CLEAR_HC_INT(chnum, OTG_HS_HCINT_CHH); + + if (hhcd->hc[chnum].state == HC_XFRC) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_DONE; + + if ((hhcd->hc[chnum].ep_type == EP_TYPE_BULK) || + (hhcd->hc[chnum].ep_type == EP_TYPE_INTR)) + { + if (hhcd->Init.dma_enable == 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + if ((hhcd->Init.dma_enable == 1U) && (hhcd->hc[chnum].xfer_len > 0U)) + { + num_packets = (hhcd->hc[chnum].xfer_len + hhcd->hc[chnum].max_packet - 1U) / hhcd->hc[chnum].max_packet; + if ((num_packets & 1U) != 0U) + { + hhcd->hc[chnum].toggle_out ^= 1U; + } + } + } + } + else if (hhcd->hc[chnum].state == HC_ACK) + { + hhcd->hc[chnum].state = HC_HALTED; + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + } + else if (hhcd->hc[chnum].state == HC_NAK) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + + if (hhcd->hc[chnum].do_csplit == 1U) + { + hhcd->hc[chnum].do_csplit = 0U; + __HCD_HS_CLEAR_HC_CSPLT(chnum); + } + } + else if (hhcd->hc[chnum].state == HC_NYET) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_NOTREADY; + } + else if (hhcd->hc[chnum].state == HC_STALL) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].urb_state = URB_STALL; + } + else if ((hhcd->hc[chnum].state == HC_XACTERR) || + (hhcd->hc[chnum].state == HC_DATATGLERR)) + { + hhcd->hc[chnum].state = HC_HALTED; + hhcd->hc[chnum].ErrCnt++; + if (hhcd->hc[chnum].ErrCnt > 2U) + { + hhcd->hc[chnum].ErrCnt = 0U; + hhcd->hc[chnum].urb_state = URB_ERROR; + } + else + { + hhcd->hc[chnum].urb_state = URB_NOTREADY; + /* re-activate the channel */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + } + } + else + { + return; + } + + HCD_HS_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state); + + } + + else + { + return; + } +} + +/** + * @brief Handle Rx Queue Level interrupt requests. + * @param hhcd HCD handle + * @retval none + */ +static void HCD_HS_RXQLVL_IRQHandler(HCD_HS_HandleTypeDef *hhcd) +{ + uint32_t pktsts; + uint32_t pktcnt; + uint32_t GrxstspReg; + uint32_t xferSizePktCnt; + uint32_t tmpreg; + uint32_t chnum; + + GrxstspReg = USB_HS->GRXSTSP; + chnum = GrxstspReg & OTG_HS_GRXSTSP_CHNUM; + pktsts = (GrxstspReg & OTG_HS_GRXSTSP_PKTSTS) >> 17; + pktcnt = (GrxstspReg & OTG_HS_GRXSTSP_BCNT) >> 4; + + switch (pktsts) + { + case GRXSTS_PKTSTS_IN: + /* Read the data into the host buffer. */ + if ((pktcnt > 0U) && (hhcd->hc[chnum].xfer_buff != (void *)0)) + { + if ((hhcd->hc[chnum].xfer_count + pktcnt) <= hhcd->hc[chnum].xfer_len) + { + USB_HS_ReadPacket(hhcd->hc[chnum].xfer_buff, (uint16_t)pktcnt); + + /* manage multiple Xfer */ + hhcd->hc[chnum].xfer_buff += pktcnt; + hhcd->hc[chnum].xfer_count += pktcnt; + + /* get transfer size packet count */ + xferSizePktCnt = (USB_HS_HC(chnum)->HCTSIZ & OTG_HS_HCTSIZ_PKTCNT) >> 19; + + if ((hhcd->hc[chnum].max_packet == pktcnt) && (xferSizePktCnt > 0U)) + { + /* re-activate the channel when more packets are expected */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + hhcd->hc[chnum].toggle_in ^= 1U; + } + } + else + { + hhcd->hc[chnum].urb_state = URB_ERROR; + } + } + break; + + case GRXSTS_PKTSTS_DATA_TOGGLE_ERR: + break; + + case GRXSTS_PKTSTS_IN_XFER_COMP: + case GRXSTS_PKTSTS_CH_HALTED: + default: + break; + } +} + +/** + * @brief Handle Host Port interrupt requests. + * @param hhcd HCD handle + * @retval None + */ +static void HCD_HS_Port_IRQHandler(HCD_HS_HandleTypeDef *hhcd) +{ + __IO uint32_t hprt0; + __IO uint32_t hprt0_dup; + + /* Handle Host Port Interrupts */ + hprt0 = USB_HS_HPRT0; + hprt0_dup = USB_HS_HPRT0; + + hprt0_dup &= ~(OTG_HS_HPRT_PENA | OTG_HS_HPRT_PCDET | \ + OTG_HS_HPRT_PENCHNG | OTG_HS_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & OTG_HS_HPRT_PCDET) == OTG_HS_HPRT_PCDET) + { + if ((hprt0 & OTG_HS_HPRT_PCSTS) == OTG_HS_HPRT_PCSTS) + { + + HCD_HS_Connect_Callback(hhcd); + } + hprt0_dup |= OTG_HS_HPRT_PCDET; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & OTG_HS_HPRT_PENCHNG) == OTG_HS_HPRT_PENCHNG) + { + hprt0_dup |= OTG_HS_HPRT_PENCHNG; + + if ((hprt0 & OTG_HS_HPRT_PENA) == OTG_HS_HPRT_PENA) + { + if((hprt0 & OTG_HS_HPRT_PSPD) == (HPRT0_PRTSPD_HIGH_SPEED<<17)) + { + USB_HS_HOST->HFIR = 0x1D4C;//HFIR_60_MHZ; + } + HCD_HS_PortEnabled_Callback(hhcd); + } + else + { + + HCD_HS_PortDisabled_Callback(hhcd); + } + } + + /* Check for an overcurrent */ + if ((hprt0 & OTG_HS_HPRT_POCCHNG) == OTG_HS_HPRT_POCCHNG) + { + hprt0_dup |= OTG_HS_HPRT_POCCHNG; + } + + /* Clear Port Interrupts */ + USB_HS_HPRT0 = hprt0_dup; +} + +/** + * @} + */ + + +#endif /* defined (USB_OTG_HS) */ +#endif /* HCD_MODULE_ENABLED */ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_i2c.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_i2c.c new file mode 100644 index 00000000000..33dc5f94c45 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_i2c.c @@ -0,0 +1,1320 @@ +/** + ****************************************************************************** + * @file ft32f4xx_i2c.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Inter-Integrated circuit (I2C): + * + Initialization and Configuration + * + Communications handling + * + SMBUS management + * + I2C registers management + * + Data transfers management + * + DMA transfers management + * + Interrupts and flags management + * @version V1.0.0 + * @date 2025-03-31 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_i2c.h" +#include "ft32f4xx_rcc.h" + + + +#define CR1_CLEAR_MASK ((uint32_t)0x00CDE0FF) /*I2C_AnalogFilter)); + assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter)); + assert_param(IS_I2C_NoStretch(I2C_InitStruct->I2C_NoStretchMode)); + assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode)); + assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1)); + assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack)); + assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress)); + + /* Disable I2Cx Peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + + /*---------------------------- I2Cx FILTERS Configuration ------------------*/ + /* Get the I2Cx CR1 value */ + tmpreg = I2Cx->CR1; + /* Clear I2Cx CR1 register */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure I2Cx: analog and digital filter */ + /* Set ANFOFF bit according to I2C_AnalogFilter value */ + /* Set DFN bits according to I2C_DigitalFilter value */ + tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter | (I2C_InitStruct->I2C_DigitalFilter << 8); + + /*---------------------------- I2Cx Nostretch Configuration ----------------*/ + /* Set NOSTRETCH bit according to I2C_NoStretchMode value */ + tmpreg |= (uint32_t)I2C_InitStruct->I2C_NoStretchMode; + + /* Write to I2Cx CR1 */ + I2Cx->CR1 = tmpreg; + + /*---------------------------- I2Cx TIMING Configuration -------------------*/ + /* Configure I2Cx: Timing */ + /* Set TIMINGR bits according to I2C_Timing */ + /* Write to I2Cx TIMING */ + I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK; + + /* Enable I2Cx Peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + + /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ + /* Clear tmpreg local variable */ + tmpreg = 0; + /* Clear OAR1 register */ + I2Cx->OAR1 = (uint32_t)tmpreg; + /* Clear OAR2 register */ + I2Cx->OAR2 = (uint32_t)tmpreg; + /* Configure I2Cx: Own Address1 and acknowledged address */ + /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */ + /* Set OA1 bits according to I2C_OwnAddress1 value */ + tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \ + (uint32_t)I2C_InitStruct->I2C_OwnAddress1); + /* Write to I2Cx OAR1 */ + I2Cx->OAR1 = tmpreg; + /* Enable Own Address1 acknowledgement */ + I2Cx->OAR1 |= I2C_OAR1_OA1EN; + + /*---------------------------- I2Cx MODE Configuration ---------------------*/ + /* Configure I2Cx: mode */ + /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */ + tmpreg = I2C_InitStruct->I2C_Mode; + /* Write to I2Cx CR1 */ + I2Cx->CR1 |= tmpreg; + + /*---------------------------- I2Cx ACK Configuration ----------------------*/ + /* Get the I2Cx CR2 value */ + tmpreg = I2Cx->CR2; + /* Clear I2Cx CR2 register */ + tmpreg &= CR2_CLEAR_MASK; + /* Configure I2Cx: acknowledgement */ + /* Set NACK bit according to I2C_Ack value */ + tmpreg |= I2C_InitStruct->I2C_Ack; + /* Write to I2Cx CR2 */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Fills each I2C_InitStruct member with its default value. + * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values --------------*/ + /* Initialize the I2C_Timing member */ + I2C_InitStruct->I2C_Timing = 0; + /* Initialize the I2C_AnalogFilter member */ + I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable; + /* Initialize the I2C_DigitalFilter member */ + I2C_InitStruct->I2C_DigitalFilter = 0; + /* Initialize the I2C_NoStretchMode member */ + I2C_InitStruct->I2C_NoStretchMode = I2C_NoStretch_Disable; + /* Initialize the I2C_Mode member */ + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + /* Initialize the I2C_OwnAddress1 member */ + I2C_InitStruct->I2C_OwnAddress1 = 0; + /* Initialize the I2C_Ack member */ + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + /* Initialize the I2C_AcknowledgedAddress member */ + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/** + * @brief Enables or disables the specified I2C peripheral. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected I2C peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; + } + else + { + /* Disable the selected I2C peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + } +} + +/** + * @brief Enables or disables the specified I2C software reset. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @retval None + */ +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Disable peripheral */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE); + + /* Perform a dummy read to delay the disable of peripheral for minimum + 3 APB clock cycles to perform the software reset functionality */ + *(__IO uint32_t *)(uint32_t)I2Cx; + + /* Enable peripheral */ + I2Cx->CR1 |= I2C_CR1_PE; +} + +/** + * @brief Enables or disables the specified I2C interrupts. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_IT_ERRI: Error interrupt mask + * @arg I2C_IT_TCI: Transfer Complete interrupt mask + * @arg I2C_IT_STOPI: Stop Detection interrupt mask + * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask + * @arg I2C_IT_ADDRI: Address Match interrupt mask + * @arg I2C_IT_RXI: RX interrupt mask + * @arg I2C_IT_TXI: TX interrupt mask + * @param NewState: new state of the specified I2C interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_CONFIG_IT(I2C_IT)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C interrupts */ + I2Cx->CR1 |= I2C_IT; + } + else + { + /* Disable the selected I2C interrupts */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT); + } +} + +/** + * @brief Enables or disables the I2C Clock stretching. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Clock stretching. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable clock stretching */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH); + } + else + { + /* Disable clock stretching */ + I2Cx->CR1 |= I2C_CR1_NOSTRETCH; + } +} + +/** + * @brief Enables or disables the I2C own address 2. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C own address 2. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable own address 2 */ + I2Cx->OAR2 |= I2C_OAR2_OA2EN; + } + else + { + /* Disable own address 2 */ + I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN); + } +} + +/** + * @brief Configures the I2C slave own address 2 and mask. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @param Mask: specifies own address 2 mask to be programmed. + * This parameter can be one of the following values: + * @arg I2C_OA2_NoMask: no mask. + * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care. + * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care. + * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care. + * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care. + * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care. + * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care. + * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care. + * @retval None + */ +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_OWN_ADDRESS2(Address)); + assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask)); + + /* Get the old register value */ + tmpreg = I2Cx->OAR2; + + /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK)); + + /* Set I2Cx SADD */ + tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \ + (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ; + + /* Store the new register value */ + I2Cx->OAR2 = tmpreg; +} + +/** + * @brief Enables or disables the I2C general call mode. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C general call mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable general call mode */ + I2Cx->CR1 |= I2C_CR1_GCEN; + } + else + { + /* Disable general call mode */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN); + } +} + +/** + * @brief Enables or disables the I2C slave byte control. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C slave byte control. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable slave byte control */ + I2Cx->CR1 |= I2C_CR1_SBC; + } + else + { + /* Disable slave byte control */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC); + } +} + +/** + * @brief Configures the slave address to be transmitted after start generation. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @note This function should be called before generating start condition. + * @retval None + */ +void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SLAVE_ADDRESS(Address)); + + /* Get the old register value */ + tmpreg = I2Cx->CR2; + + /* Reset I2Cx SADD bit [9:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD); + + /* Set I2Cx SADD */ + tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD); + + /* Store the new register value */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the I2C 10-bit addressing mode for the master. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C 10-bit addressing mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function should be called before generating start condition. + * @retval None + */ +void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 10-bit addressing mode */ + I2Cx->CR2 |= I2C_CR2_ADD10; + } + else + { + /* Disable 10-bit addressing mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10); + } +} + +/** + * @} + */ + + +/** + * @brief Enables or disables the I2C automatic end mode (stop condition is + * automatically sent when nbytes data are transferred). + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C automatic end mode. + * This parameter can be: ENABLE or DISABLE. + * @note This function has effect if Reload mode is disabled. + * @retval None + */ +void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Auto end mode */ + I2Cx->CR2 |= I2C_CR2_AUTOEND; + } + else + { + /* Disable Auto end mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND); + } +} + +/** + * @brief Enables or disables the I2C nbytes reload mode. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the nbytes reload mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Auto Reload mode */ + I2Cx->CR2 |= I2C_CR2_RELOAD; + } + else + { + /* Disable Auto Reload mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD); + } +} + +/** + * @brief Configures the number of bytes to be transmitted/received. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param Number_Bytes: specifies the number of bytes to be programmed. + * @retval None + */ +void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Get the old register value */ + tmpreg = I2Cx->CR2; + + /* Reset I2Cx Nbytes bit [7:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES); + + /* Set I2Cx Nbytes */ + tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16) & I2C_CR2_NBYTES); + + /* Store the new register value */ + I2Cx->CR2 = tmpreg; +} + +/** + * @brief Configures the type of transfer request for the master. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param I2C_Direction: specifies the transfer request direction to be programmed. + * This parameter can be one of the following values: + * @arg I2C_Direction_Transmitter: Master request a write transfer + * @arg I2C_Direction_Receiver: Master request a read transfer + * @retval None + */ +void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_DIRECTION(I2C_Direction)); + + /* Test on the direction to set/reset the read/write bit */ + if (I2C_Direction == I2C_Direction_Transmitter) + { + /* Request a write Transfer */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN); + } + else + { + /* Request a read Transfer */ + I2Cx->CR2 |= I2C_CR2_RD_WRN; + } +} + +/** + * @brief Generates I2Cx communication START condition. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C START condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a START condition */ + I2Cx->CR2 |= I2C_CR2_START; + } + else + { + /* Disable the START condition generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START); + } +} + +/** + * @brief Generates I2Cx communication STOP condition. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C STOP condition generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Generate a STOP condition */ + I2Cx->CR2 |= I2C_CR2_STOP; + } + else + { + /* Disable the STOP condition generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP); + } +} + +/** + * @brief Enables or disables the I2C 10-bit header only mode with read direction. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2C 10-bit header only mode. + * This parameter can be: ENABLE or DISABLE. + * @note This mode can be used only when switching from master transmitter mode + * to master receiver mode. + * @retval None + */ +void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 10-bit header only mode */ + I2Cx->CR2 |= I2C_CR2_HEAD10R; + } + else + { + /* Disable 10-bit header only mode */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R); + } +} + +/** + * @brief Generates I2C communication Acknowledge. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the Acknowledge. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable ACK generation */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK); + } + else + { + /* Enable NACK generation */ + I2Cx->CR2 |= I2C_CR2_NACK; + } +} + +/** + * @brief Returns the I2C slave matched address . + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @retval The value of the slave matched address . + */ +uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ; +} + +/** + * @brief Returns the I2C slave received request. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @retval The value of the received request. + */ +uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx) +{ + uint32_t tmpreg = 0; + uint16_t direction = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR); + + /* If write transfer is requested */ + if (tmpreg == 0) + { + /* write transfer is requested */ + direction = I2C_Direction_Transmitter; + } + else + { + /* Read transfer is requested */ + direction = I2C_Direction_Receiver; + } + return direction; +} + +/** + * @brief Generate I2C TXIS event. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of I2C TXIS event generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateTXIS(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Genarate I2C TXIS event */ + I2Cx->ISR |= I2C_ISR_TXIS; + } + else + { + /* No effect */ + I2Cx->ISR &= (uint32_t)~((uint32_t)I2C_ISR_TXIS); + } +} + +/** + * @brief Generate I2C TXE event. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of I2C TXE event generation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_GenerateTXE(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Genarate I2C TXE event */ + I2Cx->ISR |= I2C_ISR_TXE; + } + else + { + /* No effect */ + I2Cx->ISR &= (uint32_t)~((uint32_t)I2C_ISR_TXE); + } +} + +/** + * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param Address: specifies the slave address to be programmed. + * @param Number_Bytes: specifies the number of bytes to be programmed. + * This parameter must be a value between 0 and 255. + * @param ReloadEndMode: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_Reload_Mode: Enable Reload mode . + * @arg I2C_AutoEnd_Mode: Enable Automatic end mode. + * @arg I2C_SoftEnd_Mode: Enable Software end mode. + * @param StartStopMode: new state of the I2C START condition generation. + * This parameter can be one of the following values: + * @arg I2C_No_StartStop: Don't Generate stop and start condition. + * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0). + * @arg I2C_Generate_Start_Read: Generate Restart for read request. + * @arg I2C_Generate_Start_Write: Generate Restart for write request. + * @retval None + */ +void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_SLAVE_ADDRESS(Address)); + assert_param(IS_RELOAD_END_MODE(ReloadEndMode)); + assert_param(IS_START_STOP_MODE(StartStopMode)); + + /* Get the CR2 register value */ + tmpreg = I2Cx->CR2; + + /* clear tmpreg specific bits */ + tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)); + + /* update tmpreg */ + tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16) & I2C_CR2_NBYTES) | \ + (uint32_t)ReloadEndMode | (uint32_t)StartStopMode); + + /* update CR2 register */ + I2Cx->CR2 = tmpreg; +} + +/** + * @} + */ + +/** + * @brief Enables or disables I2C SMBus alert. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx SMBus alert. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable SMBus alert */ + I2Cx->CR1 |= I2C_CR1_ALERTEN; + } + else + { + /* Disable SMBus alert */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN); + } +} + +/** + * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection). + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN); + } +} + +/** + * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection). + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Extended clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN); + } +} + +/** + * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA + * high detection). + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx Idle clock Timeout. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Clock Timeout */ + I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE; + } + else + { + /* Disable Clock Timeout */ + I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE); + } +} + +/** + * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus + * idle SCL and SDA high when TIDLE = 1). + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param Timeout: specifies the TimeoutA to be programmed. + * @retval None + */ +void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_TIMEOUT(Timeout)); + + /* Get the old register value */ + tmpreg = I2Cx->TIMEOUTR; + + /* Reset I2Cx TIMEOUTA bit [11:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA); + + /* Set I2Cx TIMEOUTA */ + tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ; + + /* Store the new register value */ + I2Cx->TIMEOUTR = tmpreg; +} + +/** + * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout). + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param Timeout: specifies the TimeoutB to be programmed. + * @retval None + */ +void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_TIMEOUT(Timeout)); + + /* Get the old register value */ + tmpreg = I2Cx->TIMEOUTR; + + /* Reset I2Cx TIMEOUTB bit [11:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB); + + /* Set I2Cx TIMEOUTB */ + tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ; + + /* Store the new register value */ + I2Cx->TIMEOUTR = tmpreg; +} + +/** + * @brief Enables or disables I2C PEC calculation. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable PEC calculation */ + I2Cx->CR1 |= I2C_CR1_PECEN; + } + else + { + /* Disable PEC calculation */ + I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN); + } +} + +/** + * @brief Enables or disables I2C PEC transmission/reception request. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param NewState: new state of the I2Cx PEC request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable PEC transmission/reception request */ + I2Cx->CR2 |= I2C_CR2_PECBYTE; + } + else + { + /* Disable PEC transmission/reception request */ + I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE); + } +} + +/** + * @brief Returns the I2C PEC. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @retval The value of the PEC . + */ +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the slave matched address in the SR1 register */ + return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC); +} + +/** + * @} + */ + + + +/** +* @brief Reads the specified I2C register and returns its value. +* @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. +* @param I2C_Register: specifies the register to read. +* This parameter can be one of the following values: +* @arg I2C_Register_CR1: CR1 register. +* @arg I2C_Register_CR2: CR2 register. +* @arg I2C_Register_OAR1: OAR1 register. +* @arg I2C_Register_OAR2: OAR2 register. +* @arg I2C_Register_TIMINGR: TIMING register. +* @arg I2C_Register_TIMEOUTR: TIMEOUTR register. +* @arg I2C_Register_ISR: ISR register. +* @arg I2C_Register_ICR: ICR register. +* @arg I2C_Register_PECR: PECR register. +* @arg I2C_Register_RXDR: RXDR register. +* @arg I2C_Register_TXDR: TXDR register. +* @retval The value of the read register. +*/ +uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_REGISTER(I2C_Register)); + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint32_t *) tmp); +} + +/** + * @} + */ + +/** + * @brief Sends a data byte through the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Write in the DR register the data to be sent */ + I2Cx->TXDR = (uint8_t)Data; +} + +/** + * @brief Returns the most recent received data by the I2Cx peripheral. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @retval The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + + /* Return the data in the DR register */ + return (uint8_t)I2Cx->RXDR; +} + +/** + * @} + */ + +/** + * @brief Enables or disables the I2C DMA interface. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2C_DMAReq_Tx: Tx DMA transfer request + * @arg I2C_DMAReq_Rx: Rx DMA transfer request + * @param NewState: new state of the selected I2C DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2C_DMA_REQ(I2C_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected I2C DMA requests */ + I2Cx->CR1 |= I2C_DMAReq; + } + else + { + /* Disable the selected I2C DMA requests */ + I2Cx->CR1 &= (uint32_t)~I2C_DMAReq; + } +} +/** + * @} + */ +/** + * @brief Checks whether the specified I2C flag is set or not. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg I2C_FLAG_TXE: Transmit data register empty + * @arg I2C_FLAG_TXIS: Transmit interrupt status + * @arg I2C_FLAG_RXNE: Receive data register not empty + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_NACKF: NACK received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_TC: Transfer complete (master mode) + * @arg I2C_FLAG_TCR: Transfer complete reload + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus Alert + * @arg I2C_FLAG_BUSY: Bus busy + * @retval The new state of I2C_FLAG (SET or RESET). + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + uint32_t tmpreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_FLAG(I2C_FLAG)); + + /* Get the ISR register value */ + tmpreg = I2Cx->ISR; + + /* Get flag status */ + tmpreg &= I2C_FLAG; + + if (tmpreg != 0) + { + /* I2C_FLAG is set */ + bitstatus = SET; + } + else + { + /* I2C_FLAG is reset */ + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the I2Cx's pending flags. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param I2C_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg I2C_FLAG_ADDR: Address matched (slave mode) + * @arg I2C_FLAG_NACKF: NACK received flag + * @arg I2C_FLAG_STOPF: STOP detection flag + * @arg I2C_FLAG_BERR: Bus error + * @arg I2C_FLAG_ARLO: Arbitration lost + * @arg I2C_FLAG_OVR: Overrun/Underrun + * @arg I2C_FLAG_PECERR: PEC error in reception + * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_FLAG_ALERT: SMBus Alert + * @retval None + */ +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG)); + + /* Clear the selected flag */ + I2Cx->ICR = I2C_FLAG; +} + +/** + * @brief Checks whether the specified I2C interrupt has occurred or not. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2C_IT_TXIS: Transmit interrupt status + * @arg I2C_IT_RXNE: Receive data register not empty + * @arg I2C_IT_ADDR: Address matched (slave mode) + * @arg I2C_IT_NACKF: NACK received flag + * @arg I2C_IT_STOPF: STOP detection flag + * @arg I2C_IT_TC: Transfer complete (master mode) + * @arg I2C_IT_TCR: Transfer complete reload + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_ARLO: Arbitration lost + * @arg I2C_IT_OVR: Overrun/Underrun + * @arg I2C_IT_PECERR: PEC error in reception + * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_IT_ALERT: SMBus Alert + * @retval The new state of I2C_IT (SET or RESET). + */ +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + uint32_t tmpreg = 0; + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_GET_IT(I2C_IT)); + + /* Check if the interrupt source is enabled or not */ + /* If Error interrupt */ + if ((uint32_t)(I2C_IT & ERROR_IT_MASK)) + { + enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1)); + } + /* If TC interrupt */ + else if ((uint32_t)(I2C_IT & TC_IT_MASK)) + { + enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1)); + } + else + { + enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1)); + } + + /* Get the ISR register value */ + tmpreg = I2Cx->ISR; + + /* Get flag status */ + tmpreg &= I2C_IT; + + /* Check the status of the specified I2C flag */ + if ((tmpreg != RESET) && enablestatus) + { + /* I2C_IT is set */ + bitstatus = SET; + } + else + { + /* I2C_IT is reset */ + bitstatus = RESET; + } + + /* Return the I2C_IT status */ + return bitstatus; +} + +/** + * @brief Clears the I2Cx's interrupt pending bits. + * @param I2Cx: where x can be 1 or 2 or 3 to select the I2C peripheral. + * @param I2C_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2C_IT_ADDR: Address matched (slave mode) + * @arg I2C_IT_NACKF: NACK received flag + * @arg I2C_IT_STOPF: STOP detection flag + * @arg I2C_IT_BERR: Bus error + * @arg I2C_IT_ARLO: Arbitration lost + * @arg I2C_IT_OVR: Overrun/Underrun + * @arg I2C_IT_PECERR: PEC error in reception + * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag + * @arg I2C_IT_ALERT: SMBus Alert + * @retval None. + */ +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT) +{ + /* Check the parameters */ + assert_param(IS_I2C_ALL_PERIPH(I2Cx)); + assert_param(IS_I2C_CLEAR_IT(I2C_IT)); + + /* Clear the selected flag */ + I2Cx->ICR = I2C_IT; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE**********************/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_i2s.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_i2s.c new file mode 100644 index 00000000000..8c2e7e99500 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_i2s.c @@ -0,0 +1,1626 @@ +/** + ****************************************************************************** + * @file ft32f4xx_i2s.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Inter-IC Sound (I2S): + * + Initialization and Configuration + * + Communications management + * + I2S registers management + * + Data transfers management + * + Interrupts management + * @version V1.0.0 + * @date 2025-03-31 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_i2s.h" +#include "ft32f4xx_rcc.h" + +/** @defgroup I2S I2S + * @brief I2S module driver + * @{ + */ + +/** @defgroup I2S_Exported_Functions I2S Exported Functions + * @{ + */ + +/** + * @brief Deinitializes the I2Sx peripheral registers to their default reset values. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval None + */ +void I2S_DeInit(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + if (I2Sx == I2S2) + { + /* Enable I2S2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2S2, ENABLE); + /* Release I2S2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2S2, DISABLE); + } + else + { + /* Enable I2S3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2S3, ENABLE); + /* Release I2S3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2S3, DISABLE); + } +} + + +/** + * @brief Initializes the I2Sx peripheral according to the specified + * parameters in the I2S_InitStruct. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure that + * contains the configuration information for the specified I2S peripheral. + * @retval None + */ +void I2S_Init(I2S_TypeDef* I2Sx, I2S_InitTypeDef* I2S_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_CH0_CONFIG(I2S_InitStruct->I2S_Channel0)); + assert_param(IS_I2S_CH1_CONFIG(I2S_InitStruct->I2S_Channel1)); + assert_param(IS_I2S_MASTERSLAVE_STATE(I2S_InitStruct->I2S_TranMasterSlaveConfig)); + assert_param(IS_I2S_SAMPLE_RATE(I2S_InitStruct->I2S_TranSampleRate)); + assert_param(IS_I2S_SAMPLE_RATE(I2S_InitStruct->I2S_RecSampleRate)); + assert_param(IS_I2S_RESOLUTION(I2S_InitStruct->I2S_TranSampleResolution)); + assert_param(IS_I2S_RESOLUTION(I2S_InitStruct->I2S_RecSampleResolution)); + assert_param(IS_I2S_FIFO_THRESHOLD(I2S_InitStruct->I2S_TFIFOAEmptyThreshold)); + assert_param(IS_I2S_FIFO_THRESHOLD(I2S_InitStruct->I2S_TFIFOAFullThreshold)); + assert_param(IS_I2S_FIFO_THRESHOLD(I2S_InitStruct->I2S_RFIFOAEmptyThreshold)); + assert_param(IS_I2S_FIFO_THRESHOLD(I2S_InitStruct->I2S_RFIFOAFullThreshold)); + assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard)); + + /* Software reset I2S special function register + * Software reset I2S TX FIFO + * Software reset I2S RX FIFO + * Software reset I2S TX control unit + * Software reset I2S RX control unit + * Software reset I2S channel 0 + * Software reset I2S channel 1 */ + I2Sx->CTRL &= (uint32_t)~(((uint32_t)I2S_CTRL_SFRRST) | + ((uint32_t)I2S_CTRL_TFIFORST) | ((uint32_t)I2S_CTRL_RFIFORST) | + ((uint32_t)I2S_CTRL_TSYNCRST) | ((uint32_t)I2S_CTRL_RSYNCRST) | + ((uint32_t)I2S_CTRL_I2SEN0) | ((uint32_t)I2S_CTRL_I2SEN1)); + + /*---------------------------- I2Sx Channel0 Configuration ------------------*/ + /* Configure I2Sx channel : enable or disable, transmitter or receiver */ + /* Set I2SEN0 bit according to I2S_Channel0 value */ + /* Set TRCFG0 bits according to I2S_Channel0 value */ + if (I2S_InitStruct->I2S_Channel0 == I2S_Ch0_Disable) + { + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_I2SEN0); + } + else if (I2S_InitStruct->I2S_Channel0 == I2S_Ch0_Transmitter) + { + I2Sx->CTRL |= I2S_CTRL_TRCFG0; + } + else if (I2S_InitStruct->I2S_Channel0 == I2S_Ch0_Receiver) + { + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_TRCFG0); + } + + /*---------------------------- I2Sx Channel1 Configuration ------------------*/ + /* Configure I2Sx channel : enable or disable, transmitter or receiver */ + /* Set I2SEN1 bit according to I2S_Channel1 value */ + /* Set TRCFG1 bit according to I2S_Channel1 value */ + if (I2S_InitStruct->I2S_Channel1 == I2S_Ch1_Disable) + { + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_I2SEN1); + } + else if (I2S_InitStruct->I2S_Channel1 == I2S_Ch1_Transmitter) + { + I2Sx->CTRL |= I2S_CTRL_TRCFG1; + } + else if (I2S_InitStruct->I2S_Channel1 == I2S_Ch1_Receiver) + { + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_TRCFG1); + } + + /*-------------------- I2Sx transmitter master or slave configuration --------------*/ + /* Set TMS bit according to I2S_TranMasterSlaveConfig value*/ + if (I2S_InitStruct->I2S_TranMasterSlaveConfig != I2S_SLAVE) + { + /* Set I2S transmitter synchronizing unit to master */ + I2Sx->CTRL |= I2S_CTRL_TMS; + } + else + { + /* Set I2S transmitter synchronizing unit to slave */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_TMS); + } + + /*-------------------- I2Sx receiver master or slave configuration --------------*/ + /* Set RMS bit according to I2S_RecMasterSlaveConfig value*/ + if (I2S_InitStruct->I2S_RecMasterSlaveConfig != I2S_SLAVE) + { + /* Set I2S receiver synchronizing unit to master */ + I2Sx->CTRL |= I2S_CTRL_RMS; + } + else + { + /* Set I2S receiver synchronizing unit to slave */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_RMS); + } + + /*-------------- I2Sx tansmitter sample rate configuration -----------------*/ + /* Set TSAMPLERATE bits according to I2S_TranSampleRate values */ + I2Sx->SRR |= I2S_InitStruct->I2S_TranSampleRate; + /*-------------- I2Sx transmitter sample resolution configuration ----------*/ + /* Set TRESOLUTION bits according to I2S_TranSampleResolution values */ + I2Sx->SRR |= (I2S_InitStruct->I2S_TranSampleResolution << 11); + /*-------------- I2Sx receiver sample rate configuration -------------------*/ + /* Set RSAMPLERATE bits according to I2S_RecSampleRate values */ + I2Sx->SRR |= (I2S_InitStruct->I2S_RecSampleRate << 16); + /*-------------- I2Sx receiver sample resolution configuration -------------*/ + /* Set RRESOLUTION bits according to I2S_RecSampleResolution values */ + I2Sx->SRR |= (I2S_InitStruct->I2S_RecSampleResolution << 27); + + /*----------I2S transmit FIFO almost empty threshold configuration ---------*/ + /* Set TAEMPTYTHRESHOLD bits according to I2S_TFIFOAEmptyThreshold values*/ + I2Sx->TFIFO_CTRL |= (I2S_InitStruct->I2S_TFIFOAEmptyThreshold); + /*----------I2S transmit FIFO almost full threshold configuration ---------*/ + /* Get the old register value */ + tmpreg = I2Sx->TFIFO_CTRL; + /* Reset I2Sx TAFULLTHRESHOLD bit [2:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_TFIFO_CTRL_TAFULLTHRESHOLD); + /* Set TAFULLTHRESHOLD bits according to I2S_TFIFOAFullThreshold values*/ + tmpreg |= (uint32_t)(((uint32_t)I2S_InitStruct->I2S_TFIFOAFullThreshold << 16) & + I2S_TFIFO_CTRL_TAFULLTHRESHOLD); + /* Store the new register value */ + I2Sx->TFIFO_CTRL = tmpreg; + + + /*----------I2S receive FIFO almost empty threshold configuration ---------*/ + /* Set RAEMPTYTHRESHOLD bits according to I2S_RFIFOAEmptyThreshold values*/ + I2Sx->RFIFO_CTRL |= (I2S_InitStruct->I2S_RFIFOAEmptyThreshold << 16); + /*----------I2S receive FIFO almost full threshold configuration ---------*/ + /* Get the old register value */ + tmpreg = I2Sx->RFIFO_CTRL; + /* Reset I2Sx RAFULLTHRESHOLD bit [2:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_RFIFO_CTRL_RAFULLTHRESHOLD); + /* Set RAFULLTHRESHOLD bits according to I2S_RFIFOAFullThreshold values*/ + tmpreg |= (uint32_t)(((uint32_t)I2S_InitStruct->I2S_RFIFOAFullThreshold << 16) & + I2S_RFIFO_CTRL_RAFULLTHRESHOLD); + /* Store the new register value */ + I2Sx->RFIFO_CTRL = tmpreg; + + /*------------------I2S standard configuration------------------------------*/ + /* Set DEV_CONF registers according to I2S_STANDARD values */ + I2Sx->DEV_CONF = I2S_InitStruct->I2S_Standard; +} + + +/** + * @brief Fills each I2S_InitStruct member with its default value. + * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure which will be initialized. + * @retval None + */ +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct) +{ + /*---------------- Reset I2S init structure parameters values --------------*/ + /* Initialize the I2S_Channel0 member */ + I2S_InitStruct->I2S_Channel0 = 0; + /* Initialize the I2S_Channel1 member */ + I2S_InitStruct->I2S_Channel1 = 0; + + /* Initialize the I2S_TranMasterSlaveConfig member */ + I2S_InitStruct->I2S_TranMasterSlaveConfig = 0; + /* Initialize the I2S_RecMasterSlaveConfig member */ + I2S_InitStruct->I2S_RecMasterSlaveConfig = 0; + + /* Initialize the I2S_TranSampleRate member */ + I2S_InitStruct->I2S_TranSampleRate = 0; + /* Initialize the I2S_TranSampleResolution member */ + I2S_InitStruct->I2S_TranSampleResolution = 0; + /* Initialize the I2S_RecSampleRate member */ + I2S_InitStruct->I2S_RecSampleRate = 0; + /* Initialize the I2S_RecSampleResolution member */ + I2S_InitStruct->I2S_RecSampleResolution = 0; + + /* Initialize the I2S_TFIFOAEmptyThreshold member */ + I2S_InitStruct->I2S_TFIFOAEmptyThreshold = 0; + /* Initialize the I2S_TFIFOAFullThreshold member */ + I2S_InitStruct->I2S_TFIFOAFullThreshold = 7; + /* Initialize the I2S_RFIFOAEmptyThreshold member */ + I2S_InitStruct->I2S_RFIFOAEmptyThreshold = 0; + /* Initialize the I2S_RFIFOAFullThreshold member */ + I2S_InitStruct->I2S_RFIFOAFullThreshold = 7; + + /* Initialize the I2S_Standard member */ + I2S_InitStruct->I2S_Standard = 0; +} + +/** + * @brief Enables or disables I2S channel + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param CHy: I2S channel y select, where y can be 0 or 1 to select the I2S channel + * This parameter can be any combination of the following values: + * @arg I2S_CH0: I2S channel 0 select + * @arg I2S_CH1: I2S channel 1 select + * @param NewState: new state of the I2Sx channel 0/1. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_ChannelConfig(I2S_TypeDef* I2Sx, uint32_t CHy, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_CHANNEL_SEL(CHy)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable channel y */ + I2Sx->CTRL |= CHy; + } + else + { + /* Disable channel y */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)CHy); + } +} + + +/** + * @brief I2S channel 0/1 transmitter or receiver config + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param CHy_TRANREC: I2S channel y transmitter or receiver config, + * where y can be 0 or 1 to select the I2S channel. + * This parameter can be any combination of the following values: + * @arg I2S_CH0_TRANREC: I2S channel 0 is transmitter or receiver + * @arg I2S_CH1_TRANREC: I2S channel 1 is transmitter or receiver + * @param I2S_TranRec: transmitter or receiver of the I2Sx channel 0/1. + * This parameter can be one of the following values: + * @arg I2S_TRANSMITTER: I2S channel y is transmitter + * @arg I2S_RECEIVER : I2S channel y is receiver + * @retval None + */ +void I2S_ChannelTranRecConfig(I2S_TypeDef* I2Sx, uint32_t CHy_TRANREC, uint32_t I2S_TranRec) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_CHANNEL_TRANREC(CHy_TRANREC)); + assert_param(IS_I2S_TRANREC_STATE(I2S_TranRec)); + + if (I2S_TranRec != I2S_RECEIVER) + { + /* Set channel y to transmitter */ + I2Sx->CTRL |= CHy_TRANREC; + } + else + { + /* Set channel y to receiver */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)CHy_TRANREC); + } +} + + +/** + * @brief Enables or disables the Loop-back test for I2S channel 0/1 + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of the I2Sx channel 0/1 Loop-back test. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_LoopBackCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Loop-Back test mode */ + I2Sx->CTRL |= I2S_CTRL_LOOPBACK01; + } + else + { + /* Disable Loop-Back test mode */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_LOOPBACK01); + } +} + + +/** + * @brief Software reset I2S special function register. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval None + */ +void I2S_SFRResetCmd(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Reset SFR */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_SFRRST); +} + + +/** + * @brief Configures I2S transmitter synchronizing unit as the master or slave + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_MS: master or slave of the I2Sx transmitter synchronizing unit. + * This parameter can be one of the following values: + * @arg I2S_MASTER: I2S transmitter synchronizing unit is master. + * @arg I2S_SLAVE : I2S transmitter synchronizing unit is slave. + * @retval None + */ +void I2S_TranMasterSlaveConfig(I2S_TypeDef* I2Sx, uint32_t I2S_MS) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_MASTERSLAVE_STATE(I2S_MS)); + + if (I2S_MS != I2S_SLAVE) + { + /* Set I2S transmitter synchronizing unit to master */ + I2Sx->CTRL |= I2S_CTRL_TMS; + } + else + { + /* Set I2S transmitter synchronizing unit to slave */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_TMS); + } +} + + +/** + * @brief Configures I2S receiver synchronizing unit as the master or slave + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_MS: master or slave of the I2Sx receiver synchronizing unit. + * This parameter can be one of the following values: + * @arg I2S_MASTER: I2S receiver synchronizing unit is master. + * @arg I2S_SLAVE : I2S receiver synchronizing unit is slave. + * @retval None + */ +void I2S_RecMasterSlaveConfig(I2S_TypeDef* I2Sx, uint32_t I2S_MS) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_MASTERSLAVE_STATE(I2S_MS)); + + if (I2S_MS != I2S_SLAVE) + { + /* Set I2S receiver synchronizing unit to master */ + I2Sx->CTRL |= I2S_CTRL_RMS; + } + else + { + /* Set I2S receiver synchronizing unit to slave */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_RMS); + } +} + + +/** + * @brief Software reset I2S transmit FIFO. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval None + */ +void I2S_TFIFOResetCmd(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Reset transmit FIFO */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_TFIFORST); +} + + +/** + * @brief Software reset I2S receive FIFO. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval None + */ +void I2S_RFIFOResetCmd(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Reset receive FIFO */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_RFIFORST); +} + + +/** + * @brief Software reset I2S transmitter synchronizing unit. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of the I2Sx transmitter synchronizing unit software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_TranSyncResetCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Reset transmitter synchronizing unit */ + if (NewState != DISABLE) + { + /* Enable software reset transmitter synchronizing unit */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_TSYNCRST); + } + else + { + /* Disable software reset transmitter synchronizing unit */ + I2Sx->CTRL |= I2S_CTRL_TSYNCRST; + } +} + + +/** + * @brief Software reset I2S Receiver synchronizing unit. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of the I2Sx receiver synchronizing unit software reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_RecSyncResetCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable software reset receiver synchronizing unit */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_RSYNCRST); + } + else + { + /* Disable software reset receiver synchronizing unit */ + I2Sx->CTRL |= I2S_CTRL_RSYNCRST; + } +} + +/** + * @brief Enables or disables the Loop-back test for I2S transmitter + * synchronizing unit. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of the I2Sx transmitter synchronizing unit + * loop-back test. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_TranSyncLoopBackCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Loop-back test for I2S transmitter synchronizing unit */ + I2Sx->CTRL |= I2S_CTRL_TSYNCLOOPBACK; + } + else + { + /* Disable Loop-back test for I2S transmitter synchronizing unit */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_TSYNCLOOPBACK); + } +} + + +/** + * @brief Enables or disables the Loop-back test for I2S receiver + * synchronizing unit. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of the I2Sx receiver synchronizing unit + * loop-back test. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_RecSyncLoopBackCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Loop-back test for I2S receiver synchronizing unit*/ + I2Sx->CTRL |= I2S_CTRL_RSYNCLOOPBACK; + } + else + { + /* Disable Loop-back test for I2S receiver synchronizing unit */ + I2Sx->CTRL &= (uint32_t)~((uint32_t)I2S_CTRL_RSYNCLOOPBACK); + } +} + + +/** + * @brief Configures the transmitter sample rate. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param SAMPLE_RATE specifies the sample rate to be programmed. + * @retval None + */ +void I2S_TranSampleRateConfig(I2S_TypeDef* I2Sx, uint16_t SAMPLE_RATE) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_SAMPLE_RATE(SAMPLE_RATE)); + + /* Get the old register value */ + tmpreg = I2Sx->SRR; + + /* Reset I2Sx TSAMPLERATE bit [10:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_SRR_TSAMPLERATE); + + /* Set I2Sx TSAMPLERATE */ + tmpreg |= (uint32_t)((uint32_t)SAMPLE_RATE & I2S_SRR_TSAMPLERATE); + + /* Store the new register value */ + I2Sx->SRR = tmpreg; +} + + +/** + * @brief Configures the transmitter sample resolution. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param RESOLUTION specifies the sample resolution to be programmed. + * @retval None + */ +void I2S_TranSampleResolutionConfig(I2S_TypeDef* I2Sx, uint8_t RESOLUTION) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_RESOLUTION(RESOLUTION)); + + /* Get the old register value */ + tmpreg = I2Sx->SRR; + + /* Reset I2Sx TRESOLUTION bit [10:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_SRR_TRESOLUTION); + + /* Set I2Sx TRESOLUTION */ + tmpreg |= (uint32_t)(((uint32_t)RESOLUTION << 11) & I2S_SRR_TRESOLUTION); + + /* Store the new register value */ + I2Sx->SRR = tmpreg; +} + + +/** + * @brief Configures the receiver sample rate. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param SAMPLE_RATE specifies the sample rate to be programmed. + * @retval None + */ +void I2S_RecSampleRateConfig(I2S_TypeDef* I2Sx, uint16_t SAMPLE_RATE) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_SAMPLE_RATE(SAMPLE_RATE)); + + /* Get the old register value */ + tmpreg = I2Sx->SRR; + + /* Reset I2Sx RSAMPLERATE bit [10:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_SRR_RSAMPLERATE); + + /* Set I2Sx RSAMPLERATE */ + tmpreg |= (uint32_t)(((uint32_t)SAMPLE_RATE << 16) & I2S_SRR_RSAMPLERATE); + + /* Store the new register value */ + I2Sx->SRR = tmpreg; +} + + +/** + * @brief Configures the receiver sample resolution. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param RESOLUTION specifies the sample resolution to be programmed. + * @retval None + */ +void I2S_RecSampleResolutionConfig(I2S_TypeDef* I2Sx, uint8_t RESOLUTION) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_RESOLUTION(RESOLUTION)); + + /* Get the old register value */ + tmpreg = I2Sx->SRR; + + /* Reset I2Sx RRESOLUTION bit [10:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_SRR_RRESOLUTION); + + /* Set I2Sx RRESOLUTION */ + tmpreg |= (uint32_t)(((uint32_t)RESOLUTION << 27) & I2S_SRR_RRESOLUTION); + + /* Store the new register value */ + I2Sx->SRR = tmpreg; +} + + +/** + * @brief Enables or disables I2S channel 0/1 clock + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param CHy_CLOCK: I2S channel y clock strobe, where y can be 0 or 1 + * to select the I2S channel. + * This parameter can be any combination of the following values: + * @arg I2S_CH0_CLOCK_STROBE: I2S channel 0 clock strobe + * @arg I2S_CH1_CLOCK_STROBE: I2S channel 1 clock strobe + * @param NewState: new state of the I2Sx channel 0/1 clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_ChannelClockConfig(I2S_TypeDef* I2Sx, uint32_t CHy_CLOCK, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_CHANNEL_CLOCK_STROBE(CHy_CLOCK)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable channel y clock */ + I2Sx->CID_CTRL &= (uint32_t)~((uint32_t)CHy_CLOCK); + } + else + { + /* Disable channel y clock */ + I2Sx->CID_CTRL |= CHy_CLOCK; + } +} + + +/** + * @brief Enables or disables I2S transmitter synchronizing unit clock + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of the I2Sx transmitter synchronizing unit clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_TranSyncUnitCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable transmitter synchronizing unit clock*/ + I2Sx->CID_CTRL &= (uint32_t)~((uint32_t)I2S_CID_CTRL_STROBETS); + } + else + { + /* Disable transmitter synchronizing unit clock */ + I2Sx->CID_CTRL |= I2S_CID_CTRL_STROBETS; + } +} + + +/** + * @brief Enables or disables I2S receiver synchronizing unit clock + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of the I2Sx receiver synchronizing unit clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_RecSyncUnitCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable receiver synchronizing unit clock*/ + I2Sx->CID_CTRL &= (uint32_t)~((uint32_t)I2S_CID_CTRL_STROBERS); + } + else + { + /* Disable receiver synchronizing unit clock */ + I2Sx->CID_CTRL |= I2S_CID_CTRL_STROBERS; + } +} + + +/** + * @brief Returns the I2S transmit FIFO level status. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval The value of the I2S transmit FIFO level status. + */ +uint8_t I2S_GetTranFIFOLevel(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Return the I2S transmit FIFO level status */ + return (uint8_t)((uint32_t)I2Sx->TFIFO_STAT & I2S_TFIFO_STAT_TLEVEL) ; +} + + +/** + * @brief Returns the I2S receive FIFO level status. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval The value of the I2S receive FIFO level status. + */ +uint8_t I2S_GetRecFIFOLevel(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Return the I2S receive FIFO level status */ + return (uint8_t)((uint32_t)I2Sx->RFIFO_STAT & I2S_RFIFO_STAT_RLEVEL) ; +} + + +/** + * @brief Configures the threshold for almost empty flag in I2S transmit fifo. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param FIFO_Threshold specifies the fifo threshold to be programmed. + * @retval None + */ +void I2S_TFIFOAEmptyThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_FIFO_THRESHOLD(FIFO_Threshold)); + + /* Get the old register value */ + tmpreg = I2Sx->TFIFO_CTRL; + + /* Reset I2Sx TAEMPTYTHRESHOLD bit [2:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD); + + /* Set I2Sx TAEMPTYTHRESHOLD */ + tmpreg |= (uint32_t)((uint32_t)FIFO_Threshold & I2S_TFIFO_CTRL_TAEMPTYTHRESHOLD); + + /* Store the new register value */ + I2Sx->TFIFO_CTRL = tmpreg; +} + + +/** + * @brief Configures the threshold for almost full flag in I2S transmit fifo. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param FIFO_Threshold specifies the fifo threshold to be programmed. + * @retval None + */ +void I2S_TFIFOAFullThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_FIFO_THRESHOLD(FIFO_Threshold)); + + /* Get the old register value */ + tmpreg = I2Sx->TFIFO_CTRL; + + /* Reset I2Sx TAFULLTHRESHOLD bit [2:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_TFIFO_CTRL_TAFULLTHRESHOLD); + + /* Set I2Sx TAFULLTHRESHOLD */ + tmpreg |= (uint32_t)(((uint32_t)FIFO_Threshold << 16) & I2S_TFIFO_CTRL_TAFULLTHRESHOLD); + + /* Store the new register value */ + I2Sx->TFIFO_CTRL = tmpreg; +} + + +/** + * @brief Configures the threshold for almost empty flag in I2S receive fifo. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param FIFO_Threshold specifies the fifo threshold to be programmed. + * @retval None + */ +void I2S_RFIFOAEmptyThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_FIFO_THRESHOLD(FIFO_Threshold)); + + /* Get the old register value */ + tmpreg = I2Sx->RFIFO_CTRL; + + /* Reset I2Sx RAEMPTYTHRESHOLD bit [2:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD); + + /* Set I2Sx RAEMPTYTHRESHOLD */ + tmpreg |= (uint32_t)((uint32_t)FIFO_Threshold & I2S_RFIFO_CTRL_RAEMPTYTHRESHOLD); + + /* Store the new register value */ + I2Sx->RFIFO_CTRL = tmpreg; +} + + +/** + * @brief Configures the threshold for almost full flag in I2S receive fifo. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param FIFO_Threshold specifies the fifo threshold to be programmed. + * @retval None + */ +void I2S_RFIFOAFullThresholdConfig(I2S_TypeDef* I2Sx, uint8_t FIFO_Threshold) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_FIFO_THRESHOLD(FIFO_Threshold)); + + /* Get the old register value */ + tmpreg = I2Sx->RFIFO_CTRL; + + /* Reset I2Sx RAFULLTHRESHOLD bit [2:0] */ + tmpreg &= (uint32_t)~((uint32_t)I2S_RFIFO_CTRL_RAFULLTHRESHOLD); + + /* Set I2Sx RAFULLTHRESHOLD */ + tmpreg |= (uint32_t)(((uint32_t)FIFO_Threshold << 16) & I2S_RFIFO_CTRL_RAFULLTHRESHOLD); + + /* Store the new register value */ + I2Sx->RFIFO_CTRL = tmpreg; +} + + +/** + * @brief Configures the I2S standard. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param STANDARD specifies the standard to be followed in I2S transmittion. + * This parameter can be one of the following values: + * @arg I2S_Philips : I2S Philips mode + * @arg I2S_Right_Justified: I2S Right-Justified mode + * @arg I2S_Left_Justified : I2S Left-Justified mode + * @arg I2S_DSP : I2S DSP mode + * @retval None + */ +void I2S_StandardConfig(I2S_TypeDef* I2Sx, uint32_t Standard) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_STANDARD(Standard)); + + /* Store the new register value */ + I2Sx->DEV_CONF = Standard; +} + + +/** + * @brief Configures I2S continuous serial clock active edge for transmission. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_SCK_Polar specifies the active edge of I2S SCK signals. + * This parameter can be one of the following values: + * @arg I2S_SCK_POLAR_RISE: Seriral clock active edge is rising edge. + * @arg I2S_SCK_POLAR_FALL: Seriral clock active edge is falling edge. + * @retval None + */ +void I2S_TranSckPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_SCK_Polar) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_SCK_POLAR(I2S_SCK_Polar)); + + if (I2S_SCK_Polar != I2S_SCK_POLAR_RISE) + { + /* Set I2S serial clock active edge for transmission to falling edge */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_TRANSCKPOLAR; + } + else + { + /* Set I2S serial clock active edge for transmission to rising edge */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_TRANSCKPOLAR); + } +} + + +/** + * @brief Configures I2S continuous serial clock active edge for reception. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_SCK_Polar specifies the active edge of I2S SCK signals. + * This parameter can be one of the following values: + * @arg I2S_SCK_POLAR_RISE: Seriral clock active edge is rising edge. + * @arg I2S_SCK_POLAR_FALL: Seriral clock active edge is falling edge. + * @retval None + */ +void I2S_RecSckPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_SCK_Polar) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_SCK_POLAR(I2S_SCK_Polar)); + + if (I2S_SCK_Polar != I2S_SCK_POLAR_RISE) + { + /* Set I2S serial clock active edge for receprion to falling edge */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_RECSCKPOLAR; + } + else + { + /* Set I2S serial clock active edge for reception to rising edge */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_RECSCKPOLAR); + } +} + + +/** + * @brief Configures I2S word select signal polarity selection for transmission. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_WS_Polar specifies the polarity of I2S WS signals. + * This parameter can be one of the following values: + * @arg I2S_WS_POLAR_0: the level of WS signal for the transmitted + * left channel data sample is '0' and the level of WS signal + * for the transmitted right channel data sample is '1'. + * @arg I2S_WS_POLAR_1: the level of WS signal for the transmitted + * left channel data sample is '1' and the level of WS signal + * for the transmitted right channel data sample is '0'. + * @retval None + */ +void I2S_TranWSPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Polar) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_WS_POLAR(I2S_WS_Polar)); + + if (I2S_WS_Polar != I2S_WS_POLAR_0) + { + /* Set I2S WS signal polarity for transmission to 1 */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_TRANWSPOLAR; + } + else + { + /* Set I2S WS signal polarity for transmission to 0 */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_TRANWSPOLAR); + } +} + + +/** + * @brief Configures I2S word select signal polarity selection for reception. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_WS_Polar specifies the polarity of I2S WS signals. + * This parameter can be one of the following values: + * @arg I2S_WS_POLAR_0: the level of WS signal for the received + * left channel data sample is '0' and the level of WS signal + * for the received right channel data sample is '1'. + * @arg I2S_WS_POLAR_1: the level of WS signal for the received + * left channel data sample is '1' and the level of WS signal + * for the received right channel data sample is '0'. + * @retval None + */ +void I2S_RecWSPolarConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Polar) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_WS_POLAR(I2S_WS_Polar)); + + if (I2S_WS_Polar != I2S_WS_POLAR_0) + { + /* Set I2S WS signal polarity for reception to 1 */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_RECWSPOLAR; + } + else + { + /* Set I2S WS signal polarity for reception to 0 */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_RECWSPOLAR); + } +} + + +/** + * @brief Configures alignment of the transmitted digital data sample at the APB bus. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_ALIGN specifies the alignment of the digital data sample. + * This parameter can be one of the following values: + * @arg I2S_ALIGN_MSB: the MSB side alignment of the resolution-width + * data sample. + * @arg I2S_ALIGN_LSB: the MSB side alignment of the resolution-width + * data sample. + * @retval None + */ +void I2S_TranAPBAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_ALIGNMENT(I2S_Align)); + + if (I2S_Align != I2S_ALIGN_LSB) + { + /* Set the MSB side alignment the resolution-width transmitted + * digital data sample at the APB bus */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_TRANAPBALIGNLR; + } + else + { + /* Set the LSB side alignment the resolution-width transmitted + * digital data sample at the APB bus */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_TRANAPBALIGNLR); + } +} + + +/** + * @brief Configures alignment of the received digital data sample at the APB bus. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_ALIGN specifies the alignment of the digital data sample. + * This parameter can be one of the following values: + * @arg I2S_ALIGN_MSB: the MSB side alignment of the resolution-width + * data sample. + * @arg I2S_ALIGN_LSB: the MSB side alignment of the resolution-width + * data sample. + * @retval None + */ +void I2S_RecAPBAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_ALIGNMENT(I2S_Align)); + + if (I2S_Align != I2S_ALIGN_LSB) + { + /* Set the MSB side alignment the resolution-width received + * digital data sample at the APB bus */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_RECAPBALIGNLR; + } + else + { + /* Set the LSB side alignment the resolution-width received + * digital data sample at the APB bus */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_RECAPBALIGNLR); + } +} + + +/** + * @brief Configures alignment of the transmitted digital data sample at the + * I2S serial data line. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_ALIGN specifies the alignment of the digital data sample. + * This parameter can be one of the following values: + * @arg I2S_ALIGN_MSB: the MSB side alignment of the resolution-width + * data sample. + * @arg I2S_ALIGN_LSB: the MSB side alignment of the resolution-width + * data sample. + * @retval None + */ +void I2S_TranI2SAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_ALIGNMENT(I2S_Align)); + + if (I2S_Align != I2S_ALIGN_LSB) + { + /* Set the MSB side alignment the resolution-width transmitted + * digital data sample at the I2S serial data line */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_TRANI2SALIGNLR; + } + else + { + /* Set the LSB side alignment the resolution-width transmitted + * digital data sample at the I2S serial data line */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_TRANI2SALIGNLR); + } +} + + +/** + * @brief Configures alignment of the received digital data sample at the + * I2S serial data line. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_ALIGN specifies the alignment of the digital data sample. + * This parameter can be one of the following values: + * @arg I2S_ALIGN_MSB: the MSB side alignment of the resolution-width + * data sample. + * @arg I2S_ALIGN_LSB: the MSB side alignment of the resolution-width + * data sample. + * @retval None + */ +void I2S_RecI2SAlignConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Align) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_ALIGNMENT(I2S_Align)); + + if (I2S_Align != I2S_ALIGN_LSB) + { + /* Set the MSB side alignment the resolution-width received + * digital data sample at the I2S serial data line */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_RECI2SALIGNLR; + } + else + { + /* Set the LSB side alignment the resolution-width received + * digital data sample at the I2S serial data line */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_RECI2SALIGNLR); + } +} + + +/** + * @brief Configures the transmitted valid data delay at the I2S SD + * output line afte the WS line edge + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_Tran_data_WS_del specifies the the transmitted valid data delay at + * the I2S SD output line afte the WS line edge + * This parameter can be one of the following values: + * @arg I2S_TRAN_DATA_WS_DEL_0: The serial data for transmission are + * updated on the second rising/falling edge of the clock signal + * after the WS signal change. + * @arg I2S_TRAN_DATA_WS_DEL_1: The serial data for transmission are + * updated on the first rising/falling edge of the clock signal + * after the WS signal change. + * @retval None + */ +void I2S_TranDataWSDelConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Tran_Data_WS_Del) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_TRAN_DATA_WS_DEL(I2S_Tran_Data_WS_Del)); + + if (I2S_Tran_Data_WS_Del != I2S_TRAN_DATA_WS_DEL_0) + { + /* Set the serial data for transmission are updated on the + * first rising/falling edge of the clock signal after the + * WS signal change */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_TRANDATAWSDEL; + } + else + { + /* Set the serial data for transmission are updated on the + * second rising/falling edge of the clock signal after the + * WS signal change */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_TRANDATAWSDEL); + } +} + + +/** + * @brief Configures the received valid data delay at the I2S SD + * input line afte the WS line edge + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_Rec_Data_WS_Del specifies the the received valid data delay at + * the I2S SD output line afte the WS line edge + * This parameter can be one of the following values: + * @arg I2S_REC_DATA_WS_DEL_0: The received serial data are updated + * on the thired rising/falling edge of the clock signal + * after the WS signal change. + * @arg I2S_REC_DATA_WS_DEL_1: The received serial data are updated + * on the second rising/falling edge of the clock signal + * after the WS signal change. + * @retval None + */ +void I2S_RecDataWSDelConfig(I2S_TypeDef* I2Sx, uint8_t I2S_Rec_Data_WS_Del) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_REC_DATA_WS_DEL(I2S_Rec_Data_WS_Del)); + + if (I2S_Rec_Data_WS_Del != I2S_REC_DATA_WS_DEL_0) + { + /* Set the received serial data are updated on the + * second rising/falling edge of the clock signal after the + * WS signal change */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_RECDATAWSDEL; + } + else + { + /* Set the received serial data are updated on the + * third rising/falling edge of the clock signal after the + * WS signal change */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_RECDATAWSDEL); + } +} + + +/** + * @brief Configures the I2S WS signal format for the transmitter unit. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_WS_Format: I2Sx WS signal format. + * This parameter can be one of the following values: + * @arg I2S_WS_PHILIPS: WS signal format specific to the standard + * Philips I2S interface. + * @arg I2S_WS_DSP : WS signal format specific to the DSP audio + * interface mode. + * @retval None + */ + +void I2S_TranWSFormatConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Format) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_WS_FORMAT(I2S_WS_Format)); + + if (I2S_WS_Format != I2S_WS_PHILIPS) + { + /* Set I2S WS signal format to the DSP audio interface mode + * for the transmitter unit */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_TRANWSDSPMODE; + } + else + { + /* Set I2S WS signal format to the standard Philips I2S interface + * for the transmitter unit */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_TRANWSDSPMODE); + } +} + + +/** + * @brief Configures the I2S WS signal format for the receiver unit. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_WS_Format: I2Sx WS signal format. + * This parameter can be one of the following values: + * @arg I2S_WS_PHILIPS: WS signal format specific to the standard + * Philips I2S interface. + * @arg I2S_WS_DSP : WS signal format specific to the DSP audio + * interface mode. + * @retval None + */ + +void I2S_RecWSFormatConfig(I2S_TypeDef* I2Sx, uint8_t I2S_WS_Format) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_WS_FORMAT(I2S_WS_Format)); + + if (I2S_WS_Format != I2S_WS_PHILIPS) + { + /* Set I2S WS signal format to the DSP audio interface mode + * for the receiver unit */ + I2Sx->DEV_CONF |= I2S_DEV_CONF_RECWSDSPMODE; + } + else + { + /* Set I2S WS signal format to the standard Philips I2S interface + * for the receiver unit */ + I2Sx->DEV_CONF &= (uint32_t)~((uint32_t)I2S_DEV_CONF_RECWSDSPMODE); + } +} + + +/** + * @brief Reads the specified I2S register and returns its value. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_Register: specifies the register to read. + * This parameter can be one of the following values: + * @arg I2S_Register_CTRL : CTRL register + * @arg I2S_Register_INTR_STAT : INTR_STAT register + * @arg I2S_Register_SRR : SRR register + * @arg I2S_Register_CID_CTRL : CID_CTRL register + * @arg I2S_Register_TFIFO_STAT: TFIFO_STAT register + * @arg I2S_Register_RFIFO_STAT: RFIFO_STAT register + * @arg I2S_Register_TFIFO_CTRL: TFIFO_CTRL register + * @arg I2S_Register_RFIFO_CTRL: RFIFO_CTRL register + * @arg I2S_Register_DEV_CONF : DEV_CONF register + * @arg I2S_Register_POLL_STAT : POLL_STAT register + * @retval The value of the read register. + */ + +uint32_t I2S_ReadRegister(I2S_TypeDef* I2Sx, uint8_t I2S_Register) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_REGISTER(I2S_Register)); + + tmp = (uint32_t)I2Sx; + tmp += I2S_Register; + + /* Return the selected register value */ + return (*(__IO uint32_t *) tmp); +} + + +/** + * @brief Transmit a data byte through the I2Sx peripheral. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param Data: Byte to be transmitted.. + * @retval None + */ +void I2S_SendData(I2S_TypeDef* I2Sx, uint32_t Data) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Write in the FIFO the data to be sent */ + I2Sx->FIFO = (uint32_t)Data; +} + +/** + * @brief Returns the most recent received data by the I2Sx peripheral. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval The value of the received data. + */ +uint32_t I2S_ReceiveData(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Return the data in the DR register */ + return (uint32_t)I2Sx->FIFO; +} + + +/** + * @brief Enables or disables all the I2S interrupts mask request. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param NewState: new state of all the I2Sx interrupts request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_AllITMaskCmd(I2S_TypeDef* I2Sx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable all the I2S interrupts request mask*/ + I2Sx->CID_CTRL |= I2S_CID_CTRL_INTREQMASK; + } + else + { + /* I2S interrupts request individual maks*/ + I2Sx->CID_CTRL &= (uint32_t)~((uint32_t)I2S_CID_CTRL_INTREQMASK); + } +} + + +/** + * @brief Enables or disables the specified I2S FIFO interrupts. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_IT_Mask: specifies the I2S interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_TFIFOEMPTY_MASK : Transmit fifo empty flag mask + * @arg I2S_TFIFOAEMPTY_MASK: Transmit fifo almost empty flag mask + * @arg I2S_TFIFOFULL_MASK : Transmit fifo full flag mask + * @arg I2S_TFIFOAFULL_MASK : Transmit fifo almost full flag mask + * @arg I2S_RFIFOEMPTY_MASK : Receive fifo empty flag mask + * @arg I2S_RFIFOAEMPTY_MASK: Receive fifo almost empty flag mask + * @arg I2S_RFIFOFULL_MASK : Receive fifo full flag mask + * @arg I2S_RFIFOAFULL_MASK : Receive fifo almost full flag mask + * @param NewState: new state of the specified I2Sx FIFO interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_FIFOITConfig(I2S_TypeDef* I2Sx, uint32_t I2S_IT_Mask, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2S_FIFO_IT_MASK(I2S_IT_Mask)); + + if (NewState != DISABLE) + { + /* Enable the selected I2S FIFO interrupts */ + I2Sx->CID_CTRL |= I2S_IT_Mask; + } + else + { + /* Disable the selected I2S FIFO interrupts */ + I2Sx->CID_CTRL &= (uint32_t)~((uint32_t)I2S_IT_Mask); + } +} + +/** + * @brief Enables or disables the specified I2S channel 0/1 data + * underrun/overrun interrupts. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_IT_Mask: specifies the I2S interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg I2S_0_MASK: I2S channel 0 data underrun/overrun interrupts mask + * @arg I2S_1_MASK: I2S channel 1 data underrun/overrun interrupts mask + * @param NewState: new state of the specified I2Sx channel 0/1 + * data underrun/overrun interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void I2S_DataITConfig(I2S_TypeDef* I2Sx, uint32_t I2S_IT_Mask, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_I2S_DATA_IT_MASK(I2S_IT_Mask)); + + if (NewState != DISABLE) + { + /* Enable the selected I2S channel 0/1 data underrun/overrun interrupts */ + I2Sx->CID_CTRL |= I2S_IT_Mask; + } + else + { + /* Disable the selected I2S channel 0/1 data underrun/overrun interrupts */ + I2Sx->CID_CTRL &= (uint32_t)~((uint32_t)I2S_IT_Mask); + } +} + + +/** + * @brief Checks whether the specified I2S interrupt has occurred or not. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_IT: specifies the interrupt source to check. + * This parameter can be one of the following values: + * @arg I2S_IT_TDATAUNDERR: Transmitter data underrun event + * @arg I2S_IT_RDATAOVRERR: Receiver data overrun error + * @arg I2S_IT_TFIFOEMPTY : Transmit fifo empty flag + * @arg I2S_IT_TFIFOAEMPTY: Transmit fifo almost empty flag + * @arg I2S_IT_TFIFOFULL : Transmit fifo full flag + * @arg I2S_IT_TFIFOAFULL : Transmit fifo almost full flag + * @arg I2S_IT_RFIFOEMPTY : Receive fifo empty flag + * @arg I2S_IT_RFIFOAEMPTY: Receive fifo almost empty flag + * @arg I2S_IT_RFIFOFULL : Receive fifo full flag + * @arg I2S_IT_RFIFOAFULL : Receive fifo almost full flag + * @retval The new state of I2S_IT (SET or RESET). + */ +ITStatus I2S_GetITStatus(I2S_TypeDef* I2Sx, uint32_t I2S_IT) +{ + uint32_t tmpreg = 0; + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_GET_IT(I2S_IT)); + + /* Get the INTR_STAT register value */ + tmpreg = I2Sx->INTR_STAT; + + /* Get flag status */ + tmpreg &= I2S_IT; + + /* Check the status of the specified I2S flag */ + if (tmpreg != RESET) + { + /* I2S_IT is set */ + bitstatus = SET; + } + else + { + /* I2S_IT is reset */ + bitstatus = RESET; + } + + /* Return the I2S_IT status */ + return bitstatus; +} + + +/** + * @brief Clears the I2Sx's interrupt pending bits. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_IT: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg I2S_IT_TDATAUNDERR: Transmitter data underrun event + * @arg I2S_IT_RDATAOVRERR: Receiver data overrun error + * @arg I2S_IT_TFIFOEMPTY : Transmit fifo empty flag + * @arg I2S_IT_TFIFOAEMPTY: Transmit fifo almost empty flag + * @arg I2S_IT_TFIFOFULL : Transmit fifo full flag + * @arg I2S_IT_TFIFOAFULL : Transmit fifo almost full flag + * @arg I2S_IT_RFIFOEMPTY : Receive fifo empty flag + * @arg I2S_IT_RFIFOAEMPTY: Receive fifo almost empty flag + * @arg I2S_IT_RFIFOFULL : Receive fifo full flag + * @arg I2S_IT_RFIFOAFULL : Receive fifo almost full flag + * @retval The new state of I2S_IT (SET or RESET). + */ +void I2S_ClearITPendingBit(I2S_TypeDef* I2Sx, uint32_t I2S_IT) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_CLEAR_IT(I2S_IT)); + + /* Clear the selected flag */ + if ((I2S_IT & I2S_IT_RDATAOVRERR) == I2S_IT_RDATAOVRERR) + { + I2Sx->INTR_STAT &= (uint32_t)~((uint32_t)I2S_IT); + } + else + { + tmpreg = I2Sx->INTR_STAT; + tmpreg &= (uint32_t)~((uint32_t)I2S_IT); + tmpreg |= I2S_IT_RDATAOVRERR; + I2Sx->INTR_STAT = tmpreg; + } +} + + +/** + * @brief Returns the channel code of the transmitter that caused underrun event. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval The channel code of the transmitter that caused underrun event, + * it can be channel 0 or channel 1. + */ +uint8_t I2S_GetUnderrunCode(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Return the channel code of the transmitter that caused underrun event + * in INTR_STAT register */ + return (uint8_t)((uint32_t)I2Sx->INTR_STAT & I2S_INTR_STAT_UNDERRCODE); +} + + +/** + * @brief Returns the channel code of the receiver that caused overrun error. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @retval the channel code of the receiver that caused overrun error, + * it can be channel 0 or channel 1. + */ +uint8_t I2S_GetOverrunCode(I2S_TypeDef* I2Sx) +{ + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + + /* Return the channel code of the receiver that caused overrun error + * in INTR_STAT register */ + return (uint8_t)((uint32_t)I2Sx->INTR_STAT & I2S_INTR_STAT_OVRERRCODE); +} + + +/** + * @brief Returns the I2S polling status. + * @param I2Sx: where x can be 2 or 3 to select the I2S peripheral. + * @param I2S_Stat: specifies the I2S current FIFO or data status to check + * This parameter can be one of the following values: + * @arg I2S_STAT_TFIFOEMPTY : Transmit fifo empty flag + * @arg I2S_STAT_TFIFOAEMPTY: Transmit fifo almost flag + * @arg I2S_STAT_TXUNDERRUN : Transmitter data underrun + * @arg I2S_STAT_RFIFOFULL : Receive fifo full flag + * @arg I2S_STAT_RFIFOAFULL : Receive fifo almost full flag + * @arg I2S_STAT_RXOVERRUN : Receiver data overrun + * @retval The new state of I2S_STAT (SET or RESET). + */ +FlagStatus I2S_GetPollStatus(I2S_TypeDef* I2Sx, uint32_t I2S_Stat) +{ + uint32_t tmpreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_I2S_ALL_PERIPH(I2Sx)); + assert_param(IS_I2S_GET_STAT(I2S_Stat)); + + /* Get the POLL_STAT register value */ + tmpreg = I2Sx->POLL_STAT; + + /* Get flag status */ + tmpreg &= I2S_Stat; + + if (tmpreg != 0) + { + /* I2S_Stat is set */ + bitstatus = SET; + } + else + { + /* I2S_Stat is reset */ + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE**********************/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_iwdg.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_iwdg.c new file mode 100644 index 00000000000..471d3f03479 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_iwdg.c @@ -0,0 +1,167 @@ +/** + ****************************************************************************** + * @file ft32f4xx_iwdg.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Independent watchdog (IWDG) peripheral: + * + Prescaler and Counter configuration + * + IWDG activation + * + Flag management + * @version V1.0.0 + * @data 2025-03-05 + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_iwdg.h" + +/* ---------------------- IWDG registers bit mask ----------------------------*/ +/* KR register bit mask */ +#define KR_KEY_RELOAD ((uint16_t)0xAAAA) +#define KR_KEY_ENABLE ((uint16_t)0xCCCC) + + +/** + * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. + * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. + * This parameter can be one of the following values: + * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers + * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers + * @retval None + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); + IWDG->KR = IWDG_WriteAccess; +} + +/** + * @brief Sets IWDG Prescaler value. + * @param IWDG_Prescaler: specifies the IWDG Prescaler value. + * This parameter can be one of the following values: + * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 + * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 + * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 + * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 + * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 + * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 + * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 + * @retval None + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + /* Check the parameters */ + assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); + IWDG->PR = IWDG_Prescaler; +} + +/** + * @brief Sets IWDG Reload value. + * @param Reload: specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * @retval None + */ +void IWDG_SetReload(uint16_t Reload) +{ + /* Check the parameters */ + assert_param(IS_IWDG_RELOAD(Reload)); + IWDG->RLR = Reload; +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_ReloadCounter(void) +{ + IWDG->KR = KR_KEY_RELOAD; +} + + +/** + * @brief Sets the IWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * @retval None + */ +void IWDG_SetWindowValue(uint16_t WindowValue) +{ + /* Check the parameters */ + assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); + IWDG->WINR = WindowValue; +} + +/** + * @} + */ + +/** @defgroup IWDG_Group2 IWDG activation function + * @brief IWDG activation function + * +@verbatim + ============================================================================== + ##### IWDG activation function ##### + ============================================================================== + +@endverbatim + * @{ + */ + +/** + * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). + * @param None + * @retval None + */ +void IWDG_Enable(void) +{ + IWDG->KR = KR_KEY_ENABLE; +} + +/** + * @} + */ + +/** + * @brief Checks whether the specified IWDG flag is set or not. + * @param IWDG_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg IWDG_FLAG_PVU: Prescaler Value Update on going + * @arg IWDG_FLAG_RVU: Reload Value Update on going + * @arg IWDG_FLAG_WVU: Counter Window Value Update on going + * @retval The new state of IWDG_FLAG (SET or RESET). + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_IWDG_FLAG(IWDG_FLAG)); + if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_lptim.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_lptim.c new file mode 100644 index 00000000000..930bb1b2947 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_lptim.c @@ -0,0 +1,673 @@ +/** + ****************************************************************************** + * @file ft32f4xx_lptim.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (LPTIM): + * + Initialization and Configuration + * + Read CNT/ARR/CMP Register functions + * + Write ARR/CMP Register functions + * + PWM Mode Start/Stop + * + Onepulse Mode Start/Stop + * + Setonce Mode Start/Stop + * + Encoder Mode Start/Stop + * + Timeout Mode Start/Stop + * + Counter Mode Start/Stop + * + CNT reset management + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-31 + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_lptim.h" +#include "ft32f4xx_rcc.h" + +/* LPTIM registers Masks */ +#define CFGR_CLEAR_MASK ((uint32_t)0x20ebeedf) +//#define SPI_CTRLR0_CLEAR_MASK ((uint32_t)0x0c03033f) + + +/* Private function prototypes -----------------------------------------------*/ +void LPTIM_Start_Continuous(void); +void LPTIM_Start_Single(void); +void LPTIM_Disable(void); +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions. + * +@verbatim + ============================================================================== + ##### Initialization and de-initialization functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Initialize the LPTIM according to the specified parameters in the + LPTIM_InitTypeDef and initialize the associated handle. + (+) DeInitialize the LPTIM peripheral. + +@endverbatim + * @{ + */ + + +/** + * @brief Deinitializes the LPTIM peripheral registers to their default + * reset values. + */ +void LPTIM_DeInit(void) +{ + + /* Enable LPTIM reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LPTIM, ENABLE); + /* Release LPTIM from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_LPTIM, DISABLE); +} + +/** + * @brief Fills each LPTIM_InitStruct member with its default value. + * @param LPTIM_InitStruct: pointer to a LPTIM_InitTypeDef structure which will be initialized. + * @retval None + */ +void LPTIM_StructInit(LPTIM_InitTypeDef *LPTIM_InitStruct) +{ + /*--------------- Reset LPTIM init structure parameters values -----------------*/ + /* Initialize the LPTIM clock source member */ + LPTIM_InitStruct->Source = LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC; + /* Initialize the LPTIM clock prescaler member */ + LPTIM_InitStruct->Prescaler = LPTIM_PRESCALER_DIV1; + /* Initialize the LPTIM polarity of the active edge member */ + LPTIM_InitStruct->Polarity = LPTIM_CLOCKPOLARITY_RISING; + /* Initialize the LPTIM Clock_SampleTime member */ + LPTIM_InitStruct->Clock_SampleTime = LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION; + /* Initialize the LPTIM Trigger_Source member */ + LPTIM_InitStruct->Trigger_Source = LPTIM_TRIGSOURCE_0; + /* Initialize the LPTIM Trigegr_ActiveEdge member */ + LPTIM_InitStruct->Trigegr_ActiveEdge = LPTIM_SOFTWARE; + /* Initialize the LPTIM Trigg_SampleTime member */ + LPTIM_InitStruct->Trigg_SampleTime = LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION; + /* Initialize the LPTIM OutputPolarity member */ + LPTIM_InitStruct->OutputPolarity = LPTIM_OUTPUTPOLARITY_HIGH; + /* Initialize the LPTIM UpdateMode member */ + LPTIM_InitStruct->UpdateMode = LPTIM_UPDATE_IMMEDIATE; + /*Initialize the LPTIM CounterSource member*/ + LPTIM_InitStruct->CounterSource = LPTIM_COUNTERSOURCE_INTERNAL; + /*Initialize the LPTIM Input1Source member*/ + LPTIM_InitStruct->Input1Source = LPTIM_INPUT1SOURCE_GPIO; + /*Initialize the LPTIM Input2Source member*/ + LPTIM_InitStruct->Input2Source = LPTIM_INPUT2SOURCE_GPIO; + +} + +/** + * @brief Initializes the LPTIM peripheral according to the specified + * parameters in the LPTIM_InitStruct. + * @param LPTIM_InitStruct: pointer to a LPTIM_InitTypeDef structure that + * contains the configuration information for the specified LPTIM peripheral. + * @retval None + */ +void LPTIM_Init(LPTIM_InitTypeDef *LPTIM_InitStruct) +{ + uint32_t tmpreg = 0; + + /* Check the LPTIM parameters */ + assert_param(IS_LPTIM_CLOCK_SOURCE(LPTIM_InitStruct->Source)); + assert_param(IS_LPTIM_CLOCK_PRESCALER(LPTIM_InitStruct->Prescaler)); + assert_param(IS_LPTIM_CLOCK_POLARITY(LPTIM_InitStruct->Polarity)); + assert_param(IS_LPTIM_CLOCK_SAMPLE_TIME(LPTIM_InitStruct->Clock_SampleTime)); + assert_param(IS_LPTIM_TRG_SOURCE(LPTIM_InitStruct->Trigger_Source)); + assert_param(IS_LPTIM_EXT_TRG_POLARITY(LPTIM_InitStruct->Trigegr_ActiveEdge)); + assert_param(IS_LPTIM_TRIG_SAMPLE_TIME(LPTIM_InitStruct->Trigg_SampleTime)); + assert_param(IS_LPTIM_OUTPUT_POLARITY(LPTIM_InitStruct->OutputPolarity)); + assert_param(IS_LPTIM_UPDATE_MODE(LPTIM_InitStruct->UpdateMode)); + assert_param(IS_LPTIM_COUNTER_SOURCE(LPTIM_InitStruct->CounterSource)); + assert_param(IS_LPTIM_INPUT1_SOURCE(LPTIM_InitStruct->Input1Source)); + assert_param(IS_LPTIM_INPUT2_SOURCE(LPTIM_InitStruct->Input2Source)); + + /*---------------------------- LPTIM CFGR Configuration ------------------------*/ + /* Get the LPTIM CFGR value */ + tmpreg = LPTIM->CFGR; + /* Clear TRIGSEL[3:0],COUNTMODE.PRELOAD,WAVPOL,TRIGEN[1:0],PRESC[2:0],TRGFLT,CKFLT,CKPOL,CKSEL bits */ + tmpreg &= ~CFGR_CLEAR_MASK; + /* Configure LPTIM CFGR register*/ + tmpreg |= (uint32_t)((uint32_t)LPTIM_InitStruct->Source | LPTIM_InitStruct->Prescaler | + LPTIM_InitStruct->Polarity | LPTIM_InitStruct->Clock_SampleTime | + LPTIM_InitStruct->Trigger_Source | LPTIM_InitStruct->Trigegr_ActiveEdge | + LPTIM_InitStruct->Trigg_SampleTime | LPTIM_InitStruct->OutputPolarity | + LPTIM_InitStruct->CounterSource); + /* Write to LPTIM CFGR */ + LPTIM->CFGR = tmpreg; + + /*-------------------------LPTIM OR Configuration -----------------------*/ + /* Clear OR register */ + tmpreg = 0; + /* Configure LPTIM IN1[2:0], IN2[2:0] */ + tmpreg |= (uint32_t)((uint32_t)(LPTIM_InitStruct->Input1Source) | LPTIM_InitStruct->Input2Source); + /* Write to LPTIM OR */ + LPTIM->OR = tmpreg; + +} + +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions + * @brief Start-Stop operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Start Stop operation functions ##### + ============================================================================== + [..] This section provides functions allowing to: + (+) Start the PWM mode. + (+) Stop the PWM mode. + (+) Start the One pulse mode. + (+) Stop the One pulse mode. + (+) Start the Set once mode. + (+) Stop the Set once mode. + (+) Start the Encoder mode. + (+) Stop the Encoder mode. + (+) Start the Timeout mode. + (+) Stop the Timeout mode. + (+) Start the Counter mode. + (+) Stop the Counter mode. + + +@endverbatim + * @{ + */ + +/** + * @brief Start the LPTIM PWM generation. + * @param Period Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + */ + +void LPTIM_PWM_Start(uint32_t Period, uint32_t Pulse) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Reset WAVE bit to set PWM mode */ + LPTIM->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + LPTIM->CR |= LPTIM_CR_ENABLE; + + /* Write the ARR register value*/ + LPTIM_Write_ARRRegister(Period); + + /* Write the CMP register value*/ + LPTIM_Write_CMPRegister(Pulse); + + /* Start timer in continuous mode */ + LPTIM_Start_Continuous(); + +} + +/** + * @brief Stop the LPTIM PWM generation. + */ +void LPTIM_PWM_Stop(void) +{ + /* Disable the Peripheral */ + LPTIM_Disable(); +} +/** + * @brief Start the LPTIM One pulse generation. + * @param Period Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + */ +void LPTIM_OnePulse_Start(uint32_t Period, uint32_t Pulse) +{ + + /* Check the parameters */ + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Reset WAVE bit to set one pulse mode */ + LPTIM->CFGR &= ~LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + LPTIM->CR |= LPTIM_CR_ENABLE; + + /* Write the ARR register value*/ + LPTIM_Write_ARRRegister(Period); + + /* Write the CMP register value*/ + LPTIM_Write_CMPRegister(Pulse); + + /* Start timer in single mode */ + LPTIM_Start_Single(); + +} + +/** + * @brief Stop the LPTIM OnePulse generation. + */ +void LPTIM_OnePulse_Stop(void) +{ + /* Disable the Peripheral */ + LPTIM_Disable(); +} + +/** + * @brief Start the LPTIM in Set once mode. + * @param Period Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + * @param Pulse Specifies the compare value. + * This parameter must be a value between 0x0000 and 0xFFFF. + */ +void LPTIM_SetOnce_Start(uint32_t Period, uint32_t Pulse) +{ + + /* Check the parameters */ + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Pulse)); + + /* Set WAVE bit to enable the set once mode */ + LPTIM->CFGR |= LPTIM_CFGR_WAVE; + + /* Enable the Peripheral */ + LPTIM->CR |= LPTIM_CR_ENABLE; + + /* Write the ARR register value*/ + LPTIM_Write_ARRRegister(Period); + + /* Write the CMP register value*/ + LPTIM_Write_CMPRegister(Pulse); + + /* Start timer in single mode */ + LPTIM_Start_Single(); + +} + +/** + * @brief Stop the LPTIM SetOnce generation. + */ +void LPTIM_SetOnce_Stop(void) +{ + /* Disable the Peripheral */ + LPTIM_Disable(); +} + + +/** + * @brief Start the Encoder interface. + * @param Period Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + */ +void LPTIM_Encoder_Start(uint32_t Period) +{ + + /* Check the parameters */ + assert_param(IS_LPTIM_PERIOD(Period)); + + /* Set ENC bit to enable the encoder interface */ + LPTIM->CFGR |= LPTIM_CFGR_ENC; + + LPTIM_Counter_Start(Period); + ///* Enable the Peripheral */ + //LPTIM->CR |= LPTIM_CR_ENABLE; + + ///* Write the ARR register value*/ + //LPTIM_Write_ARRRegister(Period); + + ///* Start timer in continuous mode */ + //LPTIM_Start_Continuous(); + +} + + +/** + * @brief Stop the LPTIM Encoder generation. + */ +void LPTIM_Encoder_Stop(void) +{ + /* Disable the Peripheral */ + LPTIM_Disable(); + /* Reset ENC bit to disable the encoder function */ + LPTIM->CFGR &= ~LPTIM_CFGR_ENC; +} + + +void LPTIM_TimeOut_Start(uint32_t Period, uint32_t Timeout) +{ + + /* Check the parameters */ + assert_param(IS_LPTIM_PERIOD(Period)); + assert_param(IS_LPTIM_PULSE(Timeout)); + + /* Set TIMOUT bit to enable the timeout function */ + LPTIM->CFGR |= LPTIM_CFGR_TIMOUT; + + /* Enable the Peripheral */ + LPTIM->CR |= LPTIM_CR_ENABLE; + + /* Write the ARR register value*/ + LPTIM_Write_ARRRegister(Period); + + /* Write the CMP register value*/ + LPTIM_Write_CMPRegister(Timeout); + + /* Start timer in continuous mode */ + LPTIM_Start_Continuous(); + +} + +/** + * @brief Stop the LPTIM TimeOut generation. + */ +void LPTIM_TimeOut_Stop(void) +{ + /* Disable the Peripheral */ + LPTIM_Disable(); + + /* Reset TIMOUT bit to disable the timeout function */ + LPTIM->CFGR &= ~LPTIM_CFGR_TIMOUT; +} + +/** + * @brief Start the Counter mode. + * @param Period Specifies the Autoreload value. + * This parameter must be a value between 0x0000 and 0xFFFF. + */ +void LPTIM_Counter_Start(uint32_t Period) +{ + /* Check the parameters */ + assert_param(IS_LPTIM_PERIOD(Period)); + + /* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */ + if ((LPTIM->CFGR & (LPTIM_CFGR_CKSEL | LPTIM_CFGR_COUNTMODE)) == LPTIM_CFGR_COUNTMODE) + { + /* Check if clock is prescaled */ + /* Set clock prescaler to 0 */ + LPTIM->CFGR &= ~LPTIM_CFGR_PRESC; + } + + /* Enable the Peripheral */ + LPTIM->CR |= LPTIM_CR_ENABLE; + + /* Write the ARR register value*/ + LPTIM_Write_ARRRegister(Period); + + /* Start timer in continuous mode */ + LPTIM_Start_Continuous(); + +} + +/** + * @brief Stop the LPTIM Counter generation. + */ +void LPTIM_Counter_Stop(void) +{ + /* Disable the Peripheral */ + LPTIM_Disable(); + +} + +void LPTIM_Disable(void) +{ + uint32_t tmpclksource = 0; + uint32_t tmpIER; + uint32_t tmpCFGR; + uint32_t tmpCMP; + uint32_t tmpARR; + uint32_t tmpOR; + + //__disable_irq(); + + /*********** Save LPTIM Config ***********/ + /* Save LPTIM source clock */ + tmpclksource = (RCC->CCIPR & RCC_CCIPR_LPTIMSEL); + + /* Save LPTIM configuration registers */ + tmpIER = LPTIM->IER; + tmpCFGR = LPTIM->CFGR; + tmpCMP = LPTIM->CMP; + tmpARR = LPTIM->ARR; + tmpOR = LPTIM->OR; + + /*********** Reset LPTIM ***********/ + RCC_APB2PeriphResetCmd(RCC_APB2PeriphRst_LPTIM, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2PeriphRst_LPTIM, DISABLE); + + /*********** Restore LPTIM Config ***********/ + /* Force LPTIM source kernel clock from APB */ + RCC_LPTIMCLKConfig(RCC_LPTIMCLK_PCLK); + + /* Restore CMP register (LPTIM should be enabled first) */ + LPTIM->CR |= LPTIM_CR_ENABLE; + LPTIM_Write_CMPRegister(tmpCMP); + + /* Restore ARR register (LPTIM should be enabled first) */ + LPTIM->CR |= LPTIM_CR_ENABLE; + LPTIM_Write_ARRRegister(tmpARR); + + /* Restore LPTIM source kernel clock */ + RCC_LPTIMCLKConfig(tmpclksource); + + /* Restore configuration registers (LPTIM should be disabled first) */ + LPTIM->CR &= ~(LPTIM_CR_ENABLE); + LPTIM->IER = tmpIER; + LPTIM->CFGR = tmpCFGR; + LPTIM->OR = tmpOR; + + //__enable_irq(); + +} +/** + * @} + */ + + +/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions + * @brief Read operation functions. + * +@verbatim + ============================================================================== + ##### LPTIM Read/Write operation functions ##### + ============================================================================== +[..] This section provides LPTIM Reading functions. + (+) Read the counter value. + (+) Read the period (Auto-reload) value. + (+) Read the pulse (Compare)value. + (+) Write the period (Auto-reload) value. + (+) Write the pulse (Compare)value. +@endverbatim + * @{ + */ + +/** + * @brief Return the current counter value. + * @retval Counter value. + */ + +uint32_t LPTIM_ReadCounter(void) +{ + return (LPTIM->CNT); +} + +/** + * @brief Return the current Autoreload (Period) value. + * @retval Autoreload value. + */ + +uint32_t LPTIM_ReadAutoReload(void) +{ + return (LPTIM->ARR); +} + +/** + * @brief Return the current Compare (Pulse) value. + * @retval Compare value. + */ + +uint32_t LPTIM_ReadCompare(void) +{ + return (LPTIM->CMP); +} + +/** + * @brief LPTimer Write ARR register + * @param Period the ARR value + */ + +void LPTIM_Write_ARRRegister(uint32_t Period) +{ + /* Clear ARROK flag */ + LPTIM->ICR = LPTIM_ICR_ARROKCF ; + + /* Load the period value in the autoreload register*/ + LPTIM->ARR = Period ; + + /* Wait for the completion of the write operation to the LPTIM_ARR register */ + while (LPTIM_GetStatus(LPTIM_ISR_ARROK) != LPTIM_ISR_ARROK); +} + +/** + * @brief LPTimer Write CMP register + * @param Pulse the CMP value + */ + +void LPTIM_Write_CMPRegister(uint32_t Pulse) +{ + /* Clear CMPOK flag */ + LPTIM->ICR = LPTIM_ICR_CMPOKCF ; + + /* Load the pulse value in the compare register*/ + LPTIM->CMP = Pulse ; + + /* Wait for the completion of the write operation to the LPTIM_CMP register */ + while (LPTIM_GetStatus(LPTIM_ISR_CMPOK) != LPTIM_ISR_CMPOK); +} + +/** + * @brief Enables or disables LPTIM PRELOAD bit + * @param NewState: new state of the PRELOAD bit. + * This parameter can be: ENABLE or DISABLE. + */ +void LPTIM_Preload_Config(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set PRELOAD bit*/ + LPTIM->CFGR |= LPTIM_CFGR_PRELOAD ; + } + else + { + /* Clear PRELOAD bit*/ + LPTIM->CFGR &= ~LPTIM_CFGR_PRELOAD ; + } +} +/** + * @} + */ + + +/** + * @brief LPTimer Start in Continuous mode + */ +void LPTIM_Start_Continuous(void) +{ + /* Set CNTSTRT bits*/ + LPTIM->CR |= LPTIM_CR_CNTSTRT ; +} + +/** + * @brief LPTimer Start in single mode + */ +void LPTIM_Start_Single(void) +{ + /* Set SNGSTRT bits*/ + LPTIM->CR |= LPTIM_CR_SNGSTRT ; +} + +/** + * @brief Enables or disables LPTIM reset cnt after read cnt + * @param NewState: new state of the RSTARE bits. + * This parameter can be: ENABLE or DISABLE. + */ +void LPTIM_RSTARE(FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set RSTARE bits*/ + LPTIM->CR |= LPTIM_CR_RSTARE ; + } + else + { + /* Clear RSTARE bits*/ + LPTIM->CR &= ~LPTIM_CR_RSTARE ; + } +} + +void LPTIM_COUNTRST(void) +{ + + /* Set COUNTRST bits*/ + LPTIM->CR |= LPTIM_CR_COUNTRST ; + +} +/** + * @brief LPTimer interrupt enable + * @param LPTIM_IT The lptim interrupt enable + * @param NewState: new state of the LPTIM interrupts. + * This parameter can be: ENABLE or DISABLE. + */ +void LPTIM_ITConfig(uint32_t LPTIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the IT enable bits*/ + LPTIM->IER |= LPTIM_IT ; + } + else + { + /* Disable the IT enable bits*/ + LPTIM->IER &= ~LPTIM_IT ; + } +} + +/** + * @brief LPTimer Wait for flag set + * @param LPTIM_SR_FLAG The lptim flag + */ +uint32_t LPTIM_GetStatus(uint32_t LPTIM_ISR_FLAG) +{ + /* Get the QSPI status */ + return (uint32_t)(LPTIM->ISR & LPTIM_ISR_FLAG); + +} + +/** + * @brief LPTimer clear interrupt flag + * @param flag The lptim interrupt clear bit + */ +void LPTIM_ClearFlag(uint32_t flag) +{ + /* Write ICR register to clear ISR bits*/ + LPTIM->ICR = flag ; +} +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_misc.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_misc.c new file mode 100644 index 00000000000..7c6385834c6 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_misc.c @@ -0,0 +1,256 @@ +/** + ****************************************************************************** + * @file ft32f4xx_misc.c + * @author FMD AE + * @brief This file provides all the miscellaneous firmware functions (add-on + * to CMSIS functions). + * @version V1.0.0 + * @data 2025-07-01 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_misc.h" + +/** @defgroup MISC + * @brief MISC driver modules + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** @defgroup MISC_Private_Functions + * @{ + */ + +/** + * @brief Configures the priority grouping: pre-emption priority and subpriority. + * @param NVIC_PriorityGroup: specifies the priority grouping bits length. + * This parameter can be one of the following values: + * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority + * 4 bits for subpriority + * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority + * 3 bits for subpriority + * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority + * 2 bits for subpriority + * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority + * 1 bits for subpriority + * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority + * 0 bits for subpriority + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ + SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; +} + +/** + * @brief Initializes the NVIC peripheral according to the specified + * parameters in the NVIC_InitStruct. + * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() + * function should be called before. + * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains + * the configuration information for the specified NVIC peripheral. + * @retval None + */ +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) +{ + uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); + assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); + + if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + /* Compute the Corresponding IRQ Priority --------------------------------*/ + tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700)) >> 0x08; + tmppre = (0x4 - tmppriority); + tmpsub = tmpsub >> tmppriority; + + tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; + tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub); + + tmppriority = tmppriority << 0x04; + + NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; + + /* Enable the Selected IRQ Channels --------------------------------------*/ + NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } + else + { + /* Disable the Selected IRQ Channels -------------------------------------*/ + NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = + (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); + } +} + +/** + * @brief Sets the vector table location and Offset. + * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. + * This parameter can be one of the following values: + * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM. + * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH. + * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200. + * @retval None + */ +void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) +{ + /* Check the parameters */ + assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); + assert_param(IS_NVIC_OFFSET(Offset)); + + SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); +} + +/** + * @brief Selects the condition for the system to enter low power mode. + * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. + * This parameter can be one of the following values: + * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. + * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. + * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. + * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_NVIC_LP(LowPowerMode)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + SCB->SCR |= LowPowerMode; + } + else + { + SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); + } +} + + +/* Systick initial ---------------------------------------------------------- */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup Private_Variables + * @{ + */ +//__IO uint32_t uwTick; +//uint32_t uwTickPrio = (1UL << 4U); /* Invalid PRIO */ +//TickFreqTypeDef uwTickFreq = TICK_FREQ_DEFAULT; /* 1KHz */ +///** +// * @} +// */ + +//uint32_t SystemCoreClocktik = 210000000; /*SYSTEM clock frequece */ + +//#define TICK_INT_PRIORITY (0x0FU) /*!< tick interrupt priority */ + + +///** +// * @brief Initializes the System Timer and its its interrupt,and statrs the System Tick Timer. +// * Counter is in free running mode to generate periodic interrupts. +// * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. +// * @retval status: -0 Function succeeded. +// * -1 Function failed. +// */ +//uint32_t SYSTICK_Config(uint32_t TicksNumb) +//{ +// return SysTick_Config(TicksNumb); +//} + +///** +// * @brief This function configures the source of the time base. +// * The time source is configured to have 1ms time base with a dedicated +// * Tick interrupt priority. +// * @note In the default implementation, SysTick timer is the source of time base. +// * It is used to generate interrupts at regular time intervals. +// * The SysTick interrupt must have higher priority (numerically lower) +// * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. +// * The function is declared as void __attribute__((weak)) to be overwritten in case of other +// * implementation in user file. +// * @param TickPriority Tick interrupt priority. +// * @retval staus: +// */ +//void InitTick(uint32_t TickPriority,uint32_t SubPriority) +//{ +// uint32_t prioritygroup = 0x00U; + +// prioritygroup = NVIC_GetPriorityGrouping(); + +// /* Configure the SysTick to have interrupt in 1ms time basis*/ +// if (SYSTICK_Config(SystemCoreClocktik / (1000U / uwTickFreq)) > 0U) +// { +// return; +// } + +// /* Configure the SysTick IRQ priority */ +// if (TickPriority < (1UL << 4U)) +// { +// NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(prioritygroup, TickPriority, SubPriority)); +// uwTickPrio = TickPriority; +// } +// else +// { +// return; +// } + +// return; +//} + +///** +// * @brief This function is called to increment a global variable "uwTick" +// * used as application time base. +// * @note In the default implementation, this variable is incremented each 1ms +// * in SysTick ISR. +// * @note This function is declared as void __attribute__((weak)) to be overwritten in case of other +// * implementations in user file. +// * @retval None +// */ +//void IncTick(void) +//{ +// uwTick += uwTickFreq; +//} + +///** +// * @brief Provides a tick value in millisecond. +// * @note This function is declared as void __attribute__((weak)) to be overwritten in case of other +// * implementations in user file. +// * @retval tick value +// */ +//uint32_t GetTick(void) +//{ +// return uwTick; +//} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_opamp.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_opamp.c new file mode 100644 index 00000000000..fb88a274510 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_opamp.c @@ -0,0 +1,483 @@ +/** + ****************************************************************************** + * @file ft32f1xx_opa.c + * @author FMD xzhang + * @brief This file provides firmware functions to manage the following + * functionalities of the comparators (OPA1 OPA2 OPA3) peripheral + * applicable + * @version V1.0.0 + * @data 2025-03-31 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_opamp.h" +#include "ft32f4xx_rcc.h" + + +/** + * @brief Initializes the OPA peripheral according to the specified parameters + * in OPA_InitStruct + * @note If the selected opamp is locked, initialization can't be performed. + * To unlock the configuration, perform a system reset. + * @note To correctly run this function, the OPA_Cali() function must be called before. + * @param OPAMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg OPAMP_1: OPAMP1 selected + * @arg OPAMP_2: OPAMP2 selected + * @arg OPAMP_3: OPAMP3 selected + * @param OPA_InitStruct: pointer to an OPA_InitTypeDef structure that contains + * the configuration information for the specified OPA peripheral. + * @retval None + */ +void OPA_Init(OPA_InitTypeDef* OPA_InitStruct, uint32_t OPAMP_Selection) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + /* Check the parameters */ + assert_param(IS_OPAX_PERIPH(OPAMP_Selection)); + assert_param(IS_OPA_VIP_SEL(OPA_InitStruct -> OPA_VPSEL)); + assert_param(IS_OPA_VIM_SEL(OPA_InitStruct -> OPA_VMSEL)); + assert_param(IS_OPA_VIPS_SEL(OPA_InitStruct -> OPA_VPSSEL)); + assert_param(IS_OPA_VIMS_SEL(OPA_InitStruct -> OPA_VMSSEL)); + assert_param(IS_OPAX_TIM8_EN(OPA_InitStruct -> T8_CM)); + assert_param(IS_OPAX_TIM1_EN(OPA_InitStruct -> T1_CM)); + assert_param(IS_OPAX_OPAHSM(OPA_InitStruct -> OPAHSM)); + assert_param(IS_OPAX_OPINTOEN(OPA_InitStruct -> OPINTOEN)); + assert_param(IS_OPAX_O2PADSEL(OPA_InitStruct -> O2PADSEL)); + assert_param(IS_OPA_PGAGAIN(OPA_InitStruct -> OPA_PGAGAIN)); + + /*!< Configure : OPA_VPSEL OPA_VMSEL OPAHSM OPINTOEN O2PADSEL OPA_PGAGAIN*/ + tmpreg1 = (uint32_t)(OPA_InitStruct -> OPA_VPSEL | OPA_InitStruct -> OPA_VMSEL | OPA_InitStruct -> OPAHSM | OPA_InitStruct -> OPINTOEN | OPA_InitStruct -> O2PADSEL | OPA_InitStruct -> OPA_PGAGAIN); + + /*!< Configure : OPA_VPSSEL OPA_VMSSEL T8_CM T1_CM*/ + tmpreg2 = (uint32_t)(OPA_InitStruct -> OPA_VPSSEL | OPA_InitStruct -> OPA_VMSSEL | OPA_InitStruct ->T8_CM | OPA_InitStruct -> T1_CM); + + if (OPAMP_Selection == OPAMP_1) //config opamp1 + { + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC ->OPAMP1_CSR = tmpreg1; + COMP_OPAM_DAC ->OPAMP1_TCMR = tmpreg2; + } + else if (OPAMP_Selection == OPAMP_2) //config opamp2 + { + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC ->OPAMP2_CSR = tmpreg1; + COMP_OPAM_DAC ->OPAMP2_TCMR = tmpreg2; + } + else if (OPAMP_Selection == OPAMP_3) //config opamp3 + { + /*!< Write to COMP_CSR register */ + COMP_OPAM_DAC ->OPAMP3_CSR = tmpreg1; + COMP_OPAM_DAC ->OPAMP3_TCMR = tmpreg2; + } +} + + +/** + * @brief Deinitializes OPA peripheral registers to their default reset values. + * @note Deinitialization can't be performed if the OPA configuration is locked. + * To unlock the configuration, perform a system reset. + * @param OPAx: the selected comparator. + * This parameter can be one of the following values: + * @arg OPAMP_1: OPAMP1 selected + * @arg OPAMP_2: OPAMP2 selected + * @arg OPAMP_3: OPAMP3 selected + * @retval None + */ +void OPA_DeInit(uint32_t OPAMP_Selection) +{ + /* Check the parameters */ + assert_param(IS_OPAX_PERIPH(OPAMP_Selection)); + + if (OPAMP_Selection == OPAMP_1) + { + /*!< Set OPA_CSR register to reset value */ + COMP_OPAM_DAC ->OPAMP1_CSR = ((uint32_t)0x00000000); + COMP_OPAM_DAC ->OPAMP1_TCMR = ((uint32_t)0x00000000); + } + else if (OPAMP_Selection == OPAMP_2) + { + COMP_OPAM_DAC ->OPAMP2_CSR = ((uint32_t)0x00000000); + COMP_OPAM_DAC ->OPAMP2_TCMR = ((uint32_t)0x00000000); + } + else if (OPAMP_Selection == OPAMP_3) + { + COMP_OPAM_DAC ->OPAMP3_CSR = ((uint32_t)0x00000000); + COMP_OPAM_DAC ->OPAMP3_TCMR = ((uint32_t)0x00000000); + } + +} + + +/** + * @brief Enable or disable the OPA peripheral. + * @note If the selected opamp is locked, enable/disable can't be performed. + * To unlock the configuration, perform a system reset. + * @param OPAMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg OPAMP_1: OPAMP1 selected + * @arg OPAMP_2: OPAMP2 selected + * @arg OPAMP_3: OPAMP3 selected + * @param NewState: new state of the OPA peripheral. + * This parameter can be: ENABLE or DISABLE. + * @note When disabled, the opamp doesn't perform comparison and the + * output level is low. + * @retval None + */ +void OPA_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_OPAX_PERIPH(OPAMP_Selection)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + if (OPAMP_Selection == OPAMP_1) + /* Enable the selected OPA peripheral */ + COMP_OPAM_DAC ->OPAMP1_CSR |= OPAMP1_CSR_OPAEN; + else if (OPAMP_Selection == OPAMP_2) + /* Enable the selected OPA peripheral */ + COMP_OPAM_DAC ->OPAMP2_CSR |= OPAMP2_CSR_OPAEN; + else if (OPAMP_Selection == OPAMP_3) + /* Enable the selected OPA peripheral */ + COMP_OPAM_DAC ->OPAMP3_CSR |= OPAMP3_CSR_OPAEN; + } + else + { + if (OPAMP_Selection == OPAMP_1) + /* Disable the selected OPA peripheral */ + COMP_OPAM_DAC ->OPAMP1_CSR &= ~OPAMP1_CSR_OPAEN; + else if (OPAMP_Selection == OPAMP_2) + /* Disable the selected OPA peripheral */ + COMP_OPAM_DAC ->OPAMP2_CSR &= ~OPAMP2_CSR_OPAEN; + else if (OPAMP_Selection == OPAMP_3) + /* Disable the selected OPA peripheral */ + COMP_OPAM_DAC ->OPAMP3_CSR &= ~OPAMP3_CSR_OPAEN; + } +} + + + +/** + * @brief Calibration OPAMPx 's NMOS or PMOS. + * @note If you want to Calibration OPAMP ,recommend to use OPA_DeInit() firstly. + * @note Every TRIMOFFSETN/P change need delay 200 us + * @note Trim NMOS switch to PMOS need delay 500 us at least ,in this Function is 600us + * @param OPAMP_Selection: the selected comparator. + * This parameter can be one of the following values: + * @arg OPAMP_1: OPAMP1 selected + * @arg OPAMP_2: OPAMP2 selected + * @arg OPAMP_3: OPAMP3 selected + * @retval NONE + */ +volatile uint32_t flag; +volatile uint32_t flag_n; +volatile uint32_t flag_p; +volatile uint32_t nmos_cnt = 0; +volatile uint32_t pmos_cnt = 0; + +void OPAMP_Calibration(uint32_t OPAMP_Selection) +{ + uint32_t next_nmos_cnt; + uint32_t next_pmos_cnt; + uint32_t apbclock; + /*This is TIM's ARR value is calculate automaticly according to sysclk by users set */ + uint32_t ARR_value; + + RCC_ClocksTypeDef RCC_ClocksStatus; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + + if ((RCC->CFGR & 0x400) == 0x400) //if PPRE1[10] bit is 1 + ARR_value = (apbclock >> 2) / 625; //==(200*time freq)/1000000, tim freq=2 * apbclock; + else + ARR_value = (apbclock >> 3) / 625; //==(200*apbclock)/1000000; + + + /*Open TIMER6 clk */ + RCC->APB1ENR |= RCC_APB1ENR_TIM6EN; + /*set 50us as calibration delay by TIMER6 */ + NVIC_EnableIRQ(TIM6_DAC_IRQn); + TIM6 -> DIER |= TIM_DIER_UIE ; + TIM6 -> ARR = ARR_value ; //delay: 200us ;0xc80 =200000ns/T(freq clk) Now apb1clk is 16MHZ + TIM6 -> CR2 |= TIM_CR2_MMS_1 ; + TIM6 -> CR1 |= TIM_CR1_CEN ; + /* ==========================select OPAMP1==========================*/ + if (OPAMP_Selection == OPAMP_1) + { + /*-------------------calibration NMOS------------------*/ + /*make sure enable opamp1*/ + COMP_OPAM_DAC -> OPAMP1_CSR |= OPAMP1_CSR_OPAEN ; + /*enable cal trim*/ + COMP_OPAM_DAC -> OPAMP1_CSR |= OPAMP1_CSR_USERTRIM ; + /*cal sel NMOS*/ + COMP_OPAM_DAC -> OPAMP1_CSR |= OPAMP1_CSR_CALSEL_0 | OPAMP1_CSR_CALSEL_1; + /*vpsel =101*/ + COMP_OPAM_DAC -> OPAMP1_CSR |= OPAMP1_CSR_VP_SEL_2 | OPAMP1_CSR_VP_SEL_0; + + /*if nmos_cnt = 31,jump out cal NMOS*/ + while (((COMP_OPAM_DAC -> OPAMP1_CSR) & OPAMP1_CSR_TRIMOFFSETN_Msk) != OPAMP1_CSR_TRIMOFFSETN_Msk) + { + /*wait calout value become 0 */ + while ((COMP_OPAM_DAC -> OPAMP1_CSR & OPAMP1_CSR_CALOUT) == 0x40000000) + { + if (nmos_cnt >= 0x1f) + { + /*NMOS max value is 31 */ + nmos_cnt = 0x1f; + break; + } + else + { + /*wait 50us flag*/ + while (flag_n == 1) + { + next_nmos_cnt = (nmos_cnt << 24) | 0xe0ffffff; + /*updata TRIMOFFSETN value in OPAMP1_CSR and keep other bit*/ + COMP_OPAM_DAC -> OPAMP1_CSR = next_nmos_cnt & (0x1f000000 | (COMP_OPAM_DAC -> OPAMP1_CSR)); + nmos_cnt ++; + flag_n = 0; + } + } + } + break; + } + /*wait 600us*/ + for (int num = 0; num < 3; num++) + { + flag = 1; + while (flag == 1); //wait 50us + } + /*-----------------calibration PMOS-----------------*/ + /*cal sel PMOS*/ + COMP_OPAM_DAC -> OPAMP1_CSR &= ~OPAMP1_CSR_CALSEL_1 ; + /*if pmos_cnt = 31,jump out cal PMOS*/ + while (((COMP_OPAM_DAC -> OPAMP1_CSR) & OPAMP1_CSR_TRIMOFFSETP_Msk) != OPAMP1_CSR_TRIMOFFSETP_Msk) + { + while ((COMP_OPAM_DAC -> OPAMP1_CSR & OPAMP1_CSR_CALOUT) == 0x40000000) + { + if (pmos_cnt >= 0x20) + { + pmos_cnt = 0x1f; + break; + } + else + { + /*wait 50us flag*/ + while (flag_p == 1) + { + next_pmos_cnt = (pmos_cnt << 19) | 0xff07ffff; + /*updata TRIMOFFSETN value in OPAMP1_CSR and keep other bit*/ + COMP_OPAM_DAC -> OPAMP1_CSR = next_pmos_cnt & (0x00f80000 | (COMP_OPAM_DAC -> OPAMP1_CSR)); + pmos_cnt ++; + flag_p = 0; + } + } + } + break; + } + flag = 1; + while (flag == 1); //50us + COMP_OPAM_DAC -> OPAMP1_CSR &= ~OPAMP1_CSR_CALSEL_0 + & ~OPAMP1_CSR_USERTRIM + & ~OPAMP1_CSR_VP_SEL_2 //vp_sel:000 + & ~OPAMP1_CSR_VP_SEL_0; + }//end opamp1 + + + /* =============================select OPAMP2==========================*/ + else if (OPAMP_Selection == OPAMP_2) + { + /*-------------------calibration NMOS------------------*/ + /*make sure enable OPAMP2*/ + COMP_OPAM_DAC -> OPAMP2_CSR |= OPAMP2_CSR_OPAEN ; + /*enable cal trim*/ + COMP_OPAM_DAC -> OPAMP2_CSR |= OPAMP2_CSR_USERTRIM ; + /*cal sel NMOS*/ + COMP_OPAM_DAC -> OPAMP2_CSR |= OPAMP2_CSR_CALSEL_0 | OPAMP2_CSR_CALSEL_1; + /*vpsel =101*/ + COMP_OPAM_DAC -> OPAMP2_CSR |= OPAMP2_CSR_VP_SEL_2 | OPAMP2_CSR_VP_SEL_0; + /*if nmos_cnt = 31,jump out cal NMOS*/ + while (((COMP_OPAM_DAC -> OPAMP2_CSR) & OPAMP2_CSR_TRIMOFFSETN_Msk) != OPAMP2_CSR_TRIMOFFSETN_Msk) + { + /*wait calout value become 0 */ + while ((COMP_OPAM_DAC -> OPAMP2_CSR & OPAMP2_CSR_CALOUT) == 0x40000000) + { + if (nmos_cnt >= 0x1f) + { + /*NMOS max value is 31 */ + nmos_cnt = 0x1f; + break; + } + else + { + /*wait 50us flag*/ + while (flag_n == 1) + { + next_nmos_cnt = (nmos_cnt << 24) | 0xe0ffffff; + /*updata TRIMOFFSETN value in OPAMP2_CSR and keep other bit*/ + COMP_OPAM_DAC -> OPAMP2_CSR = next_nmos_cnt & (0x1f000000 | (COMP_OPAM_DAC -> OPAMP2_CSR)); + nmos_cnt ++; + flag_n = 0; + } + } + } + break; + } + /*wait 600us*/ + for (int num = 0; num < 3; num++) + { + flag = 1; + while (flag == 1); + } + /*-----------------calibration PMOS-----------------*/ + /*cal sel PMOS*/ + COMP_OPAM_DAC -> OPAMP2_CSR &= ~OPAMP2_CSR_CALSEL_1 ; + /*if pmos_cnt = 31,jump out cal PMOS*/ + while (((COMP_OPAM_DAC -> OPAMP2_CSR) & OPAMP2_CSR_TRIMOFFSETP_Msk) != OPAMP2_CSR_TRIMOFFSETP_Msk) + { + while ((COMP_OPAM_DAC -> OPAMP2_CSR & OPAMP2_CSR_CALOUT) == 0x40000000) + { + if (pmos_cnt >= 0x20) + { + pmos_cnt = 0x1f; + break; + } + else + { + /*wait 50us flag*/ + while (flag_p == 1) + { + next_pmos_cnt = (pmos_cnt << 19) | 0xff07ffff; + /*updata TRIMOFFSETN value in OPAMP2_CSR and keep other bit*/ + COMP_OPAM_DAC -> OPAMP2_CSR = next_pmos_cnt & (0x00f80000 | (COMP_OPAM_DAC -> OPAMP2_CSR)); + pmos_cnt ++; + flag_p = 0; + } + } + } + break; + } + flag = 1; + while (flag == 1); //50us + COMP_OPAM_DAC -> OPAMP2_CSR &= ~OPAMP2_CSR_CALSEL_0 + & ~OPAMP2_CSR_USERTRIM + & ~OPAMP2_CSR_VP_SEL_2 //vp_sel:000 + & ~OPAMP2_CSR_VP_SEL_0; + }//end OPAMP2 + + /*================================= select OPAMP3===============================*/ + else if (OPAMP_Selection == OPAMP_3) + { + /*-------------------calibration NMOS------------------*/ + /*make sure enable OPAMP3*/ + COMP_OPAM_DAC -> OPAMP3_CSR |= OPAMP3_CSR_OPAEN ; + /*enable cal trim*/ + COMP_OPAM_DAC -> OPAMP3_CSR |= OPAMP3_CSR_USERTRIM ; + /*cal sel NMOS*/ + COMP_OPAM_DAC -> OPAMP3_CSR |= OPAMP3_CSR_CALSEL_0 | OPAMP3_CSR_CALSEL_1; + /*vpsel =101*/ + COMP_OPAM_DAC -> OPAMP3_CSR |= OPAMP3_CSR_VP_SEL_2 | OPAMP3_CSR_VP_SEL_0; + + /*if nmos_cnt = 31,jump out cal NMOS*/ + while (((COMP_OPAM_DAC -> OPAMP3_CSR) & OPAMP3_CSR_TRIMOFFSETN_Msk) != OPAMP3_CSR_TRIMOFFSETN_Msk) + { + /*wait calout value become 0 */ + while ((COMP_OPAM_DAC -> OPAMP3_CSR & OPAMP3_CSR_CALOUT) == 0x40000000) + { + if (nmos_cnt >= 0x1f) + { + /*NMOS max value is 31 */ + nmos_cnt = 0x1f; + break; + } + else + { + /*wait 50us flag*/ + while (flag_n == 1) + { + next_nmos_cnt = (nmos_cnt << 24) | 0xe0ffffff; + /*updata TRIMOFFSETN value in OPAMP3_CSR and keep other bit*/ + COMP_OPAM_DAC -> OPAMP3_CSR = next_nmos_cnt & (0x1f000000 | (COMP_OPAM_DAC -> OPAMP3_CSR)); + nmos_cnt ++; + flag_n = 0; + } + } + } + break; + } + /*wait 600us*/ + for (int num = 0; num < 3; num++) + { + flag = 1; + while (flag == 1); //wait 50us + } + /*-----------------calibration PMOS-----------------*/ + /*cal sel PMOS*/ + COMP_OPAM_DAC -> OPAMP3_CSR &= ~OPAMP3_CSR_CALSEL_1 ; + /*if pmos_cnt = 31,jump out cal PMOS*/ + while (((COMP_OPAM_DAC -> OPAMP3_CSR) & OPAMP3_CSR_TRIMOFFSETP_Msk) != OPAMP3_CSR_TRIMOFFSETP_Msk) + { + while ((COMP_OPAM_DAC -> OPAMP3_CSR & OPAMP3_CSR_CALOUT) == 0x40000000) + { + if (pmos_cnt >= 0x20) + { + pmos_cnt = 0x1f; + break; + } + else + { + /*wait 50us flag*/ + while (flag_p == 1) + { + next_pmos_cnt = (pmos_cnt << 19) | 0xff07ffff; + /*updata TRIMOFFSETN value in OPAMP3_CSR and keep other bit*/ + COMP_OPAM_DAC -> OPAMP3_CSR = next_pmos_cnt & (0x00f80000 | (COMP_OPAM_DAC -> OPAMP3_CSR)); + pmos_cnt ++; + flag_p = 0; + } + } + } + break; + } + flag = 1; + while (flag == 1); //50us + COMP_OPAM_DAC -> OPAMP3_CSR &= ~OPAMP3_CSR_CALSEL_0 + & ~OPAMP3_CSR_USERTRIM + & ~OPAMP3_CSR_VP_SEL_2 //vp_sel:000 + & ~OPAMP3_CSR_VP_SEL_0; + }//end OPAMP3 + +} + +void TIM6_DAC_Handler(void) +{ + flag = 0; + flag_n = 1; + flag_p = 1; + + TIM6 -> SR &= ~TIM_SR_UIF; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_ex_hs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_ex_hs.c new file mode 100644 index 00000000000..2eeba1af063 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_ex_hs.c @@ -0,0 +1,112 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pcd_ex_hs.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Extended features functions + * @version V1.0.0 + * @data 2025-04-01 + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "ft32f4xx_rcc.h" + + +/** @addtogroup FT32F4xx_DRIVER + * @{ + */ + +#ifdef PCD_MODULE_ENABLED +#if defined (USB_OTG_HS) +/** @defgroup PCD_HS PCD + * @brief PCD HS module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCDEx_HS_Exported_Functions PCDEx Exported Functions + * @{ + */ + +/** @defgroup PCDEx_HS_Exported_Functions_Group1 Peripheral Control functions + * @brief PCDEx control functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) Update FIFO configuration +@endverbatim + * @{ + */ +#if defined (USB_OTG_HS) +/** + * @brief Set Tx FIFO + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval none + */ +void PCDEx_HS_SetTxFiFo(uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t Tx_Offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + Tx_Offset = USB_HS->GRXFSIZ; + + if (fifo == 0U) + { + USB_HS->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; + } + else + { + Tx_Offset += (USB_HS->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) + { + Tx_Offset += (USB_HS->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + USB_HS->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; + } + +} + +/** + * @brief Set Rx FIFO + * @param size Size of Rx fifo + * @retval none + */ +void PCDEx_HS_SetRxFiFo(uint16_t size) +{ + USB_HS->GRXFSIZ = size; + +} +#endif /* defined (USB_OTG_HS) */ + +/** + * @} + */ + + +#endif /* defined (USB_OTG_HS) */ +#endif /* PCD_MODULE_ENABLED */ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_fs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_fs.c new file mode 100644 index 00000000000..1d29cf9ec36 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_fs.c @@ -0,0 +1,1413 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pcd_fs.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * @version V1.0.0 + * @data 2025-05-30 + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a PCD_FS_HandleTypeDef handle structure, for example: + PCD_FS_HandleTypeDef hpcd; + + (#)Fill parameters of Init structure in PCD handle + + (#)Call PCD_FS_Init() API to initialize the PCD peripheral (Core, Host core, ...) + + (#)Initialize the PCD low level resources through the PCD_FS_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using the following macros + (##) Initialize the related GPIO clocks + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) PCD_FS_Start(); + + @endverbatim + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "ft32f4xx_pcd_fs.h" +#include "ft32f4xx_rcc.h" +#include "usbd_core.h" + +/** @addtogroup FT32F4xx_DRIVER + * @{ + */ + +#ifdef PCD_FS_MODULE_ENABLED +#if defined (USB_OTG_FS) +/** @defgroup PCD_FS PCD + * @brief PCD FS module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PCD_FS_Private_Macros PCD Private Functions + * @{ + */ +#define PCD_MIN(a,b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a,b) (((a) > (b)) ? (a) : (b)) +/** + * @{ + */ + +/** @defgroup PCD_FS_Private_Functions PCD Private Functions + * @{ + */ + +static USB_FS_StatusTypeDef PCD_FS_WriteEmptyTxFifo(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum); +static void PCD_FS_EP_OutXferComplete_int(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum); +static void PCD_FS_EP_OutSetupPacket_int(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum); +/** + * @{ + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_FS_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_FS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_Init(PCD_FS_HandleTypeDef *hpcd) +{ + + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return USB_FS_ERROR; + } + + if (hpcd->State == PCD_FS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = USB_FS_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + PCD_FS_MspInit(hpcd); + } + + hpcd->State = PCD_FS_STATE_BUSY; + + /* Disable the Interrupts */ + USB_FS_SetUSBInt(0U); + USB_FS_SetEPInt(0U); + /*Init the Core (common init.) */ +// if (USB_FS_CoreInit() != USB_FS_OK) +// { +// hpcd->State = PCD_FS_STATE_ERROR; +// return USB_FS_ERROR; +// } + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_FS_DevInit(hpcd->Init) != USB_FS_OK) + { + hpcd->State = PCD_FS_STATE_ERROR; + return USB_FS_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = PCD_FS_STATE_READY; + hpcd->ctrl_state = CTRL_SETUP_P; +// USB_FS_DrvSess(0U); + + return USB_FS_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_DeInit(PCD_FS_HandleTypeDef *hpcd) +{ + uint32_t i; + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return USB_FS_ERROR; + } + + hpcd->State = PCD_FS_STATE_BUSY; + + /* Stop Device */ + USB_FS_SetUSBInt(0U); + USB_FS_SetEPInt(0U); + + if (USB_FS_RstEP0Regs() != USB_FS_OK) + { + return USB_FS_ERROR; + } + for (i = 1U; i < hpcd->Init.endpoints; i++) + { + if (USB_FS_RstEPRegs(i) != USB_FS_OK) + { + return USB_FS_ERROR; + } + } + /* DeInit the low level hardware: CLOCK, NVIC.*/ + PCD_FS_MspDeInit(hpcd); + + hpcd->State = PCD_FS_STATE_RESET; + + return USB_FS_OK; +} + +/** + * @brief set iso mode. + * @param hpcd PCD handle + * @retval none + */ +void PCD_FS_SetISO(uint8_t ep_num, uint8_t state) +{ + USB_FS_IndexSel(ep_num); + if (state != 0U) + { + USB_FS->TXCSR2 |= OTG_FS_TXCSR2_ISO ; + USB_FS->RXCSR2 |= OTG_FS_RXCSR2_ISO ; + } + else + { + USB_FS->TXCSR2 &= ~OTG_FS_TXCSR2_ISO ; + USB_FS->RXCSR2 &= ~OTG_FS_RXCSR2_ISO ; + } +} + +/** + * @brief set maxpacket. + * @param hpcd PCD handle + * @retval none + */ +void PCD_FS_SetMaxPkt(uint8_t ep_num, uint16_t size) +{ + uint16_t maxpkt; + maxpkt = (size + 7U) / 8U ; + USB_FS_IndexSel(ep_num); + + USB_FS->TXMAXP = maxpkt; + USB_FS->RXMAXP = maxpkt; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_FS_MspInit(PCD_FS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_FS_MspDeInit(PCD_FS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_MspDeInit could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_Start(PCD_FS_HandleTypeDef *hpcd) +{ + __USB_FS_LOCK(hpcd); + +// USB_FS_SetUSBInt(OTG_FS_INTRUSBE_SOFINTE | OTG_FS_INTRUSBE_RSTINTE | +// OTG_FS_INTRUSBE_DISCINTE | OTG_FS_INTRUSBE_SREQINTE | +// OTG_FS_INTRUSBE_VERRINTE); + + USB_FS_DrvSess(1U); + + __USB_FS_UNLOCK(hpcd); + + return USB_FS_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_Stop(PCD_FS_HandleTypeDef *hpcd) +{ + uint32_t i; + __USB_FS_LOCK(hpcd); + + USB_FS_SetUSBInt(0U); + + USB_FS_DrvSess(0U); + if (USB_FS_FlushEp0Fifo() != USB_FS_OK) + { + return USB_FS_ERROR; + } + for (i = 1U; i < hpcd->Init.endpoints; i++) + { + if (USB_FS_FlushTxFifo(i) != USB_FS_OK) + { + return USB_FS_ERROR; + } + if (USB_FS_FlushRxFifo(i) != USB_FS_OK) + { + return USB_FS_ERROR; + } + } + __USB_FS_UNLOCK(hpcd); + + return USB_FS_OK; +} + +#if defined (USB_OTG_FS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval none + */ +void PCD_FS_IRQHandler(PCD_FS_HandleTypeDef *hpcd) +{ + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + uint32_t reg_int; + uint32_t tx_int; + uint32_t rx_int; + uint8_t reg_power; + + reg_int = USB_FS_ReadInterrupts(); + /* ensure that we are in device mode */ + if ((USB_FS_GetMode() & USB_OTG_MODE_DEVICE) == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (reg_int == 0U) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = USB_FS_GetCurrentFrame(); + + /* Handle vbus error Interrupts */ + if ((reg_int & 0xFFU) != 0U) + { + if ((reg_int & OTG_FS_INTRUSB_VERRINT) == OTG_FS_INTRUSB_VERRINT) + { + PCD_FS_VBusErrCallback(hpcd); + } + + /* Handle session request Interrupts */ + if ((reg_int & OTG_FS_INTRUSB_SREQINT) == OTG_FS_INTRUSB_SREQINT) + { + PCD_FS_SessionCallback(hpcd); + } + + /* Handle Host Disconnect Interrupts */ + if ((reg_int & OTG_FS_INTRUSB_DISCINT) == OTG_FS_INTRUSB_DISCINT) + { + /* Handle Host Port Disconnect Interrupt */ + PCD_FS_DisconnectCallback(hpcd); + } + + /* Handle Host Connect Interrupts */ +// if ((reg_int & OTG_FS_INTRUSB_CONNINT) == OTG_FS_INTRUSB_CONNINT) +// { +// /* Handle Host Port Connect Interrupt */ +// PCD_FS_ConnectCallback(hpcd); +// } + + /* Handle Host SOF Interrupt */ + if ((reg_int & OTG_FS_INTRUSB_SOFINT) == OTG_FS_INTRUSB_SOFINT) + { + PCD_FS_SOFCallback(hpcd); + } + /* Handle Host reset Interrupt */ + if ((reg_int & OTG_FS_INTRUSB_RSTINT) == OTG_FS_INTRUSB_RSTINT) + { + USB_FS->CSR0 |= (OTG_FS_CSR0_SSETUPEND | OTG_FS_CSR0_SRXPKTRDY); + USB_FS_RstEP0Regs(); + for (i = 1U; i < hpcd->Init.endpoints; i++) + { + USB_FS->TXCSR1 = 0U; + USB_FS->RXCSR1 = 0U; + (void)USB_FS_ReadInterrupts(); + USB_FS_RstEPRegs(i); + } + + USB_FS_SetEPInt(0x0FU); + + USB_FS_SetAddress(0U); + + PCD_FS_ResetCallback(hpcd); + } + /* Handle resume Interrupt */ + if ((reg_int & OTG_FS_INTRUSB_RESINT) == OTG_FS_INTRUSB_RESINT) + { + PCD_FS_ResumeCallback(hpcd); + } + /* Handle suspend Interrupt */ + if ((reg_int & OTG_FS_INTRUSB_SUSPINT) == OTG_FS_INTRUSB_SUSPINT) + { + reg_power = USB_FS_GetPower(); + if ((reg_power & OTG_FS_POWER_SUSPEND) != 0U) + { + PCD_FS_SuspendCallback(hpcd); + } + } + } + /* Handle EP0 endpoint Interrupt */ + tx_int = ((reg_int >> 8) & 0xFU); + if ((tx_int & OTG_FS_INTRTX1_EP0INF) == OTG_FS_INTRTX1_EP0INF) + { + (void)USB_FS_IndexSel(0U); + USBD_SET_ADDR(hpcd->pData); + PCD_FS_EP0_IRQHandler(hpcd); + } + + /* Handle Tx endpoint Interrupt */ + if (((reg_int >> 8) & 0xEU) != 0U) + { + for (i = 1U; i < hpcd->Init.endpoints; i++) + { + if (((tx_int >> i) & 0x01U) != 0U) + { + (void)USB_FS_IndexSel((uint8_t)i); + PCD_FS_TXEP_IRQHandler(hpcd, (uint8_t)i); + } + } + } + + /* Handle Rx endpoint Interrupt */ + if (((reg_int >> 16) & 0xFU) != 0U) + { + rx_int = ((reg_int >> 16) & 0xFU); + for (i = 1U; i < hpcd->Init.endpoints; i++) + { + if (((rx_int >> i) & 0x01U) != 0U) + { + (void)USB_FS_IndexSel((uint8_t)i); + PCD_FS_RXEP_IRQHandler(hpcd, (uint8_t)i); + } + } + } + } +} + +/** + * @brief Handles PCD Wakeup interrupt request. + * @param hpcd PCD handle + * @retval none status + */ +void PCD_FS_WKUP_IRQHandler(void) +{ + /* Clear EXTI pending Bit */ + __USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG(); +} +#endif /* defined (USB_OTG_FS) */ + + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +//void __attribute__((weak)) PCD_FS_DataOutStageCallback(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// UNUSED(epnum); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_DataOutStageCallback could be implemented in the user file +// */ +//} +// +///** +// * @brief Data IN stage callback +// * @param hpcd PCD handle +// * @param epnum endpoint number +// * @retval None +// */ +//void __attribute__((weak)) PCD_FS_DataInStageCallback(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// UNUSED(epnum); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_DataInStageCallback could be implemented in the user file +// */ +//} +///** +// * @brief Setup stage callback +// * @param hpcd PCD handle +// * @retval None +// */ +//void __attribute__((weak)) PCD_FS_SetupStageCallback(PCD_FS_HandleTypeDef *hpcd) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_SetupStageCallback could be implemented in the user file +// */ +//} +// +///** +// * @brief USB Start Of Frame callback. +// * @param hpcd PCD handle +// * @retval None +// */ +//void __attribute__((weak)) PCD_FS_SOFCallback(PCD_FS_HandleTypeDef *hpcd) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_SOFCallback could be implemented in the user file +// */ +//} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_FS_SessionCallback(PCD_FS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_FS_VBusErrCallback(PCD_FS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_FS_OVERRUNCallback(PCD_FS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_FS_UNDERRUNCallback(PCD_FS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_FS_DERRCallback(PCD_FS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_FS_SOFCallback could be implemented in the user file + */ +} +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +//void __attribute__((weak)) PCD_FS_ResetCallback(PCD_FS_HandleTypeDef *hpcd) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_ResetCallback could be implemented in the user file +// */ +//} +// +///** +// * @brief Suspend event callback. +// * @param hpcd PCD handle +// * @retval None +// */ +//void __attribute__((weak)) PCD_FS_SuspendCallback(PCD_FS_HandleTypeDef *hpcd) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_SuspendCallback could be implemented in the user file +// */ +//} +// +///** +// * @brief Resume event callback. +// * @param hpcd PCD handle +// * @retval None +// */ +//void __attribute__((weak)) PCD_FS_ResumeCallback(PCD_FS_HandleTypeDef *hpcd) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_ResumeCallback could be implemented in the user file +// */ +//} +// +// +///** +// * @brief Connection event callback. +// * @param hpcd PCD handle +// * @retval None +// */ +//void __attribute__((weak)) PCD_FS_ConnectCallback(PCD_FS_HandleTypeDef *hpcd) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_ConnectCallback could be implemented in the user file +// */ +//} +// +///** +// * @brief Disconnection event callback. +// * @param hpcd PCD handle +// * @retval None +// */ +//void __attribute__((weak)) PCD_FS_DisconnectCallback(PCD_FS_HandleTypeDef *hpcd) +//{ +// /* Prevent unused argument(s) compilation warning */ +// UNUSED(hpcd); +// +// /* NOTE : This function should not be modified, when the callback is needed, +// the PCD_FS_DisconnectCallback could be implemented in the user file +// */ +//} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +///** +// * @brief Connect the USB device +// * @param hpcd PCD handle +// * @retval USB_FS status +// */ +//USB_FS_StatusTypeDef PCD_FS_DevConnect(PCD_FS_HandleTypeDef *hpcd) +//{ +// __USB_FS_LOCK(hpcd); +// +// USB_FS_DevConnect(); +// __USB_FS_UNLOCK(hpcd); +// +// return USB_FS_OK; +//} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_DevDisconnect(PCD_FS_HandleTypeDef *hpcd) +{ + __USB_FS_LOCK(hpcd); + + USB_FS_DrvSess(0U); + __USB_FS_UNLOCK(hpcd); + + return USB_FS_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_SetAddress(PCD_FS_HandleTypeDef *hpcd, uint8_t address) +{ + __USB_FS_LOCK(hpcd); + hpcd->USB_Address = address; + USB_FS_SetAddress(address); + __USB_FS_UNLOCK(hpcd); + + return USB_FS_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_EP_Open(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) +{ + USB_FS_StatusTypeDef ret = USB_FS_OK; + PCD_FS_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __USB_FS_LOCK(hpcd); + if (ep->num != 0U) + { + USB_FS_Enable_DEP(ep); + } + __USB_FS_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_EP_Close(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_FS_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __USB_FS_LOCK(hpcd); + if (USB_FS_SendStall(ep) != USB_FS_OK) + { + return USB_FS_ERROR; + } + __USB_FS_UNLOCK(hpcd); + return USB_FS_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval none + */ +void PCD_FS_EP_Receive(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_FS_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + if (ep->num != 0U) + { + USB_FS_DEPStartXfer(ep); + } + else + { + USB_FS_DEP0StartXfer(ep); + } +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t PCD_FS_EP_GetRxCount(const PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval none + */ +void PCD_FS_EP_Transmit(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_FS_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + ep->is_stall = 0U; + + if (ep->num != 0U) + { + USB_FS_DEPStartXfer(ep); + } + else + { + USB_FS_DEP0StartXfer(ep); + } +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_EP_SetStall(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_FS_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.endpoints) + { + return USB_FS_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __USB_FS_LOCK(hpcd); + + USB_FS_SendStall(ep); + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_FS_DEP0StartXfer(ep); + } + + __USB_FS_UNLOCK(hpcd); + + return USB_FS_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_EP_ClrStall(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_FS_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.endpoints) + { + return USB_FS_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __USB_FS_LOCK(hpcd); + USB_FS_ClrStall(ep); + __USB_FS_UNLOCK(hpcd); + + return USB_FS_OK; +} + +/** + * + * @brief Abort an USB EP transaction + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_EP_Abort(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + USB_FS_StatusTypeDef ret; + PCD_FS_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + if (ep->num == 0U) + { + ret = USB_FS_RstEP0Regs(); + } + else + { + ret = USB_FS_RstEPRegs(ep->num); + } + + return ret; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_FS status + */ +USB_FS_StatusTypeDef PCD_FS_EP_Flush(PCD_FS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __USB_FS_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_FS_FlushTxFifo((uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_FS_FlushRxFifo((uint32_t)ep_addr & EP_ADDR_MSK); + } + + __USB_FS_UNLOCK(hpcd); + + return USB_FS_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval none + */ +void PCD_FS_ActivateRemoteWakeup(void) +{ + USB_FS_Activate_Resume(); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval none + */ +void PCD_FS_DeActivateRemoteWakeup(void) +{ + USB_FS_DeActivate_Resume(); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval hpcd state + */ +PCD_FS_StateTypeDef PCD_FS_GetState(PCD_FS_HandleTypeDef const *hpcd) +{ + return hpcd->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ + +#if defined (USB_OTG_FS) + + +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval USB_FS status + */ +static USB_FS_StatusTypeDef PCD_FS_WriteEmptyTxFifo(PCD_FS_HandleTypeDef *hpcd, uint8_t epnum) +{ + PCD_FS_EPTypeDef *ep; + uint32_t len; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return USB_FS_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + while (((USB_FS->TXCSR1 & OTG_FS_TXCSR1_FIFONE) == 0U) & + (ep->xfer_count < ep->xfer_len) & (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + USB_FS_FIFOWrite(ep->xfer_buff, (uint8_t)epnum, (uint16_t)len); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + return USB_FS_OK; +} + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval none + * */ +void PCD_FS_EP0_IRQHandler(PCD_FS_HandleTypeDef *hpcd) +{ + USB_OTG_FS_DEPTypeDef *ep; + uint8_t tmpreg; + uint8_t bytecount; + tmpreg = USB_FS->CSR0; + + if ((tmpreg & OTG_FS_CSR0_RXPKTRDY) == OTG_FS_CSR0_RXPKTRDY) + { + bytecount = USB_FS_Read_Count0(); + ep = &hpcd->OUT_ep[0U]; + + if (hpcd->ctrl_state == CTRL_SETUP_P) + { + hpcd->ctrl_state = CTRL_DATA; + USB_FS_FIFORead((uint8_t *)hpcd->Setup, 0U, bytecount); + USB_FS->CSR0 |= OTG_FS_CSR0_SRXPKTRDY; + PCD_FS_SetupStageCallback(hpcd); + } + else + { + USB_FS_FIFORead(ep->xfer_buff, 0U, bytecount); + + ep->xfer_buff += bytecount; + ep->xfer_count += bytecount; + + USB_FS->CSR0 |= OTG_FS_CSR0_SRXPKTRDY; + + if (ep->xfer_count >= ep->xfer_len || bytecount < ep->maxpacket) + { + hpcd->ctrl_state = CTRL_SETUP_P; + PCD_FS_DataOutStageCallback(hpcd, 0U); + } + } + } + else if (tmpreg != 0U) + { + if ((tmpreg & OTG_FS_CSR0_SETUPEND) == OTG_FS_CSR0_SETUPEND) + { + USB_FS->CSR0 |= OTG_FS_CSR0_SSETUPEND; + USB_FS_FlushEp0Fifo(); + } + if ((tmpreg & OTG_FS_CSR0_STSTALL) == OTG_FS_CSR0_STSTALL) + { + hpcd->ctrl_state = CTRL_SETUP_P; + USB_FS_FlushEp0Fifo(); /* flush fifo to halt transcation*/ + USB_FS->CSR0 &= (~(OTG_FS_CSR0_STSTALL | OTG_FS_CSR0_SDSTALL)); + } + } + else + { + PCD_FS_DataInStageCallback(hpcd, 0U); /* for packet split */ + hpcd->ctrl_state = CTRL_SETUP_P;/*...*/ + } + +} + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval none + * */ +void PCD_FS_TXEP_IRQHandler(PCD_FS_HandleTypeDef *hpcd, uint32_t epnum) +{ + uint8_t tmpreg; + uint32_t num_packets; + + tmpreg = USB_FS->TXCSR1; + + if ((tmpreg & OTG_FS_TXCSR1_FIFONE) == 0U) + { + USB_FS_FlushTxFifo(epnum); + } + + if ((tmpreg & OTG_FS_TXCSR1_STSTALL) == OTG_FS_TXCSR1_STSTALL) + { + (void)USB_FS_FlushTxFifo(epnum); /* flush fifo to halt transcation*/ + USB_FS->TXCSR1 &= (~OTG_FS_TXCSR1_STSTALL); + } + else if ((tmpreg & OTG_FS_TXCSR1_UNDERRUN) == OTG_FS_TXCSR1_UNDERRUN) + { + USB_FS->TXCSR1 &= (~OTG_FS_TXCSR1_UNDERRUN); + PCD_FS_UNDERRUNCallback(hpcd); + } + else + { + PCD_FS_DataInStageCallback(hpcd, (uint8_t)epnum); + } +} + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval none + * */ +void PCD_FS_RXEP_IRQHandler(PCD_FS_HandleTypeDef *hpcd, uint32_t epnum) +{ + uint8_t tmpreg; + uint16_t byte_count; + uint32_t num_packets; + PCD_FS_EPTypeDef *ep; + + tmpreg = USB_FS->RXCSR1; + + if (((tmpreg & OTG_FS_RXCSR1_FIFOF) == OTG_FS_RXCSR1_FIFOF) & + ((tmpreg & OTG_FS_RXCSR1_RXPKTRDY) != OTG_FS_RXCSR1_RXPKTRDY)) + { + byte_count = USB_FS_Read_RxCount(); + USB_FS_FIFORead(ep->xfer_buff, epnum, byte_count); + // PCD_FS_FIFOFULLCallback(hpcd); + } + + if ((tmpreg & OTG_FS_RXCSR1_STSTALL) == OTG_FS_RXCSR1_STSTALL) + { + (void)USB_FS_FlushRxFifo(epnum); /* flush fifo to halt transcation*/ + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_STSTALL); + } + else if ((tmpreg & OTG_FS_RXCSR1_OVERRUN) == OTG_FS_RXCSR1_OVERRUN) + { + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_OVERRUN); + PCD_FS_OVERRUNCallback(hpcd); + } + else if ((tmpreg & OTG_FS_RXCSR1_RXPKTRDY) == OTG_FS_RXCSR1_RXPKTRDY) + { + if ((tmpreg & OTG_FS_RXCSR1_DERR) == OTG_FS_RXCSR1_DERR) + { + PCD_FS_DERRCallback(hpcd); + } + else + { + byte_count = USB_FS_Read_RxCount(); + USB_FS_FIFORead(ep->xfer_buff, epnum, byte_count); +// PCD_FS_DataInStageCallback(hpcd, (uint8_t)epnum, byte_count); + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_RXPKTRDY); + } + } +} + + +#endif /* defined (USB_OTG_FS) */ + + +/** + * @brief Set Tx FIFO + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval none + */ +void PCD_FS_SetTxFiFo(uint8_t fifo, uint16_t size, uint8_t dpb) +{ + uint8_t i; + uint32_t Tx_Offset; + uint8_t fifo_size; + uint8_t dpb_cfg; + + dpb_cfg = dpb << 4 ; + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + */ + + Tx_Offset = 0x08; + if (fifo == 0U) + { + return; + } + else + { + for (i = 1U; i < fifo; i++) + { + USB_FS_IndexSel(i); + fifo_size = USB_FS->TXFIFO2 >> 5 ; + Tx_Offset += (0x01U << fifo_size); + } + USB_FS_IndexSel(fifo); + USB_FS->TXFIFO1 = Tx_Offset; + USB_FS->TXFIFO2 = ((usb_log2((size + 7U) / 8U) << 5) | dpb_cfg); + } +} + +/** + * @brief Set Rx FIFO + * @param size Size of Rx fifo + * @retval none + */ +void PCD_FS_SetRxFiFo(uint8_t fifo, uint16_t size, uint8_t dpb) +{ + uint8_t i; + uint32_t Rx_Offset; + uint8_t fifo_size; + uint8_t dpb_cfg; + + dpb_cfg = dpb << 4 ; + Rx_Offset = 0x08; + + if (fifo == 0U) + { + return; + } + else + { + for (i = 1U; i < fifo; i++) + { + USB_FS_IndexSel(i); + fifo_size = USB_FS->RXFIFO2 >> 5 ; + Rx_Offset += (0x01U << fifo_size); + } + USB_FS_IndexSel(fifo); + USB_FS->RXFIFO1 = Rx_Offset; + USB_FS->RXFIFO2 = ((usb_log2((size + 7U) / 8U) << 5) | dpb_cfg); + } +} + +/** + * @} + */ + + +#endif /* defined (USB_OTG_FS) */ +#endif /* PCD_FS_MODULE_ENABLED */ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_hs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_hs.c new file mode 100644 index 00000000000..3ad3449bbcf --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pcd_hs.c @@ -0,0 +1,1438 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pcd_hs.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * @version V1.0.0 + * @data 2025-03-26 + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#)Declare a PCD_HS_HandleTypeDef handle structure, for example: + PCD_HS_HandleTypeDef hpcd; + + (#)Fill parameters of Init structure in PCD handle + + (#)Call PCD_HS_Init() API to initialize the PCD peripheral (Core, Host core, ...) + + (#)Initialize the PCD low level resources through the PCD_HS_MspInit() API: + (##) Enable the PCD/USB Low Level interface clock using the following macros + (##) Initialize the related GPIO clocks + (##) Configure PCD NVIC interrupt + + (#)Associate the Upper USB Host stack to the PCD Driver: + (##) hpcd.pData = pdev; + + (#)Enable PCD transmission and reception: + (##) PCD_HS_Start(); + + @endverbatim + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "ft32f4xx_rcc.h" +#include "ft32f4xx_pcd_hs.h" + +/** @addtogroup FT32F4xx_DRIVER + * @{ + */ + +#ifdef PCD_MODULE_ENABLED +#if defined (USB_OTG_HS) +/** @defgroup PCD_HS PCD + * @brief PCD HS module driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup PCD_HS_Private_Macros PCD Private Functions + * @{ + */ +#define PCD_MIN(a,b) (((a) < (b)) ? (a) : (b)) +#define PCD_MAX(a,b) (((a) > (b)) ? (a) : (b)) +/** + * @{ + */ + +/** @defgroup PCD_HS_Private_Functions PCD Private Functions + * @{ + */ + +static USB_HS_StatusTypeDef PCD_HS_WriteEmptyTxFifo(PCD_HS_HandleTypeDef *hpcd, uint32_t epnum); +static void PCD_HS_EP_OutXfrComplete_int(PCD_HS_HandleTypeDef *hpcd, uint32_t epnum); +static void PCD_HS_EP_OutSetupPacket_int(PCD_HS_HandleTypeDef *hpcd, uint32_t epnum); +/** + * @{ + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup PCD_HS_Exported_Functions PCD Exported Functions + * @{ + */ + +/** @defgroup PCD_HS_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This section provides functions allowing to: + +@endverbatim + * @{ + */ + +/** + * @brief Initializes the PCD according to the specified + * parameters in the PCD_InitTypeDef and initialize the associated handle. + * @param hpcd PCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_Init(PCD_HS_HandleTypeDef *hpcd) +{ + + uint8_t i; + + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return USB_HS_ERROR; + } + + if (hpcd->State == PCD_HS_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + hpcd->Lock = USB_HS_UNLOCKED; + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + PCD_HS_MspInit(hpcd); + } + + hpcd->State = PCD_HS_STATE_BUSY; + + /* Disable the Interrupts */ + __PCD_HS_DISABLE(); + + /*Init the Core (common init.) */ + if (USB_HS_CoreInit(hpcd->Init) != USB_HS_OK) + { + hpcd->State = PCD_HS_STATE_ERROR; + return USB_HS_ERROR; + } + + /* Init endpoints structures */ + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + /* Init ep structure */ + hpcd->IN_ep[i].is_in = 1U; + hpcd->IN_ep[i].num = i; + hpcd->IN_ep[i].tx_fifo_num = i; + /* Control until ep is activated */ + hpcd->IN_ep[i].type = EP_TYPE_CTRL; + hpcd->IN_ep[i].maxpacket = 0U; + hpcd->IN_ep[i].xfer_buff = 0U; + hpcd->IN_ep[i].xfer_len = 0U; + } + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + hpcd->OUT_ep[i].is_in = 0U; + hpcd->OUT_ep[i].num = i; + /* Control until ep is activated */ + hpcd->OUT_ep[i].type = EP_TYPE_CTRL; + hpcd->OUT_ep[i].maxpacket = 0U; + hpcd->OUT_ep[i].xfer_buff = 0U; + hpcd->OUT_ep[i].xfer_len = 0U; + } + + /* Init Device */ + if (USB_HS_DevInit(hpcd->Init) != USB_HS_OK) + { + hpcd->State = PCD_HS_STATE_ERROR; + return USB_HS_ERROR; + } + + hpcd->USB_Address = 0U; + hpcd->State = PCD_HS_STATE_READY; + + USB_HS_DevDisconnect(); + + return USB_HS_OK; +} + +/** + * @brief DeInitializes the PCD peripheral. + * @param hpcd PCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_DeInit(PCD_HS_HandleTypeDef *hpcd) +{ + /* Check the PCD handle allocation */ + if (hpcd == NULL) + { + return USB_HS_ERROR; + } + + hpcd->State = PCD_HS_STATE_BUSY; + + /* Stop Device */ + if (USB_HS_StopDevice() != USB_HS_OK) + { + return USB_HS_ERROR; + } + + /* DeInit the low level hardware: CLOCK, NVIC.*/ + PCD_HS_MspDeInit(hpcd); + + hpcd->State = PCD_HS_STATE_RESET; + + return USB_HS_OK; +} + +/** + * @brief Initializes the PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_MspInit(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes PCD MSP. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_MspDeInit(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_MspDeInit could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions + * @brief Data transfers functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Start the USB device + * @param hpcd PCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_Start(PCD_HS_HandleTypeDef *hpcd) +{ + __USB_HS_LOCK(hpcd); + __PCD_HS_ENABLE(); + + USB_HS_DevConnect(); + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} + +/** + * @brief Stop the USB device. + * @param hpcd PCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_Stop(PCD_HS_HandleTypeDef *hpcd) +{ + __USB_HS_LOCK(hpcd); + __PCD_HS_DISABLE(); + + USB_HS_DevDisconnect(); + + (void)USB_HS_FlushTxFifo(0x10U); + + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} + +#if defined (USB_OTG_HS) +/** + * @brief Handles PCD interrupt request. + * @param hpcd PCD handle + * @retval none + */ +void PCD_HS_IRQHandler(PCD_HS_HandleTypeDef *hpcd) +{ + USB_OTG_HS_EPTypeDef *ep; + RCC_ClocksTypeDef RCC_ClocksStatus; + uint32_t AHBCLK; + uint32_t i; + uint32_t ep_intr; + uint32_t epint; + uint32_t epnum; + uint32_t fifoemptymsk; + uint32_t RegVal; + + /* ensure that we are in device mode */ + if (USB_HS_GetMode() == USB_OTG_MODE_DEVICE) + { + /* avoid spurious interrupt */ + if (__PCD_HS_IS_INVALID_INTERRUPT()) + { + return; + } + + /* store current frame number */ + hpcd->FrameNumber = (USB_HS_DEVICE->DSTS & OTG_HS_DSTS_FNSOF_Msk) >> OTG_HS_DSTS_FNSOF_Pos; + + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_MMIS)) + { + /* incorrect mode, acknowledge the interrupt */ + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_MMIS); + } + + /* Handle RxQLevel Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_RXFLVL)) + { + USB_HS_MASK_INTERRUPT(OTG_HS_GINTSTS_RXFLVL); + + RegVal = USB_HS->GRXSTSP; + + ep = &hpcd->OUT_ep[RegVal & OTG_HS_GRXSTSP_EPNUM]; + + if (((RegVal & OTG_HS_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) + { + if ((RegVal & OTG_HS_GRXSTSP_BCNT) != 0U) + { + (void)USB_HS_ReadPacket(ep->xfer_buff, (uint16_t)((RegVal & OTG_HS_GRXSTSP_BCNT) >> 4)); + + ep->xfer_buff += (RegVal & OTG_HS_GRXSTSP_BCNT) >> 4; + ep->xfer_count += (RegVal & OTG_HS_GRXSTSP_BCNT) >> 4; + } + } + else if (((RegVal & OTG_HS_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) + { + (void)USB_HS_ReadPacket((uint8_t *)hpcd->Setup, 8U); + ep->xfer_count += (RegVal & OTG_HS_GRXSTSP_BCNT) >> 4; + } + else + { + /* ... */ + } + USB_HS_UNMASK_INTERRUPT(OTG_HS_GINTSTS_RXFLVL); + } + /* USB_HS->GINTSTS OEPINT(OUT POINT)*/ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_OEPINT)) + { + epnum = 0U; + + /* Read in the device interrupt bits */ + ep_intr = USB_HS_ReadDevAllOutEpInterrupt(); + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) + { + epint = USB_HS_ReadDevOutEPInterrupt((uint8_t)epnum); +// if(epnum == 0)USBD_SET_ADDR_Callback(hpcd); + if ((epint & OTG_HS_DOEPINT_XFRC) == OTG_HS_DOEPINT_XFRC) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_XFRC); + (void)PCD_HS_EP_OutXfrComplete_int(hpcd, epnum); + } + + if ((epint & OTG_HS_DOEPINT_STUPD) == OTG_HS_DOEPINT_STUPD) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_STUPD); + /* Class B setup phase done for previous decoded setup */ + (void)PCD_HS_EP_OutSetupPacket_int(hpcd, epnum); + } + + if ((epint & OTG_HS_DOEPINT_OTKNEPDIS) ==OTG_HS_DOEPINT_OTKNEPDIS) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_OTKNEPDIS); + } + + /* Clear OUT Endpoint disable interrupt */ + if ((epint & OTG_HS_DOEPINT_EPDISD) == OTG_HS_DOEPINT_EPDISD) + { + if ((USB_HS->GINTSTS & OTG_HS_GINTSTS_GONAKEFF) == OTG_HS_GINTSTS_GONAKEFF) + { + USB_HS_DEVICE->DCTL |= OTG_HS_DCTL_CGONAK ; + } + + ep = &hpcd->OUT_ep[epnum]; + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + + PCD_HS_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); + } + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_EPDISD); + } + + /* Clear Status Phase Received interrupt */ + if ((epint & OTG_HS_DOEPINT_OTEPSPR) == OTG_HS_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_OTEPSPR); + } + + /* Clear OUT NAK interrupt */ + if ((epint & OTG_HS_DOEPINT_NAKINT) == OTG_HS_DOEPINT_NAKINT) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_NAKINT); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_IEPINT)) + { + /* Read in the device interrupt bits */ + ep_intr = USB_HS_ReadDevAllInEpInterrupt(); + + epnum = 0U; + + while (ep_intr != 0U) + { + if ((ep_intr & 0x1U) != 0U) /* In ITR */ + { + epint = USB_HS_ReadDevInEPInterrupt((uint8_t)epnum); + + if ((epint & OTG_HS_DIEPINT_XFRC) == OTG_HS_DIEPINT_XFRC) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USB_HS_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + + CLEAR_IN_EP_INTR(epnum, OTG_HS_DIEPINT_XFRC); + + PCD_HS_DataInStageCallback(hpcd, (uint8_t)epnum); + } + if ((epint & OTG_HS_DIEPINT_TOC) == OTG_HS_DIEPINT_TOC) + { + CLEAR_IN_EP_INTR(epnum, OTG_HS_DIEPINT_TOC); + } + if ((epint & OTG_HS_DIEPINT_ITTXFE) == OTG_HS_DIEPINT_ITTXFE) + { + CLEAR_IN_EP_INTR(epnum, OTG_HS_DIEPINT_ITTXFE); + } + if ((epint & OTG_HS_DIEPINT_INEPNE) == OTG_HS_DIEPINT_INEPNE) + { + CLEAR_IN_EP_INTR(epnum, OTG_HS_DIEPINT_INEPNE); + } + if ((epint & OTG_HS_DIEPINT_EPDISD) == OTG_HS_DIEPINT_EPDISD) + { + (void)USB_HS_FlushTxFifo(epnum); + + ep = &hpcd->IN_ep[epnum]; + if (ep->is_iso_incomplete == 1U) + { + ep->is_iso_incomplete = 0U; + + PCD_HS_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); + } + + CLEAR_IN_EP_INTR(epnum, OTG_HS_DIEPINT_EPDISD); + } + if ((epint & OTG_HS_DIEPINT_TXFE) == OTG_HS_DIEPINT_TXFE) + { + (void)PCD_HS_WriteEmptyTxFifo(hpcd, epnum); + } + } + epnum++; + ep_intr >>= 1U; + } + } + + /* Handle Resume Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_WKUPINT)) + { + /* Clear the Remote Wake-up Signaling */ + USB_HS_DEVICE->DCTL &= ~OTG_HS_DCTL_RWUSIG; + + PCD_HS_ResumeCallback(hpcd); + + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_WKUPINT); + } + + /* Handle Suspend Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_USBSUSP)) + { + if ((USB_HS_DEVICE->DSTS & OTG_HS_DSTS_SUSPSTS) == OTG_HS_DSTS_SUSPSTS) + { + +// PCD_HS_SuspendCallback(hpcd); + } + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_USBSUSP); + } + /* Handle Reset Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_USBRST)) + { + USB_HS_DEVICE->DCTL &= ~OTG_HS_DCTL_RWUSIG; + (void)USB_HS_FlushTxFifo(0x10U); + + for (i = 0U; i < hpcd->Init.dev_endpoints; i++) + { + USB_HS_INEP(i)->DIEPINT = 0xFB7FU; + USB_HS_INEP(i)->DIEPCTL &= ~OTG_HS_DIEPCTL_STALL; + USB_HS_OUTEP(i)->DOEPINT = 0xFB7FU; + USB_HS_OUTEP(i)->DOEPCTL &= ~OTG_HS_DOEPCTL_STALL; + USB_HS_OUTEP(i)->DOEPCTL |= OTG_HS_DOEPCTL_SNAK; + } + USB_HS_DEVICE->DAINTMSK |= 0x10001U; + + if (hpcd->Init.use_dedicated_ep1 != 0U) + { + USB_HS_DEVICE->DOUTEP1MSK |= OTG_HS_DOEPMSK_STUPM | + OTG_HS_DOEPMSK_XFRCM | + OTG_HS_DOEPMSK_EPDM; + + USB_HS_DEVICE->DINEP1MSK |= OTG_HS_DIEPMSK_TOM | + OTG_HS_DIEPMSK_XFRCM | + OTG_HS_DIEPMSK_EPDM; + } + else + { + USB_HS_DEVICE->DOEPMSK |= OTG_HS_DOEPMSK_STUPM | + OTG_HS_DOEPMSK_XFRCM | + OTG_HS_DOEPMSK_EPDM | + OTG_HS_DOEPMSK_OTEPSPRM | + OTG_HS_DOEPMSK_NAKM; + + USB_HS_DEVICE->DIEPMSK |= OTG_HS_DIEPMSK_TOM | + OTG_HS_DIEPMSK_XFRCM | + OTG_HS_DIEPMSK_EPDM ; + } + + /* Set Default Address to 0 */ + USB_HS_DEVICE->DCFG &= ~OTG_HS_DCFG_DAD; + + /* setup EP0 to receive SETUP packets */ + (void)USB_HS_EP0_OutStart((uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_USBRST); + } + + /* Handle Enumeration done Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_ENUMDNE)) + { + (void)USB_HS_ActivateSetup(); + hpcd->Init.speed = USB_HS_GetDevSpeed(); + + /* Set USB Turnaround time */ + /* RCC_GetClocksFreq wait for update */ + RCC_GetClocksFreq(&RCC_ClocksStatus); + AHBCLK = RCC_ClocksStatus.HCLK_Frequency; + (void)USB_HS_SetTurnaroundTime(AHBCLK, (uint8_t)hpcd->Init.speed); + + PCD_HS_ResetCallback(hpcd); + + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_ENUMDNE); + } + + /* Handle SOF Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_SOF)) + { + PCD_HS_SOFCallback(hpcd); + + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_SOF); + } + + /* Handle Global OUT NAK effective Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_GONAKEFF)) + { + USB_HS->GINTMSK &= ~OTG_HS_GINTMSK_GONAKEFM; + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) + { + /* abort current transaction and disable the EP */ + (void)PCD_HS_EP_Abort(hpcd, (uint8_t)epnum); + } + } + } + /* Handle Incomplete ISO IN Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_IISOIXFR)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USB_HS_INEP(epnum)->DIEPCTL; + + if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) & ((RegVal & OTG_HS_DIEPCTL_EPENA) == OTG_HS_DIEPCTL_EPENA)) + { + hpcd->IN_ep[epnum].is_iso_incomplete = 1U; + + /* Abort current transaction and disable the EP */ + (void)PCD_HS_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); + } + } + + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_IISOIXFR); + } + + /* Handle Incomplete ISO OUT Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_IPXFR_INCOMPISOOUT)) + { + for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) + { + RegVal = USB_HS_OUTEP(epnum)->DOEPCTL; + + if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) & ((RegVal & OTG_HS_DOEPCTL_EPENA) == OTG_HS_DIEPCTL_EPENA) + & (((RegVal & (0x1U << 16U)) >> 16U) == (hpcd->FrameNumber & 0x1U))) + { + hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; + USB_HS->GINTMSK |= OTG_HS_GINTMSK_GONAKEFM; + + if ((USB_HS->GINTSTS & OTG_HS_GINTSTS_GONAKEFF) == 0U) + { + USB_HS_DEVICE->DCTL |= OTG_HS_DCTL_SGONAK; + break; + } + } + } + + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_IPXFR_INCOMPISOOUT); + } + + /* Handle Connection event Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_SRQINT)) + { + PCD_HS_ConnectCallback(hpcd); + + __PCD_HS_CLEAR_FLAG(OTG_HS_GINTSTS_SRQINT); + } + + /* Handle Disconnection event Interrupt */ + if (__PCD_HS_GET_FLAG(OTG_HS_GINTSTS_OTGINT)) + { + RegVal = USB_HS->GOTGINT; + + if ((RegVal & OTG_HS_GOTGINT_SEDET) == OTG_HS_GOTGINT_SEDET) + { + + PCD_HS_DisconnectCallback(hpcd); + } + USB_HS->GOTGINT |= RegVal; + } + } +} + +/** + * @brief Handles PCD Wakeup interrupt request. + * @param hpcd PCD handle + * @retval none status + */ +void PCD_HS_WKUP_IRQHandler() +{ + /* Clear EXTI pending Bit */ + __USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG(); +} +#endif /* defined (USB_OTG_HS) */ + + +/** + * @brief Data OUT stage callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +void __attribute__((weak)) PCD_HS_DataOutStageCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_DataOutStageCallback could be implemented in the user file + */ +} + +/** + * @brief Data IN stage callback + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +void __attribute__((weak)) PCD_HS_DataInStageCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_DataInStageCallback could be implemented in the user file + */ +} +/** + * @brief Setup stage callback + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_SetupStageCallback(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_SetupStageCallback could be implemented in the user file + */ +} + +/** + * @brief USB Start Of Frame callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_SOFCallback(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_SOFCallback could be implemented in the user file + */ +} + +/** + * @brief USB Reset callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_ResetCallback(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_ResetCallback could be implemented in the user file + */ +} +void __attribute__((weak)) USBD_SET_ADDR_Callback(PCD_HS_HandleTypeDef *hpcd) +{ + UNUSED(hpcd); +} +/** + * @brief Suspend event callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_SuspendCallback(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_SuspendCallback could be implemented in the user file + */ +} + +/** + * @brief Resume event callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_ResumeCallback(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_ResumeCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO OUT callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +void __attribute__((weak)) PCD_HS_ISOOUTIncompleteCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_ISOOUTIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Incomplete ISO IN callback. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval None + */ +void __attribute__((weak)) PCD_HS_ISOINIncompleteCallback(PCD_HS_HandleTypeDef *hpcd, uint8_t epnum) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + UNUSED(epnum); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_ISOINIncompleteCallback could be implemented in the user file + */ +} + +/** + * @brief Connection event callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_ConnectCallback(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_ConnectCallback could be implemented in the user file + */ +} + +/** + * @brief Disconnection event callback. + * @param hpcd PCD handle + * @retval None + */ +void __attribute__((weak)) PCD_HS_DisconnectCallback(PCD_HS_HandleTypeDef *hpcd) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(hpcd); + + /* NOTE : This function should not be modified, when the callback is needed, + the PCD_HS_DisconnectCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions + * @brief management functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the PCD data + transfers. + +@endverbatim + * @{ + */ + +/** + * @brief Connect the USB device + * @param hpcd PCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_DevConnect(PCD_HS_HandleTypeDef *hpcd) +{ + __USB_HS_LOCK(hpcd); + + USB_HS_DevConnect(); + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} + +/** + * @brief Disconnect the USB device. + * @param hpcd PCD handle + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_DevDisconnect(PCD_HS_HandleTypeDef *hpcd) +{ + __USB_HS_LOCK(hpcd); + + USB_HS_DevDisconnect(); + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} + +/** + * @brief Set the USB Device address. + * @param hpcd PCD handle + * @param address new device address + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_SetAddress(PCD_HS_HandleTypeDef *hpcd, uint8_t address) +{ + __USB_HS_LOCK(hpcd); + hpcd->USB_Address = address; + USB_HS_SetDevAddress(address); + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} +/** + * @brief Open and configure an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param ep_mps endpoint max packet size + * @param ep_type endpoint type + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_EP_Open(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, + uint16_t ep_mps, uint8_t ep_type) +{ + USB_HS_StatusTypeDef ret = USB_HS_OK; + PCD_HS_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->num = ep_addr & EP_ADDR_MSK; + ep->maxpacket = ep_mps; + ep->type = ep_type; + + if (ep->is_in != 0U) + { + /* Assign a Tx FIFO */ + ep->tx_fifo_num = ep->num; + } + /* Set initial data PID. */ + if (ep_type == EP_TYPE_BULK) + { + ep->data_pid_start = 0U; + } + + __USB_HS_LOCK(hpcd); + USB_HS_ActivateEndpoint(ep); + __USB_HS_UNLOCK(hpcd); + + return ret; +} + +/** + * @brief Deactivate an endpoint. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_EP_Close(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_HS_EPTypeDef *ep; + + if ((ep_addr & 0x80U) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + ep->num = ep_addr & EP_ADDR_MSK; + + __USB_HS_LOCK(hpcd); + USB_HS_DeactivateEndpoint(ep); + __USB_HS_UNLOCK(hpcd); + return USB_HS_OK; +} + + +/** + * @brief Receive an amount of data. + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the reception buffer + * @param len amount of data to be received + * @retval none + */ +void PCD_HS_EP_Receive(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_HS_EPTypeDef *ep; + + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + if (hpcd->Init.dma_enable == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + USB_HS_EPStartXfer(ep, (uint8_t)hpcd->Init.dma_enable); + +} + +/** + * @brief Get Received Data Size + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval Data Size + */ +uint32_t PCD_HS_EP_GetRxCount(PCD_HS_HandleTypeDef const *hpcd, uint8_t ep_addr) +{ + return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; +} +/** + * @brief Send an amount of data + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @param pBuf pointer to the transmission buffer + * @param len amount of data to be sent + * @retval none + */ +void PCD_HS_EP_Transmit(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) +{ + PCD_HS_EPTypeDef *ep; + + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + + /*setup and start the Xfer */ + ep->xfer_buff = pBuf; + ep->xfer_len = len; + ep->xfer_count = 0U; + ep->is_in = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + if ((ep_addr & EP_ADDR_MSK) == 1U) + { + ep->dma_addr = (uint32_t)pBuf; + } + + USB_HS_EPStartXfer(ep, (uint8_t)hpcd->Init.dma_enable); + +} + +/** + * @brief Set a STALL condition over an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_EP_SetStall(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_HS_EPTypeDef *ep; + + if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) + { + return USB_HS_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr]; + ep->is_in = 0U; + } + + ep->is_stall = 1U; + ep->num = ep_addr & EP_ADDR_MSK; + + __USB_HS_LOCK(hpcd); + + USB_HS_EPSetStall(ep); + + if ((ep_addr & EP_ADDR_MSK) == 0U) + { + (void)USB_HS_EP0_OutStart((uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); + } + + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} + +/** + * @brief Clear a STALL condition over in an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_EP_ClrStall(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + PCD_HS_EPTypeDef *ep; + + if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) + { + return USB_HS_ERROR; + } + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 1U; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + ep->is_in = 0U; + } + + ep->is_stall = 0U; + ep->num = ep_addr & EP_ADDR_MSK; + + __USB_HS_LOCK(hpcd); + USB_HS_EPClearStall(ep); + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} + +/** + * + * @brief Abort an USB EP transaction + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_EP_Abort(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + USB_HS_StatusTypeDef ret; + PCD_HS_EPTypeDef *ep; + + if ((0x80U & ep_addr) == 0x80U) + { + ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; + } + else + { + ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; + } + + /* Stop Xfer */ + ret = USB_HS_EPStopXfer(ep); + + return ret; +} + +/** + * @brief Flush an endpoint + * @param hpcd PCD handle + * @param ep_addr endpoint address + * @retval USB_HS status + */ +USB_HS_StatusTypeDef PCD_HS_EP_Flush(PCD_HS_HandleTypeDef *hpcd, uint8_t ep_addr) +{ + __USB_HS_LOCK(hpcd); + + if ((ep_addr & 0x80U) == 0x80U) + { + (void)USB_HS_FlushTxFifo((uint32_t)ep_addr & EP_ADDR_MSK); + } + else + { + (void)USB_HS_FlushRxFifo(); + } + + __USB_HS_UNLOCK(hpcd); + + return USB_HS_OK; +} + +/** + * @brief Activate remote wakeup signalling + * @param hpcd PCD handle + * @retval none + */ +void PCD_HS_ActivateRemoteWakeup() +{ + USB_HS_ActivateRemoteWakeup(); +} + +/** + * @brief De-activate remote wakeup signalling. + * @param hpcd PCD handle + * @retval none + */ +void PCD_HS_DeActivateRemoteWakeup() +{ + USB_HS_DeActivateRemoteWakeup(); +} + +/** + * @} + */ + +/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions + * @brief Peripheral State functions + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the PCD handle state. + * @param hpcd PCD handle + * @retval hpcd state + */ +PCD_HS_StateTypeDef PCD_HS_GetState(PCD_HS_HandleTypeDef const *hpcd) +{ + return hpcd->State; +} + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup PCD_Private_Functions + * @{ + */ +#if defined (USB_OTG_HS) + +/** + * @brief Set the USB Device high speed test mode + * @param hpcd PCD handle + * @param testmode USB Device high speed testmode + * @retval none + */ +void PCD_HS_SetTestMode(uint8_t testmode) +{ + switch (testmode) + { + case TEST_J: + case TEST_K: + case TEST_SE0_NAK: + case TEST_PACKET: + case TEST_FORCE_EN: + USB_HS_DEVICE->DCTL |= (uint32_t)testmode << 4; + break; + + default: + break; + + } +} +#endif /* defined (USB_OTG_HS) */ + + +#if defined (USB_OTG_HS) + + +/** + * @brief Check FIFO for the next packet to be loaded. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval USBH status + */ +static USB_HS_StatusTypeDef PCD_HS_WriteEmptyTxFifo(PCD_HS_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_HS_EPTypeDef *ep; + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + ep = &hpcd->IN_ep[epnum]; + + if (ep->xfer_count > ep->xfer_len) + { + return USB_HS_ERROR; + } + + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + + len32b = (len + 3U) / 4U; + + while (((USB_HS_INEP(epnum)->DTXFSTS & OTG_HS_DTXFSTS_INEPTFSAV) >= len32b) & + (ep->xfer_count < ep->xfer_len) & (ep->xfer_len != 0U)) + { + /* Write the FIFO */ + len = ep->xfer_len - ep->xfer_count; + + if (len > ep->maxpacket) + { + len = ep->maxpacket; + } + len32b = (len + 3U) / 4U; + + USB_HS_WritePacket(ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, (uint8_t)hpcd->Init.dma_enable); + + ep->xfer_buff += len; + ep->xfer_count += len; + } + + if (ep->xfer_len <= ep->xfer_count) + { + fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); + USB_HS_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; + } + + return USB_HS_OK; +} + + +/** + * @brief process EP OUT transfer complete interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval none + * */ +void PCD_HS_EP_OutXfrComplete_int(PCD_HS_HandleTypeDef *hpcd, uint32_t epnum) +{ + USB_OTG_HS_EPTypeDef *ep; + uint32_t DoepintReg = USB_HS_OUTEP(epnum)->DOEPINT; + + if (hpcd->Init.dma_enable == 1U) + { + if ((DoepintReg & OTG_HS_DOEPINT_STUPD) == OTG_HS_DOEPINT_STUPD) /* Class C */ + { + /* StupPktRcvd = 1 this is a setup packet */ + if((DoepintReg & OTG_HS_DOEPINT_STPKRE) == OTG_HS_DOEPINT_STPKRE) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_STPKRE); + } + } + else if ((DoepintReg & OTG_HS_DOEPINT_OTEPSPR) == OTG_HS_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_OTEPSPR); + } + else if ((DoepintReg & (OTG_HS_DOEPINT_STUPD | OTG_HS_DOEPINT_OTEPSPR)) == 0U) + { + /* StupPktRcvd = 1 this is a setup packet */ + if((DoepintReg & OTG_HS_DOEPINT_STPKRE) == OTG_HS_DOEPINT_STPKRE) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_STPKRE); + } + else + { + ep = &hpcd->OUT_ep[epnum]; + /* out data packet received over EP */ + ep->xfer_count = ep->xfer_size - (USB_HS_OUTEP(epnum)->DOEPTSIZ & OTG_HS_DOEPTSIZ_XFRSIZ) ; + + if (epnum == 0U) + { + if (ep->xfer_len == 0U) + { + /* this is ZLP, so prepare EP0 for next setup */ + (void)USB_HS_EP0_OutStart(1U, (uint8_t *)hpcd->Setup); + } + else + { + ep->xfer_buff += ep->xfer_count; + } + } + + PCD_HS_DataOutStageCallback(hpcd, (uint8_t)epnum); + } + } + else + { + /*...*/ + } + } + else + { + /* StupPktRcvd = 1 this is a setup packet */ + if ((DoepintReg & OTG_HS_DOEPINT_STPKRE) == OTG_HS_DOEPINT_STPKRE) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_STPKRE); + } + else + { + if ((DoepintReg & OTG_HS_DOEPINT_OTEPSPR) == OTG_HS_DOEPINT_OTEPSPR) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_OTEPSPR); + } + + PCD_HS_DataOutStageCallback(hpcd, (uint8_t)epnum); + } + + } + +} + + +/** + * @brief process EP OUT setup packet received interrupt. + * @param hpcd PCD handle + * @param epnum endpoint number + * @retval none + */ +static void PCD_HS_EP_OutSetupPacket_int(PCD_HS_HandleTypeDef *hpcd, uint32_t epnum) +{ + uint32_t DoepintReg = USB_HS_OUTEP(epnum)->DOEPINT; + + if ((DoepintReg & OTG_HS_DOEPINT_STPKRE) == OTG_HS_DOEPINT_STPKRE) + { + CLEAR_OUT_EP_INTR(epnum, OTG_HS_DOEPINT_STPKRE); + } + + /* Inform the upper layer that a setup packet is available */ + PCD_HS_SetupStageCallback(hpcd); + +} +#endif /* defined (USB_OTG_HS) */ + +/** + * @} + */ + + +#endif /* defined (USB_OTG_HS) */ +#endif /* PCD_MODULE_ENABLED */ + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pwr.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pwr.c new file mode 100644 index 00000000000..ab45da17394 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_pwr.c @@ -0,0 +1,575 @@ +/** + ****************************************************************************** + * @file ft32f4xx_pwr.c + * @author Rwang + * @brief This file provides firmware functions to manage the following + * functionalities of the Power Controller (PWR) peripheral: + * + Backup Domain Access + * + PVD configuration + * + WakeUp pins configuration + * + Low Power modes configuration + * + Flags management + * + Vbat charge configuration + * @version V1.0.0 + * @data 2025-03-24 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_pwr.h" +#include "ft32f4xx_rcc.h" + + +/* ------------------ PWR registers bit mask ------------------------ */ + +/* CR register bit mask */ +#define CR_VBRS_MASK ((uint32_t)0x00080000) +#define CR_VOS_MASK ((uint32_t)0x00006000) +#define CR_PLSR_MASK ((uint32_t)0x00000E00) +#define CR_PLSF_MASK ((uint32_t)0x000001C0) +#define SCB_SCR_SLEEPONEXIT ((uint32_t)0x00000002) +#define SCB_SCR_SLEEPDEEP ((uint32_t)0x00000004) + + + +/** + * @brief Deinitializes the PWR peripheral registers to their default reset values. + * @param None + * @retval None + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} +/** + * @} + */ + + +/** + * @brief Enables or disables vbat charge + * @note Vbat will be charge by external resistance + * @param NewState: new state of the access to the Backup domain registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_VbatCharge(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Vbat charge */ + PWR->CR |= PWR_CR_VBE; + } + else + { + /* Disable the Vbat Charge*/ + PWR->CR &= ~PWR_CR_VBE; + } +} +/** + * @} + */ + + +/** + * @brief Configures the Vbat Charge Resistance. + * @param PWR_VbatRes: specifies the Vbat Resistance detection + * This parameter can be one of the following values: + * @arg PWR_Vbat_Charge_5k + * @arg PWR_Vbat_Charge_1point5k + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void PWR_VbatResConfig(uint32_t PWR_VbatRes) +{ + /* Check the parameters */ + assert_param(IS_PWR_VBAT_RES(PWR_VbatRes)); + + /* Set Vbrs and Vbrs bit according to PWR_VbatRes value */ + if (PWR_VbatRes == PWR_Vbat_Charge_5k) + { + PWR->CR &= ~PWR_CR_VBRS; + } + else + { + PWR->CR |= PWR_CR_VBRS; + } +} +/** + * @} + */ + + +/** + * @brief Configures the Main Voltage Regulator. + * @param PWR_VOSLevel: specifies the Main Voltage Regulator detection + * This parameter can be one of the following values: + * @arg PWR_VosLevel_0 + * @arg PWR_VosLevel_1 + * @arg PWR_VosLevel_2 + * @arg PWR_VosLevel_3 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection level. + * @retval None + */ +void PWR_VosLevelConfig(uint32_t PWR_VosLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_VOS_LEVEL(PWR_VosLevel)); + + tmpreg = PWR->CR; + + /* Clear vos bits */ + tmpreg &= ~CR_VOS_MASK; + + /* Set vos and vos bits according to PWR_VosLevel value */ + tmpreg |= PWR_VosLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} +/** + * @} + */ + + +/** + * @brief Enables or disables access to the Backup domain registers. + * @note If the HSE divided by 32 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @param NewState: new state of the access to the Backup domain registers. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Backup Domain Access */ + PWR->CR |= PWR_CR_DBP; + } + else + { + /* Disable the Backup Domain Access */ + PWR->CR &= ~PWR_CR_DBP; + } +} +/** + * @} + */ + + +/** + * @brief Enables or disables the Power Voltage Detector(PVD). + * @param NewState: new state of the PVD. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PVDEnable(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the PVD */ + PWR->CR |= PWR_CR_PVDE; + } + else + { + /* Disable the PVD */ + PWR->CR &= ~PWR_CR_PVDE; + } +} +/** + * @} + */ + + +/** + * @brief Configures the rise voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDRLevel: specifies the PVD rise detection level + * This parameter can be one of the following values: + * @arg PWR_PVDRLevel_0 + * @arg PWR_PVDRLevel_1 + * @arg PWR_PVDRLevel_2 + * @arg PWR_PVDRLevel_3 + * @arg PWR_PVDRLevel_4 + * @arg PWR_PVDRLevel_5 + * @arg PWR_PVDRLevel_6 + * @arg PWR_PVDRLevel_7 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection rise level. + * @retval None + */ +void PWR_PVDRLevelConfig(uint32_t PWR_PVDRLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVDR_LEVEL(PWR_PVDRLevel)); + + tmpreg = PWR->CR; + + /* Clear PVDR bits */ + tmpreg &= ~CR_PLSR_MASK; + + /* Set PVDR and PVDR bits according to PWR_PVDRLevel value */ + tmpreg |= PWR_PVDRLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} +/** + * @} + */ + + +/** + * @brief Configures the fall voltage threshold detected by the Power Voltage Detector(PVD). + * @param PWR_PVDRLevel: specifies the PVD fall detection level + * This parameter can be one of the following values: + * @arg PWR_PVDFLevel_0 + * @arg PWR_PVDFLevel_1 + * @arg PWR_PVDFLevel_2 + * @arg PWR_PVDFLevel_3 + * @arg PWR_PVDFLevel_4 + * @arg PWR_PVDFLevel_5 + * @arg PWR_PVDFLevel_6 + * @arg PWR_PVDFLevel_7 + * @note Refer to the electrical characteristics of your device datasheet for + * more details about the voltage threshold corresponding to each + * detection fall level. + * @retval None + */ +void PWR_PVDFLevelConfig(uint32_t PWR_PVDFLevel) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_PWR_PVDF_LEVEL(PWR_PVDFLevel)); + + tmpreg = PWR->CR; + + /* Clear PVDF bits */ + tmpreg &= ~CR_PLSF_MASK; + + /* Set PVDF and PVDF bits according to PWR_PVDFLevel value */ + tmpreg |= PWR_PVDFLevel; + + /* Store the new value */ + PWR->CR = tmpreg; +} +/** + * @} + */ + + +/** + * @brief Enables or Disable the Power Off Reset in standby(Pdroff). + * @param NewState: new state of the Pdroff. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_PdroffEnable(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Disable the PDR in standby*/ + PWR->CR |= PWR_CR_PDROFF; + } + else + { + /* Enable the PVD in standby*/ + PWR->CR &= ~PWR_CR_PDROFF; + } +} +/** + * @} + */ + + +/** + * @brief Enables or disables the WakeUp Pin functionality. + * @param PWR_WakeUpPin: specifies the WakeUpPin. + * This parameter can be one of the following values + * @arg PWR_WakeUpPin_1 + * @arg PWR_WakeUpPin_2 + * @arg PWR_WakeUpPin_3 + * @param NewState: new state of the WakeUp Pin functionality. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the EWUPx pin */ + PWR->CSR |= PWR_WakeUpPin; + } + else + { + /* Disable the EWUPx pin */ + PWR->CSR &= ~PWR_WakeUpPin; + } +} +/** + * @} + */ + + +/** + * @brief Enables or Disable the Backup Regulator Enable(BRE). + * @param NewState: new state of the Bre. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void PWR_BreEnable(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Backup Regulator*/ + PWR->CSR |= PWR_CSR_BRE; + } + else + { + /* Disable the Backup Regulator*/ + PWR->CSR &= ~PWR_CSR_BRE; + } +} +/** + * @} + */ + + +/** + * @brief Enters Sleep mode. + * @note In Sleep mode, all I/O pins keep the same state as in Run mode. + * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_SleepEntry_WFI: enter SLEEP mode with WFI instruction + * @arg PWR_SleepEntry_WFE: enter SLEEP mode with WFE instruction + * @arg PWR_SleepEntry_SLEEPONEXIT: enter SLEEP mode while mcu exit the lowest priority interrupt + * @retval None + */ +void PWR_EnterSleepMode(uint8_t PWR_SleepEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_SLEEP_ENTRY(PWR_SleepEntry)); + + /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP; + + /* Select SLEEP mode entry */ + if (PWR_SleepEntry == PWR_SleepEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else if (PWR_SleepEntry == PWR_SleepEntry_WFE) + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + else if (PWR_SleepEntry == PWR_SleepEntry_SLEEPONEXIT) + { + /* Set SLEEP on exit bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPONEXIT; + } +} + +/** + * @brief Enters STOP mode. + * @note In Stop mode, all I/O pins keep the same state as in Run mode. + * @note When exiting Stop mode by issuing an interrupt or a wakeup event, + * the HSI RC oscillator is selected as system clock. + * @note When the voltage regulator operates in low power mode, an additional + * startup delay is incurred when waking up from Stop mode. + * By keeping the internal regulator ON during Stop mode, the consumption + * is higher although the startup time is reduced. + * @param PWR_Regulator: specifies the regulator state in STOP mode. + * This parameter can be one of the following values: + * @arg PWR_Regulator_ON: STOP mode with regulator ON + * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode + * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_StopEntry_WFI: enter STOP mode with WFI instruction + * @arg PWR_StopEntry_WFE: enter STOP mode with WFE instruction + * @retval None + */ +void PWR_EnterStopMode(uint32_t PWR_Regulator, uint8_t PWR_StopEntry) +{ + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(PWR_Regulator)); + assert_param(IS_PWR_STOP_ENTRY(PWR_StopEntry)); + + /* Select Regulator status in stop mode */ + if (PWR_Regulator == PWR_Regulator_ON) + { + /* Clear LPDS bit make Regulator open in stop mode */ + PWR->CR &= ~PWR_CR_LPDS; + } + else if (PWR_Regulator == PWR_Regulator_LowPower) + { + /* Set LPDS bit make Regulator Lowerpower in stop mode */ + PWR->CR |= PWR_CR_LPDS; + } + + /* Select STOP mode entry */ + if (PWR_StopEntry == PWR_StopEntry_WFI) + { + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + /* Request Wait For Interrupt */ + __WFI(); + } + else if (PWR_StopEntry == PWR_StopEntry_WFE) + { + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** + * @brief Enters STANDBY mode. + * @note In Standby mode, all I/O pins are high impedance except for: + * - Reset pad (still available) + * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper, + * time-stamp, RTC Alarm out, or RTC clock calibration out. + * - WKUP pin 1 (PA0) if enabled. + * @param PWR_StandbyEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * This parameter can be one of the following values: + * @arg PWR_StandbyEntry_WFI: enter STANDBY mode with WFI instruction + * @arg PWR_StandbyEntry_WFE: enter STANDBY mode with WFE instruction + * @note The Wakeup flag (WUF) need to be cleared at application level before to call this function + * @param None + * @retval None + */ +void PWR_EnterStandbyMode(uint8_t PWR_StandbyEntry) +{ + assert_param(IS_PWR_STANDBY_ENTRY(PWR_StandbyEntry)); + + /* Select STANDBY mode */ + PWR->CR |= PWR_CR_PDDS; + + /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select Standby mode entry */ + if (PWR_StandbyEntry == PWR_StandbyEntry_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else if (PWR_StandbyEntry == PWR_StandbyEntry_WFE) + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} +/** + * @} + */ + +/** + * @brief Checks whether the specified PWR flag is set or not. + * @param PWR_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup + * event was received from the WKUP pin or from the RTC alarm + * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event + * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the + * system was resumed from Standby mode + * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD + * is enabled by the PWR_PVDEnable() function. + * @arg PWR_FLAG_BRR: Backup regulator ready. This flag is valid + * only if BRE is enabled by the PWR_BreEnable() function. + * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag + * This flag indicates the state of the internal voltage + * reference, VREFINT. + * @retval The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); + + if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + /* Return the flag status */ + return bitstatus; +} +/** + * @} + */ + + +/** + * @brief Clears the PWR's pending flags. + * @param PWR_FLAG: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg PWR_FLAG_CWU: Wake Up flag + * @arg PWR_FLAG_CSB: StandBy flag + * @retval None + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + /* Check the parameters */ + assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); + + if (PWR_FLAG == PWR_FLAG_CWU) + { + /*clear wkup flag*/ + PWR->CR |= PWR_FLAG_CWU; + } + else if (PWR_FLAG == PWR_FLAG_CWU) + { + /*clare standby flag*/ + PWR->CR |= PWR_FLAG_CSB; + } +} +/** + * @} + */ + + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_qspi.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_qspi.c new file mode 100644 index 00000000000..b42c1181952 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_qspi.c @@ -0,0 +1,1047 @@ +/** + ****************************************************************************** + * @file ft32f4xx_qspi.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (QSPI): + * + Initialization and Configuration + * + Data transfers functions + * + DMA transfers management + * + XIP transfer management + * + XIP transfer management + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_qspi.h" +#include "ft32f4xx_rcc.h" + +/* QSPI registers Masks */ +#define CTRLR0_CLEAR_MASK ((uint32_t)0x00c04fc0) +#define SPI_CTRLR0_CLEAR_MASK ((uint32_t)0x0c03033f) +/** + * @brief Deinitializes the QSPI peripheral registers to their default + * reset values. + */ +void QSPI_DeInit(void) +{ + + /* Enable QSPI reset state */ + RCC_AHB3PeriphResetCmd(RCC_AHB3Periph_QSPI, ENABLE); + /* Release QSPI from reset state */ + RCC_AHB3PeriphResetCmd(RCC_AHB3Periph_QSPI, DISABLE); +} + +/** + * @brief Fills each QSPI_InitStruct member with its default value. + * @param QSPI_InitStruct: pointer to a QSPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void QSPI_StructInit(QSPI_InitTypeDef *QSPI_InitStruct) +{ + /*--------------- Reset QSPI init structure parameters values -----------------*/ + /* Initialize the QSPI_Protocol member */ + QSPI_InitStruct->QSPI_Protocol = QSPI_PROTOCOL_SPI; + /* Initialize the QSPI_Direction member */ + QSPI_InitStruct->QSPI_Direction = QSPI_DIRECTION_Tx_ONLY; + /* Initialize the QSPI_SSTE member */ + QSPI_InitStruct->QSPI_SSTE = QSPI_SSTE_TOGGLE_DIS; + /* Initialize the QSPI_DataSize member */ + QSPI_InitStruct->QSPI_DataSize = QSPI_DATASIZE_8B; + /* Initialize the QSPI_SCPOL member */ + QSPI_InitStruct->QSPI_SCPOL = QSPI_SCPOL_LOW; + /* Initialize the QSPI_SCPHA member */ + QSPI_InitStruct->QSPI_SCPHA = QSPI_SCPHA_1EDGE; + /* Initialize the QSPI_SER member */ + QSPI_InitStruct->QSPI_SER = QSPI_NCS0; + /* Initialize the QSPI_Chio select min time member */ + QSPI_InitStruct->QSPI_CS_MIN_HIGH = 0; + /*Initialize the DataMode member*/ + QSPI_InitStruct->QSPI_DataMode = QSPI_STANDARD; + +} + + +/** + * @brief Initializes the QSPI peripheral according to the specified + * parameters in the QSPI_InitStruct. + * @param QSPI_InitStruct: pointer to a QSPI_InitTypeDef structure that + * contains the configuration information for the specified QSPI peripheral. + * Br: specifies the baundrate. Br can be the value between 0x0~0x7FFF. + * @retval None + */ +void QSPI_Init(QSPI_InitTypeDef *QSPI_InitStruct, uint16_t Br) +{ + uint32_t tmpreg = 0; + + /* Check the QSPI parameters */ + assert_param(IS_QSPI_PROPTOCOL(QSPI_InitStruct->QSPI_Protocol)); + assert_param(IS_QSPI_DIRECTION_MODE(QSPI_InitStruct->QSPI_Direction)); + assert_param(IS_QSPI_SSTE(QSPI_InitStruct->QSPI_SSTE)); + assert_param(IS_QSPI_DATA_SIZE(QSPI_InitStruct->QSPI_DataSize)); + assert_param(IS_QSPI_SCPOL(QSPI_InitStruct->QSPI_SCPOL)); + assert_param(IS_QSPI_SCPHA(QSPI_InitStruct->QSPI_SCPHA)); + assert_param(IS_QSPI_SER_SEL(QSPI_InitStruct->QSPI_SER)); + assert_param(IS_QSPI_DATA_MODE(QSPI_InitStruct->QSPI_DataMode)); + + /*---------------------------- QSPI CTRLR0 Configuration ------------------------*/ + /* Get the QSPI CTRLR0 value */ + tmpreg = QSPI->CTRLR0; + /* Clear CLK_LOOP_EN,SPI_FRF,SSTE,SRL,TMOD,SCPOL,SCPHA,FRF,DFS bits */ + tmpreg &= ~CTRLR0_CLEAR_MASK; + /* Configure QSPI: Protocol,Direction,SSTE,DataSize,SCPOL,SCPHA,SER,SRL*/ + /* Set SPI_FRF bits according to QSPI_Protocol value,select SPI/SSP/MICROWIRE proptocol */ + /* Set TMOD bit according to QSPI_Direction values,include txrx tx rx*/ + /* Set SSTE bit according to QSPI_SSTE value */ + /* Set SCPOL bit according to QSPI_SCPOL value */ + /* Set SCPHA bit according to QSPI_SCPHA value */ + + /* Set DataSize according to QSPI_DataSize value,DataSize value must >= 'h11*/ + tmpreg = (uint32_t)((uint32_t)QSPI_InitStruct->QSPI_DataSize); + tmpreg |= (uint32_t)((uint32_t)QSPI_InitStruct->QSPI_Protocol | QSPI_InitStruct->QSPI_Direction | + QSPI_InitStruct->QSPI_SSTE | QSPI_InitStruct->QSPI_SCPOL | + QSPI_InitStruct->QSPI_SCPHA | QSPI_InitStruct->QSPI_SER | + QSPI_InitStruct->QSPI_DataMode); + /* Write to QSPI CTRLR0 */ + QSPI->CTRLR0 = tmpreg; + + /*-------------------------QSPI SER Configuration -----------------------*/ + /* Get the QSPI SER value */ + tmpreg = QSPI->SER; + /* Clear SER[1:0] bits */ + tmpreg &= (uint32_t)~QSPI_SER_SER; + /* Configure QSPI: NCSx select */ + tmpreg |= (uint32_t)(QSPI_InitStruct->QSPI_SER); + /* Write to QSPI SER */ + QSPI->SER = tmpreg; + + /*---------------------------- QSPI BAUDR Configuration --------------------*/ + /* Clear SCKDV[14:0] */ + QSPI->BAUDR = 0; + QSPI->BAUDR = Br << 1; + + /*---------------------------- QSPI SPI_CTRLR1 Configuration ------------------------*/ + /* Get the QSPI SPI_CTRLR1 value */ + tmpreg = QSPI->SPI_CTRLR1; + /* Clear CS_MIN_HIGH bit */ + tmpreg &= ~0xf0000; + /* Configure CS_MIN_HIGH bit */ + tmpreg |= (uint32_t)((uint32_t)QSPI_InitStruct->QSPI_CS_MIN_HIGH) ; + /* Write to QSPI SPI_CTRLR1 */ + QSPI->SPI_CTRLR1 = tmpreg << 16; +} + +/** + * @brief Initializes the QSPI peripheral according to the specified + * parameters in the QSPI_CommandStruct. + * @param QSPI_CommandStruct: pointer to a QSPI_CommandTypeDef structure that + * contains the configuration information for the specified QSPI peripheral. + * @retval None + */ + +/** + * @brief Enables or disables the Testing Mode for QSPI. + * @retval None + */ + +void QSPI_TestMode_Enable(FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable test mode */ + QSPI->CTRLR0 |= QSPI_TESTING_MODE ; + } + else + { + /* Disable test mode*/ + QSPI->CTRLR0 &= ~QSPI_TESTING_MODE ; + } +} + +/** + * @brief Config MicroWire Mode for QSPI. + * @param MHS: specifies the MICROWIRE handshake enable or disable. + * This parameter can be any combination of the following values: + * @arg QSPI_MICROHAND_DIS: handshake disable; + * @arg QSPI_MICROHAND_EN: handshake enable; + * MDD: specifies the MICROWIRE transfer direction. + * This parameter can be any combination of the following values: + * @arg QSPI_MICRODIR_Rx: receive data; + * @arg QSPI_MICRODIR_Tx: transmit data; + * MWMOD: specifies the MICROWIRE transfer mode. + * This parameter can be any combination of the following values: + * @arg QSPI_MICROTRANS_NSEQ: nosequence transfer; + * @arg QSPI_MICROTRANS_SEQ: sequence trnsfer; + * FrameSize: specifies the control frame size. + * This parameter can be any combination of the following values: + * @arg QSPI_CFS_1B: cfs 1 bit; + * @arg QSPI_CFS_2B: cfs 2 bit; + * ...... ...... + * @arg QSPI_CFS_15B: cfs 15 bit; + * @arg QSPI_CFS_16B: cfs 16 bit; + + * @retval None + */ + +void QSPI_MicroWireMode_Config(uint32_t MHS, uint32_t MDD, uint32_t MWMOD, uint32_t FrameSize, FunctionalState NewState) +{ + + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Get the QSPI MWCR value */ + tmpreg = QSPI->MWCR; + /* Clear the MWMOD,MDD,MHS*/ + tmpreg &= ~0x7; + /* Set the MWMOD,MDD,MHS*/ + tmpreg |= MHS | MDD | MWMOD; + /* Write the QSPI MWCR register*/ + QSPI->MWCR = tmpreg ; + + /* Get the QSPI CTRLR0 value */ + tmpreg = QSPI->CTRLR0 ; + /* Clear the CFS,FRF value */ + tmpreg &= ~(0xf << 16 | QSPI_CTRLR0_FRF); + /*Set the CFS,FRF bits */ + tmpreg |= (FrameSize | QSPI_PROTOCOL_MICROWIRE); + /* Write the CFS,FRF bits in CTRLR0 */ + QSPI->CTRLR0 |= tmpreg ; + } + else + { + /* Disable the MICROWIRE mode for the selected QSPI peripheral */ + QSPI->CTRLR0 &= ~QSPI_CTRLR0_FRF ; + } +} + +/** + * @brief Enables or disables the specified QSPI peripheral. + * @param NewState: new state of the QSPI peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void QSPI_EnCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected QSPI peripheral */ + QSPI->SSIENR |= QSPI_SSIENR_SSIC_EN; + } + else + { + /* Disable the selected QSPI peripheral */ + QSPI->SSIENR &= ~QSPI_SSIENR_SSIC_EN; + } +} + +/** + * @brief Enables or disables the TI Mode. + * + * @note This function can be called only after the QSPI_Init() function has + * been called. + * + * @param NewState: new state of the selected QSPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void QSPI_TIModeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected QSPI peripheral */ + QSPI->CTRLR0 &= (uint32_t)~((uint32_t)QSPI_CTRLR0_FRF); + QSPI->CTRLR0 |= (QSPI_CTRLR0_FRF & 1 << 6); + } + else + { + /* Disable the TI mode for the selected QSPI peripheral */ + QSPI->CTRLR0 &= (uint32_t)~((uint32_t)QSPI_CTRLR0_FRF); + } +} +/** + * @brief Configures the data size for the selected QSPI. + * @param QSPI_DataSize: specifies the QSPI data size. + * For the QSPI peripheral this parameter can be one of the following values: + * @arg QSPI_DATASIZE_4B: Set data size to 4 bits + * @arg QSPI_DATASIZE_5B: Set data size to 5 bits + * @arg QSPI_DATASIZE_6B: Set data size to 6 bits + * ...... ...... + * @arg QSPI_DATASIZE_30B: Set data size to 30 bits + * @arg QSPI_DATASIZE_31B: Set data size to 31 bits + * @arg QSPI_DATASIZE_32B: Set data size to 32 bits + * @retval None + */ +void QSPI_DataSizeConfig(uint16_t QSPI_DataSize) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_QSPI_DATA_SIZE(QSPI_DataSize)); + if (QSPI_DataSize >= 3) + { + /* Read the CTRLR0 register */ + tmpreg = QSPI->CTRLR0; + /* Clear DFD[4:0] bits */ + tmpreg &= ~0x1f; + /* Set new DS[3:0] bits value */ + tmpreg = QSPI_DataSize | tmpreg; + QSPI->CTRLR0 = tmpreg; + } + else + { + // printf("ERROR ! QSPI DATA SIZE CAN NOT BE LESS THAN 4BITS!!! \n"); + } +} + +/** + * @brief Configures the number of data frames. + * @param QSPI_NDF: specifies the NDF value. + * @retval None + */ +void QSPI_DataNumberConfig(uint32_t QSPI_NDF) +{ + /* Check the parameters */ + assert_param(IS_QSPI_DATANUMBER(QSPI_NDF)); + + /* Set new NDF bits value */ + QSPI->CTRLR1 = QSPI_NDF ; +} +/** + * @brief Configures the FIFO reception threshold for the selected QSPI. + * @param QSPI_RxFIFOThreshold: specifies the FIFO reception threshold. + * @retval None + */ +void QSPI_RxFIFOThresholdConfig(uint16_t QSPI_RxFIFOThreshold) +{ + /* Check the parameters */ + assert_param(IS_QSPI_RX_FIFO_THRESHOLD(QSPI_RxFIFOThreshold)); + + /* Clear RFT bit */ + QSPI->RXFTLR &= ~QSPI_RXFTLR_RFT; + + /* Set new RFT bit value */ + QSPI->RXFTLR |= QSPI_RxFIFOThreshold; +} + +/** + * @brief Configures the FIFO transmition threshold for the selected QSPI. + * @param QSPI_TxFIFOThreshold: specifies the FIFO transmition threshold. + * @param QSPI_TxFIFOStart: specifies the FIFO transfer start interrupt level. + * @retval None + */ +void QSPI_TxFIFOThresholdConfig(uint16_t QSPI_TxFIFOStart, uint16_t QSPI_TxFIFOThreshold) +{ + /* Check the parameters */ + assert_param(IS_QSPI_TX_FIFO_THRESHOLD(QSPI_TxFIFOThreshold)); + assert_param(IS_QSPI_TX_FIFO_STARTLEVEL(QSPI_TxFIFOStart)); + + /* Clear TXFTHR TFT bit */ + QSPI->TXFTLR &= ~(QSPI_TXFTLR_TFT | QSPI_TXFTLR_TXFTHR); + + /* Set new TXFTHR TFT bit value */ + QSPI->TXFTLR |= (QSPI_TxFIFOStart << 16 | QSPI_TxFIFOThreshold); +} + +/** + * @brief Enables or disables the slave select toggle mode. + * @note This bits only can be set when SCPH = 0. + * @param NewState: new state of the NSS pulse management mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void QSPI_SSTEModeCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the NSS pulse management mode */ + QSPI->CTRLR0 |= QSPI_CTRLR0_SSTE; + } + else + { + /* Disable the NSS pulse management mode */ + QSPI->CTRLR0 &= ~QSPI_CTRLR0_SSTE; + } +} + +/** + * @} + */ +/** + * @brief Transmits a Data through the QSPI peripheral. + * @param Data: Data to be transmitted. + * @retval None + */ +void QSPI_SendData(uint32_t Data) +{ + + QSPI->DR[0] = (uint32_t)Data; +} + +/** + * @brief Returns the most recent received data by the QSPI peripheral. + * @retval The value of the received data. + */ +uint32_t QSPI_ReceiveData(void) +{ + uint32_t qspixbase = 0x00; + + qspixbase = (uint32_t)QSPI; + qspixbase += 0x60; + + return *(__IO uint32_t *) qspixbase; +} + +/** + * @brief Config the QSPI SPI frame format. + * @param LINE: specifies the QSPI line numbers. + * This parameter can be any combination of the following values: + * @arg QSPI_STANDARD: single line; + * @arg QSPI_DUAL: dual line; + * @arg QSPI_QUAD: quad line. + * @retval None + */ +void QSPI_LineCfg(uint32_t LINE) +{ + /* Check the parameters */ + assert_param(IS_QSPI_DATA_MODE(LINE)); + + /* Clear the SPI_FRF bits*/ + QSPI->CTRLR0 &= ~QSPI_CTRLR0_SPI_FRF ; + /* Set the SPI_FRF bits*/ + QSPI->CTRLR0 |= LINE; +} + +/** + * @brief Config the QSPI transfer mode. + * @param TRANS: specifies the QSPI transfer mode. + * This parameter can be any combination of the following values: + * @arg QSPI_DIRECTION_Tx_AND_Rx: txrx mode; + * @arg QSPI_DIRECTION_Tx_ONLY: tx only mode; + * @arg QSPI_DIRECTION_Rx_ONLY: rx only mode; + * @arg QSPI_DIRECTION_EEPROM_READ: eeprom read mode. + * @retval None + */ + +void QSPI_TransMode(uint32_t TRANS) +{ + /* Check the parameters */ + assert_param(IS_QSPI_DIRECTION_MODE(TRANS)); + + /* Clear the TMOD bits*/ + QSPI->CTRLR0 &= ~QSPI_CTRLR0_TMOD ; + /* Set the TMOD bits*/ + QSPI->CTRLR0 |= TRANS ; +} + +/** + * @brief Config QSPI waitcycles. + * @param NUMBER: specifies the QSPI number of waitcycles. + * This parameter can be less than 0x1f: + * @retval None + */ +void QSPI_WaitCyclesConfig(uint32_t NUMBER) +{ + + /* Check the parameters */ + assert_param(IS_QSPI_WAITCYCLES(NUMBER)); + + /* Clear the WAIT_CYCLES bits*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_WAIT_CYCLES; + /* Set the WAIT_CYCLES bits*/ + QSPI->SPI_CTRLR0 |= NUMBER << 11 ; + +} + +/** + * @brief Config QSPI waitcycles. + * @param TRANSTYPE: specifies the number of instruction and addr phase lane. + * This parameter can be any combination of the following values: + * @arg QSPI_TRANSTYPE_STAND : both instruction and addr work in standard mode + * @arg QSPI_TRANSTYPE_MIX : instruction works in standard,addr works in the SPI mode selected in the SPI_FRF filed + * @arg QSPI_TRANSTYPE_FRF : both instruction and addr work in the SPI mode selected in the SPI_FRF filed + * @retval None + */ +void QSPI_TransTypeConfig(uint32_t TRANSTYPE) +{ + + /* Check the parameters */ + assert_param(IS_QSPI_TRANSTYPE(TRANSTYPE)); + + /* Clear the TRANS_TYPE bits*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_TRANS_TYPE; + /* Set the TRANS_TYPE bits*/ + QSPI->SPI_CTRLR0 |= TRANSTYPE ; + +} + +/** + * @} + */ +/** + * @brief Enables or disables the QSPI DMA interface. + * @param QSPI_MAReq: specifies the QSPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg QSPI_DMAReq_Tx: Tx buffer DMA transfer request + * @arg QSPI_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected QSPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void QSPI_DMACmd(uint32_t QSPI_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_QSPI_DMA_REQ(QSPI_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected QSPI DMA requests */ + QSPI->DMACR |= QSPI_DMAReq; + } + else + { + /* Disable the selected QSPI DMA requests */ + QSPI->DMACR &= (uint32_t)~QSPI_DMAReq; + } +} + +/** + * @brief Config the DMA Tx data level. + * @param QSPI_DMATxDLevel: specifies the QSPI DMA Tx data level. + * This parameter can be less than 0xF. + * @retval None + */ + +void QSPI_DMA_Tx_DATALEVELCmd(uint32_t QSPI_DMATxDLevel) +{ + /* Check the parameters */ + assert_param(IS_QSPI_DMA_TX_DATA_LEVEL(QSPI_DMATxDLevel)); + + /* Config the QSPI DMA Txdata level */ + QSPI->DMATDLR = QSPI_DMATxDLevel; + +} + +/** + * @brief Config the DMA Rx data level. + * @param QSPI_DMARxDLevel: specifies the QSPI DMA Rx data level. + * This parameter can be less than 0xF. + * @retval None + */ + +void QSPI_DMA_Rx_DATALEVELCmd(uint32_t QSPI_DMARxDLevel) +{ + /* Check the parameters */ + assert_param(IS_QSPI_DMA_RX_DATA_LEVEL(QSPI_DMARxDLevel)); + + /* Config the QSPI DMA Rxdata level */ + QSPI->DMARDLR = QSPI_DMARxDLevel; + +} + + +/** + * @} + */ + +/** + * @brief Enables or disables the QSPI XIP instruction phase. + * @param NewState: new state of the selected QSPI instruction phase. + * This parameter can be: ENABLE or DISABLE. + * INST_L specifies the QSPI instruction phase length. + * This parameter can be one of the following values: + * QSPI_INSTRUCTION_0B: instruction 0 bits. + * QSPI_INSTRUCTION_4B: instruction 4 bits. + * QSPI_INSTRUCTION_8B: instruction 8 bits. + * QSPI_INSTRUCTION_16B: instruction 16 bits. + * @note Write SPI_CTRLR0 register must clear SSIENR bit. + * Normal mode instruction enable: INST_L != 0. + * XIP mode enable: (INST_L != 0) && (XIP_INST_EN == 1) + * @retval None + */ +void QSPI_XIP_INSTCmd(uint32_t INSTRUCTION_L, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_QSPI_XIP_INST(QSPI_INSTCfg)); + + if (NewState != DISABLE) + { + /* Clear the INST_L*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_INST_L ; + /* Config instruction length and enable*/ + QSPI->SPI_CTRLR0 |= INSTRUCTION_L | QSPI_SPI_CTRLR0_XIP_INST_EN; + + } + else + { + /* Clear INST_L and XIP_INST_EN bits*/ + QSPI->SPI_CTRLR0 &= ~(QSPI_SPI_CTRLR0_INST_L | QSPI_SPI_CTRLR0_XIP_INST_EN); + } +} + + +/** + * @brief Config the QSPI XIP instruction opcode. + * @param QSPI_XIP_INSTCfg: specifies the QSPI XIP mode instruction . + * This parameter can be less than 0xFFFF. + * @retval None + */ + +void QSPI_XIP_INST_Config(uint32_t QSPI_XIP_INSTCfg) +{ + /* Set mode bit phase*/ + QSPI->XIP_INCR_INST = QSPI_XIP_INSTCfg ; +} + +/** + * @brief Enables or disables the QSPI ADDR phase. + * @note Write SPI_CTRLR0 register must clear SSIENR bit. + * ADDR_L specifies the QSPI addr phase length. + * This parameter can be one of the following values: + * QSPI_ADDRESS_0B: addr length 0 bits. + * QSPI_ADDRESS_4B: addr length 4 bits. + * ...... ...... + * QSPI_ADDRESS_56B: addr length 56 bits. + * QSPI_ADDRESS_60B: addr length 60 bits. + * @retval None + */ +void QSPI_ADDRCfg(uint32_t ADDR_L) +{ + /* Check the parameters */ + assert_param(IS_QSPI_ADDRESSSIZE(ADDR_L)); + + /* Clear ADDR_L bits*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_ADDR_L; + /* Config ADDR_L bits*/ + QSPI->SPI_CTRLR0 |= ADDR_L; +} + +/** + * @brief Enables or disables the QSPI XIP mode bits . + * @param NewState: new state of the QSPI mode bits phase. + * This parameter can be: ENABLE or DISABLE. + * MODEBITS: specifies the QSPI XIP mode bits . + * This parameter can be less than 0xFFFF. + * MD_SIZE: specifies the QSPI mode bits length. + * This parameter can be one of the following values: + * QSPI_MODEBITS_2B: modebits length equal to 2 bits. + * QSPI_MODEBITS_4B: modebits length equal to 4 bits. + * QSPI_MODEBITS_8B: modebits length equal to 8 bits. + * QSPI_MODEBITS_16B: modebits length equal to 16 bits. + * @retval None + */ + +void QSPI_XIP_ModeBitsCmd(uint32_t MODEBITS, uint32_t MD_SIZE, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_QSPI_MODEBITSSIZE(MD_SIZE)); + assert_param(IS_QSPI_XIP_MODEBITS(MODEBITS)); + + if (NewState != DISABLE) + { + /* Clear XIP_MBL bits*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_XIP_MBL ; + /* Set XIP_MD_BIT_EN , XIP_MBL bits*/ + QSPI->SPI_CTRLR0 |= QSPI_SPI_CTRLR0_XIP_MD_BIT_EN | MD_SIZE; + /* Config XIP mode bits*/ + QSPI->XIP_MODE_BITS = MODEBITS; + } + else + { + /* Clear XIP_MD_BIT_EN bit*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_XIP_MD_BIT_EN ; + } +} + + +/** + * @brief Enables or disables the QSPI data/addr phase ddr mode . + * @param NewState: new state of the QSPI data/addr phase ddr mode. + * This parameter can be: ENABLE or DISABLE. + * Ddr_TXD: specifies the DDR mode driveing edge of transmit data. + * This parameter can be less than 0xFF. + * @retval None + */ + +void QSPI_Ddrcmd(uint32_t Ddr_TXD, FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_QSPI_DDR_DRIVE_EDGE(Ddr_TXD)); + if (NewState != DISABLE) + { + /* Set the SPI_DDR_EN bit*/ + QSPI->SPI_CTRLR0 |= QSPI_SPI_CTRLR0_SPI_DDR_EN ; + /* Set the TDE bit*/ + QSPI->DDR_DRIVE_EDGE = Ddr_TXD ; + } + else + { + /* Clear the SPI_DDR_EN bit*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_SPI_DDR_EN ; + /* Clear the TDE bit*/ + QSPI->DDR_DRIVE_EDGE = 0 ; + } + +} + +/** + * @brief Enables or disables the QSPI instruction phase ddr mode . + * @param NewState: new state of the QSPI instruction phase ddr mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void QSPI_InstDdrcmd(FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the INST_DDR_EN bit*/ + QSPI->SPI_CTRLR0 |= QSPI_SPI_CTRLR0_INST_DDR_EN ; + } + else + { + /* Clear the INST_DDR_EN bit*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_INST_DDR_EN ; + } + +} + +/** + * @brief Enables or disables the QSPI XIP continous transfer . + * @param NewState: new state of the QSPI XIP continous transfer. + * This parameter can be: ENABLE or DISABLE. + * TIMOUT: specifies the XIP time out value in terms of hclk. + * This parameter can be less than 0xFF. + * @retval None + */ + +void QSPI_XIP_ContinuousCmd(uint32_t TIMOUT, FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_QSPI_XIP_TIMOUT(TIMOUT)); + + if (NewState != DISABLE) + { + /* Set the SSIC_XIP_CONT_XFER_EN bit*/ + QSPI->SPI_CTRLR0 |= QSPI_SPI_CTRLR0_SSIC_XIP_CONT_XFER_EN; + /* Set the XIP_CNT_TIME_OUT */ + QSPI->XIP_CNT_TIME_OUT = TIMOUT ; + } + else + { + /* Clear the SSIC_XIP_CONT_XFER_EN bit*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_SSIC_XIP_CONT_XFER_EN; + } +} + + +/** + * @brief Enables or disables the QSPI XIP DFS Fix . + * @param NewState: new state of the QSPI XIP DFS fix. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void QSPI_XIP_DFSHCCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the XIP_DFS_HC bit*/ + QSPI->SPI_CTRLR0 |= QSPI_SPI_CTRLR0_XIP_DFS_HC; + } + else + { + /* Clear the XIP_DFS_HC bit*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_XIP_DFS_HC; + } + +} +/** + * @brief Enables or disables the QSPI CLK_LOOP_BACK MODE . + * @param NewState: new state of the QSPI clk loop back mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void QSPI_CLK_LOOPCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CLK_LOOP_EN bit*/ + QSPI->CTRLR0 |= QSPI_CTRLR0_CLK_LOOP_EN; + } + else + { + /* Clear the CLK_LOOP_EN bit*/ + QSPI->CTRLR0 &= ~QSPI_CTRLR0_CLK_LOOP_EN; + } + +} +/** + * @brief Config the rx sample delay mode . + * @param SE:specifies the receive data sample edge + * This parameter can be one of the following value: + * @arg QSPI_SAMPLE_NEGEDGE: sample negedge; + * @arg QSPI_SAMPLE_POSEDGE: sample posgedge; + * RSD:specifies the receive data sample delay. + * This parameter can be less than 0xFF . + * @retval None + */ +void QSPI_RX_SAMPLEDLYConfig(uint32_t SE, uint32_t RSD) +{ + + /* Check the parameters */ + assert_param(IS_QSPI_SAMPLE_DLY_EDGE(SE)); + assert_param(IS_QSPI_SAMPLE_DLY(RSD)); + + /* Clear SE and RSD bits*/ + QSPI->RX_SAMPLE_DELAY = 0; + /* Set SE and RSD bits*/ + QSPI->RX_SAMPLE_DELAY = (SE | RSD) ; +} + + +/** + * @brief Enables or disables the QSPI read data strobe mode. + * @param RXDS_VL_EN :specifies enable or disable variable latency mode. + * This parameter can be one of the following value: + * @arg QSPI_VARIABLE_LATEN_DIS: disable variable latency mode; + * @arg QSPI_VARIABLE_LATEN_EN: enable variable latency mode; + * @param NewState: new state of the QSPI read data strobe mod. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void QSPI_RXDSConfig(uint32_t RXDS_VL_EN, FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_QSPI_VL_EN(RXDS_VL_EN)); + + if (NewState != DISABLE) + { + /* Clear the RXDS_VL_EN,SPI_RXDS_EN bit*/ + QSPI->SPI_CTRLR0 &= ~(QSPI_SPI_CTRLR0_SPI_RXDS_EN | QSPI_SPI_CTRLR0_RXDS_VL_EN); + /* Set the RXDS_VL_EN,SPI_RXDS_EN bit*/ + QSPI->SPI_CTRLR0 |= QSPI_SPI_CTRLR0_SPI_RXDS_EN | RXDS_VL_EN ; + } + else + { + /* Clear the SPI_RXDS_EN bit*/ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_SPI_RXDS_EN ; + } +} + +/** + * @brief Enables or disables the clk stretch mode . + * @param NewState: new state of clk stretch mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ + +void QSPI_CLK_StretchCmd(FunctionalState NewState) +{ + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the CLK STRECTH */ + QSPI->SPI_CTRLR0 |= QSPI_SPI_CTRLR0_CLK_STRETCH_EN; + } + else + { + /* Disable the CLK STRECTH */ + QSPI->SPI_CTRLR0 &= ~QSPI_SPI_CTRLR0_CLK_STRETCH_EN; + } +} +/** + * @brief Enables or disables the specified QSPI interrupts. + * @param QSPI_IT: specifies the QSPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg QSPI_IT_TXEIM: Tx buffer empty interrupt mask + * @arg QSPI_IT_TXOIM: Tx buffer overflow interrupt mask + * @arg QSPI_IT_RXUIM: Rx buffer underflow interrupt mask + * @arg QSPI_IT_RXOIM: Rx buffer overflow interrupt mask + * @arg QSPI_IT_RXFIM: Rx buffer full interrupt mask + * @arg QSPI_IT_TXUIM: Tx buffer underflow interrupt mask + * @param NewState: new state of the specified QSPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void QSPI_ITConfig(uint32_t QSPI_IT, FunctionalState NewState) +{ + uint16_t itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_QSPI_CONFIG_IT(QSPI_IT)); + + /* Clear all the interrupt enable*/ + QSPI->IMR = 0 ; + + /* Set the IT mask */ + itmask = QSPI_IT; + + if (NewState != DISABLE) + { + /* Enable the selected QSPI interrupt */ + QSPI->IMR |= itmask; + } + else + { + /* Disable the selected QSPI interrupt */ + QSPI->IMR &= (uint16_t)~itmask; + } +} + +/** + * @brief Returns the current QSPI FIFO status,busy status. + * @retval The status . + * - QSPI_STATE_BUSY: when QSPI is working + * - QSPI_STATE_TFNF: Tx buffer not full. + * - QSPI_STATE_TFE: Tx buffer empty. + * - QSPI_STATE_RFNE: Rx buffer not empty. + * - QSPI_STATE_RFF: Rx buffer full. + */ +uint32_t QSPI_GetStatus(uint16_t QSPI_SR_FLAG) +{ + /* Get the QSPI status */ + return (uint16_t)((QSPI->SR & QSPI_SR_FLAG)); +} + +/** + * @brief Returns the FIFO Interrupt status after mask. + * @retval The Reception FIFO filling state. + * - QSPI_FLAG_TXEIS: Tx FIFO is empty + * - QSPI_FLAG_TXOIS: Tx FIFO is overflow. + * - QSPI_FLAG_RXUIS: Rx FIFO is underflow. + * - QSPI_FLAG_RXOIS: Rx FIFO is overflow. + * - QSPI_FLAG_RXFIS: Rx FIFO is full. + * - QSPI_FLAG_TXUIS: Tx FIFO is underflow. + */ +uint32_t QSPI_GetAfterMaskInterruptStatus(uint16_t QSPI_ISR_FLAG) +{ + /* Get the QSPI interrupt status */ + return (uint32_t)((QSPI->ISR & QSPI_ISR_FLAG)); +} + +/** + * @brief Returns the FIFO Interrupt status before mask. + * @retval The Reception FIFO filling state. + * - QSPI_FLAG_TXEIR: Tx FIFO is empty + * - QSPI_FLAG_TXOIR: Tx FIFO is overflow. + * - QSPI_FLAG_RXUIR: Rx FIFO is underflow. + * - QSPI_FLAG_RXOIR: Rx FIFO is overflow. + * - QSPI_FLAG_RXFIR: Rx FIFO is full. + * - QSPI_FLAG_TXUIR: Tx FIFO is underflow. + */ +uint32_t QSPI_GetBeforeMaskInterruptStatusuint16_t (uint16_t QSPI_RISR_FLAG) +{ + /* Get the QSPI interrupt status */ + return (uint32_t)((QSPI->RISR & QSPI_RISR_FLAG)); +} + + + + +/** + * @brief Clears the QSPI TxFIFO Error flag. + * @retval None + */ +void QSPI_ClearTxFIFOErrorInterrupt(void) +{ + uint32_t data; + + /* Read TXEICR register to Clear the Tx FIFO overflow/underflow interrupt */ + data = QSPI->TXEICR; +} + +/** + * @brief Clears the QSPI RxFIFO overflow interrupt. + * @retval None + */ +void QSPI_ClearRxFIFOOverflowInterrupt(void) +{ + uint32_t data; + + /* Read RXOICR register to Clear the Rx FIFO overflow interrupt */ + data = QSPI->RXOICR; +} + +/** + * @brief Clears the QSPI RxFIFO underflow interrupt. + * @retval None + */ +void QSPI_ClearRxFIFOUnderflowInterrupt(void) +{ + uint32_t data; + + /* Read RXUICR register to Clear the Rx FIFO underflow interrupt */ + data = QSPI->RXUICR; +} + +/** + * @brief Clears the QSPI Tx overflow/underflow,Rx overflow/underflow interrupt. + * @retval None + */ +void QSPI_ClearFIFOFlowInterrupt(void) +{ + uint32_t data; + + /* Read ICR register to Clear the FIFO flow interrupt */ + data = QSPI->ICR; +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rcc.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rcc.c new file mode 100644 index 00000000000..12a3a96b92a --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rcc.c @@ -0,0 +1,2730 @@ +/** + ****************************************************************************** + * @file ft32f4xx_rcc.c + * @author Rwang + * @brief This file provides firmware functions to manage the following + * functionalities of the Reset and clock control (RCC) peripheral: + * + Internal/external clocks, PLL, CSS and MCO configuration + * + System, AHB and APB busses clocks configuration + * + Peripheral clocks configuration + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-28 + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_rcc.h" + + +/* ---------------------- RCC registers mask -------------------------------- */ +/* RCC Flag Mask */ +#define FLAG_MASK ((uint8_t)0x1F) + +/* CR register byte 2 (Bits[23:16]) base address */ +#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802) + +/* CFGR register byte 3 (Bits[31:24]) base address */ +#define CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380F) + +/* CIR register byte 1 (Bits[15:8]) base address */ +#define CIR_BYTE1_ADDRESS ((uint32_t)0x40023811) + +/* CIR register byte 2 (Bits[23:16]) base address */ +#define CIR_BYTE2_ADDRESS ((uint32_t)0x40023812) + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * @note HSI ON and used as system clock source + * @note HSI48, HSE and PLL OFF + * @note AHB, APB prescaler set to 1. + * @note CSS and MCO OFF + * @note All interrupts disabled + * @note However, this function doesn't modify the configuration of the + * @note Peripheral clocks LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void RCC_DeInit(void) +{ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0], MCOPRE[2:0] bits */ + RCC->CFGR &= (uint32_t)0x80FFC00C; + + /* Reset HSEON, CSSON, PLLON and PLL2ON bits */ + RCC->CR &= (uint32_t)0xFAF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLR[2:0], PLLREN, PLLQ[3:0], PLLQEN, PLLP[2:0], PLLPEN, PLLSRC, PLLN[7:0], and PLLM[4:0] bits */ + RCC->PLLCFGR &= (uint32_t)0xE0008020; + + /* Reset PLL2R[2:0], PLL2REN, PLL2Q[3:0], PLL2QEN, PLL2SRC, PLL2N[7:0], and PLL2M[4:0] bits */ + RCC->PLL2CFGR &= (uint32_t)0xE00F8020; + + /* Reset QSPISEL[1:0], ADC123SEL[1:0], CANSEL[3:0], LPTIMSEL[1:0], + * I2C3SEL[1:0], I2C2SEL[1:0], I2C1SEL[1:0], LPUARTSEL RNGDIV[1:0], + * CLK48SEL, PWMSEL[1:0], EQEPSEL[1:0], ECAPSEL[1:0], and I2SSEL bits */ + RCC->CCIPR &= (uint32_t)0x00F00400; + + /* Reset HSI48ON bit */ + RCC->CR2 &= (uint32_t)0xFFFEFFFF; + + /* Reset RAMSEL */ + RCC->RAMCTL &= (uint32_t)0xFFFFFFC0; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +/** + * @brief Configures the External High Speed oscillator (HSE). + * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application + * software should wait on HSERDY flag to be set indicating that HSE clock + * is stable and can be used to clock the PLL and/or system clock. + * @note HSE state can not be changed if it is used directly or through the + * PLL as system clock. In this case, you have to select another source + * of the system clock then change the HSE state (ex. disable it). + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @param RCC_HSE: specifies the new state of the HSE. + * This parameter can be one of the following values: + * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after + * 6 HSE oscillator clock cycles. + * @arg RCC_HSE_ON: turn ON the HSE oscillator, HSERDY flag gose high after + * 512 HSE oscillator clock cycles. + * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock + * @retval None + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_HSE)); + + /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/ + RCC->CR &= (uint32_t)(~RCC_HSE_Bypass); + + /* Set the new HSE configuration -------------------------------------------*/ + RCC->CR |= RCC_HSE; + +} + +/** + * @brief Waits for HSE start up. + * @note This function waits on HSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSE_STARTUP_TIMEOUT in ft32f4xx.h file. You can tailor it depending + * on the HSE crystal used in your application. + * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSE oscillator is stable and ready to use + * - ERROR: HSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSEStatus = RESET; + + /* Wait till HSE is ready and if timeout is reached exit */ + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_HSERDY); + StartUpCounter++; + } + while ((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_HSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * Refer to the Application Note AN4067 for more details on how to + * calibrate the HSI. + * @param HSICalibrationValue: specifies the HSI calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue)); + + tmpreg = RCC->CR; + + /* Clear HSITRIM[4:0] bits */ + tmpreg &= ~RCC_CR_HSITRIM; + + /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */ + tmpreg |= ((uint32_t)HSICalibrationValue << 3); + + /* Store the new value */ + RCC->CR = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * @note After enabling the HSI, the application software should wait on + * HSIRDY flag to be set indicating that HSI clock is stable and can + * be used to clock the PLL and/or system clock. + * @note HSI can not be stopped if it is used directly or through the PLL + * as system clock. In this case, you have to select another source + * of the system clock then stop the HSI. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the HSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator + * clock cycles. + * @retval None + */ +void RCC_HSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_HSION; + } + else + { + RCC->CR &= ~RCC_CR_HSION; + } +} + +/** + * @brief Waits for HSI start up. + * @note This function waits on HSIRDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSI_STARTUP_TIMEOUT in ft32f4xx.h file. You can tailor it depending + * on the HSI crystal used in your application. + * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSU oscillator is stable and ready to use + * - ERROR: HSI oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSIStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSIStatus = RESET; + + /* Wait till HSI is ready and if timeout is reached exit */ + do + { + HSIStatus = RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_HSIRDY); + StartUpCounter++; + } + while ((StartUpCounter != HSI_STARTUP_TIMEOUT) && (HSIStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_HSIRDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Adjusts the Internal High Speed oscillator for ADC (HSI48) + * calibration value. + * @note The calibration is used to compensate for the variations in voltage + * and temperature that influence the frequency of the internal HSI RC. + * Refer to the Application Note AN4067 for more details on how to + * calibrate the HSI48. + * @param HSI48CalibrationValue: specifies the HSI48 calibration trimming value. + * This parameter must be a number between 0 and 0x1FF. + * @retval None + */ +void RCC_AdjustHSI48CalibrationValue(uint32_t HSI48CalibrationValue) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HSI48_CALIBRATION_VALUE(HSI48CalibrationValue)); + + tmpreg = RCC->CR2; + + /* Clear HSI48CAL[8:0] bits */ + tmpreg &= ~RCC_CR2_HSI48CAL; + + /* Set the HSICAL48[8:0] bits according to HSI48CalibrationValue value */ + tmpreg |= ((uint32_t)HSI48CalibrationValue << 23); + + /* Store the new value */ + RCC->CR2 = tmpreg; +} + +/** + * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI48). + * @note After enabling the HSI48, the application software should wait on + * HSI48RDY flag to be set indicating that HSI clock is stable and can + * be used to clock the ADC. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @param NewState: new state of the HSI48. + * This parameter can be: ENABLE or DISABLE. + * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI14 oscillator + * clock cycles. + * @retval None + */ +void RCC_HSI48Cmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR2 |= RCC_CR2_HSI48ON; + } + else + { + RCC->CR2 &= ~RCC_CR2_HSI48ON; + } +} + +/** + * @brief Waits for HSI48 start up. + * @note This function waits on HSI48RDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * HSI48_STARTUP_TIMEOUT in ft32f4xx.h file. You can tailor it depending + * on the HSI48 crystal used in your application. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: HSI48 oscillator is stable and ready to use + * - ERROR: HSI48 oscillator not yet ready + */ +ErrorStatus RCC_WaitForHSI48StartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus HSI48Status = RESET; + + /* Wait till HSI48 is ready and if timeout is reached exit */ + do + { + HSI48Status = RCC_GetFlagStatus(RCC_FLAG_REG_CR2, RCC_FLAG_HSI48RDY); + StartUpCounter++; + } + while ((StartUpCounter != HSI48_STARTUP_TIMEOUT) && (HSI48Status == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_REG_CR2, RCC_FLAG_HSI48RDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + + +/** + * @brief Configures the External Low Speed oscillator (LSE). + * @note As the LSE is in the Backup domain and write access is denied to this + * domain after reset, you have to enable write access using + * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE + * (to be done once after reset). + * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application + * software should wait on LSERDY flag to be set indicating that LSE clock + * is stable and can be used to clock the RTC. + * @param RCC_LSE: specifies the new state of the LSE. + * This parameter can be one of the following values: + * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after + * 6 LSE oscillator clock cycles. + * @arg RCC_LSE_ON: turn ON the LSE oscillator after 4096 clock cycle stable + * @arg RCC_LSE_BYP: LSE oscillator bypassed with external clock + * @retval None + */ +void RCC_LSEConfig(uint32_t RCC_LSE) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE(RCC_LSE)); + + /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/ + /* Reset LSEON bit */ + RCC->BDCR &= ~(RCC_BDCR_LSEON); + + /* Reset LSEBYP bit */ + RCC->BDCR &= ~(RCC_BDCR_LSEBYP); + + /* Configure LSE */ + RCC->BDCR |= RCC_LSE | RCC_LSEDrive_MediumLow; +} + +/** + * @brief Waits for LSE start up. + * @note This function waits on LSERDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * LSE_STARTUP_TIMEOUT in ft32f4xx.h file. You can tailor it depending + * on the LSE crystal used in your application. + * @note The LSE is stopped by hardware when entering STOP and STANDBY modes. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LSE oscillator is stable and ready to use + * - ERROR: LSE oscillator not yet ready + */ +ErrorStatus RCC_WaitForLSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus LSEStatus = RESET; + + /* Wait till LSE is ready and if timeout is reached exit */ + do + { + LSEStatus = RCC_GetFlagStatus(RCC_FLAG_REG_BDCR, RCC_FLAG_LSERDY); + StartUpCounter++; + } + while ((StartUpCounter != LSE_STARTUP_TIMEOUT) && (LSEStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_REG_BDCR, RCC_FLAG_LSERDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Configures the External Low Speed oscillator (LSE) drive capability. + * @param RCC_LSEDrive: specifies the new state of the LSE drive capability. + * This parameter can be one of the following values: + * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability. + * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability. + * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability. + * @arg RCC_LSEDrive_High: LSE oscillator high drive capability. + * @retval None + */ +void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive)); + + /* Clear LSEDRV[1:0] bits */ + RCC->BDCR &= ~(RCC_BDCR_LSEDRV); + + /* Set the LSE Drive */ + RCC->BDCR |= RCC_LSEDrive; +} + +/** + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * @note After enabling the LSI, the application software should wait on + * LSIRDY flag to be set indicating that LSI clock is stable and can + * be used to clock the IWDG and/or the RTC. + * @note LSI can not be disabled if the IWDG is running. + * @param NewState: new state of the LSI. + * This parameter can be: ENABLE or DISABLE. + * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator + * clock cycles. + * @retval None + */ +void RCC_LSICmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CSR |= RCC_CSR_LSION; + } + else + { + RCC->CSR &= ~RCC_CSR_LSION; + } +} + +/** + * @brief Waits for LSI start up. + * @note This function waits on LSIRDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * LSI_STARTUP_TIMEOUT in ft32f4xx.h file. You can tailor it depending + * on the LSI crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LSI oscillator is stable and ready to use + * - ERROR: LSI oscillator not yet ready + */ +ErrorStatus RCC_WaitForLSIStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus LSIStatus = RESET; + + /* Wait till LSI is ready and if timeout is reached exit */ + do + { + LSIStatus = RCC_GetFlagStatus(RCC_FLAG_REG_CSR, RCC_FLAG_LSIRDY); + StartUpCounter++; + } + while ((StartUpCounter != LSI_STARTUP_TIMEOUT) && (LSIStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_REG_CSR, RCC_FLAG_LSIRDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Configures the PLL clock source, multiplication and null factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLSource: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source + * @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source + * @note The minimum input clock frequency for PLL is 2 MHz + * @param RCC_PLLNul: specifies the PLL multiplication factor, which drive the PLLVCO clock + * This parameter must be a number between 0 and 0xFF. + * @param RCC_PLLMul: specifies the PLL Division factor, which drive the PLLVCO clock + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_PLLVcoOutputConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLNul, uint32_t RCC_PLLMul) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLSRC(RCC_PLLSource)); + assert_param(IS_RCC_PLLN_VALUE(RCC_PLLNul)); + assert_param(IS_RCC_PLLM_VALUE(RCC_PLLMul)); + + /* Clear PLLSRC[14], PLLN[7:0], and PLLM[4:0] bits */ + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLM); + + /* Set the PLL Source PLLN and PLLM */ + RCC->PLLCFGR |= (uint32_t)(((uint32_t)RCC_PLLSource << 14) | + ((uint32_t)RCC_PLLNul << 6) | + ((uint32_t)RCC_PLLMul)); +} + +/** + * @brief Configures the PLLR clock enable, division factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLRstatus: specifies the PLLR enable or disable. + * This parameter can be one of the following values: + * @arg RCC_PLLR_OFF: PLLR clock disable + * @arg RCC_PLLR_ON: PLLR clock enable + * @param RCC_PLLR: specifies the PLLR division factor + * This parameter must be a number between 0 and 0x07. + * @retval None + */ +void RCC_PLLROutputConfig(uint32_t RCC_PLLRStatus, uint32_t RCC_PLLR) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLR(RCC_PLLRStatus)); + assert_param(IS_RCC_PLLR_VALUE(RCC_PLLR)); + + /* Clear PLLR[2:0], PLLREN bits */ + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLR | RCC_PLLCFGR_PLLREN); + + /* Set the PLLREN and PLLR[2:0] */ + RCC->PLLCFGR |= (uint32_t)(((uint32_t)RCC_PLLRStatus << 25) | + ((uint32_t)RCC_PLLR << 26)); +} + +/** + * @brief Configures the PLLQ clock enable, division factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLQstatus: specifies the PLLQ enable or disable. + * This parameter can be one of the following values: + * @arg RCC_PLLQ_OFF: PLLQ clock disable + * @arg RCC_PLLQ_ON: PLLQ clock enable + * @param RCC_PLLQ: specifies the PLLQ division factor + * This parameter must be a number between 0 and 0x0F. + * @retval None + */ +void RCC_PLLQOutputConfig(uint32_t RCC_PLLQStatus, uint32_t RCC_PLLQ) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLQ(RCC_PLLQStatus)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_PLLQ)); + + /* Clear PLLQ[3:0], PLLQEN bits */ + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLQ | RCC_PLLCFGR_PLLQEN); + + /* Set the PLLQEN and PLLQ[3:0] */ + RCC->PLLCFGR |= (uint32_t)(((uint32_t)RCC_PLLQStatus << 20) | + ((uint32_t)RCC_PLLQ << 21)); +} + +/** + * @brief Configures the PLLP clock enable, division factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLLPstatus: specifies the PLLP enable or disable. + * This parameter can be one of the following values: + * @arg RCC_PLLP_OFF: PLLP clock disable + * @arg RCC_PLLP_ON: PLLP clock enable + * @param RCC_PLLP: specifies the PLLP division factor + * This parameter must be a number between 0 and 0x07. + * @retval None + */ +void RCC_PLLPOutputConfig(uint32_t RCC_PLLPStatus, uint32_t RCC_PLLP) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLLP(RCC_PLLPStatus)); + assert_param(IS_RCC_PLLP_VALUE(RCC_PLLP)); + + /* Clear PLLP[2:0], PLLPEN bits */ + RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLP | RCC_PLLCFGR_PLLPEN); + + /* Set the PLLPEN and PLLP[2:0] */ + RCC->PLLCFGR |= (uint32_t)(((uint32_t)RCC_PLLPStatus << 16) | + ((uint32_t)RCC_PLLP << 17)); +} + +/** + * @brief Configures the PLL2 clock source, multiplication and null factor. + * @note This function must be used only when the PLL is disabled. + * @param RCC_PLL2Source: specifies the PLL entry clock source. + * This parameter can be one of the following values: + * @arg RCC_PLL2Source_HSI: HSI oscillator clock selected as PLL2 clock source + * @arg RCC_PLL2Source_HSE: HSE oscillator clock selected as PLL2 clock source + * @note The minimum input clock frequency for PLL2 is 2 MHz + * @param RCC_PLL2Nul: specifies the PLL2 multiplication factor, which drive the PLL2VCO clock + * This parameter must be a number between 0 and 0xFF. + * @param RCC_PLL2Mul: specifies the PLL2 Division factor, which drive the PLL2VCO clock + * This parameter must be a number between 0 and 0x1F. + * @retval None + */ +void RCC_PLL2VcoOutputConfig(uint32_t RCC_PLL2Source, uint32_t RCC_PLL2Nul, uint32_t RCC_PLL2Mul) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL2SRC(RCC_PLL2Source)); + assert_param(IS_RCC_PLL2N_VALUE(RCC_PLL2Nul)); + assert_param(IS_RCC_PLL2M_VALUE(RCC_PLL2Mul)); + + /* Clear PLL2SRC[14], PLL2N[7:0], and PLL2M[4:0] bits */ + RCC->PLL2CFGR &= ~(RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2N | RCC_PLL2CFGR_PLL2M); + + /* Set the PLL2 Source, PLL2N and PLL2M */ + RCC->PLL2CFGR |= (uint32_t)(((uint32_t)RCC_PLL2Source << 14) | + ((uint32_t)RCC_PLL2Nul << 6) | + ((uint32_t)RCC_PLL2Mul)); +} + +/** + * @brief Configures the PLL2R clock enable, division factor. + * @note This function must be used only when the PLL2 is disabled. + * @param RCC_PLL2Rstatus: specifies the PLL2R enable or disable. + * This parameter can be one of the following values: + * @arg RCC_PLL2R_OFF: PLL2R clock disable + * @arg RCC_PLL2R_ON: PLL2R clock enable + * @param RCC_PLL2R: specifies the PLL2R division factor + * This parameter must be a number between 0 and 0x07. + * @retval None + */ +void RCC_PLL2ROutputConfig(uint32_t RCC_PLL2RStatus, uint32_t RCC_PLL2R) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL2R(RCC_PLL2RStatus)); + assert_param(IS_RCC_PLL2R_VALUE(RCC_PLL2R)); + + /* Clear PLL2R[2:0], PLL2REN bits */ + RCC->PLL2CFGR &= ~(RCC_PLL2CFGR_PLL2R | RCC_PLL2CFGR_PLL2REN); + + /* Set the PLL2REN and PLL2R[2:0] */ + RCC->PLL2CFGR |= (uint32_t)(((uint32_t)RCC_PLL2RStatus << 25) | + ((uint32_t)RCC_PLL2R << 26)); +} + +/** + * @brief Configures the PLL2Q clock enable, division factor. + * @note This function must be used only when the PLL2 is disabled. + * @param RCC_PLL2Qstatus: specifies the PLL2Q enable or disable. + * This parameter can be one of the following values: + * @arg RCC_PLL2Q_OFF: PLL2Q clock disable + * @arg RCC_PLL2Q_ON: PLL2Q clock enable + * @param RCC_PLL2Q: specifies the PLL2Q division factor + * This parameter must be a number between 0 and 0x0F. + * @retval None + */ +void RCC_PLL2QOutputConfig(uint32_t RCC_PLL2QStatus, uint32_t RCC_PLL2Q) +{ + /* Check the parameters */ + assert_param(IS_RCC_PLL2Q(RCC_PLL2QStatus)); + assert_param(IS_RCC_PLL2Q_VALUE(RCC_PLL2Q)); + + /* Clear PLL2Q[3:0], PLL2QEN bits */ + RCC->PLL2CFGR &= ~(RCC_PLL2CFGR_PLL2Q | RCC_PLL2CFGR_PLL2QEN); + + /* Set the PLL2QEN and PLL2Q[3:0] */ + RCC->PLL2CFGR |= (uint32_t)(((uint32_t)RCC_PLL2QStatus << 20) | + ((uint32_t)RCC_PLL2Q << 21)); +} + + +/** + * @brief Enables or disables the PLL. + * @note After enabling the PLL, the application software should wait on + * PLLRDY flag to be set indicating that PLL clock is stable and can + * be used as system clock source. + * @note The PLL can not be disabled if it is used as system clock source + * @note The PLL is disabled by hardware when entering STOP and STANDBY modes. + * @param RCC_PLLSelect: select enable pll or pll2. + * This parameter can be one of the following values: + * @arg RCC_SEL_PLL: PLL clock enable + * @arg RCC_SEL_PLL2: PLL2 clock enable + * @param NewState: new state of the PLL. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_PLLCmd(uint32_t RCC_PLLSelect, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_SEL(RCC_PLLSelect)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (RCC_PLLSelect == RCC_SEL_PLL) + { + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_PLLON; + } + else + { + RCC->CR &= ~RCC_CR_PLLON; + } + } + else if (RCC_PLLSelect == RCC_SEL_PLL2) + { + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_PLL2ON; + } + else + { + RCC->CR &= ~RCC_CR_PLL2ON; + } + } +} + +/** + * @brief Waits for PLL start up. + * @note This function waits on PLLRDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * PLL_STARTUP_TIMEOUT in ft32f4xx.h file. You can tailor it depending + * on the PLL crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL oscillator is stable and ready to use + * - ERROR: PLL oscillator not yet ready + */ +ErrorStatus RCC_WaitForPLLStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus PLLStatus = RESET; + + /* Wait till PLL is ready and if timeout is reached exit */ + do + { + PLLStatus = RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_PLLRDY); + StartUpCounter++; + } + while ((StartUpCounter != PLL_STARTUP_TIMEOUT) && (PLLStatus == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_PLLRDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Waits for PLL2 start up. + * @note This function waits on PLL2RDY flag to be set and return SUCCESS if + * this flag is set, otherwise returns ERROR if the timeout is reached + * and this flag is not set. The timeout value is defined by the constant + * PLL2_STARTUP_TIMEOUT in ft32f4xx.h file. You can tailor it depending + * on the PLL2 crystal used in your application. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL2 oscillator is stable and ready to use + * - ERROR: PLL2 oscillator not yet ready + */ +ErrorStatus RCC_WaitForPLL2StartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + ErrorStatus status = ERROR; + FlagStatus PLL2Status = RESET; + + /* Wait till PLL2 is ready and if timeout is reached exit */ + do + { + PLL2Status = RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_PLL2RDY); + StartUpCounter++; + } + while ((StartUpCounter != PLL2_STARTUP_TIMEOUT) && (PLL2Status == RESET)); + + if (RCC_GetFlagStatus(RCC_FLAG_REG_CR, RCC_FLAG_PLL2RDY) != RESET) + { + status = SUCCESS; + } + else + { + status = ERROR; + } + return (status); +} + +/** + * @brief Enables or disables the Clock Security System. + * @note If a failure is detected on the HSE oscillator clock, this oscillator + * is automatically disabled and an interrupt is generated to inform the + * software about the failure (Clock Security System Interrupt, CSSI), + * allowing the MCU to perform rescue operations. The CSSI is linked to + * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector. + * @param NewState: new state of the Clock Security System. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->CR |= RCC_CR_CSSON; + } + else + { + RCC->CR &= ~RCC_CR_CSSON; + } +} + +/** + * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding + * prescsaler. + * @note PA8 should be configured in alternate function mode(AF0). + * @param RCC_MCOSource: specifies the clock source to output. + * This parameter can be one of the following values: + * @arg RCC_MCOSource_NoClock: No clock selected. + * @arg RCC_MCOSource_SYSCLK: System clock selected. + * @arg RCC_MCOSource_PLL2R: PLL2R clock selected. + * @arg RCC_MCOSource_HSI16: HSI16 oscillator clock selected. + * @arg RCC_MCOSource_HSE: HSE oscillator clock selected. + * @arg RCC_MCOSource_PLLP: PLLP clock selected. + * @arg RCC_MCOSource_LSI: LSI oscillator clock selected. + * @arg RCC_MCOSource_LSE: LSE oscillator clock selected. + * @arg RCC_MCOSource_HSI48: HSI48 clock selected. + * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin. + * This parameter can be one of the following values: + * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1. + * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2. + * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4. + * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8. + * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16. + * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32. + * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64. + * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128. + * @retval None + */ +void RCC_MCOConfig(uint32_t RCC_MCOSource, uint32_t RCC_MCOPrescaler) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource)); + assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler)); + + /* Get CFGR value */ + tmpreg = RCC->CFGR; + /* Clear MCOPRE[2:0] and MCOSEL[3:0] bits */ + tmpreg &= ~(RCC_CFGR_MCOPRE | RCC_CFGR_MCOSEL); + /* Set the RCC_MCOSource and RCC_MCOPrescaler */ + tmpreg |= (RCC_MCOSource | RCC_MCOPrescaler); + /* Store the new value */ + RCC->CFGR = tmpreg; +} +/** + * @} + */ + +/** + * @brief Configures the system clock (SYSCLK). + * @note The HSI is used (enabled by hardware) as system clock source after + * startup from Reset, wake-up from STOP and STANDBY mode, or in case + * of failure of the HSE used directly or indirectly as system clock + * (if the Clock Security System CSS is enabled). + * @note A switch from one clock source to another occurs only if the target + * clock source is ready (clock stable after startup delay or PLL locked). + * If a clock source which is not yet ready is selected, the switch will + * occur when the clock source will be ready. + * You can use RCC_GetSYSCLKSource() function to know which clock is + * currently used as system clock source. + * @param RCC_SYSCLKSource: specifies the clock source used as system clock source + * This parameter can be one of the following values: + * @arg RCC_SYSCLKSource_HSI16: HSI16 selected as system clock source + * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source + * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source + * @retval None + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource)); + + tmpreg = RCC->CFGR; + + /* Clear SW[1:0] bits */ + tmpreg &= ~RCC_CFGR_SW; + + /* Set SW[1:0] bits according to RCC_SYSCLKSource value */ + tmpreg |= RCC_SYSCLKSource; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Returns the clock source used as system clock. + * @param None + * @retval The clock source used as system clock. The returned value can be one + * of the following values: + * - 0x00000000: HSI16 used as system clock + * - 0x00000004: HSE used as system clock + * - 0x00000008: PLL used as system clock + */ +uint32_t RCC_GetSYSCLKSource(void) +{ + return ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS)); +} + +/** + * @brief Configures the AHB clock (HCLK). + * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * This parameter can be one of the following values: + * @arg RCC_SYSCLK_DIV1: AHB clock = SYSCLK + * @arg RCC_SYSCLK_DIV2: AHB clock = SYSCLK/2 + * @arg RCC_SYSCLK_DIV4: AHB clock = SYSCLK/4 + * @arg RCC_SYSCLK_DIV8: AHB clock = SYSCLK/8 + * @arg RCC_SYSCLK_DIV16: AHB clock = SYSCLK/16 + * @arg RCC_SYSCLK_DIV64: AHB clock = SYSCLK/64 + * @arg RCC_SYSCLK_DIV128: AHB clock = SYSCLK/128 + * @arg RCC_SYSCLK_DIV256: AHB clock = SYSCLK/256 + * @arg RCC_SYSCLK_DIV512: AHB clock = SYSCLK/512 + * @retval None + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_HCLK(RCC_SYSCLK)); + + tmpreg = RCC->CFGR; + + /* Clear HPRE[3:0] bits */ + tmpreg &= ~RCC_CFGR_HPRE; + + /* Set HPRE[3:0] bits according to RCC_SYSCLK value */ + tmpreg |= RCC_SYSCLK; + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the APB clock (PCLK). + * @param RCC_HCLK1: defines the APB clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1: APB clock = HCLK + * @arg RCC_HCLK_DIV2: APB clock = HCLK/2 + * @arg RCC_HCLK_DIV4: APB clock = HCLK/4 + * @arg RCC_HCLK_DIV8: APB clock = HCLK/8 + * @arg RCC_HCLK_DIV16: APB clock = HCLK/16 + * @retval None + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK1) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK1)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE1[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE1; + + /* Set PPRE1[2:0] bits according to RCC_HCLK value */ + tmpreg |= ((uint32_t)RCC_HCLK1 << 8); + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the APB clock (PCLK). + * @param RCC_HCLK2: defines the APB clock divider. This clock is derived from + * the AHB clock (HCLK). + * This parameter can be one of the following values: + * @arg RCC_HCLK_DIV1: APB clock = HCLK + * @arg RCC_HCLK_DIV2: APB clock = HCLK/2 + * @arg RCC_HCLK_DIV4: APB clock = HCLK/4 + * @arg RCC_HCLK_DIV8: APB clock = HCLK/8 + * @arg RCC_HCLK_DIV16: APB clock = HCLK/16 + * @retval None + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK2) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RCC_PCLK(RCC_HCLK2)); + + tmpreg = RCC->CFGR; + + /* Clear PPRE[2:0] bits */ + tmpreg &= ~RCC_CFGR_PPRE2; + + /* Set PPRE2[2:0] bits according to RCC_HCLK value */ + tmpreg |= ((uint32_t)RCC_HCLK2 << 11); + + /* Store the new value */ + RCC->CFGR = tmpreg; +} + +/** + * @brief Configures the QSPI clock (QSPICLK). + * @note This function is obsolete. + * For proper QSPI clock selection, refer to QSPI_ClockModeConfig() in the QSPI driver + * @param RCC_QSPICLK: defines the QSPI clock source. This clock is derived + * from the HSI16, PLL1Q or SYSCLK. + * This parameter can be one of the following values: + * @arg RCC_QSPICLK_SYSCLK: QSPI clock = SYSCLK + * @arg RCC_QSPICLK_HSI16: QSPI clock = HSI16 + * @arg RCC_QSPICLK_PLL1Q: QSPI clock = PLL1Q + * @retval None + */ +void RCC_QSPICLKConfig(uint32_t RCC_QSPICLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_QSPICLK(RCC_QSPICLK)); + + /* Clear QSPISEL[1:0] bitS */ + RCC->CCIPR &= ~RCC_CCIPR_QSPISEL; + + /* Set QSPISEL bits according to RCC_QSPICLK value */ + RCC->CCIPR |= RCC_QSPICLK; +} + +/** + * @brief Configures the ADC clock (ADCCLK). + * @note This function is obsolete. + * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver + * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived + * from the PLL1R or SYSCLK. + * This parameter can be one of the following values: + * @arg RCC_ADCCLK_NOCLK: ADC no clock + * @arg RCC_ADCCLK_PLL1R: ADC clock = PLL1R + * @arg RCC_ADCCLK_SYSCLK: ADC clock = SYSCLK + * @retval None + */ +void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_ADCCLK(RCC_ADCCLK)); + + /* Clear ADC123SEL[1:0] bitS */ + RCC->CCIPR &= ~RCC_CCIPR_ADCSEL; + + /* Set ADCSEL bits according to RCC_ADCCLK value */ + RCC->CCIPR |= RCC_ADCCLK; +} + +/** + * @brief Configures the CAN clock (CANCLK). + * @note This function is obsolete. + * For proper CAN clock selection, refer to CAN_ClockModeConfig() in the CAN driver + * @param RCC_CANCLK: defines the CAN clock source. This clock is derived + * from the HCLK or HCLK's prescaler. + * This parameter can be one of the following values: + * @arg RCC_CANCLK_HCLK: CAN clock = HCLK + * @arg RCC_CANCLK_HCLK_DIV2: CAN clock = HCLK/2 + * @arg RCC_CANCLK_HCLK_DIV4: CAN clock = HCLK/4 + * @arg RCC_CANCLK_HCLK_DIV8: CAN clock = HCLK/8 + * @arg RCC_CANCLK_HCLK_DIV16: CAN clock = HCLK/16 + * @arg RCC_CANCLK_HCLK_DIV32: CAN clock = HCLK/32 + * @retval None + */ +void RCC_CANCLKConfig(uint32_t RCC_CANCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_CANCLK(RCC_CANCLK)); + + /* Clear CANSEL[3:0] bits */ + RCC->CCIPR &= ~RCC_CCIPR_CANSEL; + + /* Set CANSEL bits according to RCC_CANCLK value */ + RCC->CCIPR |= RCC_CANCLK; +} + +/** + * @brief Configures the LPTIM clock (LPTIMCLK). + * @note This function is obsolete. + * For proper LPTIM clock selection, refer to LPTIM_ClockModeConfig() in the LPTIM driver + * @param RCC_LPTIMCLK: defines the LPTIM clock source. This clock is derived + * from the PCLK, LSI, HSI16 or LSE prescaler. + * This parameter can be one of the following values: + * @arg RCC_LPTIMCLK_PCLK: LPTIM clock = PCLK + * @arg RCC_LPTIMCLK_LSI: LPTIM clock = LSI + * @arg RCC_LPTIMCLK_HSI16: LPTIM clock = HSI16 + * @arg RCC_LPTIMCLK_LSE: LPTIM clock = LSE + * @retval None + */ +void RCC_LPTIMCLKConfig(uint32_t RCC_LPTIMCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPTIMCLK(RCC_LPTIMCLK)); + + /* Clear LPTIMSEL[1:0] bits */ + RCC->CCIPR &= ~RCC_CCIPR_LPTIMSEL; + + /* Set LPTIMSEL bits according to RCC_LPTIMCLK value */ + RCC->CCIPR |= RCC_LPTIMCLK; +} + +/** + * @brief Configures the I2C3 clock (I2C3CLK). + * @note This function is obsolete. + * For proper I2C3 clock selection, refer to I2C3_ClockModeConfig() in the I2C3 driver + * @param RCC_I2C3CLK: defines the I2C3 clock source. This clock is derived + * from the PCLK, SYSCLK or HSI16. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLK_PCLK: I2C3 clock = PCLK + * @arg RCC_I2C3CLK_SYSCLK: I2C3 clock = SYSCLK + * @arg RCC_I2C3CLK_HSI16: I2C3 clock = HSI16 + * @retval None + */ +void RCC_I2C3CLKConfig(uint32_t RCC_I2C3CLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLK(RCC_I2C3CLK)); + + /* Clear I2C3SEL[1:0] bits */ + RCC->CCIPR &= ~RCC_CCIPR_I2C3SEL; + + /* Set I2C3SEL bits according to RCC_I2C3CLK value */ + RCC->CCIPR |= RCC_I2C3CLK; +} + +/** + * @brief Configures the I2C2 clock (I2C2CLK). + * @note This function is obsolete. + * For proper I2C2 clock selection, refer to I2C2_ClockModeConfig() in the I2C2 driver + * @param RCC_I2C2CLK: defines the I2C2 clock source. This clock is derived + * from the PCLK, SYSCLK or HSI16. + * This parameter can be one of the following values: + * @arg RCC_I2C2CLK_PCLK: I2C2 clock = PCLK + * @arg RCC_I2C2CLK_SYSCLK: I2C2 clock = SYSCLK + * @arg RCC_I2C2CLK_HSI16: I2C2 clock = HSI16 + * @retval None + */ +void RCC_I2C2CLKConfig(uint32_t RCC_I2C2CLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLK(RCC_I2C2CLK)); + + /* Clear I2C2SEL[1:0] bits */ + RCC->CCIPR &= ~RCC_CCIPR_I2C2SEL; + + /* Set I2C2SEL bits according to RCC_I2C2CLK value */ + RCC->CCIPR |= RCC_I2C2CLK; +} + +/** + * @brief Configures the I2C1 clock (I2C1CLK). + * @note This function is obsolete. + * For proper I2C1 clock selection, refer to I2C1_ClockModeConfig() in the I2C1 driver + * @param RCC_I2C1CLK: defines the I2C1 clock source. This clock is derived + * from the PCLK, SYSCLK or HSI16. + * This parameter can be one of the following values: + * @arg RCC_I2C1CLK_PCLK: I2C1 clock = PCLK + * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = SYSCLK + * @arg RCC_I2C1CLK_HSI16: I2C1 clock = HSI16 + * @retval None + */ +void RCC_I2C1CLKConfig(uint32_t RCC_I2C1CLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLK(RCC_I2C1CLK)); + + /* Clear I2C1SEL[1:0] bits */ + RCC->CCIPR &= ~RCC_CCIPR_I2C1SEL; + + /* Set I2C1SEL bits according to RCC_I2C1CLK value */ + RCC->CCIPR |= RCC_I2C1CLK; +} + +/** + * @brief Configures the LPUART clock (LPUARTCLK). + * @note This function is obsolete. + * For proper LPUART clock selection, refer to LPUART_ClockModeConfig() in the LPUART driver + * @param RCC_LPUARTCLK: defines the LPUART clock source. This clock is derived + * from the PCLK or LSE. + * This parameter can be one of the following values: + * @arg RCC_LPUARTCLK_PCLK: LPUART clock = PCLK + * @arg RCC_LPUARTCLK_LSE: LPUART clock = LSE + * @retval None + */ +void RCC_LPUARTCLKConfig(uint32_t RCC_LPUARTCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_LPUARTCLK(RCC_LPUARTCLK)); + + /* Clear LPUARTSEL[1:0] bits */ + RCC->CCIPR &= ~RCC_CCIPR_LPUARTSEL; + + /* Set LPUARTSEL bits according to RCC_LPUARTCLK value */ + RCC->CCIPR |= RCC_LPUARTCLK; +} + +/** + * @brief Configures the RNG clock division(RNGCLKDIV). + * @note This function is obsolete. + * For proper RNG clock selection, refer to RNG_ClockModeConfig() in the RNG driver + * @param RCC_RNGCLKDIV: defines the RNG clock division. This clock is derived + * from the work clk's 1/2/4/8. + * This parameter can be one of the following values: + * @arg RCC_RNGCLK_DIV1: RNG clock = RNG work clock/1 + * @arg RCC_RNGCLK_DIV2: RNG clock = RNG work clock/2 + * @arg RCC_RNGCLK_DIV4: RNG clock = RNG work clock/4 + * @arg RCC_RNGCLK_DIV8: RNG clock = RNG work clock/8 + * @retval None + */ +void RCC_RNGCLKDIVConfig(uint32_t RCC_RNGCLKDIV) +{ + /* Check the parameters */ + assert_param(IS_RCC_RNGCLK_DIV(RCC_RNGCLKDIV)); + + /* Clear RNGDIV[1:0] bits */ + RCC->CCIPR &= ~RCC_CCIPR_RNGDIV; + + /* Set RNGDIV[1:0] bits according to RCC_RNGCLKDIV value */ + RCC->CCIPR |= RCC_RNGCLKDIV; +} + +/** + * @brief Configures the 48M clock source(48MCLK). + * @note This function is obsolete. + * For proper 48M clock selection + * @param RCC_48MCLK: defines the 48M clock source. This clock is derived + * from the HSI48 or PLLQ . + * This parameter can be one of the following values: + * @arg RCC_48MCLK_HSI48: 48M clock = HSI48 + * @arg RCC_48MCLK_PLLQ: 48M clock = PLLQ + * @retval None + */ +void RCC_48MCLKConfig(uint32_t RCC_48MCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_48MCLK(RCC_48MCLK)); + + /* Clear CLK48SEL bit */ + RCC->CCIPR &= ~RCC_CCIPR_CLK48SEL; + + /* Set CLK48SEL bits according to RCC_48MCLK value */ + RCC->CCIPR |= RCC_48MCLK; +} + +/** + * @brief Configures the EPWM clock source(EPWMCLK). + * @note This function is obsolete. + * For proper EPWM clock selection + * @param RCC_EPWMCLK: defines the EPWM clock source. This clock is derived + * from the SYSCLK or SYSCLK/2/4 . + * This parameter can be one of the following values: + * @arg RCC_EPWMCLK_SYSCLK: EPWM clock = SYSCLK + * @arg RCC_EPWMCLK_SYSCLK_DIV2: EPWM clock = SYSCLK/2 + * @arg RCC_EPWMCLK_SYSCLK_DIV4: EPWM clock = SYSCLK/4 + * @retval None + */ +void RCC_EPWMCLKConfig(uint32_t RCC_EPWMCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_EPWMCLK(RCC_EPWMCLK)); + + /* Clear PWMSEL[1:0] bit */ + RCC->CCIPR &= ~RCC_CCIPR_PWMSEL; + + /* Set PWMSEL bits according to RCC_EPWMCLK value */ + RCC->CCIPR |= RCC_EPWMCLK; +} + +/** + * @brief Configures the EQEP clock source(EQEPCLK). + * @note This function is obsolete. + * For proper EQEP clock selection + * @param RCC_EQEPCLK: defines the EQEP clock source. This clock is derived + * from the SYSCLK or SYSCLK/2/4 . + * This parameter can be one of the following values: + * @arg RCC_EQEPCLK_SYSCLK: EQEP clock = SYSCLK + * @arg RCC_EQEPCLK_SYSCLK_DIV2: EQEP clock = SYSCLK/2 + * @arg RCC_EQEPCLK_SYSCLK_DIV4: EQEP clock = SYSCLK/4 + * @retval None + */ +void RCC_EQEPCLKConfig(uint32_t RCC_EQEPCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_EQEPCLK(RCC_EQEPCLK)); + + /* Clear EQEPSEL[1:0] bit */ + RCC->CCIPR &= ~RCC_CCIPR_EQEPSEL; + + /* Set EQEPSEL bits according to RCC_EQEPCLK value */ + RCC->CCIPR |= RCC_EQEPCLK; +} + +/** + * @brief Configures the ECAP clock source(ECAPCLK). + * @note This function is obsolete. + * For proper ECAP clock selection + * @param RCC_ECAPCLK: defines the ECAP clock source. This clock is derived + * from the SYSCLK or SYSCLK/2/4 . + * This parameter can be one of the following values: + * @arg RCC_ECAPCLK_SYSCLK: ECAP clock = SYSCLK + * @arg RCC_ECAPCLK_SYSCLK_DIV2: ECAP clock = SYSCLK/2 + * @arg RCC_ECAPCLK_SYSCLK_DIV4: ECAP clock = SYSCLK/4 + * @retval None + */ +void RCC_ECAPCLKConfig(uint32_t RCC_ECAPCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_ECAPCLK(RCC_ECAPCLK)); + + /* Clear ECAPSEL[1:0] bit */ + RCC->CCIPR &= ~RCC_CCIPR_ECAPSEL; + + /* Set ECAPSEL bits according to RCC_ECAPCLK value */ + RCC->CCIPR |= RCC_ECAPCLK; +} + +/** + * @brief Configures the I2S clock source(I2SCLK). + * @note This function is obsolete. + * For proper I2S clock selection + * @param RCC_I2SCLK: defines the I2S clock source. This clock is derived + * from the PLL2Q or external I2S_CKIN . + * This parameter can be one of the following values: + * @arg RCC_I2SCLK_PLL2Q: I2S clock = PLL2Q + * @arg RCC_I2SCLK_I2S_CLKIN: I2S clock = EXTERNAL I2S_CKIN + * @retval None + */ +void RCC_I2SCLKConfig(uint32_t RCC_I2SCLK) +{ + /* Check the parameters */ + assert_param(IS_RCC_I2SCLK(RCC_I2SCLK)); + + /* Clear I2SSEL bit */ + RCC->CCIPR &= ~RCC_CCIPR_I2SSEL; + + /* Set I2SSEL bits according to RCC_I2SCLK value */ + RCC->CCIPR |= RCC_I2SCLK; +} + + + +/** + * @brief Returns the frequencies of the System, AHB and APB busses clocks. + * @note The frequency returned by this function is not the real frequency + * in the chip. It is calculated based on the predefined constant and + * the source selected by RCC_SYSCLKConfig(): + * + * @note If SYSCLK source is HSI16, function returns constant HSI_VALUE(*) + * + * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**) + * + * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLLN and PLLM factors. + * + * @note (*) HSI_VALUE is a constant defined in ft32f0xx.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue(). + * + * @note (**) HSE_VALUE is a constant defined in ft32f0xx.h file (default value + * 24 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * return wrong result. + * + * @note (***) HSI48_VALUE is a constant defined in ft32f0xx.h file (default value + * 48 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * @note The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @note This function can be used by the user application to compute the + * baudrate for the communication peripherals or configure other parameters. + * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function + * must be called to update the structure's field. Otherwise, any + * configuration based on this function will be incorrect. + * + * @retval None + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks) +{ + uint32_t tmp = 0, pllmul = 0, pllnul = 0, pllp = 0, pllr = 0, pllq = 0, pllsource = 0, pllvcoclk = 0, pllpclk = 0, + pll2mul = 0, pll2nul = 0, pll2r = 0, pll2q = 0, pll2source = 0, pll2vcoclk = 0, + hpresc = 0, presc1 = 0, presc2 = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: /* HSE used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: /* PLL used as system clock */ + /* Get PLL clock source and pllm and plln factor ----------------------*/ + pllp = (((RCC -> PLLCFGR) & RCC_PLLCFGR_PLLP) >> 17); + pllsource = (((RCC -> PLLCFGR) & RCC_PLLCFGR_PLLSRC) >> 14); + pllnul = (((RCC -> PLLCFGR) & RCC_PLLCFGR_PLLN) >> 6); + pllmul = (RCC -> PLLCFGR) & RCC_PLLCFGR_PLLM; + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by pllmul and multiplicat by pllnul as pllvcoclk output */ + pllvcoclk = (HSI_VALUE * pllnul) / pllmul; + if (pllp == 0) + { + pllpclk = pllvcoclk / 2; + } + else + { + pllpclk = pllvcoclk / (pllp + 1); + } + } + else + { + /* HSE oscillator clock divided by pllmul and multiplicat by pllnul as pllvcoclk output */ + pllvcoclk = (HSE_VALUE * pllnul) / pllmul; + if (pllp == 0) + { + pllpclk = pllvcoclk / 2; + } + else + { + pllpclk = pllvcoclk / (pllp + 1); + } + } + + RCC_Clocks->SYSCLK_Frequency = pllpclk; + break; + + default: /* HSI used as system clock */ + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + /* Compute HCLK, PCLK and P2CLK clocks frequencies */ + /* Get HCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_HPRE; + tmp = tmp >> 4; + hpresc = APBAHBPrescTable[tmp]; + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = ((RCC_Clocks->SYSCLK_Frequency) >> hpresc); + + /* Get PCLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE1; + tmp = tmp >> 8; + presc1 = APBAHBPrescTable[tmp]; + /* PCLK clock frequency */ + RCC_Clocks->PCLK_Frequency = ((RCC_Clocks->HCLK_Frequency) >> presc1); + /* Get PLLQ and PLLR clk */ + pllr = (((RCC -> PLLCFGR) & RCC_PLLCFGR_PLLR) >> 26); + pllq = (((RCC -> PLLCFGR) & RCC_PLLCFGR_PLLQ) >> 21); + pllsource = (((RCC -> PLLCFGR) & RCC_PLLCFGR_PLLSRC) >> 14); + pllnul = (((RCC -> PLLCFGR) & RCC_PLLCFGR_PLLN) >> 6); + pllmul = (RCC -> PLLCFGR) & RCC_PLLCFGR_PLLM; + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by pllmul and multiplicat by pllnul as pllvcoclk output */ + pllvcoclk = (HSI_VALUE * pllnul) / pllmul; + if (pllq == 0) + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / (pllq + 1); + } + if (pllr == 0) + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / (pllr + 1); + } + } + else + { + /* HSE oscillator clock divided by pllmul and multiplicat by pllnul as pllvcoclk output */ + pllvcoclk = (HSE_VALUE * pllnul) / pllmul; + if (pllq == 0) + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / (pllq + 1); + } + if (pllr == 0) + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / (pllr + 1); + } + } + + /* Get P2CLK prescaler */ + tmp = RCC->CFGR & RCC_CFGR_PPRE2; + tmp = tmp >> 11; + presc2 = APBAHBPrescTable[tmp]; + /* PCLK clock frequency */ + RCC_Clocks->P2CLK_Frequency = ((RCC_Clocks->HCLK_Frequency) >> presc2); + /* Get PLL2Q and PLL2R clk */ + pll2r = (((RCC -> PLL2CFGR) & RCC_PLL2CFGR_PLL2R) >> 26); + pll2q = (((RCC -> PLL2CFGR) & RCC_PLL2CFGR_PLL2Q) >> 21); + pll2source = (((RCC -> PLL2CFGR) & RCC_PLL2CFGR_PLL2SRC) >> 14); + pll2nul = (((RCC -> PLL2CFGR) & RCC_PLL2CFGR_PLL2N) >> 6); + pll2mul = (RCC -> PLL2CFGR) & RCC_PLL2CFGR_PLL2M; + if (pll2source == 0x00) + { + /* HSI oscillator clock divided by pll2mul and multiplicat by pll2nul as pll2vcoclk output */ + pll2vcoclk = (HSI_VALUE * pll2nul) / pll2mul; + if (pll2q == 0) + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / (pll2q + 1); + } + if (pll2r == 0) + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / (pll2r + 1); + } + } + else + { + /* HSE oscillator clock divided by pll2mul and multiplicat by pll2nul as pll2vcoclk output */ + pll2vcoclk = (HSE_VALUE * pll2nul) / pll2mul; + if (pll2q == 0) + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLQ_Frequency = pllvcoclk / (pll2q + 1); + } + if (pll2r == 0) + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / 2; + } + else + { + RCC_Clocks->PLLR_Frequency = pllvcoclk / (pll2r + 1); + } + } + + /* QSPICLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_QSPISEL) == RESET) + { + RCC_Clocks->QSPICLK_Frequency = RCC_Clocks->SYSCLK_Frequency ; + } + else if ((RCC->CCIPR & RCC_CCIPR_QSPISEL) == RCC_CCIPR_QSPISEL_HSI16) + { + RCC_Clocks->QSPICLK_Frequency = HSI_VALUE; + } + else if ((RCC->CCIPR & RCC_CCIPR_QSPISEL) == RCC_CCIPR_QSPISEL_PLLQ) + { + RCC_Clocks->QSPICLK_Frequency = RCC_Clocks->PLLQ_Frequency; + } + + /* ADCCLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_ADCSEL) == RESET) + { + RCC_Clocks->ADCCLK_Frequency = RESET ; + } + else if ((RCC->CCIPR & RCC_CCIPR_ADCSEL) == RCC_CCIPR_ADCSEL_PLLR) + { + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PLLR_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_ADCSEL) == RCC_CCIPR_ADCSEL_SYS) + { + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + + /* CANCLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_CANSEL) == RCC_CCIPR_CANSEL_HD2) + { + RCC_Clocks->CANCLK_Frequency = (RCC_Clocks->HCLK_Frequency >> 1); + } + else if ((RCC->CCIPR & RCC_CCIPR_CANSEL) == RCC_CCIPR_CANSEL_HD4) + { + RCC_Clocks->CANCLK_Frequency = (RCC_Clocks->HCLK_Frequency >> 2); + } + else if ((RCC->CCIPR & RCC_CCIPR_CANSEL) == RCC_CCIPR_CANSEL_HD8) + { + RCC_Clocks->CANCLK_Frequency = (RCC_Clocks->HCLK_Frequency >> 3); + } + else if ((RCC->CCIPR & RCC_CCIPR_CANSEL) == RCC_CCIPR_CANSEL_HD16) + { + RCC_Clocks->CANCLK_Frequency = (RCC_Clocks->HCLK_Frequency >> 4); + } + else if ((RCC->CCIPR & RCC_CCIPR_CANSEL) == RCC_CCIPR_CANSEL_HD32) + { + RCC_Clocks->CANCLK_Frequency = (RCC_Clocks->HCLK_Frequency >> 5); + } + else + { + RCC_Clocks->CANCLK_Frequency = RCC_Clocks->HCLK_Frequency; + } + + /* LPTIMCLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_LPTIMSEL) == RCC_CCIPR_LPTIMSEL_PCLK) + { + RCC_Clocks->LPTIMCLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_LPTIMSEL) == RCC_CCIPR_LPTIMSEL_LSI) + { + RCC_Clocks->LPTIMCLK_Frequency = LSI_VALUE; + } + else if ((RCC->CCIPR & RCC_CCIPR_LPTIMSEL) == RCC_CCIPR_LPTIMSEL_HSI16) + { + RCC_Clocks->LPTIMCLK_Frequency = HSI_VALUE; + } + else if ((RCC->CCIPR & RCC_CCIPR_LPTIMSEL) == RCC_CCIPR_LPTIMSEL_LSE) + { + RCC_Clocks->LPTIMCLK_Frequency = LSE_VALUE; + } + + /* I2C3CLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_I2C3SEL) == RCC_CCIPR_I2C3SEL_PCLK) + { + RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_I2C3SEL) == RCC_CCIPR_I2C3SEL_SYS) + { + RCC_Clocks->I2C3CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_I2C3SEL) == RCC_CCIPR_I2C3SEL_HSI16) + { + RCC_Clocks->I2C3CLK_Frequency = HSI_VALUE; + } + + /* I2C2CLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_I2C2SEL) == RCC_CCIPR_I2C2SEL_PCLK) + { + RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_I2C2SEL) == RCC_CCIPR_I2C2SEL_SYS) + { + RCC_Clocks->I2C2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_I2C2SEL) == RCC_CCIPR_I2C2SEL_HSI16) + { + RCC_Clocks->I2C2CLK_Frequency = HSI_VALUE; + } + + /* I2C1CLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_I2C1SEL) == RCC_CCIPR_I2C1SEL_PCLK) + { + RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_I2C1SEL) == RCC_CCIPR_I2C1SEL_SYS) + { + RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_I2C1SEL) == RCC_CCIPR_I2C1SEL_HSI16) + { + RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE; + } + + /* LPUARTCLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_LPUARTSEL) == RCC_CCIPR_LPUARTSEL_PCLK) + { + RCC_Clocks->LPUARTCLK_Frequency = RCC_Clocks->PCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_LPUARTSEL) == RCC_CCIPR_LPUARTSEL_LSE) + { + RCC_Clocks->LPUARTCLK_Frequency = LSE_VALUE; + } + + /* PWMCLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_PWMSEL) == RCC_CCIPR_PWMSEL_SYS) + { + RCC_Clocks->PWMCLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_PWMSEL) == RCC_CCIPR_PWMSEL_SYSD2) + { + RCC_Clocks->PWMCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency >> 1); + } + else if ((RCC->CCIPR & RCC_CCIPR_PWMSEL) == RCC_CCIPR_PWMSEL_SYSD4) + { + RCC_Clocks->PWMCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency >> 2); + } + + /* EQEPCLK clock frrequency */ + if ((RCC->CCIPR & RCC_CCIPR_EQEPSEL) == RCC_CCIPR_EQEPSEL_SYS) + { + RCC_Clocks->EQEPCLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_EQEPSEL) == RCC_CCIPR_EQEPSEL_SYSD2) + { + RCC_Clocks->EQEPCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency >> 1); + } + else if ((RCC->CCIPR & RCC_CCIPR_EQEPSEL) == RCC_CCIPR_EQEPSEL_SYSD4) + { + RCC_Clocks->EQEPCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency >> 2); + } + + /* ECAPCLK clock frrequency */ + if ((RCC->CCIPR & RCC_CCIPR_ECAPSEL) == RCC_CCIPR_ECAPSEL_SYS) + { + RCC_Clocks->ECAPCLK_Frequency = RCC_Clocks->SYSCLK_Frequency; + } + else if ((RCC->CCIPR & RCC_CCIPR_ECAPSEL) == RCC_CCIPR_ECAPSEL_SYSD2) + { + RCC_Clocks->ECAPCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency >> 1); + } + else if ((RCC->CCIPR & RCC_CCIPR_ECAPSEL) == RCC_CCIPR_ECAPSEL_SYSD4) + { + RCC_Clocks->ECAPCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency >> 2); + } + + /* I2SCLK clock frequency */ + if ((RCC->CCIPR & RCC_CCIPR_I2SSEL) == RESET) + { + RCC_Clocks->I2SCLK_Frequency = RCC_Clocks->PLL2Q_Frequency; + } + else + { + RCC_Clocks->I2SCLK_Frequency = ((uint32_t)0x00000000);//I2S_CKIN; + } +} +/** + * @} + */ + +/** + * @brief Configures the LSCO clock (LSCOCLK). + * @note As the LSCO clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the LSCO clock source (to be done once after reset). + * @param RCC_LSCOCLKSource: specifies the LSCO clock source. + * This parameter can be one of the following values: + * @arg RCC_LSCOCLK_LSE: LSE selected as LSCO clock + * @arg RCC_LSCOCLK_LSI: LSI selected as LSCO clock + * @retval None + */ +void RCC_LSCOCLKConfig(uint32_t RCC_LSCOCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_LSCOCLK_SRC(RCC_LSCOCLKSource)); + + /* Select the LSCO clock source */ + RCC->BDCR |= RCC_LSCOCLKSource; +} + +/** + * @brief Enables or disables the LSCO clock. + * @note This function must be used only after the LSCO clock source was selected + * using the RCC_LSCOCLKConfig function. + * @param NewState: new state of the RTC clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_LSCOCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= RCC_LSCOCLK_ON; + } + else + { + RCC->BDCR &= ~RCC_LSCOCLK_ON; + } +} + +/** + * @brief Configures the RTC clock (RTCCLK). + * @note As the RTC clock configuration bits are in the Backup domain and write + * access is denied to this domain after reset, you have to enable write + * access using PWR_BackupAccessCmd(ENABLE) function before to configure + * the RTC clock source (to be done once after reset). + * @note Once the RTC clock is configured it can't be changed unless the RTC + * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR) + * @param RCC_RTCCLKSource: specifies the RTC clock source. + * This parameter can be one of the following values: + * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock + * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock + * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock + * @note If the LSE or LSI is used as RTC clock source, the RTC continues to + * work in STOP and STANDBY modes, and can be used as wakeup source. + * However, when the HSE clock is used as RTC clock source, the RTC + * cannot be used in STOP and STANDBY modes. + * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as + * RTC clock source). + * @retval None + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + /* Check the parameters */ + assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource)); + + /* Select the RTC clock source */ + RCC->BDCR |= RCC_RTCCLKSource; +} + +/** + * @brief Enables or disables the RTC clock. + * @note This function must be used only after the RTC clock source was selected + * using the RCC_RTCCLKConfig function. + * @param NewState: new state of the RTC clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= RCC_BDCR_RTCEN; + } + else + { + RCC->BDCR &= ~RCC_BDCR_RTCEN; + } +} + +/** + * @brief Forces or releases the Backup domain reset. + * @note This function resets the RTC peripheral (including the backup registers) + * and the RTC clock source selection in RCC_BDCR register. + * @param NewState: new state of the Backup domain reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->BDCR |= RCC_BDCR_BDRST; + } + else + { + RCC->BDCR &= ~RCC_BDCR_BDRST; + } +} + +/** + * @brief Enables or disables the AHB1 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHB1Periph: specifies the AHB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1Periph_USBOTGHS: USBOTGHS clock + * @arg RCC_AHB1Periph_ETHMACPTP: ETHMACPTP clock + * @arg RCC_AHB1Periph_ETHMACRX: ETHMACRX clock + * @arg RCC_AHB1Periph_ETHMACTX: ETHMACTX clock + * @arg RCC_AHB1Periph_ETHMAC: ETHMAC clock + * @arg RCC_AHB1Periph_DMA2: DMA2 clock + * @arg RCC_AHB1Periph_DMA1: DMA1 clock + * @arg RCC_AHB1Periph_CCMDATARAM: CCMDATARAM clock + * @arg RCC_AHB1Periph_BKPSRAM: BKPSRAM clock + * @arg RCC_AHB1Periph_CRC: CRC clock + * @arg RCC_AHB1Periph_GPIOH: GPIOH clock + * @arg RCC_AHB1Periph_GPIOE: GPIOE clock + * @arg RCC_AHB1Periph_GPIOD: GPIOD clock + * @arg RCC_AHB1Periph_GPIOC: GPIOC clock + * @arg RCC_AHB1Periph_GPIOB: GPIOB clock + * @arg RCC_AHB1Periph_GPIOA: GPIOA clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1_PERIPH(RCC_AHB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1ENR |= RCC_AHB1Periph; + volatile uint32_t tmpreg = RCC->AHB1ENR; + (void)tmpreg; + } + else + { + RCC->AHB1ENR &= ~RCC_AHB1Periph; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHB2Periph: specifies the AHB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2Periph_USBOTGFS: USBOTGFS clock + * @arg RCC_AHB2Periph_RNG: RNG clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2ENR |= RCC_AHB2Periph; + volatile uint32_t tmpreg = RCC->AHB2ENR; + (void)tmpreg; + } + else + { + RCC->AHB2ENR &= ~RCC_AHB2Periph; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_AHB3Periph: specifies the AHB3 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB3Periph_QSPI: QSPI clock + * @arg RCC_AHB3Periph_FMC: FMC clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3ENR |= RCC_AHB3Periph; + volatile uint32_t tmpreg = RCC->AHB3ENR; + (void)tmpreg; + } + else + { + RCC->AHB3ENR &= ~RCC_AHB3Periph; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB1) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1Periph_USART7: USART7 clock + * @arg RCC_APB1Periph_RAMP: RAMP clock + * @arg RCC_APB1Periph_DAC: DAC clock + * @arg RCC_APB1Periph_PWR: PWR clock + * @arg RCC_APB1Periph_CAN4: CAN4 clock + * @arg RCC_APB1Periph_CAN3: CAN3 clock + * @arg RCC_APB1Periph_CAN2: CAN2 clock + * @arg RCC_APB1Periph_CAN1: CAN1 clock + * @arg RCC_APB1Periph_I2C3: I2C3 clock + * @arg RCC_APB1Periph_I2C2: I2C2 clock + * @arg RCC_APB1Periph_I2C1: I2C1 clock + * @arg RCC_APB1Periph_UART5: UART5 clock + * @arg RCC_APB1Periph_UART4: UART4 clock + * @arg RCC_APB1Periph_UART3: UART3 clock + * @arg RCC_APB1Periph_UART2: UART2 clock + * @arg RCC_APB1Periph_LPUART: LPUART clock + * @arg RCC_APB1Periph_SPI3: SPI3 clock + * @arg RCC_APB1Periph_SPI2: SPI2 clock + * @arg RCC_APB1Periph_I2S3: I2S3 clock + * @arg RCC_APB1Periph_I2S2: I2S2 clock + * @arg RCC_APB1Periph_WWDG: WWDG clock + * @arg RCC_APB1Periph_AC97: AC97 clock + * @arg RCC_APB1Periph_CRS: CRS clock + * @arg RCC_APB1Periph_TIM14: TIM14 clock + * @arg RCC_APB1Periph_TIM13: TIM13 clock + * @arg RCC_APB1Periph_TIM12: TIM12 clock + * @arg RCC_APB1Periph_TIM7: TIM7 clock + * @arg RCC_APB1Periph_TIM6: TIM6 clock + * @arg RCC_APB1Periph_TIM5: TIM5 clock + * @arg RCC_APB1Periph_TIM4: TIM4 clock + * @arg RCC_APB1Periph_TIM3: TIM3 clock + * @arg RCC_APB1Periph_TIM2: TIM2 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1ENR |= RCC_APB1Periph; + volatile uint32_t tmpreg = RCC->APB1ENR; + (void)tmpreg; + } + else + { + RCC->APB1ENR &= ~RCC_APB1Periph; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB2) peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2Periph_TBCLK: TBCLK clock + * @arg RCC_APB2Periph_EQEP: EQEP clock + * @arg RCC_APB2Periph_ECAP: ECAP clock + * @arg RCC_APB2Periph_EPWM4: EPWM4 clock + * @arg RCC_APB2Periph_EPWM3: EPWM3 clock + * @arg RCC_APB2Periph_EPWM2: EPWM2 clock + * @arg RCC_APB2Periph_EPWM1: EPWM1 clock + * @arg RCC_APB2Periph_TIM11: TIM11 clock + * @arg RCC_APB2Periph_TIM10: TIM10 clock + * @arg RCC_APB2Periph_TIM9: TIM9 clock + * @arg RCC_APB2Periph_LPTIM: LPTIM clock + * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock + * @arg RCC_APB2Periph_SPI1: SPI1 clock + * @arg RCC_APB2Periph_SDIO: SDIO clock + * @arg RCC_APB2Periph_SPD: SPD clock + * @arg RCC_APB2Periph_ADC: ADC clock + * @arg RCC_APB2Periph_USART6: USART6 clock + * @arg RCC_APB2Periph_USART1: USART1 clock + * @arg RCC_APB2Periph_TIM8: TIM8 clock + * @arg RCC_APB2Periph_TIM1: TIM1 clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2ENR |= RCC_APB2Periph; + volatile uint32_t tmpreg = RCC->APB2ENR; + (void)tmpreg; + } + else + { + RCC->APB2ENR &= ~RCC_APB2Periph; + } +} + +/** + * @brief Enables or disables the AHB1 peripheral low-power clock. + * @note while enter sleep, want periph will work contiue, shoule enable + * this periph's lpen. + * @param RCC_AHB1PeriphLpen: specifies the AHB1 peripheral low-power to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1PeriphLpen_USBOTGHS: USBOTGHS low-power clock + * @arg RCC_AHB1PeriphLpen_ETHMACPTP: ETHMACPTP low-power clock + * @arg RCC_AHB1PeriphLpen_ETHMACRX: ETHMACRX low-power clock + * @arg RCC_AHB1PeriphLpen_ETHMACTX: ETHMACTX low-power clock + * @arg RCC_AHB1PeriphLpen_ETHMAC: ETHMAC low-power clock + * @arg RCC_AHB1PeriphLpen_DMA2: DMA2 low-power clock + * @arg RCC_AHB1PeriphLpen_DMA1: DMA1 low-power clock + * @arg RCC_AHB1PeriphLpen_CCMDATARAM: CCMDATARAM low-power clock + * @arg RCC_AHB1PeriphLpen_BKPSRAM: BKPSRAM low-power clock + * @arg RCC_AHB1PeriphLpen_CRC: CRC low-power clock + * @arg RCC_AHB1PeriphLpen_GPIOH: GPIOH low-power clock + * @arg RCC_AHB1PeriphLpen_GPIOE: GPIOE low-power clock + * @arg RCC_AHB1PeriphLpen_GPIOD: GPIOD low-power clock + * @arg RCC_AHB1PeriphLpen_GPIOC: GPIOC low-power clock + * @arg RCC_AHB1PeriphLpen_GPIOB: GPIOB low-power clock + * @arg RCC_AHB1PeriphLpen_GPIOA: GPIOA low-power clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphLpenCmd(uint32_t RCC_AHB1PeriphLpen, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1LP_PERIPH(RCC_AHB1PeriphLpen)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1LPENR |= RCC_AHB1PeriphLpen; + } + else + { + RCC->AHB1LPENR &= ~RCC_AHB1PeriphLpen; + } +} + +/** + * @brief Enables or disables the AHB2 peripheral low-power clock. + * @note while enter sleep, want periph will work contiue, shoule enable + * this periph's lpen. + * @param RCC_AHB2PeriphLpen: specifies the AHB2 peripheral low-power to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2PeriphLpen_USBOTGFS: USBOTGFS low-power clock + * @arg RCC_AHB2PeriphLpen_RNG: RNG low-power clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphLpenCmd(uint32_t RCC_AHB2PeriphLpen, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2LP_PERIPH(RCC_AHB2PeriphLpen)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2LPENR |= RCC_AHB2PeriphLpen; + } + else + { + RCC->AHB2LPENR &= ~RCC_AHB2PeriphLpen; + } +} + +/** + * @brief Enables or disables the AHB3 peripheral low-power clock. + * @note while enter sleep, want periph will work contiue, shoule enable + * this periph's lpen. + * @param RCC_AHB3PeriphLpen: specifies the AHB3 peripheral low-power to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_AHB3PeriphLpen_QSPI: QSPI low-power clock + * @arg RCC_AHB3PeriphLpen_FMC: FMC low-power clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphLpenCmd(uint32_t RCC_AHB3PeriphLpen, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2LP_PERIPH(RCC_AHB3PeriphLpen)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3LPENR |= RCC_AHB3PeriphLpen; + } + else + { + RCC->AHB3LPENR &= ~RCC_AHB3PeriphLpen; + } +} + +/** + * @brief Enables or disables the High Speed APB (APB1) peripheral low-power clock. + * @note while enter sleep, want periph will work contiue, shoule enable + * this periph's lpen. + * @param RCC_APB1PeriphLpen: specifies the APB1 peripheral low-power to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB1PeriphLpen_UART7: UART7 low-power clock + * @arg RCC_APB1PeriphLpen_RAMP: RAMP low-power clock + * @arg RCC_APB1PeriphLpen_DAC: DAC low-power clock + * @arg RCC_APB1PeriphLpen_PWR: PWR low-power clock + * @arg RCC_APB1PeriphLpen_CAN4: CAN4 low-power clock + * @arg RCC_APB1PeriphLpen_CAN3: CAN3 low-power clock + * @arg RCC_APB1PeriphLpen_CAN2: CAN2 low-power clock + * @arg RCC_APB1PeriphLpen_CAN1: CAN1 low-power clock + * @arg RCC_APB1PeriphLpen_I2C3: I2C3 low-power clock + * @arg RCC_APB1PeriphLpen_I2C2: I2C2 low-power clock + * @arg RCC_APB1PeriphLpen_I2C1: I2C1 low-power clock + * @arg RCC_APB1PeriphLpen_UART5: UART5 low-power clock + * @arg RCC_APB1PeriphLpen_UART4: UART4 low-power clock + * @arg RCC_APB1PeriphLpen_UART3: UART3 low-power clock + * @arg RCC_APB1PeriphLpen_UART2: UART2 low-power clock + * @arg RCC_APB1PeriphLpen_LPUART: LPUART low-power clock + * @arg RCC_APB1PeriphLpen_SPI3: SPI3 low-power clock + * @arg RCC_APB1PeriphLpen_SPI2: SPI2 low-power clock + * @arg RCC_APB1PeriphLpen_I2S3: I2S3 low-power clock + * @arg RCC_APB1PeriphLpen_I2S2: I2S2 low-power clock + * @arg RCC_APB1PeriphLpen_WWDG: WWDG low-power clock + * @arg RCC_APB1PeriphLpen_AC97: AC97 low-power clock + * @arg RCC_APB1PeriphLpen_CRS: CRS low-power clock + * @arg RCC_APB1PeriphLpen_TIM14: TIM14 low-power clock + * @arg RCC_APB1PeriphLpen_TIM13: TIM13 low-power clock + * @arg RCC_APB1PeriphLpen_TIM12: TIM12 low-power clock + * @arg RCC_APB1PeriphLpen_TIM7: TIM7 low-power clock + * @arg RCC_APB1PeriphLpen_TIM6: TIM6 low-power clock + * @arg RCC_APB1PeriphLpen_TIM5: TIM5 low-power clock + * @arg RCC_APB1PeriphLpen_TIM4: TIM4 low-power clock + * @arg RCC_APB1PeriphLpen_TIM3: TIM3 low-power clock + * @arg RCC_APB1PeriphLpen_TIM2: TIM2 low-power clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphLpenCmd(uint32_t RCC_APB1PeriphLpen, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1LP_PERIPH(RCC_APB1PeriphLpen)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1LPENR |= RCC_APB1PeriphLpen; + } + else + { + RCC->APB1LPENR &= ~RCC_APB1PeriphLpen; + } +} + +/** + * @brief Enables or disables the Low Speed APB (APB2) peripheral low-power clock. + * @note while enter sleep, want periph will work contiue, shoule enable + * this periph's lpen. + * @param RCC_APB2PeriphLpen: specifies the APB2 peripheral low-power to gates its clock. + * This parameter can be any combination of the following values: + * @arg RCC_APB2PeriphLpen_TBCLK: TBCLK low-power clock + * @arg RCC_APB2PeriphLpen_EQEP: EQEP low-power clock + * @arg RCC_APB2PeriphLpen_ECAP: ECAP low-power clock + * @arg RCC_APB2PeriphLpen_EPWM4: EPWM4 low-power clock + * @arg RCC_APB2PeriphLpen_EPWM3: EPWM3 low-power clock + * @arg RCC_APB2PeriphLpen_EPWM2: EPWM2 low-power clock + * @arg RCC_APB2PeriphLpen_EPWM1: EPWM1 low-power clock + * @arg RCC_APB2PeriphLpen_TIM11: TIM11 low-power clock + * @arg RCC_APB2PeriphLpen_TIM10: TIM10 low-power clock + * @arg RCC_APB2PeriphLpen_TIM9: TIM9 low-power clock + * @arg RCC_APB2PeriphLpen_LPTIM: LPTIM low-power clock + * @arg RCC_APB2PeriphLpen_SYSCFG: SYSCFG low-power clock + * @arg RCC_APB2PeriphLpen_SPI1: SPI1 low-power clock + * @arg RCC_APB2PeriphLpen_SDIO: SDIO low-power clock + * @arg RCC_APB2PeriphLpen_SPD: SPD low-power clock + * @arg RCC_APB2PeriphLpen_ADC: ADC low-power clock + * @arg RCC_APB2PeriphLpen_USART6: USART6 low-power clock + * @arg RCC_APB2PeriphLpen_USART1: USART1 low-power clock + * @arg RCC_APB2PeriphLpen_TIM8: TIM8 low-power clock + * @arg RCC_APB2PeriphLpen_TIM1: TIM1 low-power clock + * @param NewState: new state of the specified peripheral clock. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphLpenCmd(uint32_t RCC_APB2PeriphLpen, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2LP_PERIPH(RCC_APB2PeriphLpen)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2LPENR |= RCC_APB2PeriphLpen; + } + else + { + RCC->APB2LPENR &= ~RCC_APB2PeriphLpen; + } +} + +/** + * @brief Forces or releases AHB1 peripheral reset. + * @param RCC_AHB1PeriphRst: specifies the AHB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB1PeriphRst_USBOTGHS: USBOTGHS reset + * @arg RCC_AHB1PeriphRst_ETHMAC: ETHMAC reset + * @arg RCC_AHB1PeriphRst_DMA2: DMA2 reset + * @arg RCC_AHB1PeriphRst_DMA1: DMA1 reset + * @arg RCC_AHB1PeriphRst_CRC: CRC reset + * @arg RCC_AHB1PeriphRst_GPIOH: GPIOH reset + * @arg RCC_AHB1PeriphRst_GPIOE: GPIOE reset + * @arg RCC_AHB1PeriphRst_GPIOD: GPIOD reset + * @arg RCC_AHB1PeriphRst_GPIOC: GPIOC reset + * @arg RCC_AHB1PeriphRst_GPIOB: GPIOB reset + * @arg RCC_AHB1PeriphRst_GPIOA: GPIOA reset + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1PeriphRst, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB1RST_PERIPH(RCC_AHB1PeriphRst)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB1RSTR |= RCC_AHB1PeriphRst; + } + else + { + RCC->AHB1RSTR &= ~RCC_AHB1PeriphRst; + } +} + +/** + * @brief Forces or releases AHB2 peripheral reset. + * @param RCC_AHB2PeriphRst: specifies the AHB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB2PeriphRst_USBOTGFS: USBOTGFS reset + * @arg RCC_AHB2PeriphRst_RNG: RNG reset + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2PeriphRst, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB2RST_PERIPH(RCC_AHB2PeriphRst)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB2RSTR |= RCC_AHB2PeriphRst; + } + else + { + RCC->AHB2RSTR &= ~RCC_AHB2PeriphRst; + } +} + +/** + * @brief Forces or releases AHB3 peripheral reset. + * @param RCC_AHB3PeriphRst: specifies the AHB3 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_AHB3PeriphRst_QSPI: QSPI reset + * @arg RCC_AHB3PeriphRst_FMC: FMC reset + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3PeriphRst, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_AHB3RST_PERIPH(RCC_AHB3PeriphRst)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->AHB3RSTR |= RCC_AHB3PeriphRst; + } + else + { + RCC->AHB3RSTR &= ~RCC_AHB3PeriphRst; + } +} + +/** + * @brief Forces or releases High Speed APB (APB1) peripheral reset. + * @param RCC_APB1PeriphRst: specifies the APB1 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB1PeriphRst_UART7: UART7 reset + * @arg RCC_APB1PeriphRst_DAC: DAC reset + * @arg RCC_APB1PeriphRst_PWR: PWR reset + * @arg RCC_APB1PeriphRst_CAN4: CAN4 reset + * @arg RCC_APB1PeriphRst_CAN3: CAN3 reset + * @arg RCC_APB1PeriphRst_CAN2: CAN2 reset + * @arg RCC_APB1PeriphRst_CAN1: CAN1 reset + * @arg RCC_APB1PeriphRst_I2C3: I2C3 reset + * @arg RCC_APB1PeriphRst_I2C2: I2C2 reset + * @arg RCC_APB1PeriphRst_I2C1: I2C1 reset + * @arg RCC_APB1PeriphRst_UART5: UART5 reset + * @arg RCC_APB1PeriphRst_UART4: UART4 reset + * @arg RCC_APB1PeriphRst_UART3: UART3 reset + * @arg RCC_APB1PeriphRst_UART2: UART2 reset + * @arg RCC_APB1PeriphRst_LPUART: LPUART reset + * @arg RCC_APB1PeriphRst_SPI3: SPI3 reset + * @arg RCC_APB1PeriphRst_SPI2: SPI2 reset + * @arg RCC_APB1PeriphRst_I2S3: I2S3 reset + * @arg RCC_APB1PeriphRst_I2S2: I2S2 reset + * @arg RCC_APB1PeriphRst_WWDG: WWDG reset + * @arg RCC_APB1PeriphRst_AC97: AC97 reset + * @arg RCC_APB1PeriphRst_CRS: CRS reset + * @arg RCC_APB1PeriphRst_TIM14: TIM14 reset + * @arg RCC_APB1PeriphRst_TIM13: TIM13 reset + * @arg RCC_APB1PeriphRst_TIM12: TIM12 reset + * @arg RCC_APB1PeriphRst_TIM7: TIM7 reset + * @arg RCC_APB1PeriphRst_TIM6: TIM6 reset + * @arg RCC_APB1PeriphRst_TIM5: TIM5 reset + * @arg RCC_APB1PeriphRst_TIM4: TIM4 reset + * @arg RCC_APB1PeriphRst_TIM3: TIM3 reset + * @arg RCC_APB1PeriphRst_TIM2: TIM2 reset + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1PeriphRst, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB1RST_PERIPH(RCC_APB1PeriphRst)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB1RSTR |= RCC_APB1PeriphRst; + } + else + { + RCC->APB1RSTR &= ~RCC_APB1PeriphRst; + } +} + +/** + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * @param RCC_APB2PeriphRst: specifies the APB2 peripheral to reset. + * This parameter can be any combination of the following values: + * @arg RCC_APB2PeriphRst_EQEP: EQEP reset + * @arg RCC_APB2PeriphRst_ECAP: ECAP reset + * @arg RCC_APB2PeriphRst_EPWM4: EPWM4 reset + * @arg RCC_APB2PeriphRst_EPWM3: EPWM3 reset + * @arg RCC_APB2PeriphRst_EPWM2: EPWM2 reset + * @arg RCC_APB2PeriphRst_EPWM1: EPWM1 reset + * @arg RCC_APB2PeriphRst_TIM11: TIM11 reset + * @arg RCC_APB2PeriphRst_TIM10: TIM10 reset + * @arg RCC_APB2PeriphRst_TIM9: TIM9 reset + * @arg RCC_APB2PeriphRst_LPTIM: LPTIM reset + * @arg RCC_APB2PeriphRst_SYSCFG: SYSCFG reset + * @arg RCC_APB2PeriphRst_SPI1: SPI1 reset + * @arg RCC_APB2PeriphRst_SDIO: SDIO reset + * @arg RCC_APB2PeriphRst_SPD: SPD reset + * @arg RCC_APB2PeriphRst_ADC: ADC reset + * @arg RCC_APB2PeriphRst_USART6: USART6 reset + * @arg RCC_APB2PeriphRst_USART1: USART1 reset + * @arg RCC_APB2PeriphRst_TIM8: TIM8 reset + * @arg RCC_APB2PeriphRst_TIM1: TIM1 reset + * @param NewState: new state of the specified peripheral reset. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2PeriphRst, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_APB2RST_PERIPH(RCC_APB2PeriphRst)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + RCC->APB2RSTR |= RCC_APB2PeriphRst; + } + else + { + RCC->APB2RSTR &= ~RCC_APB2PeriphRst; + } +} +/** + * @} + */ + +/** + * @brief Checks whether the specified RCC flag is set or not. + * @param RCC_FLAG_REG: the flag in which register. + * This parameter can be one of the following values: + * @arg RCC_FLAG_REG_CR: The flag in cr register + * @arg RCC_FLAG_REG_CR2: The flag in cr2 register + * @arg RCC_FLAG_REG_BDCR:The flag in bdcr register + * @arg RCC_FLAG_REG_CSR: The flag in csr register + * @param RCC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready + * @arg RCC_FLAG_PLLRDY: PLL clock ready + * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready + * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready + * @arg RCC_FLAG_HSI48RDY:HSI48 oscillator clock ready + * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready + * @arg RCC_FLAG_LPWRRST: Low Power reset + * @arg RCC_FLAG_WWDGRST: Window Watchdog reset + * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset + * @arg RCC_FLAG_SFTRST: Software reset + * @arg RCC_FLAG_PORRST: POR/PDR reset + * @arg RCC_FLAG_PINRST: Pin reset + * @arg RCC_FLAG_RMVF: Remove all reset flag + * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @retval The new state of RCC_FLAG (SET or RESET). + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG_REG, uint32_t RCC_FLAG) +{ + uint8_t tmp = 0; + uint32_t statusreg = 0; + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_FLAG_REG(RCC_FLAG_REG)); + assert_param(IS_RCC_FLAG(RCC_FLAG)); + + /* Get the RCC register index */ + tmp = RCC_FLAG_REG; + + if (tmp == 0) /* The flag to check is in CR register */ + { + statusreg = RCC->CR; + } + else if (tmp == 1) /* The flag to check is in CR2 register */ + { + statusreg = RCC->CR2; + } + else if (tmp == 2) /* The flag to check is in BDCR register */ + { + statusreg = RCC->BDCR; + } + else /* The flag to check is in CSR register */ + { + statusreg = RCC->CSR; + } + + if ((statusreg & RCC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC reset flags. + * The reset flags are: RCC_FLAG_PINRSTF, RCC_FLAG_PORRSTF, RCC_FLAG_SFTRSTF, + * RCC_FLAG_IWDGRSTF, RCC_FLAG_WWDGRSTF, RCC_FLAG_LPWRRSTF. + * @param None + * @retval None + */ +void RCC_ClrRstFlag(void) +{ + /* Set RMVF bit to clear the reset flags */ + RCC->CSR |= RCC_CSR_RMVF; +} + +/** + * @brief Enables or disables the specified RCC interrupts. + * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled + * and if the HSE clock fails, the CSS interrupt occurs and an NMI is + * automatically generated. The NMI will be executed indefinitely, and + * since NMI has higher priority than any other IRQ (and main program) + * the application will be stacked in the NMI ISR unless the CSS interrupt + * pending bit is cleared. + * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RCC_ITEN_PLL2RDY: PLL2 ready interrupt enable + * @arg RCC_ITEN_PLLRDY: PLL ready interrupt enable + * @arg RCC_ITEN_HSERDY: HSE ready interrupt enable + * @arg RCC_ITEN_HSI48RDY: HSI48 ready interrupt enable + * @arg RCC_ITEN_HSIRDY: HSI ready interrupt enable + * @arg RCC_ITEN_LSERDY: LSE ready interrupt enable + * @arg RCC_ITEN_LSIRDY: LSI ready interrupt enable + * @param NewState: new state of the specified RCC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RCC_ITConfig(uint32_t RCC_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RCC_ITEN(RCC_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* enable the selected interrupts */ + RCC->CIR |= RCC_IT; + } + else + { + /* disable the selected interrupts */ + RCC->CIR &= ~RCC_IT; + } +} + +/** + * @brief Checks whether the specified RCC interrupt flag is set or not. + * @param RCC_IT_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RCC_ITFLAG_CSS: CSS clock secure system interrupt flag + * @arg RCC_ITFLAG_PLL2RDY: PLL2 clock ready interrupt flag + * @arg RCC_ITFLAG_PLLRDY: PLL clock ready interrupt flag + * @arg RCC_ITFLAG_HSERDY: HSE oscillator clock ready interrupt flag + * @arg RCC_ITFLAG_HSI48RDY: HSI48 oscillator clock ready interrupt flag + * @arg RCC_ITFLAG_HSIRDY: HSI oscillator clock ready interrupt flag + * @arg RCC_ITFLAG_LSIRDY: LSI oscillator clock ready interrupt flag + * @arg RCC_ITFLAG_LSERDY: LSE oscillator clock ready interrupt flag + * @retval The new state of RCC_FLAG (SET or RESET). + */ +ITStatus RCC_GetITStatus(uint32_t RCC_IT_FLAG) +{ + uint32_t statusreg = 0; + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_RCC_ITFLAG(RCC_IT_FLAG)); + + /* Get the interrupts flag */ + statusreg = RCC->CIR; + + if ((statusreg & RCC_IT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + /* Return the flag status */ + return bitstatus; +} + +/** + * @brief Clears the RCC's interrupt pending bits. + * @param RCC_IT_CLR: specifies the interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RCC_ITCLR_CSS: Clear Clock Security System interrupt Pending + * @arg RCC_ITCLR_PLL2RDY: Clear PLL2 ready interrupt Pending + * @arg RCC_ITCLR_PLLRDY: Clear PLL ready interrupt Pending + * @arg RCC_ITCLR_HSERDY: Clear HSE ready interrupt Pending + * @arg RCC_ITCLR_HSI48RDY: Clear HSI48 ready interrupt Pending + * @arg RCC_ITCLR_HSIRDY: Clear HSI ready interrupt Pending + * @arg RCC_ITCLR_LSERDY: Clear LSE ready interrupt Pending + * @arg RCC_ITCLR_LSIRDY: Clear LSI ready interrupt Pending + * @retval None + */ +void RCC_ClearITPendingBit(uint32_t RCC_IT_CLR) +{ + /* Check the parameters */ + assert_param(IS_RCC_ITCLR(RCC_IT_CLR)); + + /* Clear the selected interrupt pending bits */ + RCC->CIR |= RCC_IT_CLR; +} + +/** + * @brief Select the RAM Control by themself or AHB. + * @param RCC_RAM_CTL: specifies the RAM. + * This parameter can be any combination of the following values: + * @arg RCC_DCACHE_CTL: Dcache Ram Control by Dcache or AHB + * @arg RCC_ICACHE_CTL: Icache Ram Control by Icache or AHB + * @arg RCC_ETHMAC_CTL: Ethmac Ram Control by Ethmac or AHB + * @arg RCC_CAN_CTL: Can Ram Control by Can or AHB + * @arg RCC_USBHS_CTL: Usbhs Ram Control by Usbhs or AHB + * @arg RCC_USBFS_CTL: Usbfs Ram Control by Usbfs or AHB + * @param RCC_RAM_CTL_SEL: specifies the RAM Control by Themself or AHB. + * This parameter can be any combination of the following values: + * @arg RCC_RAM_CTL_SELF: Ram Control by Themself + * @arg RCC_RAM_CTL_AHB: Ram Control by AHB + * @retval None + */ +void RCC_RamCtrlSel(uint32_t RCC_RAM_CTL, uint32_t RCC_RAM_CTL_SEL) +{ + /* Check the parameters */ + assert_param(IS_RCC_RAMCTL(RCC_RAM_CTL)); + assert_param(IS_RCC_RAMCTL_SEL(RCC_RAM_CTL_SEL)); + + if (RCC_RAM_CTL_SEL == RCC_RAM_CTL_SELF) + { + /* Select the Ram Control by Themself */ + RCC->RAMCTL &= ~RCC_RAM_CTL; + } + else if (RCC_RAM_CTL_SEL == RCC_RAM_CTL_AHB) + { + /* Select the Ram Control by AHB */ + RCC->RAMCTL |= RCC_RAM_CTL; + } +} +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rng.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rng.c new file mode 100644 index 00000000000..26c94031b3d --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rng.c @@ -0,0 +1,103 @@ +/* ****************************************************************************** + * @file ft32f0xx_dac.c + * @author FMD xzhang + * @brief This file provides firmware functions to manage the following + * functionalities of RNG peripheral + * @version V1.0.0 + * @data 2025-03-11 + *******************************************************************************/ +#include "ft32f4xx_rng.h" +/*RNG initial config include:1 rng_clk config (48mhz) + * 2 rng enable + * 3 rng interrupt enable + */ +/** + * @brief Initializes the RNG peripheral. + * @param + * @retval + */ +void RNG_Init() +{ + /* Enable the RNG Peripheral */ + RNG -> RNG_CR |= RNG_EN; +} + +/** + * @brief DeInitializes the RNG peripheral and all register. + * @param NewState: new state of the configed undervoltage reset :BOR_EN. + * This parameter can be: ENABLE or DISABLE. + * @retval + */ +void RNG_DeInit(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Disable the RNG Peripheral */ + RNG -> RNG_CR &= ~RNG_EN; + /* Disable the RNG interrupt and SEIS CEIS */ + RNG -> RNG_CR &= ~RNG_IE; + /* SEIS and CEIS RC_W0 */ + RNG -> RNG_SR &= ~RNG_SEIS; + RNG -> RNG_SR &= ~RNG_CEIS; + } +} +/** + * @brief Generates a 32-bit random number. + * @note When no more random number data is available in DR register, RNG_DRDY + * flag is automatically cleared. + * @retval + */ +uint32_t RNG_GenerateRandomNumber() +{ + uint32_t random32bit; + /* Check if data register contains valid random data */ + if ((RNG->RNG_SR & RNG_DRDY) == RNG_DRDY) + { + //if DRDY is ready random data can be read + random32bit = RNG -> RNG_DR; //if random data is read DRDY will be clear auto + } + return random32bit; +} + + +/** + * @brief enable interrupt mode. + * @param NewState: new state of the configed undervoltage reset :BOR_EN. + * This parameter can be: ENABLE or DISABLE. + * @retval + */ +void RNG_IT(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ + RNG -> RNG_CR |= RNG_IE; + } + else + { + RNG -> RNG_CR &= ~RNG_IE; + } +} +/** + * @brief Back ERROR status include SEIS:0x01 SECS:0x02 CEIS:0x10 CECS:0x20. + * @param + * @retval + */ +uint8_t RNG_get_error_status() +{ + + uint8_t bit_status; + if ((RNG -> RNG_CR & RNG_IE) == RNG_IE) + { + + if (((RNG -> RNG_SR) & RNG_SECS) == RNG_SECS) + + bit_status = 0x01; + + if ((RNG -> RNG_SR & RNG_CECS) == RNG_CECS) + + bit_status = 0x10; + } + return bit_status; +} + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rtc.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rtc.c new file mode 100644 index 00000000000..192b603c242 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_rtc.c @@ -0,0 +1,2403 @@ +/** + ****************************************************************************** + * @file ft32f4xx_rtc.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Real-Time Clock (RTC) peripheral: + * + Initialization + * + Calendar (Time and Date) configuration + * + Alarms (Alarm A and Alarm B) configuration + * + Daylight Saving configuration + * + Output pin Configuration + * + Digital Calibration configuration + * + Rough Digtial Calibration configuration + * + TimeStamp configuration + * + Tampers (tamp1 and tamp2)configuration + * + Output Type Config configuration + * + Shift control synchronisation + * + Interrupts and flags management + * + Auot WeakUp Config configuration + * + Backup Data Registers configuration + * @version V1.0.0 + * @data 2025-03-25 + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_rtc.h" +#include "ft32f4xx_rcc.h" + +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_TSTR_RESERVED_MASK ((uint32_t)0x007F7F7F) +#define RTC_TSDR_RESERVED_MASK ((uint32_t)0x00FFFF3F) +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) +#define RTC_RSF_MASK ((uint32_t)0xFFFFFFDF) +#define RTC_WUTR_MASK ((uint32_t)0x0000FFFF) +#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP1F | \ + RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \ + RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_SHPF | \ + RTC_FLAG_WUTWF | RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF )) + +#define INITMODE_TIMEOUT ((uint32_t) 0x00004000) +#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000) +#define RECALPF_TIMEOUT ((uint32_t) 0x00001000) +#define SHPF_TIMEOUT ((uint32_t) 0x00001000) + + +static uint8_t RTC_ByteToBcd2(uint8_t Value); +static uint8_t RTC_Bcd2ToByte(uint8_t Value); + +/** + * @brief Deinitializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are deinitialized + * - ERROR: RTC registers are not deinitialized + */ +ErrorStatus RTC_DeInit(void) +{ + ErrorStatus status = ERROR; + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Set Initialization mode */ + if (RTC_EnterInitMode() == ERROR) + { + status = ERROR; + } + else + { + /* Reset TR, DR and CR registers */ + RTC->TR = (uint32_t)0x00000000; + RTC->DR = (uint32_t)0x00002101; + RTC->CR = (uint32_t)0x00000000; + RTC->PRER = (uint32_t)0x007F00FF; + RTC->WUTR = (uint32_t)0x0000FFFF; + RTC->CALIBR = (uint32_t)0x00000000; + RTC->ALRMAR = (uint32_t)0x00000000; + RTC->ALRMBR = (uint32_t)0x00000000; + RTC->SHIFTR = (uint32_t)0x00000000; + RTC->CALR = (uint32_t)0x00000000; + RTC->ALRMASSR = (uint32_t)0x00000000; + RTC->ALRMBSSR = (uint32_t)0x00000000; + + /* Reset ISR register and exit initialization mode */ + RTC->ISR = (uint32_t)0x00000000; + + /* Reset Tamper and alternate functions configuration register */ + RTC->TAFCR = (uint32_t)0x00000000; + + /* Wait till the RTC RSF flag is set */ + if (RTC_WaitForSynchro() == ERROR) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + } + + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * The function use config hour format, async and sync value + */ +void RTC_SetInit(RTC_InitTypeDef* RTC_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat)); + assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv)); + assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv)); + + /* Clear RTC CR FMT Bit set 24 hour*/ + RTC->CR &= ((uint32_t)~(RTC_CR_FMT)); + /* Set RTC_CR register */ + RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat)); + + /*clear async and sync value*/ + RTC->PRER &= ~(RTC_PRER_PREDIV_A | RTC_PRER_PREDIV_S); + + /* Configure the RTC PRER */ + RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_SynchPrediv); + RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16); +} + +/** + * @brief Fills each RTC_InitStruct member with its default value. + * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be + * initialized.async lower than 0x7F,sync lower than 0x1FFF + * Use this function config specific value to Rtc_InitStruct + * @retval None + */ +void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct) +{ + /* Initialize the RTC_HourFormat member */ + RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24 /*RTC_HourFormat_12*/; + + /* Initialize the RTC_AsynchPrediv member */ + RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F; + + /* Initialize the RTC_SynchPrediv member */ + RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; +} + +/** + * @brief Enables or disables the RTC registers write protection. + * @note All the RTC registers are write protected except for RTC_ISR[13:8], + * RTC_TAFCR and RTC_BKPxR. + * @note Writing a wrong key reactivates the write protection. + * @note The protection mechanism is not affected by system reset. + * @param NewState: new state of the write protection. + * This parameter can be: ENABLE reactive write protect + * DISABLE open write protect. + * @retval None + */ +void RTC_WriteProtectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + else + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + } +} + +/** + * @brief Enters the RTC Initialization mode. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) open write protect + * before calling this function. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus RTC_EnterInitMode(void) +{ + __IO uint32_t initcounter = 0x00; + ErrorStatus status = ERROR; + uint32_t initstatus = 0x00; + + /* Check if the Initialization mode is set */ + if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)/*the init not be set*/ + { + /* Set the Initialization mode */ + RTC->ISR |= RTC_ISR_INIT; + + /* Wait till RTC is in INIT state INITF be set + * and if Time out is reached exit */ + do + { + initstatus = (uint32_t)(RTC->ISR & RTC_ISR_INITF); + initcounter++; + } + while ((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00)); + + if ((RTC->ISR & RTC_ISR_INITF) != RESET)/*check if initf be set*/ + { + status = SUCCESS;/*initf has be set,enter init mode*/ + } + else + { + status = ERROR;/*enter init mode has error*/ + } + } + else/*the init has be set*/ + { + status = SUCCESS; + } + return (status); +} + +/** + * @brief Exits the RTC Initialization mode + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @note The RTC Initialization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @param None + * @retval None + */ +void RTC_ExitInitMode(void) +{ + /* Exit Initialization mode */ + RTC->ISR &= ~RTC_ISR_INIT;/* clear init bit */ + + /*when BypassShadow is enable,should wait initf bit clear zero*/ + if ((RTC->CR & RTC_CR_BYPSHAD) == RTC_CR_BYPSHAD) + { + while ((RTC->ISR & RTC_ISR_INITF) != RESET) {} + } +} + +/** + * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * RTC_WriteProtectionCmd(DISABLE) before calling this function. + * @note To read the calendar through the shadow registers after Calendar + * initialization, calendar update or after wakeup from low power modes + * the software must first clear the RSF flag. + * The software must then wait until it is set again before reading + * the calendar, which means that the calendar registers have been + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param None + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus RTC_WaitForSynchro(void) +{ + __IO uint32_t synchrocounter = 0; + ErrorStatus status = ERROR; + uint32_t synchrostatus = 0x00; + + /* check if bypass shadow register */ + if ((RTC->CR & RTC_CR_BYPSHAD) != RESET) + { + /* Bypass shadow register,read calendar will + * direct access rtc_ssr,rtc_tr and rtc_dr register */ + status = SUCCESS; + } + else/*read calendar from rtc_ssr,rtc_tr,rtc_dr's shadow register*/ + { + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + /* Clear RSF flag */ + RTC->ISR &= (uint32_t)RTC_RSF_MASK; + + /* Wait the registers to be synchronised */ + do + { + synchrostatus = (uint32_t)(RTC->ISR & RTC_ISR_RSF);/* rsf be set again */ + synchrocounter++; + } + while ((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00)); + + /* check if RSF be set again */ + if ((RTC->ISR & RTC_ISR_RSF) != RESET) + { + /* while not in bypass mode, rsf be set again + * the calendar update finish*/ + status = SUCCESS; + } + else + { + status = ERROR; + } + + /* Disable the write protection for RTC registers */ + RTC->WPR = 0xFF; + } + + return (status); +} + +/** + * @brief Enables or disables the RTC reference clock detection. + * @param NewState: new state of the RTC reference clock. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_RefClockCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RTC reference clock detection */ + RTC->CR |= (uint32_t)RTC_CR_REFCKON; + } + else + { + /* Disable the RTC reference clock detection */ + RTC->CR &= (uint32_t)(~RTC_CR_REFCKON); + } + +} + +/** + * @brief Enables or Disables the Bypass Shadow feature. + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. + * @param NewState: new state of the Bypass Shadow feature. + * This parameter can be: ENABLE or DISABLE. + * @retval None +*/ +void RTC_BypassShadowCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the BYPSHAD bit */ + RTC->CR |= (uint32_t)RTC_CR_BYPSHAD; + } + else + { + /* Reset the BYPSHAD bit */ + RTC->CR &= (uint32_t)(~RTC_CR_BYPSHAD); + } +} +/** + * @} + */ + +/** + * @brief Set the RTC current time. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * rtc's hours minutes and seconds,that rtc_h12 represent am/pm + */ +void RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters if RTC_Format_BIN or RTC_Format_BCD */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* check rtc time format if binary */ + if (RTC_Format == RTC_Format_BIN) + { + /* check if hour format is 12 or 24 */ + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + /* set rtc_hours format is 12 + * check rtc hour if in range 0-12 + * set hour is am/pm */ + assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + /* set rtc_hours format is 24 */ + RTC_TimeStruct->RTC_H12 = 0x00; + /* check hour if in range 0-23 */ + assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours)); + } + /* check rtc minutes and seconds in right range */ + assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds)); + } + else/* rtc time format is bcd */ + { + /* check if hour format is 12 or 24 */ + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + /* set rtc_hours format is 12 and am/pm + * convert bcd to binary and set am/pm*/ + tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + /* check hour if in range 0-12 */ + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); + } + else + { + /* set rtc_hours format is 24 */ + RTC_TimeStruct->RTC_H12 = 0x00; + /* check hour if in range 0-23 */ + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours))); + } + /* check rtc minutes and seconds in right range */ + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds))); + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + /* rtc time format is binary */ + tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_H12) << 22) | \ + ((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t) RTC_TimeStruct->RTC_Seconds)); + } + else + { + /* rtc time format is bcd + * convert byte to bcd */ + tmpreg = (uint32_t)((((uint32_t)RTC_TimeStruct->RTC_H12) << 22) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds))); + } + + /* Set the RTC_TR register */ + RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); +} + +/** + * @brief Fills each RTC_TimeStruct member with its default value + * (Time = 00h:00min:00sec). + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be + * initialized. + * @retval None + */ +void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->RTC_H12 = RTC_H12_AM; + RTC_TimeStruct->RTC_Hours = 0; + RTC_TimeStruct->RTC_Minutes = 0; + RTC_TimeStruct->RTC_Seconds = 0; +} + +/** + * @brief Get the RTC current Time. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contain the returned current time configuration. + * @retval None + */ +void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + /* the get's rtc time is bcd format*/ + tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16); + RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >> 8); + RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU)); + RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 22); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* want get the binary format rtc time */ + /* Convert the structure parameters to Binary format */ + RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours); + RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes); + RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds); + } +} + +/** + * @brief Gets the RTC current Calendar Subseconds value. + * @note This function freeze the Time and Date registers after reading the + * SSR register. + * @param None + * @retval RTC current Calendar Subseconds value. + */ +uint32_t RTC_GetSubSecond(void) +{ + uint32_t tmpreg = 0; + + /* Get subseconds values from the correspondent registers*/ + tmpreg = (uint32_t)(RTC->SSR); + + /* Read DR register to unfroze calendar registers */ + (void)(RTC->DR); + + return (tmpreg); +} + +/** + * @brief Set the RTC current date. + * @param RTC_Format: specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * the date configuration information for the RTC. + */ +void RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* check rtc_month's mt if is 1 */ + if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10)) + { + /* rtc_month's mt is 1,convert as low 4 bits expression */ + RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A; + } + if (RTC_Format == RTC_Format_BIN) + { + /* rtc_date is binary + * check the rtc date in right range */ + assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year)); + assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month)); + assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date)); + } + else + { + /* rtc_date is bcd need convert as binary + * check the rtc date in right range */ + assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year))); + assert_param(IS_RTC_MONTH(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month))); + assert_param(IS_RTC_DATE(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date))); + } + /* check the weekday in right range */ + assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay)); + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + /* rtc_datestruct as binary format */ + tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \ + (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_DateStruct->RTC_Date) | \ + (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); + } + else + { + /* rtc_datestruct as bcd format + * need convert as binary format */ + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \ + ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13)); + } + + /* Set the RTC_DR register */ + RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK); +} + +/** + * @brief Fills each RTC_DateStruct member with its default value + * (Monday, January 01 xx00). + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure + * which will be initialized. + * @retval None + */ +void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct) +{ + /* Monday, January 01 xx00 */ + RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday; + RTC_DateStruct->RTC_Date = 1; + RTC_DateStruct->RTC_Month = RTC_Month_January; + RTC_DateStruct->RTC_Year = 0; +} + +/** + * @brief Get the RTC current date. + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will + * contain the returned current date configuration. + * @retval None + */ +uint32_t RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the RTC_TR register */ + tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); + + /* Fill the structure fields with the read parameters */ + /* the rtc_date format as bcd */ + RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16); + RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8); + RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU)); + RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13); + + /* Check the input parameters format */ + /* the rtc_date format as binary */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the structure parameters to Binary format */ + RTC_DateStruct->RTC_Year = (uint8_t) RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year); + RTC_DateStruct->RTC_Month = (uint8_t) RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month); + RTC_DateStruct->RTC_Date = (uint8_t) RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date); + RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay); + } + return 0; +} +/** + * @} + */ + + +/** + * @brief Set the specified RTC Alarm. + * @note The Alarm register can only be written when the corresponding + * Alarm is disabled (Use the RTC_AlarmaCmd(DISABLE)). + * @param RTC_Format: specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * This parameter can be one of the following values: + * @arg RTC_AlarmTime: RTC_Hours RTC_Minutes RTC_Seconds RTC_H12 + * @arg RTC_AlarmMask: RTC_AlarmMask_None RTC_AlarmMask_DateWeekDay + * RTC_AlarmMask_Hours RTC_AlarmMask_Minutes + * RTC_AlarmMask_Seconds RTC_AlarmMask_All + * @arg RTC_AlarmDateWeekDaySel:RTC_AlarmDateWeekDaySel_Date + * RTC_AlarmDateWeekDaySel_WeekDay + * @arg RTC_AlarmDateWeekDay:date range 1-31 + * RTC_Weekday_Monday RTC_Weekday_Tuesday + * RTC_Weekday_Wednesday RTC_Weekday_Thursday + * RTC_Weekday_Friday RTC_Weekday_Saturday + * RTC_Weekday_Sunday + * @retval None + */ +void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format));/* config alarma/alarmb register's struct format */ + assert_param(IS_RTC_ALARM(RTC_Alarm));/* choose alarma/alarmb */ + assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));/* config alarm mask */ + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));/* config alarm wdsel */ + + if (RTC_Format == RTC_Format_BIN)/* rtc alarma/alarmb struct format is binary */ + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)/* rtc hour format is 12 */ + { + /* check alarma/alarmb's hour range in 0-12 */ + assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else/* rtc hour format is 24 */ + { + /* check alarma/alarmb's hour range in 0-23 */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)); + } + /* check alarma/alarmb's minutes and seconds in right range */ + assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)); + assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)); + + /* judgement alarma/alarmb's wdsel=0 or 1 */ + if (RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + /* while wdsel=0 check DU[3:0] if express day */ + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + else + { + /* while wdsel=1 check DU[3:0] if express weekday */ + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay)); + } + } + else/* rtc alarma/alarmb struct format is bcd */ + { + if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET) + { + /* check alarma/alarmb's hour range in 0-12 */ + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours); + assert_param(IS_RTC_HOUR12(tmpreg)); + assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12)); + } + else/* rtc hour format is 24 */ + { + /* check alarma/alarmb's hour range in 0-23 */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00; + assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours))); + } + /* check alarma/alarmb's minutes and seconds in right range */ + assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes))); + assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds))); + + /* judgement alarma/alarmb's wdsel=0 or 1 */ + if (RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date) + { + /* while wdsel=0 check DU[3:0] if express day */ + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg)); + } + else + { + /* while wdsel=1 check DU[3:0] if express weekday */ + tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay); + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg)); + } + } + + /* Check the input parameters format */ + if (RTC_Format != RTC_Format_BIN) + { + tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 22) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + else + { + tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \ + ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 22) | \ + ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \ + ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); + } + + if (RTC_Alarm == RTC_Alarm_A) + { + /* Configure the Alarm register */ + RTC->ALRMAR = (uint32_t)tmpreg; + } + else if (RTC_Alarm == RTC_Alarm_B) + { + /* Configure the Alarm register */ + RTC->ALRMBR = (uint32_t)tmpreg; + } + +} + +/** + * @brief Fills each RTC_AlarmStruct member with its default value + * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask = + * all fields are masked). + * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which + * will be initialized. + * @retval None + */ +void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0; + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0; + + /* Alarm Date Settings : Date = 1st day of the month */ + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date; + RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1; + + /* Alarm Masks Settings : Mask = all fields are not masked */ + RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None; +} + +/** + * @brief Get the RTC Alarm value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will + * contains the output alarm configuration values. + * This parameter can be one of the following values: + * @arg RTC_AlarmTime: RTC_Hours RTC_Minutes RTC_Seconds RTC_H12 + * @arg RTC_AlarmMask: RTC_AlarmMask_None RTC_AlarmMask_DateWeekDay + * RTC_AlarmMask_Hours RTC_AlarmMask_Minutes + * RTC_AlarmMask_Seconds RTC_AlarmMask_All + * @arg RTC_AlarmDateWeekDaySel:RTC_AlarmDateWeekDaySel_Date + * RTC_AlarmDateWeekDaySel_WeekDay + * @arg RTC_AlarmDateWeekDay:date range 1-31 + * RTC_Weekday_Monday RTC_Weekday_Tuesday + * RTC_Weekday_Wednesday RTC_Weekday_Thursday + * RTC_Weekday_Friday RTC_Weekday_Saturday + * RTC_Weekday_Sunday + * @retval None + */ +void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + assert_param(IS_RTC_ALARM(RTC_Alarm)); + + if (RTC_Alarm == RTC_Alarm_A) + { + /* Get the RTC_ALRMAR register */ + tmpreg = (uint32_t)(RTC->ALRMAR); + } + else if (RTC_Alarm == RTC_Alarm_B) + { + /* Get the RTC_ALRMBR register */ + tmpreg = (uint32_t)(RTC->ALRMBR); + } + + /* Fill the structure with the read parameters */ + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 22); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All); + + if (RTC_Format == RTC_Format_BIN) + { + RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct -> RTC_AlarmTime.RTC_Hours); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct -> RTC_AlarmTime.RTC_Minutes); + RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct -> RTC_AlarmTime.RTC_Seconds); + RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct -> RTC_AlarmDateWeekDay); + } +} + +/** + * @brief Enables or disables the specified RTC Alarm. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be any combination of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param NewState: new state of the specified alarm. + * This parameter can be: ENABLE or DISABLE. + */ +void RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_CMD_ALARM(RTC_Alarm)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Configure the Alarm state */ + if (NewState != DISABLE) + { + RTC->CR |= (uint32_t)RTC_Alarm;/* enable rtc alarma or alarmb */ + } + else + { + /* Disable the Alarm in RTC_CR register */ + RTC->CR &= (uint32_t)~RTC_Alarm; + } +} + +/** + * @brief Configure the RTC AlarmA/B Subseconds value and mask. + * @note This function is performed only when the Alarm is disabled. + * @param RTC_Alarm: specifies the alarm to be configured. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param RTC_AlarmSubSecondValue: specifies the Subseconds value. + * This parameter can be a value from 0 to 0x00007FFF. + * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask. + * This parameter can be any combination of the following values: + * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked. + * There is no comparison on sub seconds for Alarm. + * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison. + * Only SS[0] is compared + * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison. + * Only SS[1:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison. + * Only SS[2:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison. + * Only SS[3:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison. + * Only SS[4:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison. + * Only SS[5:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison. + * Only SS[6:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison. + * Only SS[7:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison. + * Only SS[8:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison. + * Only SS[9:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison. + * Only SS[10:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison. + * Only SS[11:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison. + * Only SS[12:0] are compared + * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison. + * Only SS[13:0] are compared + * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm + * @retval None + */ +void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALARM(RTC_Alarm)); + assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue)); + assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask)); + + /* Configure the Alarm A or Alarm B SubSecond registers */ + tmpreg = (uint32_t)(((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24)); + + if (RTC_Alarm == RTC_Alarm_A) + { + /* Configure the AlarmA SubSecond register */ + RTC->ALRMASSR = (uint32_t)tmpreg; + } + else if (RTC_Alarm == RTC_Alarm_B) + { + /* Configure the AlarmB SubSecond register */ + RTC->ALRMBSSR = (uint32_t)tmpreg; + } +} + +/** + * @brief Gets the RTC Alarm Subseconds value. + * @param RTC_Alarm: specifies the alarm to be read. + * This parameter can be one of the following values: + * @arg RTC_Alarm_A: to select Alarm A + * @arg RTC_Alarm_B: to select Alarm B + * @param None + * @retval RTC Alarm Subseconds value. + */ +uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm) +{ + uint32_t tmpreg = 0; + + if (RTC_Alarm == RTC_Alarm_A) + { + /* Get the RTC_ALRMAR register */ + tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS); + } + else if (RTC_Alarm == RTC_Alarm_B) + { + /* Get the RTC_ALRMBR register */ + tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS); + } + + return (tmpreg); +} +/** + * @} + */ + + + +/** + * @brief Adds or substract one hour from the current time. + * @param RTC_DayLightSaveOperation: the value of hour adjustment. + * This parameter can be one of the following values: + * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time) + * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time) + * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit + * in CR register to store the operation. + * This parameter can be one of the following values: + * @arg RTC_StoreOperation_Reset: BKP Bit Reset + * @arg RTC_StoreOperation_Set: BKP Bit Set + * @retval None + */ +void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation) +{ + /* Check the parameters */ + assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving)); + assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation)); + + /* Clear the bits to be configured */ + RTC->CR &= (uint32_t)~(RTC_CR_BKP); + + /* Configure the RTC_CR register */ + /* Based on the parameter config DayLightSaving ADD1H/SUB1H + * and StoreOperation set/clear RTC_CR[BKP]*/ + RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation); +} + +/** + * @brief Returns the RTC Day Light Saving stored operation. + * @param None + * @retval RTC Day Light Saving stored operation. + * - RTC_StoreOperation_Reset + * - RTC_StoreOperation_Set + */ +uint32_t RTC_GetStoreOperation(void) +{ + return (RTC->CR & RTC_CR_BKP); +} + +/** + * @} + */ + +/** + * @brief Configures the RTC output source (AFO_ALARM). + * @param RTC_Output: Specifies which signal will be routed to the RTC output. + * This parameter can be one of the following values: + * @arg RTC_Output_Disable: No output selected + * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output + * @arg RTC_Output_AlarmB: signal of AlarmB mapped to output + * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output + * @param RTC_OutputPolarity: Specifies the polarity of the output signal. + * This parameter can be one of the following: + * @arg RTC_OutputPolarity_High: The output pin is high when the + * ALRAF is high (depending on OSEL) + * @arg RTC_OutputPolarity_Low: The output pin is low when the + * ALRAF is high (depending on OSEL) + * @retval None + */ +void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT(RTC_Output)); + assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity)); + + /* Clear the bits before configured */ + RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL); + + /* Configure the output selection and polarity + * select rtc_alarm output is alraf/alrbf/wutf + * and rtc_alarm output polarity is high/low*/ + RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity); +} +/** + * @} + */ + + +/** + * @brief Enables or disables the RTC_CALIB output through the relative pin. + * @param NewState: new state of the digital calibration Output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_CalibOutputCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RTC_CALIB output */ + RTC->CR |= (uint32_t)RTC_CR_COE; + } + else + { + /* Disable the RTC_CALIB output */ + RTC->CR &= (uint32_t)~RTC_CR_COE; + } + +} + +/** + * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (512Hz or 1Hz). + * @param RTC_CalibOutput: Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. + * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz. + * @retval None +*/ +void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput)); + + /*clear flags before config*/ + RTC->CR &= (uint32_t)~(RTC_CR_COSEL); + + /* Configure the RTC_CR register + * Based on parameter RTC_CalibOutput_512Hz/1Hz*/ + RTC->CR |= (uint32_t)RTC_CalibOutput; + +} + +/** + * @brief Configures the Smooth Calibration Settings. + * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period. + * This parameter can be can be one of the following values: + * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s. + * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s. + * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s. + * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses. + * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added. + * @param RTC_SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Calib registers are configured + * - ERROR: RTC Calib registers are not configured +*/ +ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, + uint32_t RTC_SmoothCalibPlusPulses, + uint32_t RTC_SmoothCalibMinusPulsesValue) +{ + ErrorStatus status = ERROR; + uint32_t recalpfcount = 0; + + /* Check the parameters satisfy format*/ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmoothCalibMinusPulsesValue)); + + /* check if a calibration is pending*/ + if ((RTC->ISR & RTC_ISR_RECALPF) != RESET) + { + /* wait until the Calibration is completed*/ + while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT)) + { + recalpfcount++; + } + } + + /* check if the calibration pending is completed or if there is no calibration operation at all*/ + if ((RTC->ISR & RTC_ISR_RECALPF) == RESET) + { + /* Configure the Smooth calibration settings */ + RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | \ + (uint32_t)RTC_SmoothCalibPlusPulses | \ + (uint32_t)RTC_SmoothCalibMinusPulsesValue); + status = SUCCESS; + } + else + { + status = ERROR; + } + + return (ErrorStatus)(status); +} +/** + * @} + */ + +/** + * @brief Enables or disables the RTC Rough Calibration. + * @param NewState: new state of the digital calibration Output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_RoughCalibration(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the RTC Rough Calibration */ + RTC->CR |= (uint32_t)RTC_CR_DCE; + } + else + { + /* Disable the RTC Rough Calibration */ + RTC->CR &= (uint32_t)~RTC_CR_DCE; + } + +} + +/** + * @brief Configures the Rough Digtial Calibration Settings. + * @param RTC_RoughCalibPlority: Select to Set or reset the DCS bit. + * This parameter can be one of the following values: + * @arg RTC_RoughCalibSymbol_Positive: Add calendar update frequence. + * @arg RTC_RoughCalibSymbol_Negative: Substract calendar update frequence. + * @param RTC_RoughCalibMinusPulsesValue: Select the value of DC[4:0] bits. + * This parameter can be one any value from 0 to 0x000001F. +*/ +void RTC_RoughDigtialCalibConfig(uint32_t RTC_RoughCalibPolarity, + uint32_t RTC_RoughCalibMinusPulsesValue) +{ + + /* Check the parameters satisfy format*/ + assert_param(IS_RTC_ROUGH_CALIB_SYMBOL(RTC_RoughCalibPolarity)); + assert_param(IS_RTC_ROUGH_CALIB_DC_VALUE(RTC_RoughCalibMinusPulsesValue)); + + /* clear the bits before config */ + RTC->CALIBR &= (uint32_t)~(RTC_CALIBR_DCS | RTC_CALIBR_DC); + + /* Configure the Smooth calibration settings */ + RTC->CALIBR |= (uint32_t)((uint32_t)RTC_RoughCalibPolarity | \ + (uint32_t)RTC_RoughCalibMinusPulsesValue); +} +/** + * @} + */ + + +/** + * @brief Enables or Disables the RTC TimeStamp functionality with + * the specified time stamp pin stimulating edge. + * @param RTC_TimeStampEdge: Specifies the pin edge on which the + * TimeStamp is activated. + * This parameter can be one of the following: + * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising + * edge of the related pin. + * @arg RTC_TimeStampEdge_Falling:the Time stamp event occurs on the + * falling edge of the related pin. + * @param NewState: new state of the TimeStamp. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + /* Get the RTC_CR register and clear the bits before configured */ + tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE)); + + /* Get the new configuration */ + if (NewState != DISABLE) + { + /* Enable Timestamp and config occur edge */ + tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE); + } + else + { + /* Not Enable Timestamp */ + tmpreg |= (uint32_t)(RTC_TimeStampEdge); + } + + /* Configure the Time Stamp TSEDGE and Enable bits */ + RTC->CR = (uint32_t)tmpreg; +} + +/** + * @brief Get the RTC TimeStamp value and masks. + * @param RTC_Format: specifies the format of the output parameters. + * This parameter can be one of the following values: + * @arg RTC_Format_BIN: Binary data format + * @arg RTC_Format_BCD: BCD data format + * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will + * contains the TimeStamp time values. + * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will + * contains the TimeStamp date values. + * @retval None + */ +void RTC_GetTimeStamp(uint32_t RTC_Format, + RTC_TimeTypeDef* RTC_StampTimeStruct, + RTC_DateTypeDef* RTC_StampDateStruct) +{ + uint32_t tmptime = 0, tmpdate = 0; + + /* Check the parameters */ + assert_param(IS_RTC_FORMAT(RTC_Format)); + + /* Get the TimeStamp time and date registers values */ + tmptime = (uint32_t)(RTC->TSTR & RTC_TSTR_RESERVED_MASK); + tmpdate = (uint32_t)(RTC->TSDR & RTC_TSDR_RESERVED_MASK); + + /* Fill the Time structure fields with the read parameters */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TSTR_HT | RTC_TSTR_HU)) >> 16); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TSTR_MNT | RTC_TSTR_MNU)) >> 8); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TSTR_ST | RTC_TSTR_SU)); + RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TSTR_PM)) >> 22); + + /* Fill the Date structure fields with the read parameters */ + RTC_StampDateStruct->RTC_Year = 0; + RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_TSDR_MT | RTC_TSDR_MU)) >> 8); + RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_TSDR_DT | RTC_TSDR_DU)); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_TSDR_WDU)) >> 13); + + /* Check the input parameters format */ + if (RTC_Format == RTC_Format_BIN) + { + /* Convert the Time structure parameters to Binary format */ + RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours); + RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes); + RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds); + + /* Convert the Date structure parameters to Binary format */ + RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month); + RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date); + RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay); + } +} + +/** + * @brief Get the RTC timestamp Subseconds value. + * @param None + * @retval RTC current timestamp Subseconds value. + */ +uint32_t RTC_GetTimeStampSubSecond(void) +{ + /* Get timestamp subseconds values from the correspondent registers */ + return (uint32_t)(RTC->TSSSR); +} +/** + * @} + */ + +/** + * @brief Configures the select Tamper pin edge. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that + * stimulates tamper event. + * This parameter can be one of the following values: + * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event. + * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event. + * @retval None + */ +void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger)); + + /* while tampflt==00,the pin edge trigger tamper event */ + if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge) + { + /* Configure the RTC_TAFCR register */ + /* Clear Tamp1trg or Tamp2trg */ + RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); + } + + if (RTC_TamperTrigger == RTC_TamperTrigger_FallingEdge) + { + /* Configure the RTC_TAFCR register */ + /* Set Tamp1trg or Tamp2trg */ + RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); + } + + /* while tampflt!=00,the pin level trigger tamper event */ + if (RTC_TamperTrigger == RTC_TamperTrigger_LowLevel) + { + /* Configure the RTC_TAFCR register */ + /* Clear Tamp1trg or Tamp2trg */ + RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1)); + } + + if (RTC_TamperTrigger == RTC_TamperTrigger_HighLevel) + { + /* Configure the RTC_TAFCR register */ + /* Set Tamp1trg or Tamp2trg */ + RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1); + } +} + +/** + * @brief Enables or Disables the Tamper detection. + * @param RTC_Tamper: Selected tamper pin. + * This parameter can be any combination of the following values: + * @arg RTC_Tamper_1: Select Tamper 1. + * @arg RTC_Tamper_2: Select Tamper 2. + * @param NewState: new state of the tamper pin. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER(RTC_Tamper)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected Tamper1 or Tamper2 pin */ + RTC->TAFCR |= (uint32_t)RTC_Tamper; + } + else + { + /* Disable the selected Tamper1 or Tamper2 pin */ + RTC->TAFCR &= (uint32_t)~RTC_Tamper; + } +} + +/** + * @brief Configures the Tampers Filter. + * @param RTC_TamperFilter: Specifies the tampers filter. + * This parameter can be one of the following values: + * @arg RTC_TamperFilter_Disable: Tamper filter is disabled. + * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 + * consecutive samples at the active level + * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 + * consecutive samples at the active level + * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 + * consecutive samples at the active level + * @retval None + */ +void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter)); + + /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperFilter; +} + +/** + * @brief Configures the Tampers Sampling Frequency. + * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Tamper inputs sampled frequency = RTCCLK / 32768 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Tamper inputs sampled frequency = RTCCLK / 16384 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Tamper inputs sampled frequency = RTCCLK / 8192 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Tamper inputs sampled frequency = RTCCLK / 4096 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Tamper inputs sampled frequency = RTCCLK / 2048 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Tamper inputs sampled frequency = RTCCLK / 1024 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Tamper inputs sampled frequency = RTCCLK / 512 + * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Tamper inputs sampled frequency = RTCCLK / 256 + * @retval None + */ +void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq)); + + /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq; +} + +/** + * @brief Configures the Tampers Pins input Precharge Duration. + * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input Precharge Duration. + * This parameter can be one of the following values: + * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are precharged 1 RTCCLK + * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are precharged 2 RTCCLK + * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are precharged 4 RTCCLK + * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are precharged 8 RTCCLK + * @retval None + */ +void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration) +{ + /* Check the parameters */ + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration)); + + /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */ + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH); + + /* Configure the RTC_TAFCR register */ + RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration; +} + +/** + * @brief Enables or Disables the TimeStamp on Tamper Detection Event. + * @note The timestamp is valid even the TSE bit in tamper control register + * is reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Save timestamp on tamper detection event */ + /* tamp event trigger timestamp */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS; + } + else + { + /* Tamper detection does not cause a timestamp to be saved */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS; + } +} + +/** + * @brief Enables or Disables the Precharge of Tamper pin. + * @param NewState: new state of tamper pull up. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_TamperPullUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable precharge of the selected Tamper pin */ + /* precharge tamp pin before sampled */ + RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; + } + else + { + /* Disable precharge of the selected Tamper pin */ + /* Forbidded tamp pins precharge function */ + RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS; + } +} +/** + * @} + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in + * Open Drain mode. + * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in + * Push Pull mode. + * @retval None + */ +void RTC_OutputTypeConfig(uint32_t RTC_OutputType) +{ + /* Check the parameters */ + assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_PC13VALUE); + RTC->TAFCR |= (uint32_t)(RTC_OutputType); +} +/** + * @} + */ + +/** + * @brief Configures the RTC Output Pin mode. + * @param RTC_OutputMode: specifies the RTC Output (PC13) pin mode. + * This parameter can be one of the following values: + * @arg RTC_PC13_OutputType_GPIO: RTC Output (PC13) is configured in + * gpio. + * @arg RTC_PC13_OutputType_PushPull: RTC Output (PC13) is configured in + * Push Pull mode. + * @retval None + */ +void RTC_OutputModeConfig(uint32_t RTC_OutputMode) +{ + /* Check the parameters */ + assert_param(IS_RTC_PC13_OUTPUT_TYPE(RTC_OutputMode)); + + RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_PC13MODE); + RTC->TAFCR |= (uint32_t)(RTC_OutputMode); +} +/** + * @} + */ + +/** + * @brief Configures the RTC Pc15 Output Pin mode. + * @param RTC_Pc15_OutputType: specifies the RTC Output (PC15) pin mode. + * This parameter can be one of the following values: + * @arg RTC_PC15_OutputType_GPIO: RTC Output (PC15) is configured by gpio. + * @arg RTC_PC15_OutputType_PushPull: RTC Output (PC15) is configured Push Pull mode. + * @param RTC_Pc15_OutputData: specifies the RTC Output (PC15) data. + * This parameter can be one of the following values: + * @arg RTC_PC15_OutputData_0: RTC Output Data (PC15) is configured 0. + * @arg RTC_PC15_OutputData_1: RTC Output Data (PC15) is configured 1. + * @retval None + */ +void RTC_Pc15_OutputTypeDataConfig(uint32_t RTC_Pc15_OutputType, uint32_t RTC_Pc15_OutputData) +{ + /* Check the parameters */ + assert_param(IS_RTC_PC15_OUTPUT_TYPE(RTC_Pc15_OutputType)); + assert_param(IS_RTC_PC15_OUTPUT_DATA(RTC_Pc15_OutputData)); + + /*clear pc15mode and value*/ + RTC->TAFCR &= ~(uint32_t)(RTC_PC15_OutputType_PushPull | RTC_PC15_OutputData_1); + + /* config pc14mode and value */ + RTC->TAFCR |= (uint32_t)(RTC_Pc15_OutputType | RTC_Pc15_OutputData); +} +/** + * @} + */ + +/** + * @brief Configures the RTC Pc14 Output Pin mode. + * @param RTC_Pc14_OutputType: specifies the RTC Output (PC14) pin mode. + * This parameter can be one of the following values: + * @arg RTC_PC14_OutputType_GPIO: RTC Output (PC14) is configured by gpio. + * @arg RTC_PC14_OutputType_PushPull: RTC Output (PC14) is configured Push Pull mode. + * @param RTC_Pc14_OutputData: specifies the RTC Output (PC14) data. + * This parameter can be one of the following values: + * @arg RTC_PC14_OutputData_0: RTC Output Data (PC14) is configured 0. + * @arg RTC_PC14_OutputData_1: RTC Output Data (PC14) is configured 1. + * @retval None + */ +void RTC_Pc14_OutputTypeDataConfig(uint32_t RTC_Pc14_OutputType, uint32_t RTC_Pc14_OutputData) +{ + /* Check the parameters */ + assert_param(IS_RTC_PC14_OUTPUT_TYPE(RTC_Pc14_OutputType)); + assert_param(IS_RTC_PC14_OUTPUT_DATA(RTC_Pc14_OutputData)); + + /*clear pc14mode and value*/ + RTC->TAFCR &= ~(uint32_t)(RTC_PC14_OutputType_PushPull | RTC_PC14_OutputData_1); + + /* config pc14mode and value */ + RTC->TAFCR |= (uint32_t)(RTC_Pc14_OutputType | RTC_Pc14_OutputData); +} +/** + * @} + */ + +/** + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register + * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar. + * This parameter can be one of the following values : + * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar. + * @arg RTC_ShiftAdd1S_Reset: No effect. + * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute. + * This parameter can be one any value from 0 to 0x7FFF. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Shift registers are configured + * - ERROR: RTC Shift registers are not configured +*/ +ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS) +{ + ErrorStatus status = ERROR; + uint32_t shpfcount = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS)); + + /* Check if a Shift is pending*/ + if ((RTC->ISR & RTC_ISR_SHPF) != RESET) + { + /* Wait until the shift is completed*/ + while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT)) + { + shpfcount++; + } + } + + /* Check if the Shift pending is completed or if there is no Shift operation at all*/ + if ((RTC->ISR & RTC_ISR_SHPF) == RESET) + { + /* check if the reference clock detection is disabled */ + if ((RTC->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S); + status = SUCCESS;/* reference clock detection is disabled, shiftr can be config */ + } + else + { + status = ERROR;/* reference clock detection is enabled, shiftr can not config */ + } + } + else + { + status = ERROR;/* shpf be set, shiftr can not config */ + } + + return (ErrorStatus)(status); +} +/** + * @} + */ + +/** + * @brief Enables or disables the specified RTC interrupts. + * @param RTC_IT_ENABLE: specifies the RTC interrupt sources to + * be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS_EN: Time Stamp interrupt mask + * @arg RTC_IT_WUT_EN: WakeUp Timer interrupt mask + * @arg RTC_IT_ALRB_EN: Alarm B interrupt mask + * @arg RTC_IT_ALRA_EN: Alarm A interrupt mask + * @arg RTC_IT_TAMP_EN: Tamper event interrupt mask + * @param NewState: new state of the specified RTC interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_ITConfig(uint32_t RTC_IT_ENABLE, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_RTC_CONFIG_IT(RTC_IT_ENABLE)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR |= (uint32_t)(RTC_IT_ENABLE & ~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR |= (uint32_t)(RTC_IT_ENABLE & RTC_TAFCR_TAMPIE); + } + else + { + /* Configure the Interrupts in the RTC_CR register */ + RTC->CR &= (uint32_t)~(RTC_IT_ENABLE & ~RTC_TAFCR_TAMPIE); + /* Configure the Tamper Interrupt in the RTC_TAFCR */ + RTC->TAFCR &= (uint32_t)~(RTC_IT_ENABLE & RTC_TAFCR_TAMPIE); + } +} + +/** + * @brief Checks whether the specified RTC flag is set or not. + * @param RTC_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg RTC_FLAG_RECALPF: RECALPF event flag + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: Auto WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_INITF: Initialization mode flag + * @arg RTC_FLAG_RSF: Calendar Shadow Registers Synchronized flag + * @arg RTC_FLAG_INITS: Calendar initialization flag + * @arg RTC_FLAG_SHPF: Shift Operation Pending flag + * @arg RTC_FLAG_WUTWF: Auto Weakup Register allow write flag + * @arg RTC_FLAG_ALRBWF: Alarma Registers allow write flag + * @arg RTC_FLAG_ALRAWF: Alarmb Registers allow write flag + * @retval The new state of RTC_FLAG (SET or RESET). + */ +FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_FLAG(RTC_FLAG)); + + /* Get all the flags */ + tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK); + + /* Return the status of the flag */ + /* Check Rtc_Flag if be set */ + if ((tmpreg & RTC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET;/* rtc_flag be set */ + } + else + { + bitstatus = RESET;/* rtc_flag not be set */ + } + return bitstatus; +} + +/** + * @brief Clears the RTC's pending flags. + * @param RTC_FLAG: specifies the RTC flag to clear. + * This parameter can be any combination of the following values: + * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag + * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag + * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag + * @arg RTC_FLAG_TSF: Time Stamp event flag + * @arg RTC_FLAG_WUTF: aUTO WakeUp Timer flag + * @arg RTC_FLAG_ALRBF: Alarm B flag + * @arg RTC_FLAG_ALRAF: Alarm A flag + * @arg RTC_FLAG_RSF: Calendar Shadow Registers Synchronized flag + * @retval None + */ +void RTC_ClearFlag(uint32_t RTC_FLAG) +{ + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG)); + + /* Clear the Flags in the RTC_ISR register */ + RTC->ISR &= ~(uint32_t)RTC_FLAG; +} + +/** + * @brief Checks whether the specified RTC interrupt has occurred or not. + * @param RTC_IT_ENABLE: specifies the RTC interrupt source to check. + * This parameter can be one of the following values: + * @arg RTC_IT_TS_EN: Time Stamp interrupt + * @arg RTC_IT_WUT_EN: Auto WakeUp Timer interrupt + * @arg RTC_IT_ALRB_EN: Alarm B interrupt + * @arg RTC_IT_ALRA_EN: Alarm A interrupt + * @arg RTC_IT_TAMP_EN: Tamper interrupt + * @retval The new state of RTC_IT (SET or RESET). + */ +ITStatus RTC_GetITStatus(uint32_t RTC_IT_ENABLE) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_RTC_GET_IT(RTC_IT_ENABLE)); + + if (RTC_IT_ENABLE == RTC_IT_TAMP_EN) + { + /* Get rtc_tamp interrupt enable */ + tmpreg = (uint32_t)(RTC->TAFCR & RTC_TAFCR_TAMPIE); + /* Check rtc_tamp interrupt if be enable */ + if (tmpreg != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + /* Get rtc_cr register's interrupt enable */ + tmpreg = (uint32_t)(RTC->CR & RTC_IT_ENABLE); + /* Check rtc_cr register's interrupt if be enable */ + if (tmpreg != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/** + * @brief Clears the RTC's interrupt pending bits. + * @param RTC_IT_FLAG: specifies the RTC interrupt pending bit to clear. + * This parameter can be any combination of the following values: + * @arg RTC_IT_TS: Time Stamp interrupt + * @arg RTC_IT_WUT: WakeUp Timer interrupt + * @arg RTC_IT_ALRB: Alarm B interrupt + * @arg RTC_IT_ALRA: Alarm A interrupt + * @arg RTC_IT_TAMP1: Tamper1 event interrupt + * @arg RTC_IT_TAMP2: Tamper2 event interrupt + * @retval None + */ +void RTC_ClearITPendingBit(uint32_t RTC_IT_FLAG) +{ + + /* Check the parameters */ + assert_param(IS_RTC_CLEAR_IT(RTC_IT_FLAG)); + + /* Clear the interrupt pending bits in the RTC_ISR register */ + RTC->ISR &= (uint32_t)~((uint32_t)RTC_IT_FLAG); +} +/** + * @} + */ + +/** + * @brief Enables or Disables the Auto Weakup. + * @note The auto weakup is valid even the WUTE bit in rtc control register + * is defaut reset. + * @param NewState: new state of the timestamp on tamper event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void RTC_WeakUpCmd(FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable Auto WeakUp Function */ + RTC->CR |= (uint32_t)RTC_CR_WUTE; + } + else + { + /* Disable Auto WeakUp Function */ + RTC->CR &= (uint32_t)~RTC_CR_WUTE; + } +} + +/** + * @brief Configures the Auto WeakUp Counter. + * @param RTC_WeakUp_Counter: Specifies the tampers filter. + * This parameter only on the range of 0~0xFFFF + * @retval None + */ +void RTC_SetWeakUpCounter(uint32_t RTC_WeakUp_Counter) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_COUNTER(RTC_WeakUp_Counter)); + + /* Clear WUTR[15:0] bits in the RTC_WUTR register */ + RTC->WUTR &= (uint32_t)~(RTC_WUTR_MASK); + + /* Configure the RTC_WUTR register */ + RTC->WUTR |= (uint32_t)RTC_WeakUp_Counter; +} + +/** + * @brief Get the Auto WeakUp Counter. + * @param RTC_WeakUp_Counter: Specifies the tampers filter. + * This parameter only on the range of 0~0xFFFF + * @retval None + */ +uint32_t RTC_GetWeakUpCounter(void) +{ + /* Return the RTC_WUTR register */ + return (uint32_t)(RTC->WUTR); +} + +/** + * @brief Configures the Auto WeakUp Counting Frequency. + * @param RTC_WeakUpCountFreq: Specifies the tampers Sampling Frequency. + * This parameter can be one of the following values: + * @arg RTC_WeakUp_RTCCLK_Div16: Auto WeakUp Counting frequency = RTCCLK/16 + * @arg RTC_WeakUp_RTCCLK_Div8: Auto WeakUp Counting frequency = RTCCLK/8 + * @arg RTC_WeakUp_RTCCLK_Div4: Auto WeakUp Counting frequency = RTCCLK/4 + * @arg RTC_WeakUp_RTCCLK_Div2: Auto WeakUp Counting frequency = RTCCLK/2 + * @arg RTC_WeakUp_RTCCLK_CkSpre4: Auto WeakUp Counting frequency = CK_SPRE4 + * @arg RTC_WeakUp_RTCCLK_CkSpre5: Auto WeakUp Counting frequency = CK_SPRE5 + * @arg RTC_WeakUp_RTCCLK_CkSpre6: Auto WeakUp Counting frequency = CK_SPRE6 + * @arg RTC_WeakUp_RTCCLK_CkSpre7: Auto WeakUp Counting frequency = CK_SPRE7 + * @retval None + */ +void RTC_WeakUpCountFreqConfig(uint32_t RTC_WeakUpCountFreq) +{ + /* Check the parameters */ + assert_param(IS_RTC_WKUP_COUNTER(RTC_WeakUpCountFreq)); + + /* Clear WUCKSEL[2:0] bits in the RTC_CR register */ + RTC->CR &= (uint32_t)~(RTC_CR_WUCKSEL); + + /* Configure the RTC_CR register */ + RTC->CR |= (uint32_t)RTC_WeakUpCountFreq; +} + +/** + * @brief Configures the BackUp Register Data. + * @param RTC_BackUpReg:choose rtc backup reg + * This parameter can be one of the following values: + * @arg RTC_BackUp0Reg: choose bkp0r reg + * @arg RTC_BackUp1Reg: choose bkp1r reg + * @arg RTC_BackUp2Reg: choose bkp2r reg + * @arg RTC_BackUp3Reg: choose bkp3r reg + * @arg RTC_BackUp4Reg: choose bkp4r reg + * @arg RTC_BackUp5Reg: choose bkp5r reg + * @arg RTC_BackUp6Reg: choose bkp6r reg + * @arg RTC_BackUp7Reg: choose bkp7r reg + * @arg RTC_BackUp8Reg: choose bkp8r reg + * @arg RTC_BackUp9Reg: choose bkp9r reg + * @arg RTC_BackUp10Reg: choose bkp10r reg + * @arg RTC_BackUp11Reg: choose bkp11r reg + * @arg RTC_BackUp12Reg: choose bkp12r reg + * @arg RTC_BackUp13Reg: choose bkp13r reg + * @arg RTC_BackUp14Reg: choose bkp14r reg + * @arg RTC_BackUp15Reg: choose bkp15r reg + * @arg RTC_BackUp16Reg: choose bkp16r reg + * @arg RTC_BackUp17Reg: choose bkp17r reg + * @arg RTC_BackUp18Reg: choose bkp18r reg + * @arg RTC_BackUp19Reg: choose bkp19r reg + * @param RTC_BackUpRegData: Specifies the rtc backup register data. + * This parameter can be only range of the 0~0xFFFFFFFF: + * @retval None + */ +void RTC_BackUpRegConfig(uint32_t RTC_BackUpReg, uint32_t RTC_BackUpRegData) +{ + /* Check the parameters */ + assert_param(IS_RTC_BACKUP_REG(RTC_BackUpReg)); + assert_param(IS_RTC_BACKUP_DATA(RTC_BackUpRegData)); + + if (RTC_BackUpReg == RTC_BackUp0Reg) + { + /* Clear BackUp0 register */ + RTC->BKP0R &= (uint32_t)~(RTC_BKP0R); + + /* Configure the RTC_BKP0R register */ + RTC->BKP0R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp1Reg) + { + /* Clear BackUp1 register */ + RTC->BKP1R &= (uint32_t)~(RTC_BKP1R); + + /* Configure the RTC_BKP1R register */ + RTC->BKP1R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp2Reg) + { + /* Clear BackUp2 register */ + RTC->BKP2R &= (uint32_t)~(RTC_BKP2R); + + /* Configure the RTC_BKP2R register */ + RTC->BKP2R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp3Reg) + { + /* Clear BackUp3 register */ + RTC->BKP3R &= (uint32_t)~(RTC_BKP3R); + + /* Configure the RTC_BKP3R register */ + RTC->BKP3R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp4Reg) + { + /* Clear BackUp4 register */ + RTC->BKP4R &= (uint32_t)~(RTC_BKP4R); + + /* Configure the RTC_BKP4R register */ + RTC->BKP4R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp5Reg) + { + /* Clear BackUp5 register */ + RTC->BKP5R &= (uint32_t)~(RTC_BKP5R); + + /* Configure the RTC_BKP5R register */ + RTC->BKP5R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp6Reg) + { + /* Clear BackUp6 register */ + RTC->BKP6R &= (uint32_t)~(RTC_BKP6R); + + /* Configure the RTC_BKP6R register */ + RTC->BKP6R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp7Reg) + { + /* Clear BackUp7 register */ + RTC->BKP7R &= (uint32_t)~(RTC_BKP7R); + + /* Configure the RTC_BKP7R register */ + RTC->BKP7R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp8Reg) + { + /* Clear BackUp8 register */ + RTC->BKP8R &= (uint32_t)~(RTC_BKP8R); + + /* Configure the RTC_BKP8R register */ + RTC->BKP8R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp9Reg) + { + /* Clear BackUp9 register */ + RTC->BKP9R &= (uint32_t)~(RTC_BKP9R); + + /* Configure the RTC_BKP9R register */ + RTC->BKP9R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp10Reg) + { + /* Clear BackUp10 register */ + RTC->BKP10R &= (uint32_t)~(RTC_BKP10R); + + /* Configure the RTC_BKP10R register */ + RTC->BKP10R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp11Reg) + { + /* Clear BackUp11 register */ + RTC->BKP11R &= (uint32_t)~(RTC_BKP11R); + + /* Configure the RTC_BKP11R register */ + RTC->BKP11R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp12Reg) + { + /* Clear BackUp12 register */ + RTC->BKP12R &= (uint32_t)~(RTC_BKP12R); + + /* Configure the RTC_BKP12R register */ + RTC->BKP12R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp13Reg) + { + /* Clear BackUp13 register */ + RTC->BKP13R &= (uint32_t)~(RTC_BKP13R); + + /* Configure the RTC_BKP13R register */ + RTC->BKP13R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp14Reg) + { + /* Clear BackUp14 register */ + RTC->BKP14R &= (uint32_t)~(RTC_BKP14R); + + /* Configure the RTC_BKP14R register */ + RTC->BKP14R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp15Reg) + { + /* Clear BackUp15 register */ + RTC->BKP15R &= (uint32_t)~(RTC_BKP15R); + + /* Configure the RTC_BKP15R register */ + RTC->BKP15R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp16Reg) + { + /* Clear BackUp16 register */ + RTC->BKP16R &= (uint32_t)~(RTC_BKP16R); + + /* Configure the RTC_BKP16R register */ + RTC->BKP16R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp17Reg) + { + /* Clear BackUp17 register */ + RTC->BKP17R &= (uint32_t)~(RTC_BKP17R); + + /* Configure the RTC_BKP17R register */ + RTC->BKP17R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp18Reg) + { + /* Clear BackUp18 register */ + RTC->BKP18R &= (uint32_t)~(RTC_BKP18R); + + /* Configure the RTC_BKP18R register */ + RTC->BKP18R |= (uint32_t)RTC_BackUpRegData; + } + + if (RTC_BackUpReg == RTC_BackUp19Reg) + { + /* Clear BackUp19 register */ + RTC->BKP19R &= (uint32_t)~(RTC_BKP19R); + + /* Configure the RTC_BKP19R register */ + RTC->BKP19R |= (uint32_t)RTC_BackUpRegData; + } +} + +/** + * @brief Get the RTC BackUp Register value. + * @param RTC_BackUpReg:choose rtc backup reg + * This parameter can be one of the following values: + * @arg RTC_BackUp0Reg: choose bkp0r reg + * @arg RTC_BackUp1Reg: choose bkp1r reg + * @arg RTC_BackUp2Reg: choose bkp2r reg + * @arg RTC_BackUp3Reg: choose bkp3r reg + * @arg RTC_BackUp4Reg: choose bkp4r reg + * @arg RTC_BackUp5Reg: choose bkp5r reg + * @arg RTC_BackUp6Reg: choose bkp6r reg + * @arg RTC_BackUp7Reg: choose bkp7r reg + * @arg RTC_BackUp8Reg: choose bkp8r reg + * @arg RTC_BackUp9Reg: choose bkp9r reg + * @arg RTC_BackUp10Reg: choose bkp10r reg + * @arg RTC_BackUp11Reg: choose bkp11r reg + * @arg RTC_BackUp12Reg: choose bkp12r reg + * @arg RTC_BackUp13Reg: choose bkp13r reg + * @arg RTC_BackUp14Reg: choose bkp14r reg + * @arg RTC_BackUp15Reg: choose bkp15r reg + * @arg RTC_BackUp16Reg: choose bkp16r reg + * @arg RTC_BackUp17Reg: choose bkp17r reg + * @arg RTC_BackUp18Reg: choose bkp18r reg + * @arg RTC_BackUp19Reg: choose bkp19r reg + * * @retval RTC current BackUp Register value. + */ +uint32_t RTC_GetBackUpReg(uint32_t RTC_BackUpReg) +{ + /* Get BackUp Register values from the correspondent registers */ + /* Check the parameters */ + assert_param(IS_RTC_BACKUP_REG(RTC_BackUpReg)); + + if (RTC_BackUpReg == RTC_BackUp0Reg) + { + /* Return the RTC_BKP0R register */ + return (uint32_t)(RTC->BKP0R); + } + + if (RTC_BackUpReg == RTC_BackUp1Reg) + { + /* Return the RTC_BKP1R register */ + return (uint32_t)(RTC->BKP1R); + } + + if (RTC_BackUpReg == RTC_BackUp2Reg) + { + /* Return the RTC_BKP2R register */ + return (uint32_t)(RTC->BKP2R); + } + + if (RTC_BackUpReg == RTC_BackUp3Reg) + { + /* Return the RTC_BKP3R register */ + return (uint32_t)(RTC->BKP3R); + } + + if (RTC_BackUpReg == RTC_BackUp4Reg) + { + /* Return the RTC_BKP4R register */ + return (uint32_t)(RTC->BKP4R); + } + + if (RTC_BackUpReg == RTC_BackUp5Reg) + { + /* Return the RTC_BKP5R register */ + return (uint32_t)(RTC->BKP5R); + } + + if (RTC_BackUpReg == RTC_BackUp6Reg) + { + /* Return the RTC_BKP6R register */ + return (uint32_t)(RTC->BKP6R); + } + + if (RTC_BackUpReg == RTC_BackUp7Reg) + { + /* Return the RTC_BKP7R register */ + return (uint32_t)(RTC->BKP7R); + } + + if (RTC_BackUpReg == RTC_BackUp8Reg) + { + /* Return the RTC_BKP8R register */ + return (uint32_t)(RTC->BKP8R); + } + + if (RTC_BackUpReg == RTC_BackUp9Reg) + { + /* Return the RTC_BKP9R register */ + return (uint32_t)(RTC->BKP9R); + } + + if (RTC_BackUpReg == RTC_BackUp10Reg) + { + /* Return the RTC_BKP10R register */ + return (uint32_t)(RTC->BKP10R); + } + + if (RTC_BackUpReg == RTC_BackUp11Reg) + { + /* Return the RTC_BKP11R register */ + return (uint32_t)(RTC->BKP11R); + } + + if (RTC_BackUpReg == RTC_BackUp12Reg) + { + /* Return the RTC_BKP12R register */ + return (uint32_t)(RTC->BKP12R); + } + + if (RTC_BackUpReg == RTC_BackUp13Reg) + { + /* Return the RTC_BKP13R register */ + return (uint32_t)(RTC->BKP13R); + } + + if (RTC_BackUpReg == RTC_BackUp14Reg) + { + /* Return the RTC_BKP14R register */ + return (uint32_t)(RTC->BKP14R); + } + + if (RTC_BackUpReg == RTC_BackUp15Reg) + { + /* Return the RTC_BKP15R register */ + return (uint32_t)(RTC->BKP15R); + } + + if (RTC_BackUpReg == RTC_BackUp16Reg) + { + /* Return the RTC_BKP16R register */ + return (uint32_t)(RTC->BKP16R); + } + + if (RTC_BackUpReg == RTC_BackUp17Reg) + { + /* Return the RTC_BKP17R register */ + return (uint32_t)(RTC->BKP17R); + } + + if (RTC_BackUpReg == RTC_BackUp18Reg) + { + /* Return the RTC_BKP18R register */ + return (uint32_t)(RTC->BKP18R); + } + + if (RTC_BackUpReg == RTC_BackUp19Reg) + { + /* Return the RTC_BKP19R register */ + return (uint32_t)(RTC->BKP19R); + } + return 0; +} + + + + + + +/** + * @} + */ + + +/** + * @brief Converts a 2 digit decimal to BCD format. + * @param Value: Byte to be converted. + * @retval Converted byte + */ +static uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + uint8_t bcdhigh = 0; + + while (Value >= 10) + { + bcdhigh++; + Value -= 10; + } + + return ((uint8_t)(bcdhigh << 4) | Value); +} + +/** + * @brief Convert from 2 digit BCD to Binary. + * @param Value: BCD value to be converted. + * @retval Converted word + */ +static uint8_t RTC_Bcd2ToByte(uint8_t Value) +{ + uint8_t tmp = 0; + tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; + return (tmp + (Value & (uint8_t)0x0F)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_sdio.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_sdio.c new file mode 100644 index 00000000000..3046101d0df --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_sdio.c @@ -0,0 +1,246 @@ +/** + ****************************************************************************** + * @file ft32f4xx_sdio.c + ****************************************************************************** + */ + + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_sdio.h" +#include "system_ft32f4xx.h" +#include "ft32f4xx_rcc.h" + + +/** @defgroup SDIO + * @brief SDIO driver modules + * @{ + */ + +/*******************/ +void SDIO_DeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE); +} + +/*******************/ +void SDIO_odpullupConfig(uint32_t SDIO_odenable) +{ + /* 1.Clear CTRL_enable_OD_pullup bit */ + SDIO -> CTRL &= ~(0x1 << 24); + assert_param(IS_SDIO_OD_PULLUP(SDIO_odenable)); + SDIO -> CTRL |= SDIO_odenable; +} + + +/*******************/ +void SDIO_UseholdregConfig(uint32_t SDIO_Useholdregenable) +{ + /* 1.Clear CMD_use_hold_reg bit */ + SDIO -> CMD &= ~(0x1 << 29); + assert_param(IS_SDIO_USE_HOLD_REG(SDIO_Useholdregenable)); + SDIO -> CMD |= SDIO_Useholdregenable; +} + +/*******************/ +void SDIO_PowerEnableConfig(uint32_t SDIO_PowerEnable) +{ + assert_param(IS_SDIO_POWER_ON(SDIO_PowerEnable)); + SDIO -> PWREN = SDIO_PowerEnable; +} + + +/*******************/ +void SDIO_TimeOutConfig(uint32_t SDIO_TMOUTValue) +{ + /* Set the TMOUT bits include RESPONSE TMOUT and DATA TMOUT values */ + SDIO -> TMOUT = (uint32_t)SDIO_TMOUTValue; +} + + +/*******************/ +void SDIO_FifoThConfig(uint32_t SDIO_FIFOTHValue) +{ + /* Set the FIFOTH bits include Tx_WMark and Rx_WMark values */ + SDIO -> FIFOTH = (uint32_t)SDIO_FIFOTHValue; +} + + +/*******************/ +void SDIO_CardWidthConfig(uint32_t SDIO_CardWidth) +{ + assert_param(IS_SDIO_CARD_WIDE(SDIO_CardWidth)); + SDIO -> CTYPE = SDIO_CardWidth; +} + + +/*******************/ +void SDIO_TransferModeConfig(uint32_t SDIO_TransferMode) +{ + SDIO -> CMD &= ~(0x1 << 11); + assert_param(IS_SDIO_TRANSFER_MODE(SDIO_TransferMode)); + SDIO -> CMD |= SDIO_TransferMode; +} + + +/*******************/ +void SDIO_TransferDirectionConfig(uint32_t SDIO_ReadWrite) +{ + SDIO -> CMD &= ~(0x1 << 10); + assert_param(IS_SDIO_TRANSFER_DIR(SDIO_ReadWrite)); + SDIO -> CMD |= SDIO_ReadWrite; +} + + +/*******************/ +void SDIO_DataExpectedConfig(uint32_t SDIO_DataExpected) +{ + /* 1.Clear DataExpected bit */ + SDIO -> CMD &= ~(0x1 << 9); + assert_param(IS_SDIO_DATA_EXPECT(SDIO_DataExpected)); + SDIO -> CMD |= SDIO_DataExpected; +} + + +/*******************/ +void SDIO_CheckResponseCRCConfig(uint32_t SDIO_CheckResponseCRC) +{ + /* 1.Clear CheckResponseCRC bit */ + SDIO -> CMD &= ~(0x1 << 8); + assert_param(IS_SDIO_CHECK_RESPONSE_CRC(SDIO_CheckResponseCRC)); + SDIO -> CMD |= SDIO_CheckResponseCRC; +} + + +/*******************/ +void SDIO_ResponseLengthConfig(uint32_t SDIO_ResponseLength) +{ + /* 1.Clear ResponseLength bit */ + SDIO -> CMD &= ~(0x1 << 7); + assert_param(IS_SDIO_RESPONSE(SDIO_ResponseLength)); + SDIO -> CMD |= SDIO_ResponseLength; +} + + +/*******************/ +void SDIO_ResponseExpectConfig(uint32_t SDIO_ResponseExpect) +{ + /* 1.Clear ResponseExpect bit */ + SDIO -> CMD &= ~(0x1 << 6); + assert_param(IS_SDIO_RESPONSE_EXPECT(SDIO_ResponseExpect)); + SDIO -> CMD |= SDIO_ResponseExpect; +} + + +/*******************/ +void SDIO_ChangeCardClock(uint32_t SDIO_Clkdiv) +{ + /* 1.Clear CLKENA[0] bit */ + SDIO->CLKENA &= ~SDIO_CLKENA_CCLK_ENABLE_0; + /* 2.1.Check the parameters */ + assert_param(IS_SDIO_CLKDIV(SDIO_Clkdiv)); + /* 2.2.Clear CLKDIV[7:0] bits */ + SDIO->CLKDIV &= ~SDIO_CLKDIV_CLK_DIVIDER0; + /* 2.3.Set the SDIO_CLKDIV[7:0] bits according to SDIO_Clkdiv value */ + SDIO->CLKDIV |= SDIO_Clkdiv; + /* 3.Enable CMD_UPDATE_CLOCK_REGISTERS_ONLY bit */ + SDIO->CMD |= SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY; + /* 4.Enable CLKENA[0] bit */ + SDIO->CLKENA |= SDIO_CLKENA_CCLK_ENABLE_0; + /* 5.Enable CMD_START_CMD bit */ + SDIO->CMD |= SDIO_CMD_START_CMD; + while (((SDIO -> CMD) & SDIO_CMD_START_CMD) == SDIO_CMD_START_CMD); + /* 6.Clean CMD_UPDATE_CLOCK_REGISTERS_ONLY bit */ + SDIO->CMD &= ~SDIO_CMD_UPDATE_CLOCK_REGISTERS_ONLY; +} + +/*******************/ +void SDIO_SendCMD(uint32_t SDIO_CmdIndex) +{ + /* 1.Clear CMD_INDEX bit */ + SDIO -> CMD &= ~(0x3F << 0); + /* 2.1.Check the parameters */ + assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdIndex)); + /* 2.2.Send Command */ + SDIO -> CMD |= SDIO_CmdIndex; + /* 3.Enable CMD_START_CMD bit */ + SDIO->CMD |= SDIO_CMD_START_CMD; + while (((SDIO -> CMD) & SDIO_CMD_START_CMD) == SDIO_CMD_START_CMD); +} + + +/*******************/ +void SDIO_CMDARGConfig(uint32_t SDIO_CmdArgument) +{ + assert_param(IS_SDIO_CMD_ARG(SDIO_CmdArgument)); + SDIO -> CMDARG = SDIO_CmdArgument; +} + + +/*******************/ +void SDIO_BlockSizeConfig(uint32_t SDIO_BlockSize) +{ + assert_param(IS_SDIO_BLOCK_SIZE(SDIO_BlockSize)); + SDIO -> BLKSIZ = SDIO_BlockSize; +} + + +/*******************/ +void SDIO_ByteCountConfig(uint32_t SDIO_ByteCount) +{ + assert_param(IS_SDIO_DATA_BYTE_COUNT(SDIO_ByteCount)); + SDIO -> BYTCNT = SDIO_ByteCount; +} + + +/*******************/ +void SDIO_ITConfig(uint32_t SDIO_IT) +{ + /* 1.enable CTRL_int_enable bit */ + SDIO -> CTRL |= SDIO_CTRL_INT_ENABLE; + /* Check the parameters */ + assert_param(IS_SDIO_IT_MASK(SDIO_IT)); + SDIO->INTMASK |= SDIO_IT; +} + + +/*******************/ +FlagStatus SDIO_GetITFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT_FLAG(SDIO_FLAG)); + return ((FlagStatus)(SDIO->MINTSTS & SDIO_FLAG)); +} + + +/*******************/ +void SDIO_ClearITFlag(uint32_t SDIO_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SDIO_IT_CLEAN(SDIO_FLAG)); + SDIO->RINTSTS |= SDIO_FLAG; +} + + +/*************/ +uint32_t SDIO_GetFifoStatus(uint32_t SDIO_FIFOStatus) +{ + /* Check the parameters */ + assert_param(IS_SDIO_STATUS(SDIO_FIFOStatus)); + return (uint32_t)((SDIO->STATUS) & SDIO_FIFOStatus); +} + + +/*************/ +uint32_t SDIO_GetStatus(uint32_t SDIO_Status) +{ + /* Check the parameters */ + assert_param(IS_SDIO_STATUS(SDIO_Status)); + return (uint32_t)((SDIO->STATUS) & SDIO_Status); +} +/***********************************************************************************/ +/***********************************************************************************/ + + + + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_spdif.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_spdif.c new file mode 100644 index 00000000000..6dfead8dfb8 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_spdif.c @@ -0,0 +1,207 @@ +/** + ****************************************************************************** + * @file ft32f4xx_spdif.c + * @author xcao + * @brief This file provides firmware functions to manage the following + * functionalities of the SPDIFRX audio interface: + * + Initialization and Configuration + * + Data transfers functions + * + DMA transfers management + * + Interrupts and flags management + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_spdif.h" +#include "ft32f4xx_misc.h" +#define MAX_DELAY 0xFFFF +/** @addtogroup FT32F4XX_Driver + * @{ + */ + +/** @defgroup SPDIF SPDIF + * @brief SPDIFmodule driver + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup SPDIF_Private_Defines SPDIF Private Defines + * @{ + */ + +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ + +/** @defgroup SPDIF_Exported_Functions SPDIF Exported Functions + * @{ + */ + +/** @defgroup SPDIF_Exported_Functions_Group1 Initialization + * @brief Initialization and Configuration functions + * + @verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SPDIF peripheral: + + @endverbatim + * @{ + */ + +/** + * @brief Initializes the SPDIF according to the specified parameters + * in the SPDIF_InitTypeDef and create the associated handle. + * @param spdif SPDIF handle + * @retval NONE + */ +void SPDIFRX_Init(SPDIF_HandleTypeDef *spdif, SPDIFRX_InitTypeDef *spdifrx_init) +{ + uint32_t tmpreg; + + /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ + SPDIF_MspInit(spdif); + + /* SFR block register reset */ + spdif->Instance->SPDIF_CTRL &= ~SPDIF_CTRL_SFR_ENABLE; + //while((spdif->Instance->SPDIF_CTRL&SPDIF_CTRL_SFR_ENABLE) != SPDIF_CTRL_SFR_ENABLE) + spdif->Instance->SPDIF_CTRL |= SPDIF_CTRL_SFR_ENABLE; + + /* SPDIF core reset */ + spdif->Instance->SPDIF_CTRL &= ~SPDIF_CTRL_SPDIF_ENABLE; + /* SPDIF core enable */ + spdif->Instance->SPDIF_CTRL |= SPDIF_CTRL_SPDIF_ENABLE; + + /* FIFO reset */ + spdif->Instance->SPDIF_CTRL &= ~SPDIF_CTRL_FIFO_ENABLE; + while ((spdif->Instance->SPDIF_CTRL & SPDIF_CTRL_FIFO_ENABLE) != SPDIF_CTRL_FIFO_ENABLE) + + /* Reset the old SPDIF CTRL configuration */ + tmpreg = spdif->Instance->SPDIF_CTRL; + + tmpreg &= ~(SPDIF_CTRL_TR_MODE | SPDIF_CTRL_VALIDITYCHECK | SPDIF_CTRL_PARITYCHECK); + + tmpreg |= (uint32_t)(spdifrx_init->StereoMode | + spdifrx_init->ValidityBitMask | + spdifrx_init->ParityErrorMask | + SPDIF_CTRL_INTREQ_MASK); + + spdif->Instance->SPDIF_CTRL = tmpreg; + + /* Set receive fifo almost full and empty threshold */ + spdif->Instance->FIFO_CTRL = ((spdifrx_init->FifoAfullThreshold << 16U) | (spdifrx_init->FifoAemptyThreshold)); +} + +/** + * @brief SPDIF MSP Init + * @param spdif SPDIF handle + * @retval None + */ +void __attribute__((weak)) SPDIF_MspInit(SPDIF_HandleTypeDef *spdif) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(spdif); + + /* NOTE : This function Should not be modified, when the callback is needed, + the SPDIFRX_MspInit could be implemented in the user file + */ +} + + +/** + * @brief Receives an amount of data (Data Flow) in blocking mode. + * @param spdif pointer to SPDIF_HandleTypeDef structure that contains + * the configuration information for SPDIF module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration + * @retval none + */ +void SPDIF_ReceiveDataFlow(SPDIF_HandleTypeDef *spdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t sizeCounter = Size; + uint32_t *pTmpBuf = pData; + + if ((pData == NULL) || (Size == 0U)) + { + return; + } + + /* Start reception */ + spdif->Instance->SPDIF_CTRL |= SPDIF_CTRL_SPDIF_ENABLE; + + /* Wait until lock flag is set */ + while ((spdif->Instance->STAT & SPDIF_STAT_LOCK_FLAG) != SPDIF_STAT_LOCK_FLAG) + { + if (Timeout != MAX_DELAY) + { + if ((GetTick() - tickstart > Timeout) || (Timeout == 0U)) + { + return; + } + } + } + + /* Receive data flow */ + while (sizeCounter > 0U) + { + if ((spdif->Instance->STAT & SPDIF_STAT_EMPTY_FLAG) != SPDIF_STAT_EMPTY_FLAG) + { + (*pTmpBuf) = spdif->Instance->DATA; + pTmpBuf++; + sizeCounter--; + } + } +} + +/** + * @brief Receives an amount of data (Data Flow) in non-blocking mode. + * @param spdif pointer to SPDIF_HandleTypeDef structure that contains + * the configuration information for SPDIF module. + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration + * @retval none + */ +void SPDIFRX_ReceiveDataFlow_IT(SPDIF_HandleTypeDef *spdif, uint32_t *pData, uint16_t Size, + uint32_t Timeout) +{ + uint32_t tickstart; + uint16_t sizeCounter = Size; + uint32_t *pTmpBuf = pData; + + if ((pData == NULL) || (Size == 0U)) + { + return; + } + + /* Enable the SPDIFRX Parity Error Interrupt */ + spdif->Instance->SPDIF_CTRL |= SPDIF_CTRL_PARITY_MASK; + + /* Enable the SPDIFRX OVR Error Interrupt */ + spdif->Instance->SPDIF_CTRL |= SPDIF_CTRL_OVRERR_MASK; + + /* Start reception */ + spdif->Instance->SPDIF_CTRL |= SPDIF_CTRL_SPDIF_ENABLE; + + /* Wait until lock flag is set */ + while ((spdif->Instance->STAT & SPDIF_STAT_LOCK_FLAG) != SPDIF_STAT_LOCK_FLAG) + { + if (Timeout != MAX_DELAY) + { + if ((GetTick() - tickstart > Timeout) || (Timeout == 0U)) + { + return; + } + } + } + +} diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_spi.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_spi.c new file mode 100644 index 00000000000..c9e395c7641 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_spi.c @@ -0,0 +1,827 @@ +/** + ****************************************************************************** + * @file ft32f4xx_spi.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Serial peripheral interface (SPI): + * + Initialization and Configuration + * + Data transfers functions + * + Hardware CRC Calculation + * + DMA transfers management + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-06 + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_spi.h" +#include "ft32f4xx_rcc.h" + +/* SPI registers Masks */ +#define CR1_CLEAR_MASK ((uint16_t)0x3040) +#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB) +#define CR2_LDMA_MASK ((uint16_t)0x9FFF) + +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + + +/** + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_DeInit(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + if (SPIx == SPI1) + { + /* Enable SPI1 reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + /* Release SPI1 from reset state */ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if (SPIx == SPI2) + { + /* Enable SPI2 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + /* Release SPI2 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else if (SPIx == SPI3) + { + /* Enable SPI3 reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + /* Release SPI3 from reset state */ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + +} + +/** + * @brief Fills each SPI_InitStruct member with its default value. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized. + * @retval None + */ +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct) +{ + /*--------------- Reset SPI init structure parameters values -----------------*/ + /* Initialize the SPI_Direction member */ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + /* Initialize the SPI_Mode member */ + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + /* Initialize the SPI_DataSize member */ + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + /* Initialize the SPI_CPOL member */ + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + /* Initialize the SPI_CPHA member */ + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + /* Initialize the SPI_NSS member */ + SPI_InitStruct->SPI_NSS = SPI_NSS_Hard; + /* Initialize the SPI_BaudRatePrescaler member */ + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + /* Initialize the SPI_FirstBit member */ + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + /* Initialize the SPI_CRCPolynomial member */ + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/** + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * @retval None + */ +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + /* check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Check the SPI parameters */ + assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction)); + assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode)); + assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize)); + assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL)); + assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA)); + assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS)); + assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler)); + assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit)); + assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial)); + + /*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */ + tmpreg &= CR1_CLEAR_MASK; + /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler + master/slave mode, CPOL and CPHA */ + /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */ + /* Set SSM, SSI bit according to SPI_NSS values */ + /* Set LSBFirst bit according to SPI_FirstBit value */ + /* Set BR bits according to SPI_BaudRatePrescaler value */ + /* Set CPOL bit according to SPI_CPOL value */ + /* Set CPHA bit according to SPI_CPHA value */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit | + SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA | + SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + /*-------------------------Data Size Configuration -----------------------*/ + /* Get the SPIx CR2 value */ + tmpreg = SPIx->CR2; + /* Clear DS[3:0] bits */ + tmpreg &= (uint16_t)~SPI_CR2_DS; + /* Configure SPIx: Data Size */ + tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize); + /* Write to SPIx CR2 */ + SPIx->CR2 = tmpreg; + + /*---------------------------- SPIx CRCPOLY Configuration --------------------*/ + /* Write to SPIx CRCPOLY */ + SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial; + + /*---------------------------- SPIx CR1 Configuration ------------------------*/ + /* Get the SPIx CR1 value */ + tmpreg = SPIx->CR1; + /* Clear MSTR bit */ + tmpreg &= CR1_CLEAR_MASK2; + /* Configure SPIx: master/slave mode */ + /* Set MSTR bit according to SPI_Mode */ + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode); + /* Write to SPIx CR1 */ + SPIx->CR1 = tmpreg; + +// /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ +// SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD); +} +/** + * @brief Enables or disables the specified SPI peripheral. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI peripheral */ + SPIx->CR1 |= SPI_CR1_SPE; + } + else + { + /* Disable the selected SPI peripheral */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE); + } +} + +/** + * @brief Enables or disables the TI Mode. + * + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA + * are not taken into consideration and are configured by hardware + * respectively to the TI mode requirements. + * + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the selected SPI TI communication mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TI mode for the selected SPI peripheral */ + SPIx->CR2 |= SPI_CR2_FRF; + } + else + { + /* Disable the TI mode for the selected SPI peripheral */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF); + } +} +/** + * @brief Configures the data size for the selected SPI. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_DataSize: specifies the SPI data size. + * For the SPIx peripheral this parameter can be one of the following values: + * @arg SPI_DataSize_4b: Set data size to 4 bits + * @arg SPI_DataSize_5b: Set data size to 5 bits + * @arg SPI_DataSize_6b: Set data size to 6 bits + * @arg SPI_DataSize_7b: Set data size to 7 bits + * @arg SPI_DataSize_8b: Set data size to 8 bits + * @arg SPI_DataSize_9b: Set data size to 9 bits + * @arg SPI_DataSize_10b: Set data size to 10 bits + * @arg SPI_DataSize_11b: Set data size to 11 bits + * @arg SPI_DataSize_12b: Set data size to 12 bits + * @arg SPI_DataSize_13b: Set data size to 13 bits + * @arg SPI_DataSize_14b: Set data size to 14 bits + * @arg SPI_DataSize_15b: Set data size to 15 bits + * @arg SPI_DataSize_16b: Set data size to 16 bits + * @retval None + */ +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize) +{ + uint16_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DATA_SIZE(SPI_DataSize)); + /* Read the CR2 register */ + tmpreg = SPIx->CR2; + /* Clear DS[3:0] bits */ + tmpreg &= (uint16_t)~SPI_CR2_DS; + /* Set new DS[3:0] bits value */ + tmpreg |= SPI_DataSize; + SPIx->CR2 = tmpreg; +} + +/** + * @brief Configures the FIFO reception threshold for the selected SPI. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold. + * This parameter can be one of the following values: + * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO + * level is greater or equal to 1/2. + * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO + * level is greater or equal to 1/4. + * @retval None + */ +void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold)); + + /* Clear FRXTH bit */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH); + + /* Set new FRXTH bit value */ + SPIx->CR2 |= SPI_RxFIFOThreshold; +} + +/** + * @brief Selects the data transfer direction in bidirectional mode for the specified SPI. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_Direction: specifies the data transfer direction in bidirectional mode. + * This parameter can be one of the following values: + * @arg SPI_Direction_Tx: Selects Tx transmission direction + * @arg SPI_Direction_Rx: Selects Rx receive direction + * @retval None + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_DIRECTION(SPI_Direction)); + if (SPI_Direction == SPI_Direction_Tx) + { + /* Set the Tx only mode */ + SPIx->CR1 |= SPI_Direction_Tx; + } + else + { + /* Set the Rx only mode */ + SPIx->CR1 &= SPI_Direction_Rx; + } +} + +/** + * @brief Configures internally by software the NSS pin for the selected SPI. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state. + * This parameter can be one of the following values: + * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally + * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally + * @retval None + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft)); + + if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + /* Set NSS pin internally by software */ + SPIx->CR1 |= SPI_NSSInternalSoft_Set; + } + else + { + /* Reset NSS pin internally by software */ + SPIx->CR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/** + * @brief Enables or disables the SS output for the selected SPI. + * @note This function can be called only after the SPI_Init() function has + * been called and the NSS hardware management mode is selected. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx SS output. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Enable the selected SPI SS output */ + SPIx->CR2 |= SPI_CR2_SSOE; + } + else + { + /* Disable the selected SPI SS output */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE); + } +} + +/** + * @brief Enables or disables the NSS pulse management mode. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @note When TI mode is selected, the control bits NSSP is not taken into + * consideration and are configured by hardware respectively to the + * TI mode requirements. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the NSS pulse management mode. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the NSS pulse management mode */ + SPIx->CR2 |= SPI_CR2_NSSP; + } + else + { + /* Disable the NSS pulse management mode */ + SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP); + } +} + +/** + * @} + */ +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode to select the SPI peripheral. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data) +{ + uint32_t spixbase = 0x00; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + spixbase = (uint32_t)SPIx; + spixbase += 0x0C; + + *(__IO uint8_t *) spixbase = Data; +} + +/** + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param Data: Data to be transmitted. + * @retval None + */ +void SPI_SendData16(SPI_TypeDef* SPIx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + SPIx->DR = (uint16_t)Data; +} + +/** + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode to select the SPI peripheral. + * @retval The value of the received data. + */ +uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx) +{ + uint32_t spixbase = 0x00; + + spixbase = (uint32_t)SPIx; + spixbase += 0x0C; + + return *(__IO uint8_t *) spixbase; +} + +/** + * @brief Returns the most recent received data by the SPIx peripheral. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @retval The value of the received data. + */ +uint16_t SPI_ReceiveData16(SPI_TypeDef* SPIx) +{ + return SPIx->DR; +} +/** + * @} + */ +/** + * @brief Configures the CRC calculation length for the selected SPI. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_CRCLength: specifies the SPI CRC calculation length. + * This parameter can be one of the following values: + * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits + * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits + * @retval None + */ +void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength)); + + /* Clear CRCL bit */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL); + + /* Set new CRCL bit value */ + SPIx->CR1 |= SPI_CRCLength; +} + +/** + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * @note This function can be called only after the SPI_Init() function has + * been called. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param NewState: new state of the SPIx CRC value calculation. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI CRC calculation */ + SPIx->CR1 |= SPI_CR1_CRCEN; + } + else + { + /* Disable the selected SPI CRC calculation */ + SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN); + } +} + +/** + * @brief Transmit the SPIx CRC value. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @retval None + */ +void SPI_TransmitCRC(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Enable the selected SPI CRC transmission */ + SPIx->CR1 |= SPI_CR1_CRCNEXT; +} + +/** + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_CRC: specifies the CRC register to be read. + * This parameter can be one of the following values: + * @arg SPI_CRC_Tx: Selects Tx CRC register + * @arg SPI_CRC_Rx: Selects Rx CRC register + * @retval The selected CRC register value.. + */ +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CRC(SPI_CRC)); + + if (SPI_CRC != SPI_CRC_Rx) + { + /* Get the Tx CRC register */ + crcreg = SPIx->TXCRCR; + } + else + { + /* Get the Rx CRC register */ + crcreg = SPIx->RXCRCR; + } + /* Return the selected CRC register */ + return crcreg; +} + +/** + * @brief Returns the CRC Polynomial register value for the specified SPI. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @retval The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + + /* Return the CRC polynomial register */ + return SPIx->CRCPR; +} + +/** + * @} + */ +/** + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg SPI_DMAReq_Tx: Tx buffer DMA transfer request + * @arg SPI_DMAReq_Rx: Rx buffer DMA transfer request + * @param NewState: new state of the selected SPI DMA transfer request. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_DMAReq, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_DMA_REQ(SPI_DMAReq)); + + if (NewState != DISABLE) + { + /* Enable the selected SPI DMA requests */ + SPIx->CR2 |= SPI_DMAReq; + } + else + { + /* Disable the selected SPI DMA requests */ + SPIx->CR2 &= (uint16_t)~SPI_DMAReq; + } +} + +/** + * @brief Configures the number of data to transfer type(Even/Odd) for the DMA + * last transfers and for the selected SPI. + * @note This function have a meaning only if DMA mode is selected and if + * the packing mode is used (data length <= 8 and DMA transfer size halfword) + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state. + * This parameter can be one of the following values: + * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even + * and number of data for reception Even. + * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd + * and number of data for reception Even. + * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even + * and number of data for reception Odd. + * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd + * and number of data for reception Odd. + * @retval None + */ +void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer)); + + /* Clear LDMA_TX and LDMA_RX bits */ + SPIx->CR2 &= CR2_LDMA_MASK; + + /* Set new LDMA_TX and LDMA_RX bits value */ + SPIx->CR2 |= SPI_LastDMATransfer; +} + +/** + * @} + */ +/** + * @brief Enables or disables the specified SPI/I2S interrupts. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_IT: specifies the SPI interrupt source to be enabled or disabled. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt mask + * @arg SPI_IT_RXNE: Rx buffer not empty interrupt mask + * @arg SPI_IT_ERR: Error interrupt mask + * @param NewState: new state of the specified SPI interrupt. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void SPI_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0 ; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + assert_param(IS_SPI_CONFIG_IT(SPI_IT)); + + /* Get the SPI IT index */ + itpos = SPI_IT >> 4; + + /* Set the IT mask */ + itmask = (uint16_t)1 << (uint16_t)itpos; + + if (NewState != DISABLE) + { + /* Enable the selected SPI interrupt */ + SPIx->CR2 |= itmask; + } + else + { + /* Disable the selected SPI interrupt */ + SPIx->CR2 &= (uint16_t)~itmask; + } +} + +/** + * @brief Returns the current SPIx Transmission FIFO filled level. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @retval The Transmission FIFO filling state. + * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty + * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full. + * - SPI_TransmissionFIFOStatus_Full: when FIFO is full. + */ +uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx) +{ + /* Get the SPIx Transmission FIFO level bits */ + return (uint16_t)((SPIx->SR & SPI_SR_FTLVL)); +} + +/** + * @brief Returns the current SPIx Reception FIFO filled level. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @retval The Reception FIFO filling state. + * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty + * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full. + * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full. + * - SPI_ReceptionFIFOStatus_Full: when FIFO is full. + */ +uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx) +{ + /* Get the SPIx Reception FIFO level bits */ + return (uint16_t)((SPIx->SR & SPI_SR_FRLVL)); +} + +/** + * @brief Checks whether the specified SPI flag is set or not. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_FLAG: specifies the SPI flag to check. + * This parameter can be one of the following values: + * @arg SPI_FLAG_TXE: Transmit buffer empty flag. + * @arg SPI_FLAG_RXNE: Receive buffer not empty flag. + * @arg SPI_FLAG_BSY: Busy flag. + * @arg SPI_FLAG_OVR: Overrun flag. + * @arg SPI_FLAG_MODF: Mode Fault flag. + * @arg SPI_FLAG_CRCERR: CRC Error flag. + * @arg SPI_FLAG_FRE: TI frame format error flag. + * @retval The new state of SPI_FLAG (SET or RESET). + */ +FlagStatus SPI_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + FlagStatus bitstatus = RESET; + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_GET_FLAG(SPI_FLAG)); + + /* Check the status of the specified SPI flag */ + if ((SPIx->SR & SPI_FLAG) != (uint16_t)RESET) + { + /* SPI_FLAG is set */ + bitstatus = SET; + } + else + { + /* SPI_FLAG is reset */ + bitstatus = RESET; + } + /* Return the SPI_FLAG status */ + return bitstatus; +} + +/** + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * @param SPIx: where x can be 1 or 2 or 3 to select the SPI peripheral. + * @param SPI_FLAG: specifies the SPI flag to clear. + * This function clears only CRCERR flag. + * @note OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DR register (SPI_ReceiveData()) followed by + * a read operation to SPI_SR register (SPI_GetFlagStatus()). + * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_SR register (SPI_GetFlagStatus()) followed by + * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI). + * @retval None + */ +void SPI_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_FLAG) +{ + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_CLEAR_FLAG(SPI_FLAG)); + + /* Clear the selected SPI CRC Error (CRCERR) flag */ + SPIx->SR = (uint16_t)~SPI_FLAG; +} + +/** + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * @param SPIx: where x can be 1 or 2 or 3 in SPI mode or 1 in I2S mode to select + * the SPI peripheral. + * @param SPI_IT: specifies the SPI interrupt source to check. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Transmit buffer empty interrupt. + * @arg SPI_IT_RXNE: Receive buffer not empty interrupt. + * @arg SPI_IT_MODF: Mode Fault interrupt. + * @arg SPI_IT_OVR: Overrun interrupt. + * @arg SPI_IT_FRE: Format Error interrupt. + * @retval The new state of SPI_IT (SET or RESET). + */ +ITStatus SPI_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_PERIPH(SPIx)); + assert_param(IS_SPI_GET_IT(SPI_IT)); + + /* Get the SPI_IT index */ + itpos = 0x01 << (SPI_IT & 0x0F); + + /* Get the SPI_IT IT mask */ + itmask = SPI_IT >> 4; + + /* Set the IT mask */ + itmask = 0x01 << itmask; + + /* Get the SPI_IT enable bit status */ + enablestatus = (SPIx->CR2 & itmask) ; + + /* Check the status of the specified SPI interrupt */ + if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus) + { + /* SPI_IT is set */ + bitstatus = SET; + } + else + { + /* SPI_IT is reset */ + bitstatus = RESET; + } + /* Return the SPI_IT status */ + return bitstatus; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_ssi.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_ssi.c new file mode 100644 index 00000000000..70ea014bc44 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_ssi.c @@ -0,0 +1,1297 @@ +/** + ************************************************************************** + * @file ft32f4xx_eth.c + * @author xcao + * @brief ssi module driver + * This file provides firmware functions to manage the following + * functionalities of the ssi peripheral: + * + Initialization and deinitialization functions + * + IO operation :functions + * + Peripheral Control funtions + * + Peripheral State and Errors functions + * + ************************************************************************** + * @attention + * + ************************************************************************** + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + + [..] + The SSI driver can be used as follows: + + (#) Declare a SSI_HandleTypeDef handle structure (eg. SSI_HandleTypeDef hssi). + (#) Initialize the SSI low level resources by implementing the SSI_MspInit() API: + (##) ENABLE the SSI interface clock. + (##) SSI pins configuration: + (+++) ENABLE the clock for the SSI GPIOs. + (+++) Configure these SSI pins as alternate function pull-up. + (##) NVIC configuration if you need to use interrupt process (SSI_Transmit_IT() + and SSI_Receive_IT() APIs): + (+++) Configure the SSI interrupt priority. + (+++) ENABLE the NVIC SSI IRQ handle. + + [..] + (@) The specific SSI interrupts (FIFO request and Overrun underrun interrupt) + will be managed using the macros __SSI_ENABLE_IT() and __SSI_DISABLE_IT() + inside the transmit and receive process. + + + [..] + Two operation modes are available within this driver : + + *** Polling mode IO operation *** + ================================= + [..] + (+) Send an amount of data in blocking mode using _SSI_Transmit() + (+) Receive an amount of data in blocking mode using _SSI_Receive() + + *** Interrupt mode IO operation *** + =================================== + + + @endverbatim + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_ssi.h" +#include "ft32f4xx_misc.h" +#define MAX_DELAY 0xFFFF +/** @addtogroup FT32F4xx__Driver + * @{ + */ + +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup SSI_Private_Functions SSI Private Functions + * @{ + */ +static void TxClkFreqSet(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit); +static void RxClkFreqSet(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit); +static void SSI_Fifo0Tx(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit, uint32_t Timeout, uint32_t tickstart); +static void SSI_Fifo1Tx(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit, uint32_t Timeout, uint32_t tickstart); +static void SSI_STX0Tx(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit, uint32_t Timeout, uint32_t tickstart); +static void SSI_SRX0Rx(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit, uint32_t Timeout, uint32_t tickstart); +static void SSI_Fifo0Rx(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit, uint32_t Timeout, uint32_t tickstart); +static void SSI_Fifo1Rx(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit, uint32_t Timeout, uint32_t tickstart); +static void SSI_STX0Rx(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit, uint32_t Timeout, uint32_t tickstart); +static void SSI_FillDfifo(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit); +static void SSI_FillFifo_0(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit); +static void SSI_FillFifo_1(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit); +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup SSI_Exported_Functions SSI Exported Functions + * @{ + */ + +/** @defgroup SSI_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization and de-initialization functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to initialize and + de-initialize the SSI peripheral: + + (+) User must implement SSI_MspInit() function in which he configures + all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). + + (+) Call the function SSI_Init() to configure the selected device with + the selected configuration: + (++) Mode (Normal/Net/I2S/AC97) + (++) Data Size + (++) Bit clk frequency + (++) FIFO Threshold + (++) Frame Config + (++) Slot Config + +@endverbatim + * @{ + */ + + +/** + * @brief Initialize the SSI according to the specified parameters. + * in the SSI_InitTypeDef structure and initialize the associated handle. + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_init pointer to a SSI_InitTypeDef structure that contains + * the SSI initialization information + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @param ssi_rxinit pointer to a SSI_RxInitTypeDef structure that contains + * the SSI Rx initialization information + * @retval void + */ +void SSI_Init(SSI_HandleTypeDef *ssi, + SSI_InitTypeDef *ssi_init, + SSI_TxInitTypeDef *ssi_txinit, + SSI_RxInitTypeDef *ssi_rxinit) +{ + uint32_t temreg = (uint32_t)0U; + + /* Check the SSI parameters */ + assert_param(IS_SSI_MODE(ssi_init->Mode)); + + if (ssi->State == SSI_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + SSI_MspInit(ssi); + printf("Low level initialization finish!\n"); + } + + ssi->State = SSI_STATE_BUSY; + + /*Disable SSI*/ + ssi->Instance->SCR &= ~SSI_SCR_SSIEN; + + switch (ssi_init->Mode) + { + case NET : + { + temreg |= (uint32_t)SSI_SCR_NET; + } + break; + case I2S_MASTER : + { + temreg |= (uint32_t)I2S_MASTER_PARAM; + } + break; + case I2S_SLAVE: + { + temreg |= (uint32_t)I2S_SLAVE_PARAM; + } + case AC97: + { + assert_param(IS_SSI_AC97SLOTWIDTH(ssi_init->AC97SLOTWIDTH)); + } + break; + default: + break; + } + + if (ssi_init->SyncMode == ENABLE) + { + temreg |= (uint32_t)SSI_SCR_SYN; + } + + if (ssi_init->TCHEN == ENABLE) + { + temreg |= (uint32_t)SSI_SCR_TCH_EN; + } + + if (ssi_init->OVERSAMPLE == ENABLE) + { + temreg |= (uint32_t)SSI_SCR_SYS_CLK_EN; + } + + if (ssi_init->RFRCLKDIS == ENABLE) + { + temreg |= (uint32_t)SSI_SCR_RFR_CLK_DIS; + } + + if (ssi_init->TFRCLKDIS == ENABLE) + { + temreg |= (uint32_t)SSI_SCR_TFR_CLK_DIS; + } + + ssi->Instance->SCR &= (uint32_t)(~(SSI_SCR_RFR_CLK_DIS | SSI_SCR_TFR_CLK_DIS + | SSI_SCR_TCH_EN | SSI_SCR_SYS_CLK_EN + | SSI_SCR_I2SMODE | SSI_SCR_SYN | SSI_SCR_NET + | SSI_SCR_TE | SSI_SCR_RE)); + + if (ssi_init->Mode == AC97) + { + ssi->Instance->STCCR &= (uint32_t)(~(SSI_STCCR_WL | SSI_STCCR_DC)); + ssi->Instance->SRCCR &= (uint32_t)(~(SSI_SRCCR_WL | SSI_SRCCR_DC)); + + /*AC97 word lenth can only set to 16 or 20 , and frame length can only set to 13 slots*/ + if (ssi_init->AC97SLOTWIDTH == SLOTWIDEQ20) + { + ssi->Instance->STCCR |= (uint32_t)((SSI_DATA_WL20 << 13U) | (SSI_FRAME_LEN12 << 8U)); + ssi->Instance->SRCCR |= (uint32_t)((SSI_DATA_WL20 << 13U) | (SSI_FRAME_LEN12 << 8U)); + } + else if (ssi_init->AC97SLOTWIDTH == SLOTWIDEQ16) + { + ssi->Instance->STCCR |= (uint32_t)((SSI_DATA_WL16 << 13U) | (SSI_FRAME_LEN12 << 8U)); + ssi->Instance->SRCCR |= (uint32_t)((SSI_DATA_WL16 << 13U) | (SSI_FRAME_LEN12 << 8U)); + } + + ssi->Instance->SACNT &= (uint32_t)(~(SSI_SACNT_FRDIV | SSI_SACNT_TIF + | SSI_SACNT_FV | SSI_SACNT_AC97EN)); + + /*AC97 frame rate divider*/ + ssi->Instance->SACNT |= (uint32_t)((ssi_init->AC97FRDIV) << 5U); + + if (ssi_init->AC97RXTAGINFIFO == ENABLE) + { + ssi->Instance->SACNT |= SSI_SACNT_TIF; + } + + if (ssi_init->AC97VarMode == ENABLE) + { + ssi->Instance->SACNT |= SSI_SACNT_FV; + } + + } + + ssi->Instance->SCR |= temreg | (uint32_t)SSI_SCR_SSIEN; + + ssi->State = SSI_STATE_READY; +} +/** + * @} + */ + + +/** + * @brief Configure TX bit clock frequency using specified parameters. + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module + * + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI initialization information + * @retval NONE + */ +static void TxClkFreqSet(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit) +{ + uint32_t temreg = (uint32_t)0U; + + assert_param(IS_SSI_BITCLK_FIXDIV(ssi_txinit->FixedDivParam)); + assert_param(IS_SSI_DATA_SIZE(ssi_txinit->DataSize)); + + /*Configure bit clock frequency using the following formula : + f(Bit_clk) = f(ssi_system_clk(pll2_q)) / ((DIV2 + 1) * ((PSR * 7)+1) * ((PM + 1)*2)) + DIV2 and PSR are bit configuration option which belongs fixed prescaler paramter. + PM can be modify by usrs according to application. + */ + + /* Note:f(Bit_clk) is never greater than 1/5 of the f(pclk1) */ + + switch (ssi_txinit->FixedDivParam) + { + case FIX_CLOCK_DIV4: + { + temreg = (uint32_t)SSI_STCCR_DIV2; + } + break; + case FIX_CLOCK_DIV16: + { + temreg = (uint32_t)SSI_STCCR_PSR; + } + break; + case FIX_CLOCK_DIV32: + { + temreg = (uint32_t)(SSI_STCCR_DIV2 | SSI_STCCR_PSR); + } + break; + default: + break; + } + + + temreg |= (uint32_t)((ssi_txinit->CustomDivParam) & 0x000000ff); + + /* Configure Word clock */ + temreg |= (uint32_t)((ssi_txinit-> DataSize) << 13U); + + /* Configure Frame length */ + temreg |= (uint32_t)((ssi_txinit-> FrameRate) << 8U); + + ssi->Instance->STCCR &= (uint32_t)(~(SSI_STCCR_DIV2 | SSI_STCCR_PSR + | SSI_STCCR_WL | SSI_STCCR_DC + | SSI_STCCR_PM)); + ssi->Instance->STCCR |= temreg; +} + + +/** + * @brief Configure RX bit clock frequency using specified parameters. + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module + * + * @param ssi_rxinit pointer to a SSI_RxInitTypeDef structure that contains + * the SSI Rx initialization information + * @retval NONE + */ +static void RxClkFreqSet(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit) +{ + uint32_t temreg = (uint32_t)0U; + + assert_param(IS_SSI_BITCLK_FIXDIV(ssi_rxinit->FixedDivParam)); + assert_param(IS_DATA_SIZE(ssi_rxinit->DataSize)); + + /*Configure bit clock frequency using the following formula : + f(Bit_clk) = f(ssi_system_clk(pll2_q)) / ((DIV2 + 1) * ((PSR * 7)+1) * ((PM + 1)*2)) + DIV2 and PSR are bit configuration option which belongs fixed prescaler paramter. + PM can be modify by usrs according to application. + */ + + /* Note:f(Bit_clk) is never greater than 1/5 of the f(pclk1) */ + + switch (ssi_rxinit->FixedDivParam) + { + case FIX_CLOCK_DIV4: + { + temreg = (uint32_t)SSI_SRCCR_DIV2; + } + break; + case FIX_CLOCK_DIV16: + { + temreg = (uint32_t)SSI_SRCCR_PSR; + } + break; + case FIX_CLOCK_DIV32: + { + temreg = (uint32_t)(SSI_SRCCR_DIV2 | SSI_SRCCR_PSR); + } + break; + default: + break; + } + + + temreg |= (uint32_t)((ssi_rxinit->CustomDivParam) & 0x000000ff); + + + /* Configure Word clock */ + temreg |= (uint32_t)((ssi_rxinit->DataSize) << 13U); + + /* Configure Frame length */ + temreg |= (uint32_t)((ssi_rxinit->FrameRate) << 8U); + + ssi->Instance->SRCCR &= (uint32_t)(~(SSI_SRCCR_DIV2 | SSI_SRCCR_PSR + | SSI_SRCCR_WL | SSI_SRCCR_DC + | SSI_SRCCR_PM)); + ssi->Instance->SRCCR |= temreg; +} + +/** @addtogroup SSI_Private_Functions SSI Private Functions + * @{ + */ + + + + +/** + * @brief Configure Transmit initial flow . + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module + * + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @retval NONE + */ +void TxConfigInit(SSI_HandleTypeDef *ssi, SSI_InitTypeDef *ssi_init, SSI_TxInitTypeDef *ssi_txinit) +{ + uint32_t temreg1 = (uint32_t)0U; + uint32_t temreg2 = (uint32_t)0U; + + assert_param(IS_SSI_TRANSDATA_TYPE(ssi_txinit->TxDataType)); + assert_param(IS_SSI_FIFO_WATERMARK(ssi_txinit->FIFO0WaterMark)); + assert_param(IS_SSI_FIFO_WATERMARK(ssi_txinit->FIFO1WaterMark)); + assert_param(IS_SSI_FRAMESYNC_POLARITY(ssi_txinit->FrameSyncPolarity)); + assert_param(IS_SSI_CLOCK_POLARITY(ssi_txinit->TxClkPolarity)); + + /* ENABLE Tx FIFO */ + /* Configure Tx FIFO Water Mark */ + if (ssi_txinit->FIFO0EN == ENABLE) + { + temreg1 |= (uint32_t)(SSI_STCR_TFEN0); + temreg2 |= ssi_txinit->FIFO0WaterMark; + } + + if (ssi_txinit->FIFO1EN == ENABLE) + { + temreg1 |= (uint32_t)(SSI_STCR_TFEN1); + temreg2 |= (uint32_t)(ssi_txinit->FIFO1WaterMark << 16U); + } + + /*Configure Tx data MSB or LSB transmission*/ + switch (ssi_txinit->TxDataType) + { + case MSB_MSW: + { + temreg1 &= (uint32_t)(~(SSI_STCR_TXBIT0 | SSI_STCR_TSHFD)); + } + break; + case LSB_MSW: + { + temreg1 |= (uint32_t)SSI_STCR_TSHFD; + temreg1 &= (uint32_t)(~(SSI_STCR_TXBIT0)); + } + break; + case MSB_LSW: + { + temreg1 &= (uint32_t)(~(SSI_STCR_TSHFD)); + temreg1 |= (uint32_t)SSI_STCR_TXBIT0; + } + break; + default: + break; + } + + + /* Configure frame sync direction */ + if (ssi_txinit->FrameSyncFromExit != ENABLE) + { + temreg1 |= (uint32_t)SSI_STCR_TFDIR; + } + + /* Configure Tx direction */ + if (ssi_txinit->TxClkFromExit != ENABLE) + { + temreg1 |= (uint32_t)SSI_STCR_TXDIR; + } + + /* Configure Tx clock polarity */ + if (ssi_txinit->TxClkPolarity == FALLINGEDGE) + { + temreg1 |= (uint32_t)SSI_STCR_TSCKP; + } + + /* Configure Frame sync Length mode*/ + if (ssi_txinit->FrameSyncLenBit == ENABLE) + { + temreg1 |= (uint32_t)SSI_STCR_TFSL; + } + + /* Configure Frame sync early */ + if (ssi_txinit->FrameSyncEarly == ENABLE) + { + temreg1 |= (uint32_t)SSI_STCR_TEFS; + } + + /* Configure Frame sync polarity */ + if (ssi_txinit->FrameSyncPolarity == ACTIVELOW) + { + temreg1 |= (uint32_t)SSI_STCR_TFSI; + } + + ssi->Instance->STCR &= (uint32_t)(~(SSI_STCR_TFEN0 | SSI_STCR_TFEN1 + | SSI_STCR_TSHFD | SSI_STCR_TXBIT0 + | SSI_STCR_TFDIR | SSI_STCR_TXDIR + | SSI_STCR_TSCKP | SSI_STCR_TEFS + | SSI_STCR_TFSL | SSI_STCR_TFSI)); + + ssi->Instance->STCR |= temreg1; + + ssi->Instance->SFCSR &= (uint32_t)(~(SSI_SFCSR_TFWM0 | SSI_SFCSR_TFWM1)); + + ssi->Instance->SFCSR |= temreg2; + + ssi->Instance->STMSK &= ~(SSI_STMSK_STMSK); + + ssi->Instance->STMSK = ssi_txinit->TxSlotMsk; + + /* fill tag register if AC97 fixed mode */ + if (ssi_init->Mode == AC97) + { + if (ssi_init->AC97VarMode != ENABLE) + { + ssi->Instance->SATAG &= ~(SSI_SATAG_SATAG); + + ssi->Instance->SATAG |= (uint32_t)(ssi_txinit->AC97TxSlotEn); + } + else + { + /* Disable all slots when initial ac97 tx flow at variable mode */ + ssi->Instance->SACCDIS |= SSI_SACCDIS_SACCDIS; + } + } + + TxClkFreqSet(ssi, ssi_txinit); + +} + +/** + * @brief Configure Receive initial flow . + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module + * + * @param ssi_rxinit pointer to a SSI_RxInitTypeDef structure that contains + * the SSI Rx initialization information + * @retval NONE + */ +void RxConfigInit(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit) +{ + uint32_t temreg1 = (uint32_t)0U; + uint32_t temreg2 = (uint32_t)0U; + + assert_param(IS_SSI_TRANSDATA_TYPE(ssi_rxinit->RxDataType)); + assert_param(IS_SSI_FIFO_WATERMARK(ssi_rxinit->FIFO0WaterMark)); + assert_param(IS_SSI_FIFO_WATERMARK(ssi_rxinit->FIFO1WaterMark)); + assert_param(IS_SSI_FRAMESYNC_POLARITY(ssi_rxinit->FrameSyncPolarity)); + assert_param(IS_SSI_CLOCK_POLARITY(ssi_rxinit->RxClkPolarity)); + + /* ENABLE Rx FIFO */ + /* Configure Rx FIFO Water Mark */ + if (ssi_rxinit->FIFO0EN == ENABLE) + { + temreg1 |= (uint32_t)(SSI_SRCR_RFEN0); + temreg2 |= (uint32_t)(ssi_rxinit->FIFO0WaterMark << 4U); + } + + if (ssi_rxinit->FIFO1EN == ENABLE) + { + temreg1 |= (uint32_t)(SSI_SRCR_RFEN1); + temreg2 |= (uint32_t)(ssi_rxinit->FIFO1WaterMark << 20U); + } + + /*Configure Rx data MSB or LSB transmission*/ + switch (ssi_rxinit->RxDataType) + { + case MSB_MSW: + { + temreg1 &= (uint32_t)(~(SSI_SRCR_RXBIT0 | SSI_SRCR_RSHFD)); + } + break; + case LSB_MSW: + { + temreg1 |= (uint32_t)SSI_SRCR_RSHFD; + temreg1 &= (uint32_t)(~(SSI_SRCR_RXBIT0)); + } + break; + case MSB_LSW: + { + temreg1 &= (uint32_t)(~(SSI_SRCR_RSHFD)); + temreg1 |= (uint32_t)SSI_SRCR_RXBIT0; + } + break; + default: + break; + } + + /* Configure frame sync direction */ + if (ssi_rxinit->FrameSyncFromExit != ENABLE) + { + temreg1 |= (uint32_t)SSI_SRCR_RFDIR; + } + + /* Configure Rx direction */ + if (ssi_rxinit->RxClkFromExit != ENABLE) + { + temreg1 |= (uint32_t)SSI_SRCR_RXDIR; + } + + /* Configure Rx clock polarity */ + if (ssi_rxinit->RxClkPolarity == FALLINGEDGE) + { + temreg1 |= (uint32_t)SSI_SRCR_RSCKP; + } + + /* Configure Frame sync Length mode*/ + if (ssi_rxinit->FrameSyncLenBit == ENABLE) + { + temreg1 |= (uint32_t)SSI_SRCR_RFSL; + } + + /* Configure Frame sync early */ + if (ssi_rxinit->FrameSyncEarly == ENABLE) + { + temreg1 |= (uint32_t)SSI_SRCR_REFS; + } + + /* Configure Frame sync polarity */ + if (ssi_rxinit->FrameSyncPolarity == ACTIVELOW) + { + temreg1 |= (uint32_t)SSI_SRCR_RFSI; + } + + ssi->Instance->SRCR &= (uint32_t)(~(SSI_SRCR_RFEN0 | SSI_SRCR_RFEN1 + | SSI_SRCR_RSHFD | SSI_SRCR_RXBIT0 + | SSI_SRCR_RFDIR | SSI_SRCR_RXDIR + | SSI_SRCR_RSCKP | SSI_SRCR_REFS + | SSI_SRCR_RFSL | SSI_SRCR_RFSI)); + + ssi->Instance->SRCR |= temreg1; + + ssi->Instance->SFCSR &= (uint32_t)(~(SSI_SFCSR_RFWM0 | SSI_SFCSR_RFWM1)); + + ssi->Instance->SFCSR |= temreg2; + + ssi->Instance->SRMSK &= ~(SSI_SRMSK_SRMSK); + + ssi->Instance->SRMSK = ssi_rxinit->RxSlotMsk; + + RxClkFreqSet(ssi, ssi_rxinit); +} + + +/** + * @brief Initialize the SSI MSP. + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @retval None + */ +void __attribute__((weak)) SSI_MspInit(SSI_HandleTypeDef *ssi) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(ssi); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_SSI_MspInit could be implemented in the user file + */ +} + + +/** + * @} + */ + +/** @defgroup SSI_Exported_Functions_Group2 IO operation functions + * @brief Data transfers functions + * +@verbatim + ============================================================================== + ##### IO operation functions ##### + ============================================================================== + [..] + This subsection provides a set of functions allowing to manage the SSI data + transfers. + + (+) There are two modes of transfer: + (++) Blocking mode : The communication is performed in the polling mode. + The status of all data processing is returned by the same function + after finishing transfer. + (++) No-Blocking mode : The communication is performed using Interrupts + or DMA. These functions return the status of the transfer startup. + The end of the data processing will be indicated through the + dedicated SSI IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + + (+) Blocking mode functions are : + (++) SSI_Transmit() + (++) SSI_Receive() + +@endverbatim + * @{ + */ + +/** + * @brief Transmit an amount of data in polling mode. + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @param pData Pointer to data buffer + * @param Size Amount of data to be sent + * @param Timeout Timeout duration + * @retval void + * + */ +void SSI_Transmit(SSI_HandleTypeDef *ssi, \ + SSI_InitTypeDef *ssi_init, \ + SSI_TxInitTypeDef *ssi_txinit, \ + uint8_t *pData0, \ + uint8_t *pData1, \ + uint16_t Size0, \ + uint16_t Size1, \ + uint32_t Timeout) +{ + uint32_t tickstart = GetTick(); + + if (((pData0 == NULL) && (pData1 == NULL)) + || ((Size0 == 0)) && (Size1 == 0)) + { + return; + } + + if (ssi->State == SSI_STATE_READY) + { + ssi->XferSize0 = Size0; + ssi->XferSize1 = Size1; + ssi->XferCount0 = Size0; + ssi->XferCount1 = Size1; + ssi->pBuffPtr0 = pData0; + ssi->pBuffPtr1 = pData1; + ssi->State = SSI_STATE_BUSY_TX; + ssi->ErrorCode = SSI_ERROR_NONE; + + if (ssi_init->Mode == AC97) + { + if ((ssi->Instance->SACNT & SSI_SACNT_AC97EN) != SSI_SACNT_AC97EN) + { + if (ssi_init->AC97VarMode == ENABLE) + { + ssi->Instance->SACADD = (uint32_t)((ssi_txinit->CODECCMDADDR) & 0x0007ffff); + ssi->Instance->SACNT |= SSI_SACNT_RD | SSI_SACNT_AC97EN; + } + else + { + printf("CODEC ADDR = %08x\n", ((ssi_txinit->CODECCMDADDR) & 0x0007ffff)); + printf("Write data = %08x\n", ((ssi_txinit->CODECCMDDATA) & 0x000fffff)); + ssi->Instance->SACADD = (uint32_t)((ssi_txinit->CODECCMDADDR) & 0x0007ffff); + ssi->Instance->SACDAT = (uint32_t)((ssi_txinit->CODECCMDDATA) & 0x000fffff); + ssi->Instance->SACNT |= SSI_SACNT_WR | SSI_SACNT_AC97EN; + } + } + else if (ssi_init->AC97VarMode == ENABLE) + { + ssi->Instance->SACADD = (uint32_t)((ssi_txinit->CODECCMDADDR) & 0x0007ffff); + ssi->Instance->SACDAT = (uint32_t)((ssi_txinit->CODECCMDDATA) & 0x000fffff); + ssi->Instance->SACNT |= SSI_SACNT_WR; + + uint32_t slotreq = ((ssi->Instance->SACCST) & 0x000003ff); + + ssi->Instance->SACCEN = slotreq; + + ssi->Instance->SACCDIS = slotreq; + } + else + { + ssi->Instance->SACADD = (uint32_t)((ssi_txinit->CODECCMDADDR) & 0x0007ffff); + ssi->Instance->SACDAT = (uint32_t)((ssi_txinit->CODECCMDDATA) & 0x000fffff); + ssi->Instance->SACNT |= SSI_SACNT_WR; + } + } + + /* Prepare tx data before trasmit start */ + if ((ssi->Instance->SCR & SSI_SCR_TE) != SSI_SCR_TE) + { + if (ssi_init->TCHEN == ENABLE) + { + /* Two FIFOs are filled with data if enbale two channels */ + SSI_FillDfifo(ssi, ssi_txinit); + } + else if (ssi_txinit->FIFO0EN || ssi_init->Mode == AC97) + { + + //printf("Use FIFO0 to transmit data!\n"); + /* Only channel 0 is enabled if single channel mode */ + SSI_FillFifo_0(ssi, ssi_txinit); + } + else + { + if ((ssi->Instance->SISR & SSI_SISR_TDE0) == SSI_SISR_TDE0) + { + if (ssi_txinit->DataSize == SSI_DATA_WL8) + { + ssi->Instance->STX0 = (*ssi->pBuffPtr0++); + } + else if (ssi_txinit->DataSize == SSI_DATA_WL16) + { + ssi->Instance->STX0 = *((uint16_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 2U; + } + else + { + ssi->Instance->STX0 = *((uint32_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 4U; + } + ssi->XferCount0--; + } + } + /* Start transmit */ + ssi->Instance->SCR |= SSI_SCR_TE; + printf("Start transmit data!\n"); + } + + if (ssi_init->TCHEN == ENABLE) + { + while ((ssi->XferCount0 > 0U) || (ssi->XferCount1 > 0U)) + { + if (ssi->XferCount0 > 0U) + { + SSI_Fifo0Tx(ssi, ssi_txinit, Timeout, tickstart); + } + + if (ssi->XferCount1 > 0U) + { + SSI_Fifo1Tx(ssi, ssi_txinit, Timeout, tickstart); + } + } + } + else if ((ssi_txinit->FIFO0EN == ENABLE) || (ssi_init->Mode == AC97)) + { + while (ssi->XferCount0 > 0U) + { + printf("Remain %d data need to be send!\n", ssi->XferCount0); + SSI_Fifo0Tx(ssi, ssi_txinit, Timeout, tickstart); + } + } + else + { + while (ssi->XferCount0 > 0U) + { + SSI_STX0Tx(ssi, ssi_txinit, Timeout, tickstart); + } + } + + } + + ssi->State = SSI_STATE_READY; + + while ((ssi->Instance->SISR & SSI_SISR_TUE0) != SSI_SISR_TUE0) + { + + } + + ssi->Instance->SCR &= ~SSI_SCR_TE; +} + + +/** + * @brief Tx fifo_0 transmit function + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @param Timeout Timeout duration + * @param tickstart Transmit start time + * @retval None + */ +static void SSI_Fifo0Tx(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit, uint32_t Timeout, uint32_t tickstart) +{ + if (ssi->Instance->SISR & SSI_SISR_TFE0) + { + + if (ssi_txinit->DataSize == SSI_DATA_WL8) + { + ssi->Instance->STX0 = (*ssi->pBuffPtr0++); + } + else if (ssi_txinit->DataSize == SSI_DATA_WL16) + { + ssi->Instance->STX0 = *((uint16_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 2U; + } + else + { + ssi->Instance->STX0 = *((uint32_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 4U; + } + ssi->XferCount0--; + } + else + { + if ((Timeout != MAX_DELAY) && ((Timeout == 0U) || ((GetTick() - tickstart) > Timeout))) + { + /* Update error code */ + ssi->ErrorCode |= SSI_ERROR_TIMEOUT; + + /* Disable SSI peripheral */ + ssi->Instance->SCR &= ~(SSI_SCR_TE); + + /* Flush the fifo */ + ssi->Instance->SOR |= SSI_SOR_TX_CLR; + + /* Change the SSI state */ + ssi->State = SSI_STATE_READY; + + return ; + } + } +} + + +/** + * @brief Tx fifo_1 transmit function + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @param Timeout Timeout duration + * @param tickstart Transmit start time + * @retval None + */ +static void SSI_Fifo1Tx(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit, uint32_t Timeout, uint32_t tickstart) +{ + if (ssi->Instance->SISR & SSI_SISR_TFE1) + { + if (ssi_txinit->DataSize == SSI_DATA_WL8) + { + ssi->Instance->STX1 = (*ssi->pBuffPtr1++); + } + else if (ssi_txinit->DataSize == SSI_DATA_WL16) + { + ssi->Instance->STX1 = *((uint16_t *)(ssi->pBuffPtr1)); + ssi->pBuffPtr1 += 2U; + } + else + { + ssi->Instance->STX1 = *((uint32_t *)(ssi->pBuffPtr1)); + ssi->pBuffPtr1 += 4U; + } + ssi->XferCount1--; + } + else + { + if ((Timeout != MAX_DELAY) && ((Timeout == 0U) || ((GetTick() - tickstart) > Timeout))) + { + /* Update error code */ + ssi->ErrorCode |= SSI_ERROR_TIMEOUT; + + /* Disable SSI peripheral */ + ssi->Instance->SCR &= ~(SSI_SCR_TE); + + /* Change the SSI state */ + ssi->State = SSI_STATE_READY; + + return ; + } + } +} + +/** + * @brief Tx stx register transmit function + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @param Timeout Timeout duration + * @param tickstart Transmit start time + * @retval None + */ +static void SSI_STX0Tx(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit, uint32_t Timeout, uint32_t tickstart) +{ + if ((ssi->Instance->SISR & SSI_SISR_TDE0) == SSI_SISR_TDE0) + { + if (ssi_txinit->DataSize == SSI_DATA_WL8) + { + ssi->Instance->STX0 = (*ssi->pBuffPtr0++); + } + else if (ssi_txinit->DataSize == SSI_DATA_WL16) + { + ssi->Instance->STX0 = *((uint16_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 2U; + } + else + { + ssi->Instance->STX0 = *((uint32_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 4U; + } + ssi->XferCount0--; + } + else + { + if ((Timeout != MAX_DELAY) && ((Timeout == 0U) || ((GetTick() - tickstart) > Timeout))) + { + /* Update error code */ + ssi->ErrorCode |= SSI_ERROR_TIMEOUT; + + /* Disable SSI peripheral */ + ssi->Instance->SCR &= ~(SSI_SCR_TE); + + /* Change the SSI state */ + ssi->State = SSI_STATE_READY; + + return ; + } + } +} +/** + * @brief Fill the tx fifo_0 + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @retval None + */ +static void SSI_FillFifo_0(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit) +{ + /* fill the fifo with data before to enable the SSI*/ + while (((ssi->Instance->SISR & SSI_SISR_TFE0) == SSI_SISR_TFE0) && (ssi->XferCount0 > 0U)) + { + //printf("Fill FIFO0!\n"); + //printf("There are %d data need to be sended!\n",ssi->XferCount0); + if (ssi_txinit->DataSize == SSI_DATA_WL8) + { + ssi->Instance->STX0 = (*ssi->pBuffPtr0++); + } + else if (ssi_txinit->DataSize == SSI_DATA_WL16) + { + ssi->Instance->STX0 = *((uint16_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 2U; + } + else + { + //printf("Fill data = %08x\n",*((uint32_t *)(ssi->pBuffPtr0))); + ssi->Instance->STX0 = *((uint32_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 4U; + } + ssi->XferCount0--; + } +} + + +/** + * @brief Fill the tx fifo_1 and fifo_2 alternatively + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_txinit pointer to a SSI_TxInitTypeDef structure that contains + * the SSI Tx initialization information + * @retval None + */ +static void SSI_FillDfifo(SSI_HandleTypeDef *ssi, SSI_TxInitTypeDef *ssi_txinit) +{ + while (((ssi->Instance->SISR & SSI_SISR_TFE0) == SSI_SISR_TFE0) && (ssi->XferCount0 > 0U)) + { + if (ssi_txinit->DataSize == SSI_DATA_WL8) + { + ssi->Instance->STX0 = (*ssi->pBuffPtr0++); + } + else if (ssi_txinit->DataSize == SSI_DATA_WL16) + { + ssi->Instance->STX0 = *((uint16_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 2U; + } + else + { + ssi->Instance->STX0 = *((uint32_t *)(ssi->pBuffPtr0)); + ssi->pBuffPtr0 += 4U; + } + ssi->XferCount0--; + } + + while (((ssi->Instance->SISR & SSI_SISR_TFE1) == SSI_SISR_TFE1) && (ssi->XferCount1 > 0U)) + { + if (ssi_txinit->DataSize == SSI_DATA_WL8) + { + ssi->Instance->STX1 = (*ssi->pBuffPtr1++); + } + else if (ssi_txinit->DataSize == SSI_DATA_WL16) + { + ssi->Instance->STX1 = *((uint16_t *)(ssi->pBuffPtr1)); + ssi->pBuffPtr1 += 2U; + } + else + { + ssi->Instance->STX1 = *((uint32_t *)(ssi->pBuffPtr1)); + ssi->pBuffPtr1 += 4U; + } + ssi->XferCount1--; + } +} + +/** + * @brief Receive an amount of data in polling mode. + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_rxinit pointer to a SSI_RxInitTypeDef structure that contains + * the SSI Rx initialization information + * @param pData0 Pointer to data buffer for channel 0 + * @param pData1 Pointer to data buffer for channel 1 + * @param Size0 Amount of data to be sent for channel 0 + * @param Size1 Amount of data to be sent for channel 1 + * @param Timeout Timeout duration + * @retval void + */ +void SSI_Receive(SSI_HandleTypeDef *ssi, \ + SSI_InitTypeDef *ssi_init, \ + SSI_RxInitTypeDef *ssi_rxinit, \ + uint8_t *pData0, \ + uint8_t *pData1, \ + uint16_t Size0, \ + uint16_t Size1, \ + uint32_t Timeout) +{ + uint32_t tickstart = GetTick(); + + if (((pData0 == NULL) && (pData1 == NULL)) + || ((Size0 == 0)) && (Size1 == 0)) + { + return; + } + + if (ssi->State == SSI_STATE_READY) + { + ssi->XferSize0 = Size0; + ssi->XferSize1 = Size1; + ssi->XferCount0 = Size0; + ssi->XferCount1 = Size1; + ssi->pBuffPtr0 = pData0; + ssi->pBuffPtr1 = pData1; + ssi->State = SSI_STATE_BUSY_RX; + ssi->ErrorCode = SSI_ERROR_NONE; + + if ((ssi->Instance->SCR & SSI_SCR_RE) != SSI_SCR_RE) + { + ssi->Instance->SCR |= SSI_SCR_RE; + } + + /* Receive Data*/ + + if (ssi_init->TCHEN == ENABLE) + { + while ((ssi->XferCount0 > 0U) || (ssi->XferCount1 > 0U)) + { + if (ssi->XferCount0 > 0U) + { + SSI_Fifo0Rx(ssi, ssi_rxinit, Timeout, tickstart); + } + + + if (ssi->XferCount1 > 0U) + { + SSI_Fifo1Rx(ssi, ssi_rxinit, Timeout, tickstart); + } + } + } + else if (ssi_rxinit->FIFO0EN || ssi_init->Mode == AC97) + { + while (ssi->XferCount0 > 0U) + { + SSI_Fifo0Rx(ssi, ssi_rxinit, Timeout, tickstart); + } + } + else + { + while (ssi->XferCount0 > 0U) + { + SSI_SRX0Rx(ssi, ssi_rxinit, Timeout, tickstart); + } + } + } +} + + +/** + * @brief Rx fifo_0 transmit function + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_rxinit pointer to a SSI_RxInitTypeDef structure that contains + * the SSI Rx initialization information + * @param Timeout Timeout duration + * @param tickstart Receive start time + * @retval None + */ +static void SSI_Fifo0Rx(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit, uint32_t Timeout, uint32_t tickstart) +{ + if ((ssi->Instance->SISR & SSI_SISR_RFF0) == SSI_SISR_RFF0) + { + if (ssi_rxinit->DataSize == SSI_DATA_WL8) + { + (*ssi->pBuffPtr0++) = ssi->Instance->SRX0; + } + else if (ssi_rxinit->DataSize == SSI_DATA_WL16) + { + *((uint16_t *)(ssi->pBuffPtr0)) = ssi->Instance->SRX0; + ssi->pBuffPtr0 += 2U; + } + else + { + *((uint32_t *)(ssi->pBuffPtr0)) = ssi->Instance->SRX0; + ssi->pBuffPtr0 += 4U; + } + ssi->XferCount0--; + } + else + { + if ((Timeout != MAX_DELAY) && ((Timeout == 0U) || ((GetTick() - tickstart) > Timeout))) + { + /* Update error code */ + ssi->ErrorCode |= SSI_ERROR_TIMEOUT; + + /* Disable SSI Rx channel */ + ssi->Instance->SCR &= ~(SSI_SCR_RE); + + /* Flush the fifo */ + ssi->Instance->SOR |= SSI_SOR_RX_CLR; + + /* Change the SSI state */ + ssi->State = SSI_STATE_READY; + + return ; + } + } +} + +/** + * @brief Rx fifo_1 transmit function + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_rxinit pointer to a SSI_RxInitTypeDef structure that contains + * the SSI Rx initialization information + * @param Timeout Timeout duration + * @param tickstart Receive start time + * @retval None + */ +static void SSI_Fifo1Rx(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit, uint32_t Timeout, uint32_t tickstart) +{ + if ((ssi->Instance->SISR & SSI_SISR_RFF1) == SSI_SISR_RFF1) + { + if (ssi_rxinit->DataSize == SSI_DATA_WL8) + { + (*ssi->pBuffPtr1++) = ssi->Instance->SRX1; + } + else if (ssi_rxinit->DataSize == SSI_DATA_WL16) + { + *((uint16_t *)(ssi->pBuffPtr1)) = ssi->Instance->SRX1; + ssi->pBuffPtr1 += 2U; + } + else + { + *((uint32_t *)(ssi->pBuffPtr1)) = ssi->Instance->SRX1; + ssi->pBuffPtr1 += 4U; + } + ssi->XferCount1--; + } + else + { + if ((Timeout != MAX_DELAY) && ((Timeout == 0U) || ((GetTick() - tickstart) > Timeout))) + { + /* Update error code */ + ssi->ErrorCode |= SSI_ERROR_TIMEOUT; + + /* Disable SSI Rx Function */ + ssi->Instance->SCR &= ~(SSI_SCR_RE); + + /* Change the SSI state */ + ssi->State = SSI_STATE_READY; + + return ; + } + } +} + +/** + * @brief Rx srx register transmit function + * @param ssi pointer to a SSI_HandleTypeDef structure that contains + * the configuration information for SSI module. + * @param ssi_rxinit pointer to a SSI_RxInitTypeDef structure that contains + * the SSI Rx initialization information + * @param Timeout Timeout duration + * @param tickstart Receive start time + * @retval None + */ +static void SSI_SRX0Rx(SSI_HandleTypeDef *ssi, SSI_RxInitTypeDef *ssi_rxinit, uint32_t Timeout, uint32_t tickstart) +{ + if ((ssi->Instance->SISR & SSI_SISR_RDR0) == SSI_SISR_RDR0) + { + if (ssi_rxinit->DataSize == SSI_DATA_WL8) + { + (*ssi->pBuffPtr0++) = ssi->Instance->SRX0; + } + else if (ssi_rxinit->DataSize == SSI_DATA_WL16) + { + *((uint16_t *)(ssi->pBuffPtr0)) = ssi->Instance->SRX0; + ssi->pBuffPtr0 += 2U; + } + else + { + *((uint32_t *)(ssi->pBuffPtr0)) = ssi->Instance->SRX0; + ssi->pBuffPtr0 += 4U; + } + ssi->XferCount0--; + } + else + { + if ((Timeout != MAX_DELAY) && ((Timeout == 0U) || ((GetTick() - tickstart) > Timeout))) + { + /* Update error code */ + ssi->ErrorCode |= SSI_ERROR_TIMEOUT; + + /* Disable SSI Rx Function */ + ssi->Instance->SCR &= ~(SSI_SCR_RE); + + /* Change the SSI state */ + ssi->State = SSI_STATE_READY; + + return ; + } + } +} + diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_syscfg.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_syscfg.c new file mode 100644 index 00000000000..246c6dae8b6 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_syscfg.c @@ -0,0 +1,252 @@ +/** + ****************************************************************************** + * @file ft32f4xx_syscfg.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the SYSCFG peripheral: + * + Remapping the memory mapped at 0x00000000 + * + Enabling I2C fast mode plus driving capability for I2C pins + * + Configuring the EXTI lines connection to the GPIO port + * + Configuring the CFGR features (Connecting some internal signal + * to the break input of TIM1/8 and EPWM) + * @version V1.0.0 + * @data 2025-04-08 + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_syscfg.h" + +/** + * @brief Deinitializes the SYSCFG registers to their default reset values. + * @param None + * @retval None + * @note MEM_MODE bits took the value from bootpin after por_reset. + */ +void SYSCFG_DeInit(void) +{ + /* Set SYSCFG_MEMRMP register to reset value without affecting MEM_MODE bits */ + SYSCFG->MEMRMP &= SYSCFG_MEMRMP_MEM_MODE; + /* Set PMC registers to reset value */ + SYSCFG->PMC = 0; + /* Set EXTICRx registers to reset value */ + SYSCFG->EXTICR[0] = 0; + SYSCFG->EXTICR[1] = 0; + SYSCFG->EXTICR[2] = 0; + SYSCFG->EXTICR[3] = 0; + /* Set CFGR register to reset value */ + SYSCFG->CFGR |= 0; +} + +/** + * @brief Configures the memory mapping at address 0x00000000. + * @param SYSCFG_MemoryRemap: selects the memory remapping. + * This parameter can be one of the following values: + * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_FMC1: Embedded FMC1 mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_FMC2: Embedded FMC2 mapped at 0x00000000 + * @arg SYSCFG_MemoryRemap_QSPI: Embedded QSPI mapped at 0x00000000 + * @retval None + */ +void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap) +{ + uint32_t tmpctrl = 0; + + /* Check the parameter */ + assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap)); + + /* Get MEMRMP register value */ + tmpctrl = SYSCFG->MEMRMP; + + /* Clear MEM_MODE bits */ + tmpctrl &= (uint32_t)(~SYSCFG_MEMRMP_MEM_MODE); + + /* Set the new MEM_MODE bits value */ + tmpctrl |= (uint32_t) SYSCFG_MemoryRemap; + + /* Set MEMRMP register with the new memory remap configuration */ + SYSCFG->MEMRMP = tmpctrl; +} + +/** + * @brief Configure FMC memory mapping swap. + * @param SYSCFG_FMCSWPConfig: enable or disable FMC memory mapping swap. + * This parameter can be one of the following values: + * @arg SYSCFG_FMC_SWP_ENABLE: Configure FMC memory mapping swap enable + * SDRAM bank1/2 and NAND bank1/2 mapping are swap + * @arg SYSCFG_FMC_SWP_DISABLE: Configure FMC memory mapping swap disable + * + * @retval None + */ +void SYSCFG_FMCSWPConfig(uint32_t SYSCFG_FMCSWPCFG) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_FMC_SWP(SYSCFG_FMCSWPCFG)); + + if (SYSCFG_FMCSWPCFG != DISABLE) + { + /* Enable FMC memory mapping swap */ + SYSCFG->MEMRMP &= (uint32_t)(~SYSCFG_MEMRMP_SWP_FMC); + SYSCFG->MEMRMP |= (uint32_t)SYSCFG_FMCSWPCFG; + } + else + { + /* Disable FMC memory mapping swap */ + SYSCFG->MEMRMP &= (uint32_t)(~SYSCFG_FMCSWPCFG); + } +} + + +/** + * @brief Configure the boost enable for adc. + * @param SYSCFG_BoostENConfig: enable or disable boost function. + * This parameter can be one of the following values: + * @arg SYSCFG_PMC_BoostEN_ENABLE: Configure boost function enable + * @arg SYSCFG_PMC_BoostEN_DISABLE: Configure boost function disable + * + * @retval None + */ +void SYSCFG_BoostENConfig(uint32_t SYSCFG_BoostENCFG) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_PMC_BoostEN(SYSCFG_BoostENCFG)); + + if (SYSCFG_BoostENCFG != DISABLE) + { + /* Enable boost function */ + SYSCFG->PMC |= (uint32_t)SYSCFG_BoostENCFG; + } + else + { + /* Disable boost function */ + SYSCFG->PMC &= (uint32_t)(~SYSCFG_BoostENCFG); + } +} + + +/** + * @brief Configure the I2C fast mode plus driving capability. + * @param SYSCFG_I2CFastModePlus: selects the pin. + * This parameter can be one of the following values: + * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 + * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 + * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 + * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 + * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 + * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 + * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7 + * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins + * + * @param NewState: new state of the DMA channel remapping. + * This parameter can be: ENABLE or DISABLE. + * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin + * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using SYSCFG_I2CFastModePlus_I2C2 parameter. + * @retval None + */ +void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable fast mode plus driving capability for selected pin */ + SYSCFG->PMC |= (uint32_t)SYSCFG_I2CFastModePlus; + } + else + { + /* Disable fast mode plus driving capability for selected pin */ + SYSCFG->PMC &= (uint32_t)(~SYSCFG_I2CFastModePlus); + } +} + +/** + * @brief Configure the mii function or rmii function for ethernet. + * @param SYSCFG_MII_RMIIConfig: select ethernet use mii or rmii. + * This parameter can be one of the following values: + * @arg SYSCFG_ETH_MII_RMII_SEL_MII: select mii function + * @arg SYSCFG_ETH_MII_RMII_SEL_RMII: select rmii function + * + * @retval None + */ +void SYSCFG_MII_RMIIConfig(uint32_t SYSCFG_MII_RMIICFG) +{ + /* Check the parameters */ + assert_param(IS_SYSCFG_ETH_MII_RMII_SEL(SYSCFG_MII_RMIICFG)); + + if (SYSCFG_MII_RMIICFG != DISABLE) + { + /* select rmii function */ + SYSCFG->PMC |= (uint32_t)SYSCFG_MII_RMIICFG; + } + else + { + /* select mii function */ + SYSCFG->PMC &= (uint32_t)(~SYSCFG_MII_RMIICFG); + } +} + +/** + * @brief Selects the GPIO pin used as EXTI Line. + * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source + * for EXTI lines where x can be (A, B, C, D, E or H). + * @param EXTI_PinSourcex: specifies the EXTI line to be configured. + * @note This parameter can be EXTI_PinSourcex where x can be: + * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0,1) for GPIOH. + * @retval None + */ +void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex) +{ + uint32_t tmp = 0x00; + + /* Check the parameters */ + assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx)); + assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex)); + + tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)); + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp; + SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03))); +} + +/** + * @brief Connect the selected parameter to the break input of TIM. + * @param SYSCFG_Break: selects the configuration to be connected to break + * input of TIM + * This parameter can be any combination of the following values: + * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break + * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1/8 or EPWM + * @retval None + */ +void SYSCFG_BreakConfig(uint32_t SYSCFG_Break) +{ + /* Check the parameter */ + assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break)); + + SYSCFG->CFGR |= (uint32_t) SYSCFG_Break; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_tim.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_tim.c new file mode 100644 index 00000000000..b221579f7d9 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_tim.c @@ -0,0 +1,4243 @@ +/** + ****************************************************************************** + * @file ft32f4xx_tim.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the TIM peripheral: + * + TimeBase management + * + Advanced-control timers specific features + * + Output Compare management + * + Input Capture management + * + Interrupts, DMA and flags management + * + Clocks management + * + Synchronization management + * + Specific interface management + * + Specific remapping management + * @version V1.0.0 + * @date 2025-04-07 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_tim.h" +#include "ft32f4xx_rcc.h" + + +/* ------------------------ TIM registers bit mask -------------------------- */ +#define SMCR_ETR_MASK ((uint32_t)0x000000FF) +#define CCMR_OFFSET ((uint32_t)0x00000018) +#define CCER_CCE_SET ((uint32_t)0x00000001) +#define CCER_CCNE_SET ((uint32_t)0x00000004) + + +static void TI1_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter); + +/** + * @brief Deinitializes the TIMx peripheral registers to their default reset values. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @retval None + * + */ +void TIM_DeInit(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + if (TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if (TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if (TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if (TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if (TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if (TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if (TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } + else if (TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if (TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if (TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if (TIMx == TIM11) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); + } + else if (TIMx == TIM12) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); + } + else if (TIMx == TIM13) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); + } + else + { + if (TIMx == TIM14) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); + } + } +} + +/** + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef + * structure that contains the configuration information for + * the specified TIM peripheral. + * @retval None + */ +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); + assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); + + tmpcr1 = TIMx->CR1; + + if ((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || + (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + /* Select the Counter Mode */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if ((TIMx != TIM6) || (TIMx != TIM7)) + { + /* Set the clock division */ + tmpcr1 &= (uint32_t)(~((uint32_t)TIM_CR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CR1 = tmpcr1; + + /* Set the Autoreload value */ + TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; + + /* Set the Prescaler value */ + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Set the Repetition Counter value */ + TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + /* Generate an update event to reload the Prescaler and the Repetition counter + values immediately */ + TIMx->EGR = TIM_PSCReloadMode_Immediate; +} + +/** + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure + * which will be initialized. + * @retval None + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/** + * @brief Configures the TIMx Prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param Prescaler: specifies the Prescaler Register value + * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode + * This parameter can be one of the following values: + * @arg TIM_PSCReloadMode_Update : The Prescaler is loaded at the update event. + * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly. + * @retval None + */ +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint32_t Prescaler, uint32_t TIM_PSCReloadMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); + + /* Set the Prescaler value */ + TIMx->PSC = Prescaler; + /* Set or reset the UG Bit */ + TIMx->EGR = TIM_PSCReloadMode; +} + +/** + * @brief Specifies the TIMx Counter Mode to be used. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_CounterMode: specifies the Counter Mode to be used + * This parameter can be one of the following values: + * @arg TIM_CounterMode_Up : TIM Up Counting Mode + * @arg TIM_CounterMode_Down : TIM Down Counting Mode + * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 + * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 + * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 + * @retval None + */ +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint32_t TIM_CounterMode) +{ + uint32_t tmpcr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); + tmpcr1 = TIMx->CR1; + + /* Reset the CMS and DIR Bits */ + tmpcr1 &= (uint32_t)(~((uint32_t)(TIM_CR1_DIR | TIM_CR1_CMS))); + + /* Set the Counter Mode */ + tmpcr1 |= TIM_CounterMode; + + /* Write to TIMx CR1 register */ + TIMx->CR1 = tmpcr1; +} + +/** + * @brief Sets the TIMx Counter Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param Counter: specifies the Counter register new value. + * @retval None + */ +void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Counter Register value */ + TIMx->CNT = Counter; +} + +/** + * @brief Sets the TIMx Autoreload Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param Autoreload: specifies the Autoreload register new value. + * @retval None + */ +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Set the Autoreload Register value */ + TIMx->ARR = Autoreload; +} + +/** + * @brief Sets the TIMx RepetitionCounter Register value + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param RepetitionCounter: specifies the RepetitionCounter register new value. + * @retval None + */ +void TIM_SetRepetitionCounter(TIM_TypeDef* TIMx, uint32_t RepetitionCounter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Set the RepetitionCounter Register value */ + TIMx->RCR = RepetitionCounter; +} + +/** + * @brief Gets the TIMx Counter value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @retval Counter Register value. + */ +uint32_t TIM_GetCounter(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Counter Register value */ + return TIMx->CNT; +} + +/** + * @brief Gets the TIMx Prescaler value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @retval Prescaler Register value. + */ +uint32_t TIM_GetPrescaler(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + + /* Get the Prescaler Register value */ + return TIMx->PSC; +} + +/** + * @brief Enables or Disables the TIMx Update event. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param NewState: new state of the TIMx UDIS bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the Update Disable Bit */ + TIMx->CR1 |= TIM_CR1_UDIS; + } + else + { + /* Reset the Update Disable Bit */ + TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_UDIS); + } +} + +/** + * @brief Configures the TIMx Update Request Interrupt source. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param TIM_UpdateSource: specifies the Update source. + * This parameter can be one of the following values: + * @arg TIM_UpdateSource_Global : Source of update is the counter overflow/underflow + * or the setting of UG bit, or an update generation + * through the slave mode controller. + * @arg TIM_UpdateSource_Regular: Source of update is counter overflow/underflow. + * @retval None + */ +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint32_t TIM_UpdateSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); + + if (TIM_UpdateSource != TIM_UpdateSource_Global) + { + /* Set the URS Bit */ + TIMx->CR1 |= TIM_CR1_URS; + } + else + { + /* Reset the URS Bit */ + TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_URS); + } +} + +/** + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral Preload register + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the ARR Preload Bit */ + TIMx->CR1 |= TIM_CR1_ARPE; + TIMx->EGR |= TIM_EGR_UG; + TIMx->SR &= (uint32_t)~((uint32_t)TIM_SR_UIF); + } + else + { + /* Reset the ARR Preload Bit */ + TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_ARPE); + } +} + +/** + * @brief Selects the TIMx's One Pulse Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param TIM_OPMode: specifies the OPM Mode to be used. + * This parameter can be one of the following values: + * @arg TIM_OPMode_Single + * @arg TIM_OPMode_Repetitive + * @retval None + */ +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint32_t TIM_OPMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); + + /* Reset the OPM Bit */ + TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_OPM); + + /* Configure the OPM Mode */ + TIMx->CR1 |= TIM_OPMode; +} + +/** + * @brief Sets the TIMx Clock Division value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, + * 13 and 14 to select the TIM peripheral. + * @param TIM_CKD: specifies the clock division value. + * This parameter can be one of the following value: + * @arg TIM_CKD_DIV1: TDTS = 1*Tck_tim + * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim + * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim + * @retval None + */ +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint32_t TIM_CKD) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CKD_DIV(TIM_CKD)); + + /* Reset the CKD Bits */ + TIMx->CR1 &= (uint32_t)~((uint32_t)TIM_CR1_CKD); + + /* Set the CKD value */ + TIMx->CR1 |= TIM_CKD; +} + +/** + * @brief Enables or disables the specified TIM peripheral. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param NewState: new state of the TIMx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Counter */ + TIMx->CR1 |= TIM_CR1_CEN; + } + else + { + /* Disable the TIM Counter */ + TIMx->CR1 &= (uint32_t)(~((uint32_t)TIM_CR1_CEN)); + } +} + +/** + * @} + */ + +/** + * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_DEADTIME(TIM_BDTRInitStruct->TIM_DeadTime)); + assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); + assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); + assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); + assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); + assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); + assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); + assert_param(IS_TIM_BREAK_FILTER(TIM_BDTRInitStruct->TIM_BreakFilter)); + assert_param(IS_TIM_BREAK_BID_MODE(TIM_BDTRInitStruct->TIM_BreakBIDMode)); + assert_param(IS_TIM_CONTROL_PWM_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_CtrlPWMOutput)); + + /* Set the Lock level LOCK[1:0], the Break enable Bit BKE and the Ploarity BKP, the OSSR State, + the OSSI State, the dead time value DTG[7:0], the Automatic Output Enable Bit AOE, the Break + Filter BKF[3:0], output control MOE bit and the bidirectional function mode of break input + bit BKBID */ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_LOCKLevel | + TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_OSSRState | + TIM_BDTRInitStruct->TIM_Break | + TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput | + TIM_BDTRInitStruct->TIM_CtrlPWMOutput | + ((TIM_BDTRInitStruct->TIM_BreakFilter) << (uint32_t)16) | + TIM_BDTRInitStruct->TIM_BreakBIDMode ; +} + +/** + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which + * will be initialized. + * @retval None + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; + TIM_BDTRInitStruct->TIM_BreakFilter = 0x0; + TIM_BDTRInitStruct->TIM_BreakBIDMode = TIM_Break_Bid_MODE_INPUT; +} + +/** + * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State + * and the AOE(automatic output enable). + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that + * contains the BDTR Register configuration information for the TIM peripheral. + * @retval None + */ + +/** + * @brief Configures the break input source. + * @param TIMx: where x can be 1 or 8 to select the TIM + * @param BreakInputConfig: pointer to a TIMx_BreakInputConfigTypeDef structure that + * contains the AF1 Register Break input source configuration information for + * the TIM peripheral. + * + * There are three instance variables in BreakInputConfig as follows: + * + * - TIM_Break_Input_Source: specifies the source of the timer break input. + * This parameter can be one of the following value: + * @arg TIM_BREAKINPUTSOURCE_BKIN : An external source (GPIO) is connected to the BKIN pin + * @arg TIM_BREAKINPUTSOURCE_COMP1: The COMP1 output is connected to the break input + * @arg TIM_BREAKINPUTSOURCE_COMP2: The COMP2 output is connected to the break input + * @arg TIM_BREAKINPUTSOURCE_COMP3: The COMP3 output is connected to the break input + * @arg TIM_BREAKINPUTSOURCE_COMP4: The COMP4 output is connected to the break input + * @arg TIM_BREAKINPUTSOURCE_COMP5: The COMP5 output is connected to the break input + * @arg TIM_BREAKINPUTSOURCE_COMP6: The COMP6 output is connected to the break input + * + * - TIM_Enable: specifies whether or not the break input source is enabled. + * This parameter can be one of the following value: + * @arg TIM_BREAKINPUTSOURCE_DISABLE: Break input source is disabled + * @arg TIM_BREAKINPUTSOURCE_ENABLE : Break input source is enabled + * + * - TIM_Polarity: specifies the break input source polarity. + * This parameter can be one of the following value: + * @arg TIM_BREAKINPUTSOURCE_POLARITY_INVERTED : Break input source is inverted + * (active high if BKP = 0, active low if BKP = 1) + * @arg TIM_BREAKINPUTSOURCE_POLARITY_NOT_INVERTED: Break input source is not inverted + * (active low if BKP = 0, active high if BKP = 1) + * + * @retval None + */ +void TIM_ConfigBreakInput(TIM_TypeDef* TIMx, TIM_BreakInputConfigTypeDef* BreakInputConfig) + +{ + uint32_t tmporx; + uint32_t bkin_enable_mask; + uint32_t bkin_polarity_mask; + uint32_t bkin_enable_bitpos; + uint32_t bkin_polarity_bitpos; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_BREAKINPUTSOURCE(BreakInputConfig->TIM_Source)); + assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(BreakInputConfig->TIM_Enable)); + assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(BreakInputConfig->TIM_Polarity)); + + switch (BreakInputConfig->TIM_Source) + { + case TIM_BREAKINPUTSOURCE_BKIN: + { + bkin_enable_mask = TIM_AF_BKINE; + bkin_enable_bitpos = TIM_AF_BKINE_Pos; + bkin_polarity_mask = TIM_AF_BKINP; + bkin_polarity_bitpos = TIM_AF_BKINP_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP1: + { + bkin_enable_mask = TIM_AF_BKCMP1E; + bkin_enable_bitpos = TIM_AF_BKCMP1E_Pos; + bkin_polarity_mask = TIM_AF_BKCMP1P; + bkin_polarity_bitpos = TIM_AF_BKCMP1P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP2: + { + bkin_enable_mask = TIM_AF_BKCMP2E; + bkin_enable_bitpos = TIM_AF_BKCMP2E_Pos; + bkin_polarity_mask = TIM_AF_BKCMP2P; + bkin_polarity_bitpos = TIM_AF_BKCMP2P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP3: + { + bkin_enable_mask = TIM_AF_BKCMP3E; + bkin_enable_bitpos = TIM_AF_BKCMP3E_Pos; + bkin_polarity_mask = TIM_AF_BKCMP3P; + bkin_polarity_bitpos = TIM_AF_BKCMP3P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP4: + { + bkin_enable_mask = TIM_AF_BKCMP4E; + bkin_enable_bitpos = TIM_AF_BKCMP4E_Pos; + bkin_polarity_mask = TIM_AF_BKCMP4P; + bkin_polarity_bitpos = TIM_AF_BKCMP4P_Pos; + break; + } + case TIM_BREAKINPUTSOURCE_COMP5: + { + bkin_enable_mask = TIM_AF_BKCMP5E; + bkin_enable_bitpos = TIM_AF_BKCMP5E_Pos; + /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } + case TIM_BREAKINPUTSOURCE_COMP6: + { + bkin_enable_mask = TIM_AF_BKCMP6E; + bkin_enable_bitpos = TIM_AF_BKCMP6E_Pos; + /* No palarity bit for this COMP. Variable bkin_polarity_mask keeps its default value 0 */ + bkin_polarity_mask = 0U; + bkin_polarity_bitpos = 0U; + break; + } + default: + { + bkin_enable_mask = 0U; + bkin_polarity_mask = 0U; + bkin_enable_bitpos = 0U; + bkin_polarity_bitpos = 0U; + break; + } + } + + /* Get the TIMx_AF1 register value */ + tmporx = TIMx->AF1; + + /* Enable the break input */ + tmporx &= ~bkin_enable_mask; + tmporx |= (BreakInputConfig->TIM_Enable << bkin_enable_bitpos) & bkin_enable_mask; + + /* Set the break input polarity */ + tmporx &= ~bkin_polarity_mask; + tmporx |= (BreakInputConfig->TIM_Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; + + /* Set TIMx_AF1 */ + TIMx->AF1 = tmporx; +} + +/** + * @brief Enables or disables the TIM peripheral Main Outputs. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @param NewState: new state of the TIM peripheral Main Outputs. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the TIM Main Output */ + TIMx->BDTR |= TIM_BDTR_MOE; + } + else + { + /* Disable the TIM Main Output */ + TIMx->BDTR &= (uint32_t)(~((uint32_t)TIM_BDTR_MOE)); + } +} + +/** + * @brief Disarm the designated break input (when it operates in bidirectional mode). + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @note The break input can be disarmed only when it is configured in + * bidirectional mode and when when MOE is reset. + * @note Purpose is to be able to have the input voltage back to high-state, + * whatever the time constant on the output. + * @retval None + */ +void TIM_DisarmBreakInput(TIM_TypeDef* TIMx) +{ + uint32_t tmpbdtr; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Check initial conditions */ + tmpbdtr = TIMx->BDTR; + + if ((((TIMx->BDTR)&TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && + (((TIMx->BDTR)&TIM_BDTR_MOE) != TIM_BDTR_MOE)) + { + /* Break input BRK is disarmed */ + TIMx->BDTR |= TIM_BDTR_BKDSRM; + } +} + +/** + * @brief Wait the BKDSRM bit is cleared by hardware when no break source active + * (when it operates in bidirectional mode). + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral. + * @note The BKDSRM bit is cleared by hardware when no break source active. + * @retval The new state of BKDSRM (SET or RESET). + */ +FlagStatus TIM_WaitBkdsrmIsHardwareClear(TIM_TypeDef* TIMx) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Check initial conditions */ + if (((TIMx->BDTR)&TIM_BDTR_BKBID) == TIM_BDTR_BKBID) + { + /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ + if ((TIMx->BDTR & TIM_BDTR_BKDSRM) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/** + * @} + */ + +/** + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 + * and 14 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)(~(uint32_t)TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare Mode Bits */ + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_OC1M)); + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_CC1S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC1P)); + /* Set the Output Compare Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + + /* Set the Output State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC1NP)); + /* Set the Output N Polarity */ + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC1NE)); + /* Set the Output N State */ + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS1)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS1N)); + /* Set the Output Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + /* Set the Output N Idle state */ + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Set the Capture Compare Register value */ + if (((TIMx->CCMR1)&TIM_CCMR1_OC1PE) != TIM_CCMR1_OC1PE) + { + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + } + else if (((TIMx->CCMR1)&TIM_CCMR1_OC1PE) == TIM_CCMR1_OC1PE) + { + TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; + TIMx->EGR |= TIM_EGR_UG; + TIMx->SR &= (uint32_t)~((uint32_t)TIM_SR_UIF); + } + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select + * the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * + * @retval None + */ +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC2E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR1 register value */ + tmpccmrx = TIMx->CCMR1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_OC2M)); + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR1_CC2S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC2P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + /* Check the parameters */ + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC2NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC2NE)); + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + /* Reset the Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS2)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS2N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Set the Capture Compare Register value */ + if (((TIMx->CCMR1)&TIM_CCMR1_OC2PE) != TIM_CCMR1_OC2PE) + { + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + } + else if (((TIMx->CCMR1)&TIM_CCMR1_OC2PE) == TIM_CCMR1_OC2PE) + { + TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; + TIMx->EGR |= TIM_EGR_UG; + TIMx->SR &= (uint32_t)~((uint32_t)TIM_SR_UIF); + } + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC3E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_OC3M)); + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_CC3S)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC3P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); + assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Output N Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC3NP)); + /* Set the Output N Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + + /* Reset the Output N State */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC3NE)); + /* Set the Output N State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + + /* Reset the Ouput Compare and Output Compare N IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS3)); + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS3N)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + /* Set the Output N Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Set the Capture Compare Register value */ + if (((TIMx->CCMR2)&TIM_CCMR2_OC3PE) != TIM_CCMR2_OC3PE) + { + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + } + else if (((TIMx->CCMR2)&TIM_CCMR2_OC3PE) == TIM_CCMR2_OC3PE) + { + TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; + TIMx->EGR |= TIM_EGR_UG; + TIMx->SR &= (uint32_t)~((uint32_t)TIM_SR_UIF); + } + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC4E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR2 register value */ + tmpccmrx = TIMx->CCMR2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_OC4M)); + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR2_CC4S)); + + /* Select the Output Compare Mode */ + tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC4P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS4)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Set the Capture Compare Register value */ + if (((TIMx->CCMR2)&TIM_CCMR2_OC4PE) != TIM_CCMR2_OC4PE) + { + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + } + else if (((TIMx->CCMR2)&TIM_CCMR2_OC4PE) == TIM_CCMR2_OC4PE) + { + TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; + TIMx->EGR |= TIM_EGR_UG; + TIMx->SR &= (uint32_t)~((uint32_t)TIM_SR_UIF); + } + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel5 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 5: Reset the CC5E Bit */ + TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC5E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR3 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare mode Bits */ + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR3_OC5M)); + /* Select the Output Compare Mode */ + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC5P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 16); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 16); + + /* Check the parameters */ + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS5)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->TIM_OCIdleState << 8); + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Set the Capture Compare Register value */ + if (((TIMx->CCMR3)&TIM_CCMR3_OC5PE) != TIM_CCMR3_OC5PE) + { + TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse; + } + else if (((TIMx->CCMR3)&TIM_CCMR3_OC5PE) == TIM_CCMR3_OC5PE) + { + TIMx->CCR5 = TIM_OCInitStruct->TIM_Pulse; + TIMx->EGR |= TIM_EGR_UG; + TIMx->SR &= (uint32_t)~((uint32_t)TIM_SR_UIF); + } + + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Initializes the TIMx Channel6 according to the specified + * parameters in the TIM_OCInitStruct. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + uint32_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); + assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); + + /* Disable the Channel 6: Reset the CC6E Bit */ + TIMx->CCER &= (uint32_t)(~((uint32_t)TIM_CCER_CC6E)); + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Get the TIMx CR2 register value */ + tmpcr2 = TIMx->CR2; + + /* Get the TIMx CCMR3 register value */ + tmpccmrx = TIMx->CCMR3; + + /* Reset the Output Compare mode Bits */ + tmpccmrx &= (uint32_t)(~((uint32_t)TIM_CCMR3_OC6M)); + /* Select the Output Compare Mode */ + tmpccmrx |= (uint32_t)(TIM_OCInitStruct->TIM_OCMode << 8); + + /* Reset the Output Polarity level */ + tmpccer &= (uint32_t)(~((uint32_t)TIM_CCER_CC6P)); + /* Set the Output Compare Polarity */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OCPolarity << 20); + + /* Set the Output State */ + tmpccer |= (uint32_t)(TIM_OCInitStruct->TIM_OutputState << 20); + + /* Check the parameters */ + assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); + + /* Reset the Ouput Compare IDLE State */ + tmpcr2 &= (uint32_t)(~((uint32_t)TIM_CR2_OIS6)); + /* Set the Output Idle state */ + tmpcr2 |= (uint32_t)(TIM_OCInitStruct->TIM_OCIdleState << 10); + + /* Write to TIMx CR2 */ + TIMx->CR2 = tmpcr2; + + /* Set the Capture Compare Register value */ + if (((TIMx->CCMR3)&TIM_CCMR3_OC6PE) != TIM_CCMR3_OC6PE) + { + TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse; + } + else if (((TIMx->CCMR3)&TIM_CCMR3_OC6PE) == TIM_CCMR3_OC6PE) + { + TIMx->CCR6 = TIM_OCInitStruct->TIM_Pulse; + TIMx->EGR |= TIM_EGR_UG; + TIMx->SR &= (uint32_t)~((uint32_t)TIM_SR_UIF); + } + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmrx; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Group channel 5 and channel 1, 2 or 3 + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_Group_Channel5 specifies the reference signal(s) the OC5REF is combined with. + * This parameter can be any combination of the following values: + * TIM_GroupCH5_None : No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC + * TIM_GroupCH5_OC1Refc: OC1REFC is the logical AND of OC1REFC and OC5REF + * TIM_GroupCH5_OC2Refc: OC2REFC is the logical AND of OC2REFC and OC5REF + * TIM_GroupCH5_OC3Refc: OC3REFC is the logical AND of OC3REFC and OC5REF + * @retval None + */ +void TIM_GroupChannel5(TIM_TypeDef* TIMx, uint32_t TIM_Group_Channel5) +{ + /* Check parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_GROUPCH5(TIM_Group_Channel5)); + + /* Clear GC5Cx bit fields */ + TIMx->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); + + /* Set GC5Cx bit fields */ + TIMx->CCR5 |= TIM_Group_Channel5; +} + +/** + * @brief Fills each TIM_OCInitStruct member with its default value. + * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCNPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/** + * @brief Selects the TIM Output Compare Mode. + * @note This function disables the selected channel before changing the Output + * Compare Mode. + * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select + * the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @arg TIM_Channel_5: TIM Channel 5 + * @arg TIM_Channel_6: TIM Channel 6 + * @param TIM_OCMode: specifies the TIM Output Compare Mode. + * This parameter can be one of the following values: + * @arg TIM_OCMode_Timing + * @arg TIM_OCMode_Active + * @arg TIM_OCMode_Inactive + * @arg TIM_OCMode_Toggle + * @arg TIM_OCMODE_Forced_Inactive + * @arg TIM_OCMODE_Forced_Active + * @arg TIM_OCMode_PWM1 + * @arg TIM_OCMode_PWM2 + * @arg TIM_OCMode_Combined_PWM1 + * @arg TIM_OCMode_Combined_PWM2 + * @arg TIM_OCMode_Asymmetric_PWM1 + * @arg TIM_OCMode_Asymmetric_PWM2 + * @retval None + */ +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint32_t tmp1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_MODE(TIM_OCMode)); + + /* Check the parameters - TIM_Channel */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + } + else if ((TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) || (TIMx == TIM5)) + { + assert_param(IS_TIM_2_TO_5_CHANNEL(TIM_Channel)); + } + else if ((TIMx == TIM9) || (TIMx == TIM12)) + { + assert_param(IS_TIM_9_AND_12_CHANNEL(TIM_Channel)); + } + else/*if((TIMx == TIM10) || (TIMx == TIM11) || + (TIMx == TIM13) || (TIMx == TIM14))*/ + { + assert_param(IS_TIM_10_11_13_14_CHANNEL(TIM_Channel)); + } + + tmp = (uint32_t) TIMx; + tmp += CCMR_OFFSET; + + tmp1 = CCER_CCE_SET << (uint32_t)TIM_Channel; + + /* Disable the Channel: Reset the CCxE Bit */ + TIMx->CCER &= (uint32_t) ~tmp1; + + if ((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3) || (TIM_Channel == TIM_Channel_5)) + { + if ((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + } + else /* if(TIM_Channel == TIM_Channel_5) */ + { + tmp += ((uint32_t)0x0000003C); + } + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= TIM_OCMode; + } + else + { + if ((TIM_Channel == TIM_Channel_2) || (TIM_Channel == TIM_Channel_4)) + { + tmp += (uint32_t)(TIM_Channel - (uint32_t)4) >> (uint32_t)1; + } + else /* if(TIM_Channel == TIM_Channel_6) */ + { + tmp += ((uint32_t)0x0000003C); + } + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t *) tmp |= (uint32_t)(TIM_OCMode << 8); + } +} + +/** + * @brief Sets the TIMx Capture Compare1 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param Compare1: specifies the Capture Compare1 register new value. + * @retval None + */ +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Set the Capture Compare1 Register value */ + TIMx->CCR1 = Compare1; +} + +/** + * @brief Sets the TIMx Capture Compare2 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select + * the TIM peripheral. + * @param Compare2: specifies the Capture Compare2 register new value. + * @retval None + */ +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + + /* Set the Capture Compare2 Register value */ + TIMx->CCR2 = Compare2; +} + +/** + * @brief Sets the TIMx Capture Compare3 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare3: specifies the Capture Compare3 register new value. + * @retval None + */ +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare3 Register value */ + TIMx->CCR3 = Compare3; +} + +/** + * @brief Sets the TIMx Capture Compare4 Register value + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param Compare4: specifies the Capture Compare4 register new value. + * @retval None + */ +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Set the Capture Compare4 Register value */ + TIMx->CCR4 = Compare4; +} + +/** + * @brief Sets the TIMx Capture Compare5 Register value + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param Compare5: specifies the Capture Compare5 register new value. + * @retval None + */ +void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Set the Capture Compare5 Register value */ + TIMx->CCR5 = Compare5; +} + +/** + * @brief Sets the TIMx Capture Compare6 Register value + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param Compare6: specifies the Capture Compare6 register new value. + * @retval None + */ +void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Set the Capture Compare6 Register value */ + TIMx->CCR6 = Compare6; +} + +/** + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select the + * TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active : Force active level on OC1REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. + * @retval None + */ +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1M Bits */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); + + /* Configure The Forced output Mode */ + tmpccmr1 |= TIM_ForcedAction; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active : Force active level on OC2REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. + * @retval None + */ +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2M Bits */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); + + /* Configure The Forced output Mode */ + tmpccmr1 |= (uint32_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active : Force active level on OC3REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. + * @retval None + */ +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3M Bits */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC3M); + + /* Configure The Forced output Mode */ + tmpccmr2 |= TIM_ForcedAction; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active : Force active level on OC4REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. + * @retval None + */ +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmr2 = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4M Bits */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC4M); + + /* Configure The Forced output Mode */ + tmpccmr2 |= (uint32_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Forces the TIMx output 5 waveform to active or inactive level. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active : Force active level on OC5REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC5REF. + * @retval None + */ +void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC5M Bits */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC5M); + + /* Configure The Forced output Mode */ + tmpccmr3 |= TIM_ForcedAction; + + /* Write to TIMx CCMR3 register */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Forces the TIMx output 6 waveform to active or inactive level. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. + * This parameter can be one of the following values: + * @arg TIM_ForcedAction_Active : Force active level on OC6REF + * @arg TIM_ForcedAction_InActive: Force inactive level on OC6REF. + * @retval None + */ +void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint32_t TIM_ForcedAction) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC6M Bits */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC6M); + + /* Configure The Forced output Mode */ + tmpccmr3 |= (uint32_t)(TIM_ForcedAction << 8); + + /* Write to TIMx CCMR3 register */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Capture Compare Preload Control bit + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + if (NewState != DISABLE) + { + /* Set the CCPC Bit */ + TIMx->CR2 |= TIM_CR2_CCPC; + } + else + { + /* Reset the CCPC Bit */ + TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_CCPC); + } +} + + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 and 14 to + * select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1PE Bit */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= TIM_OCPreload; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 and 12 to select the + * TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2PE Bit */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr1 |= (uint32_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3PE Bit */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC3PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= TIM_OCPreload; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4PE Bit */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC4PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr2 |= (uint32_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR5. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC5PE Bit */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC5PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= TIM_OCPreload; + + /* Write to TIMx CCMR3 register */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Enables or disables the TIMx peripheral Preload register on CCR6. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPreload: new state of the TIMx peripheral Preload register + * This parameter can be one of the following values: + * @arg TIM_OCPreload_Enable + * @arg TIM_OCPreload_Disable + * @retval None + */ +void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPreload) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); + + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC6PE Bit */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC6PE); + + /* Enable or Disable the Output Compare Preload feature */ + tmpccmr3 |= (uint32_t)(TIM_OCPreload << 8); + + /* Write to TIMx CCMR3 register */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 1 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable : TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1FE Bit */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= TIM_OCFast; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 2 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select + * the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable : TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2FE Bit */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr1 |= (uint32_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Configures the TIMx Output Compare 3 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable : TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3FE Bit */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC3FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= TIM_OCFast; + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 4 Fast feature. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable : TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4FE Bit */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC4FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr2 |= (uint32_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR2 */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Configures the TIMx Output Compare 5 Fast feature. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable : TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC5FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC5FE Bit */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC5FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= TIM_OCFast; + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx Output Compare 6 Fast feature. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCFast_Enable : TIM output compare fast enable + * @arg TIM_OCFast_Disable: TIM output compare fast disable + * @retval None + */ +void TIM_OC6FastConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCFast) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); + + /* Get the TIMx CCMR3 register value */ + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC6FE Bit */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC6FE); + + /* Enable or Disable the Output Compare Fast Bit */ + tmpccmr3 |= (uint32_t)(TIM_OCFast << 8); + + /* Write to TIMx CCMR3 */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF1 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable : TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC1CE Bit */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1CE); + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= TIM_OCClear; + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF2 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable : TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmr1 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr1 = TIMx->CCMR1; + + /* Reset the OC2CE Bit */ + tmpccmr1 &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2CE); + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr1 |= (uint32_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR1 register */ + TIMx->CCMR1 = tmpccmr1; +} + +/** + * @brief Clears or safeguards the OCREF3 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable : TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC3CE Bit */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC3CE); + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= TIM_OCClear; + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF4 signal on an external event + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable : TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmr2 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr2 = TIMx->CCMR2; + + /* Reset the OC4CE Bit */ + tmpccmr2 &= (uint32_t)~((uint32_t)TIM_CCMR2_OC4CE); + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr2 |= (uint32_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR2 register */ + TIMx->CCMR2 = tmpccmr2; +} + +/** + * @brief Clears or safeguards the OCREF5 signal on an external event + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable : TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC5CE Bit */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC5CE); + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= TIM_OCClear; + + /* Write to TIMx CCMR3 register */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Clears or safeguards the OCREF6 signal on an external event + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. + * This parameter can be one of the following values: + * @arg TIM_OCClear_Enable : TIM Output clear enable + * @arg TIM_OCClear_Disable: TIM Output clear disable + * @retval None + */ +void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint32_t TIM_OCClear) +{ + uint32_t tmpccmr3 = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); + + tmpccmr3 = TIMx->CCMR3; + + /* Reset the OC6CE Bit */ + tmpccmr3 &= (uint32_t)~((uint32_t)TIM_CCMR3_OC6CE); + + /* Enable or Disable the Output Compare Clear Bit */ + tmpccmr3 |= (uint32_t)(TIM_OCClear << 8); + + /* Write to TIMx CCMR3 register */ + TIMx->CCMR3 = tmpccmr3; +} + +/** + * @brief Configures the TIMx channel 1 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 + * or 14 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1P Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC1P); + tmpccer |= TIM_OCPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 1N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC1N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC1NP Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC1NP); + tmpccer |= TIM_OCNPolarity; + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 2 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to + * select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2P Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC2P); + tmpccer |= (uint32_t)(TIM_OCPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 2N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC2N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCNPolarity) +{ + uint32_t tmpccer = 0; + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC2NP Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_OCNPolarity << 4); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 3 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select + * the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC3 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3P Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC3P); + tmpccer |= (uint32_t)(TIM_OCPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx Channel 3N polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCNPolarity: specifies the OC3N Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCNPolarity_High: Output Compare active high + * @arg TIM_OCNPolarity_Low: Output Compare active low + * @retval None + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCNPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC3NP Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC3NP); + tmpccer |= (uint32_t)(TIM_OCNPolarity << 8); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 4 polarity. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select + * the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC4 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC4P Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC4P); + tmpccer |= (uint32_t)(TIM_OCPolarity << 12); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 5 polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC5 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC5P Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC5P); + tmpccer |= (uint32_t)(TIM_OCPolarity << 16); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Configures the TIMx channel 6 polarity. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_OCPolarity: specifies the OC6 Polarity + * This parmeter can be one of the following values: + * @arg TIM_OCPolarity_High: Output Compare active high + * @arg TIM_OCPolarity_Low : Output Compare active low + * @retval None + */ +void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCPolarity) +{ + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); + + tmpccer = TIMx->CCER; + + /* Set or Reset the CC6P Bit */ + tmpccer &= (uint32_t)~((uint32_t)TIM_CCER_CC6P); + tmpccer |= (uint32_t)(TIM_OCPolarity << 20); + + /* Write to TIMx CCER register */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Selects the OCReference Clear source. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCReferenceClear: specifies the OCReference Clear source. + * This parameter can be one of the following values: + * @arg TIM_OCReferenceClear_ETRF : The internal OCreference clear input is connected to ETRF. + * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input. + * @retval None + */ +void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint32_t TIM_OCReferenceClear) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear)); + + /* Set the TIM_OCReferenceClear source */ + TIMx->SMCR &= (uint32_t)~((uint32_t)TIM_SMCR_OCCS); + TIMx->SMCR |= TIM_OCReferenceClear; +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel x. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select + * the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parameter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @arg TIM_Channel_4: TIM Channel 4 + * @arg TIM_Channel_5: TIM Channel 5 + * @arg TIM_Channel_6: TIM Channel 6 + * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. + * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable . + * @retval None + */ +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_CCx) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_CCX(TIM_CCx)); + + /* Check the parameters - TIM_Channel */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_CHANNEL(TIM_Channel)); + } + else if ((TIMx == TIM2) || (TIMx == TIM3) || + (TIMx == TIM4) || (TIMx == TIM5)) + { + assert_param(IS_TIM_2_TO_5_CHANNEL(TIM_Channel)); + } + else if ((TIMx == TIM9) || (TIMx == TIM12)) + { + assert_param(IS_TIM_9_AND_12_CHANNEL(TIM_Channel)); + } + else/*if((TIMx == TIM10) || (TIMx == TIM11) || + (TIMx == TIM13) || (TIMx == TIM14))*/ + { + assert_param(IS_TIM_10_11_13_14_CHANNEL(TIM_Channel)); + } + + tmp = CCER_CCE_SET << TIM_Channel; + + /* Reset the CCxE Bit */ + TIMx->CCER &= (uint32_t)~ tmp; + + /* Set or reset the CCxE Bit */ + TIMx->CCER |= (uint32_t)(TIM_CCx << TIM_Channel); +} + +/** + * @brief Enables or disables the TIM Capture Compare Channel xN. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_Channel: specifies the TIM Channel + * This parmeter can be one of the following values: + * @arg TIM_Channel_1: TIM Channel 1 + * @arg TIM_Channel_2: TIM Channel 2 + * @arg TIM_Channel_3: TIM Channel 3 + * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. + * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. + * @retval None + */ +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint32_t TIM_Channel, uint32_t TIM_CCxN) +{ + uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); + assert_param(IS_TIM_CCXN(TIM_CCxN)); + + tmp = CCER_CCNE_SET << TIM_Channel; + + /* Reset the CCxNE Bit */ + TIMx->CCER &= (uint32_t) ~tmp; + + /* Set or reset the CCxNE Bit */ + TIMx->CCER |= (uint32_t)(TIM_CCxN << TIM_Channel); +} + +/** + * @brief Selects the TIM peripheral Commutation event. + * @param TIMx: where x can be 1 or 8 to select the TIMx peripheral + * @param NewState: new state of the Commutation event. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the COM Bit */ + TIMx->CR2 |= TIM_CR2_CCUS; + } + else + { + /* Reset the COM Bit */ + TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_CCUS); + } +} + +/** + * @} + */ +/** + * @brief Initializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); + assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); + assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI3 Configuration */ + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + /* TI4 Configuration */ + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Fills each TIM_ICInitStruct member with its default value. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will + * be initialized. + * @retval None + */ +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/** + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure + * that contains the configuration information for the specified TIM + * peripheral. + * @retval None + */ +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) +{ + uint32_t icoppositepolarity = TIM_ICPolarity_Rising; + uint32_t icoppositeselection = TIM_ICSelection_DirectTI; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + /* Select the Opposite Input */ + if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + /* TI1 Configuration */ + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI2 Configuration */ + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + /* TI2 Configuration */ + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + /* TI1 Configuration */ + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + /* Set the Input Capture Prescaler value */ + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/** + * @brief Gets the TIMx Input Capture 1 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @retval Capture Compare 1 Register value. + */ +uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + + /* Get the Capture 1 Register value */ + return TIMx->CCR1; +} + +/** + * @brief Gets the TIMx Input Capture 2 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the + * TIM peripheral. + * @retval Capture Compare 2 Register value. + */ +uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + + /* Get the Capture 2 Register value */ + return TIMx->CCR2; +} + +/** + * @brief Gets the TIMx Input Capture 3 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 3 Register value. + */ +uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 3 Register value */ + return TIMx->CCR3; +} + +/** + * @brief Gets the TIMx Input Capture 4 value. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @retval Capture Compare 4 Register value. + */ +uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Get the Capture 4 Register value */ + return TIMx->CCR4; +} + +/** + * @brief Gets the TIMx Input Capture 5 value. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @retval Capture Compare 5 Register value. + */ +uint32_t TIM_GetCapture5(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Get the Capture 5 Register value */ + return TIMx->CCR5; +} + +/** + * @brief Gets the TIMx Input Capture 6 value. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @retval Capture Compare 6 Register value. + */ +uint32_t TIM_GetCapture6(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + + /* Get the Capture 6 Register value */ + return TIMx->CCR6; +} + +/** + * @brief Sets the TIMx Input Capture 1 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST4_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC1PSC Bits */ + TIMx->CCMR1 &= (uint32_t)~((uint32_t)TIM_CCMR1_IC1PSC); + + /* Set the IC1PSC value */ + TIMx->CCMR1 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 2 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC2PSC Bits */ + TIMx->CCMR1 &= (uint32_t)~((uint32_t)TIM_CCMR1_IC2PSC); + + /* Set the IC2PSC value */ + TIMx->CCMR1 |= (uint32_t)(TIM_ICPSC << 8); +} + +/** + * @brief Sets the TIMx Input Capture 3 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC3PSC Bits */ + TIMx->CCMR2 &= (uint32_t)~((uint32_t)TIM_CCMR2_IC3PSC); + + /* Set the IC3PSC value */ + TIMx->CCMR2 |= TIM_ICPSC; +} + +/** + * @brief Sets the TIMx Input Capture 4 prescaler. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. + * This parameter can be one of the following values: + * @arg TIM_ICPSC_DIV1: no prescaler + * @arg TIM_ICPSC_DIV2: capture is done once every 2 events + * @arg TIM_ICPSC_DIV4: capture is done once every 4 events + * @arg TIM_ICPSC_DIV8: capture is done once every 8 events + * @retval None + */ +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint32_t TIM_ICPSC) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); + + /* Reset the IC4PSC Bits */ + TIMx->CCMR2 &= (uint32_t)~((uint32_t)TIM_CCMR2_IC4PSC); + + /* Set the IC4PSC value */ + TIMx->CCMR2 |= (uint32_t)(TIM_ICPSC << 8); +} + +/** + * @} + */ + +/** + * @brief Enables or disables the specified TIM interrupts. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update : TIM update Interrupt source + * @arg TIM_IT_CC1 : TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2 : TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3 : TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4 : TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM : TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break : TIM Break Interrupt source + * + * @note TIM2, TIM3, TIM4 and TIM5 can generate TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger interrupt. + * @note TIM6 and TIM7 can only generate an update interrupt. + * @note TIM9 and TIM12 can generate TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 and + * TIM_IT_Trigger interrupt. + * @note TIM10, TIM11, TIM13 and TIM14 can generate TIM_IT_Update and TIM_IT_CC1 + * interrupt. + * + * @note TIM_IT_Break is used only with TIM1 and TIM8. + * @note TIM_IT_COM is used only with TIM1 and TIM8. + * + * @param NewState: new state of the TIM interrupts. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_ITConfig(TIM_TypeDef* TIMx, uint32_t TIM_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the Interrupt sources */ + TIMx->DIER |= TIM_IT; + } + else + { + /* Disable the Interrupt sources */ + TIMx->DIER &= (uint32_t)~TIM_IT; + } +} + +/** + * @brief Configures the TIMx event to be generate by software. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIMx peripheral. + * @param TIM_EventSource: specifies the event source. + * This parameter can be one or more of the following values: + * @arg TIM_EventSource_Update : Timer update Event source + * @arg TIM_EventSource_CC1 : Timer Capture Compare 1 Event source + * @arg TIM_EventSource_CC2 : Timer Capture Compare 2 Event source + * @arg TIM_EventSource_CC3 : Timer Capture Compare 3 Event source + * @arg TIM_EventSource_CC4 : Timer Capture Compare 4 Event source + * @arg TIM_EventSource_COM : Timer COM event source + * @arg TIM_EventSource_Trigger: Timer Trigger Event source + * @arg TIM_EventSource_Break : Timer Break event source + * + * @note TIM2, TIM3, TIM4 and TIM5 can generate Update, CC1, CC2, CC3, CC4 and trigger event. + * @note TIM6 and TIM7 can only generate an update event. + * @note TIM9 and TIM12 can generate Update, CC1, CC2 and trigger event. + * @note TIM10, TIM11, TIM13 and TIM14 can generate Update and CC1 event. + * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint32_t TIM_EventSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); + + /* Set the event sources */ + TIMx->EGR = TIM_EventSource; +} + +/** + * @brief Checks whether the specified TIM flag is set or not. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIMx peripheral. + * @param TIM_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg TIM_FLAG_Update : TIM update Flag + * @arg TIM_FLAG_CC1 : TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 : TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 : TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 : TIM Capture Compare 4 Flag + * @arg TIM_FLAG_CC5 : TIM Capture Compare 5 Flag + * @arg TIM_FLAG_CC6 : TIM Capture Compare 6 Flag + * @arg TIM_FLAG_COM : TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break : TIM Break Flag + * @arg TIM_FLAG_CC1OF : TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF : TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF : TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF : TIM Capture Compare 4 overcapture Flag + * + * @note TIM2, TIM3, TIM4 and TIM5 can have Update, CC1, CC2, CC3, CC4, trigger, + * CC1OF, CC2OF, CC3OF and CC4OF flag. + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM9 and TIM12 can have Update, CC1, CC2, trigger, CC1OF and CC2OF flag. + * @note TIM10, TIM11, TIM13 and TIM14 can have Update, CC1 and CC1OF flag. + * @note TIM_FLAG_Break, TIM_FLAG_COM, TIM_FLAG_CC5 and TIM_FLAG_CC6 are used only + * with TIM1 and TIM8. + * + * @retval The new state of TIM_FLAG (SET or RESET). + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); + + if ((TIMx->SR & TIM_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's pending flags. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIMx peripheral. + * @param TIM_FLAG: specifies the flag bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_FLAG_Update : TIM update Flag + * @arg TIM_FLAG_CC1 : TIM Capture Compare 1 Flag + * @arg TIM_FLAG_CC2 : TIM Capture Compare 2 Flag + * @arg TIM_FLAG_CC3 : TIM Capture Compare 3 Flag + * @arg TIM_FLAG_CC4 : TIM Capture Compare 4 Flag + * @arg TIM_FLAG_CC5 : TIM Capture Compare 5 Flag + * @arg TIM_FLAG_CC6 : TIM Capture Compare 6 Flag + * @arg TIM_FLAG_COM : TIM Commutation Flag + * @arg TIM_FLAG_Trigger: TIM Trigger Flag + * @arg TIM_FLAG_Break : TIM Break Flag + * @arg TIM_FLAG_CC1OF : TIM Capture Compare 1 overcapture Flag + * @arg TIM_FLAG_CC2OF : TIM Capture Compare 2 overcapture Flag + * @arg TIM_FLAG_CC3OF : TIM Capture Compare 3 overcapture Flag + * @arg TIM_FLAG_CC4OF : TIM Capture Compare 4 overcapture Flag + * + * @note TIM2, TIM3, TIM4 and TIM5 can have Update, CC1, CC2, CC3, CC4, trigger, + * CC1OF, CC2OF, CC3OF and CC4OF flag. + * @note TIM6 and TIM7 can have only one update flag. + * @note TIM9 and TIM12 can have Update, CC1, CC2, trigger, CC1OF and CC2OF flag. + * @note TIM10, TIM11, TIM13 and TIM14 can have Update, CC1 and CC1OF flag. + * @note TIM_FLAG_Break, TIM_FLAG_COM, TIM_FLAG_CC5 and TIM_FLAG_CC6 are used only + * with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint32_t TIM_FLAG) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); + + /* Clear the flags */ + TIMx->SR = (uint32_t)~TIM_FLAG; +} + +/** + * @brief Checks whether the TIM interrupt has occurred or not. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIMx peripheral. + * @param TIM_IT: specifies the TIM interrupt source to check. + * This parameter can be one of the following values: + * @arg TIM_IT_Update : TIM update Interrupt source + * @arg TIM_IT_CC1 : TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2 : TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3 : TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4 : TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM : TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break : TIM Break Interrupt source + * + * @note TIM2, TIM3, TIM4 and TIM5 can generate TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger interrupt. + * @note TIM6 and TIM7 can only generate an update interrupt. + * @note TIM9 and TIM12 can generate TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 and + * TIM_IT_Trigger interrupt. + * @note TIM10, TIM11, TIM13 and TIM14 can generate TIM_IT_Update and TIM_IT_CC1 + * interrupt. + * + * @note TIM_IT_Break is used only with TIM1 and TIM8. + * @note TIM_IT_COM is used only with TIM1 and TIM8. + * + * @retval The new state of the TIM_IT(SET or RESET). + */ +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint32_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itstatus = 0x0, itenable = 0x0; + + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_GET_IT(TIM_IT)); + + itstatus = TIMx->SR & TIM_IT; + + itenable = TIMx->DIER & TIM_IT; + if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the TIMx's interrupt pending bits. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 or 14 + * to select the TIMx peripheral. + * @param TIM_IT: specifies the pending bit to clear. + * This parameter can be any combination of the following values: + * @arg TIM_IT_Update : TIM1 update Interrupt source + * @arg TIM_IT_CC1 : TIM Capture Compare 1 Interrupt source + * @arg TIM_IT_CC2 : TIM Capture Compare 2 Interrupt source + * @arg TIM_IT_CC3 : TIM Capture Compare 3 Interrupt source + * @arg TIM_IT_CC4 : TIM Capture Compare 4 Interrupt source + * @arg TIM_IT_COM : TIM Commutation Interrupt source + * @arg TIM_IT_Trigger: TIM Trigger Interrupt source + * @arg TIM_IT_Break : TIM Break Interrupt source + * + * @note TIM2, TIM3, TIM4 and TIM5 can generate TIM_IT_Update, TIM_IT_CC1, + * TIM_IT_CC2, TIM_IT_CC3, TIM_IT_CC4 and TIM_IT_Trigger interrupt. + * @note TIM6 and TIM7 can only generate an update interrupt. + * @note TIM9 and TIM12 can generate TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 and + * TIM_IT_Trigger interrupt. + * @note TIM10, TIM11, TIM13 and TIM14 can generate TIM_IT_Update and TIM_IT_CC1 + * interrupt. + * + * @note TIM_IT_Break is used only with TIM1 and TIM8. + * @note TIM_IT_COM is used only with TIM1 and TIM8. + * + * @retval None + */ +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint32_t TIM_IT) +{ + /* Check the parameters */ + assert_param(IS_TIM_ALL_PERIPH(TIMx)); + assert_param(IS_TIM_IT(TIM_IT)); + + /* Clear the IT pending Bit */ + TIMx->SR = (uint32_t)~TIM_IT; +} + +/** + * @brief Configures the TIMx's DMA interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_DMABase: DMA Base address. + * This parameter can be one of the following values: + * @arg TIM_DMABase_CR1 + * @arg TIM_DMABase_CR2 + * @arg TIM_DMABase_SMCR + * @arg TIM_DMABase_DIER + * @arg TIM_DMABase_SR + * @arg TIM_DMABase_EGR + * @arg TIM_DMABase_CCMR1 + * @arg TIM_DMABase_CCMR2 + * @arg TIM_DMABase_CCER + * @arg TIM_DMABase_CNT + * @arg TIM_DMABase_PSC + * @arg TIM_DMABase_ARR + * @arg TIM_DMABase_RCR + * @arg TIM_DMABase_CCR1 + * @arg TIM_DMABase_CCR2 + * @arg TIM_DMABase_CCR3 + * @arg TIM_DMABase_CCR4 + * @arg TIM_DMABase_BDTR + * @arg TIM_DMABase_DCR + * @arg TIM_DMABase_OR + * @arg TIM_DMABase_CCMR3 + * @arg TIM_DMABase_CCR5 + * @arg TIM_DMABase_CCR6 + * @arg TIM_DMABase_AF1 + * @arg TIM_DMABase_AF2 + * @arg TIM_DMABase_TISEL + * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value + * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * @retval None + */ +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint32_t TIM_DMABase, uint32_t TIM_DMABurstLength) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); + assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); + + /* Set the DMA Base and the DMA Burst Length */ + TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; +} + +/** + * @brief Enables or disables the TIMx's DMA Requests. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * @param TIM_DMASource: specifies the DMA Request sources. + * This parameter can be any combination of the following values: + * @arg TIM_DMA_Update : TIM update Interrupt source + * @arg TIM_DMA_CC1 : TIM Capture Compare 1 DMA source + * @arg TIM_DMA_CC2 : TIM Capture Compare 2 DMA source + * @arg TIM_DMA_CC3 : TIM Capture Compare 3 DMA source + * @arg TIM_DMA_CC4 : TIM Capture Compare 4 DMA source + * @arg TIM_DMA_COM : TIM Commutation DMA source + * @arg TIM_DMA_Trigger: TIM Trigger DMA source + * @param NewState: new state of the DMA Request sources. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_DMACmd(TIM_TypeDef* TIMx, uint32_t TIM_DMASource, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA sources */ + TIMx->DIER |= TIM_DMASource; + } + else + { + /* Disable the DMA sources */ + TIMx->DIER &= (uint32_t)~TIM_DMASource; + } +} + +/** + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the + * TIM peripheral. + * @param NewState: new state of the Capture Compare DMA source + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the CCDS Bit */ + TIMx->CR2 |= TIM_CR2_CCDS; + } + else + { + /* Reset the CCDS Bit */ + TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_CCDS); + } +} + +/** + * @} + */ + +/** + * @brief Configures the TIMx internal Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to + * select the TIM peripheral. + * @retval None + */ +void TIM_InternalClockConfig(TIM_TypeDef* TIMx) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCR &= (uint32_t)(~((uint32_t)TIM_SMCR_SMS)); +} + +/** + * @brief Configures the TIMx Internal Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select + * the TIM peripheral. + * @param TIM_ITRSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0: Internal Trigger 0 + * @arg TIM_TS_ITR1: Internal Trigger 1 + * @arg TIM_TS_ITR2: Internal Trigger 2 + * @arg TIM_TS_ITR3: Internal Trigger 3 + * @retval None + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Select the Internal Trigger */ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the TIMx Trigger as External Clock + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the + * TIM peripheral. + * @param TIM_TIxExternalCLKSource: Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector + * @arg TIM_TIxExternalCLK1Source_TI1 : Filtered Timer Input 1 + * @arg TIM_TIxExternalCLK1Source_TI2 : Filtered Timer Input 2 + * @param TIM_ICPolarity: specifies the TIx Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param ICFilter: specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * @retval None + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint32_t TIM_TIxExternalCLKSource, + uint32_t TIM_ICPolarity, uint32_t ICFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); + assert_param(IS_TIM_IC_FILTER(ICFilter)); + + /* Configure the Timer Input Clock Source */ + if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + /* Select the Trigger source */ + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + + /* Select the External clock mode1 */ + TIMx->SMCR |= TIM_SlaveMode_External1; +} + +/** + * @brief Configures the External clock Mode1 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF : ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, + uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the SMS Bits */ + tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_SMS)); + + /* Select the External clock mode1 */ + tmpsmcr |= TIM_SlaveMode_External1; + + /* Select the Trigger selection : ETRF */ + tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_TS)); + tmpsmcr |= TIM_TS_ETRF; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Configures the External clock Mode2 + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF : ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted : active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, + uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + /* Configure the ETR Clock source */ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + + /* Enable the External clock mode2 */ + TIMx->SMCR |= TIM_SMCR_ECE; +} + +/** + * @} + */ +/** + * @brief Selects the Input Trigger source + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to + * select the TIM peripheral. + * @param TIM_InputTriggerSource: The Input Trigger source. + * This parameter can be one of the following values: + * @arg TIM_TS_ITR0 : Internal Trigger 0 + * @arg TIM_TS_ITR1 : Internal Trigger 1 + * @arg TIM_TS_ITR2 : Internal Trigger 2 + * @arg TIM_TS_ITR3 : Internal Trigger 3 + * @arg TIM_TS_TI1F_ED: TI1 Edge Detector + * @arg TIM_TS_TI1FP1 : Filtered Timer Input 1 + * @arg TIM_TS_TI2FP2 : Filtered Timer Input 2 + * @arg TIM_TS_ETRF : External Trigger input + * + * @note TIM9 and TIM12 don't include TIM_TS_ETRF. + * + * @retval None + */ +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_InputTriggerSource) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Reset the TS Bits */ + tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_TS)); + + /* Set the Input Trigger source */ + tmpsmcr |= TIM_InputTriggerSource; + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This parameter can be one of the following values: + * + * - For all TIMx + * @arg TIM_TRGOSource_Reset : The UG bit in the TIM_EGR register is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). + * + * - For all TIMx except TIM6 and TIM7 + * @arg TIM_TRGOSource_OC1 : The trigger output sends a positive pulse when the CC1IF flag + * is to be set, as soon as a capture or compare match occurs (TRGO). + * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). + * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). + * + * @retval None + */ +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint32_t TIM_TRGOSource) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST6_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_MMS); + + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGOSource; +} + +/** + * @brief Selects the TIMx Trigger Output Mode. + * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. + * @param TIM_TRGOSource: specifies the Trigger Output source. + * This parameter can be one of the following values: + * @arg TIM_TRGO2Source_Reset : TIMx_EGR.UG bit is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_Enable : TIMx_CR1.CEN bit is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_Update : Update event is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC1 : Capture or a compare match 1 is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC1Ref : OC1REF signal is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC2Ref : OC2REF signal is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC3Ref : OC3REF signal is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC4Ref : OC4REF signal is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC5Ref : OC5REF signal is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC6Ref : OC6REF signal is used as trigger output (TRGO2) + * @arg TIM_TRGO2Source_OC4Ref_RisingFalling : OC4REF rising or falling edges generate pulses on TRGO2 + * @arg TIM_TRGO2Source_OC6Ref_RisingFalling : OC6REF rising or falling edges generate pulses on TRGO2 + * @arg TIM_TRGO2Source_OC4Ref_Rising_OC6Ref_Rising : OC4REF or OC6REF rising edges generate pulses on TRGO2 + * @arg TIM_TRGO2Source_OC4Ref_Rising_OC6Ref_Falling: OC4REF rising or OC6REF falling edges generate pulses on TRGO2 + * @arg TIM_TRGO2Source_OC5Ref_Rising_OC6Ref_Rising : OC5REF or OC6REF rising edges generate pulses on TRGO2 + * @arg TIM_TRGO2Source_OC5Ref_Rising_OC6Ref_Falling: OC5REF or OC6REF rising edges generate pulses on TRGO2 + * + * @retval None + */ +void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST2_PERIPH(TIMx)); + assert_param(IS_TIM_TRGO2_SOURCE(TIM_TRGO2Source)); + + /* Reset the MMS Bits */ + TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_MMS2); + + /* Select the TRGO source */ + TIMx->CR2 |= TIM_TRGO2Source; +} + +/** + * @brief Selects the TIMx Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_SlaveMode: specifies the Timer Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_SlaveMode_Reset : Rising edge of the selected trigger signal (TRGI) re-initializes + * the counter and triggers an update of the registers. + * @arg TIM_SlaveMode_Gated : The counter clock is enabled when the trigger signal (TRGI) is high. + * @arg TIM_SlaveMode_Trigger : The counter starts at a rising edge of the trigger TRGI. + * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. + * @retval None + */ +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); + + /* Reset the SMS Bits */ + TIMx->SMCR &= (uint32_t)~((uint32_t)TIM_SMCR_SMS); + + /* Select the Slave Mode */ + TIMx->SMCR |= TIM_SlaveMode; +} + +/** + * @brief Sets or Resets the TIMx Master/Slave Mode. + * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. + * This parameter can be one of the following values: + * @arg TIM_MasterSlaveMode_Enable : synchronization between the current timer + * and its slaves (through TRGO). + * @arg TIM_MasterSlaveMode_Disable: No action + * @retval None + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_MasterSlaveMode) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST5_PERIPH(TIMx)); + assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); + + /* Reset the MSM Bit */ + TIMx->SMCR &= (uint32_t)~((uint32_t)TIM_SMCR_MSM); + + /* Set or Reset the MSM Bit */ + TIMx->SMCR |= TIM_MasterSlaveMode; +} + +/** + * @brief Configures the TIMx External Trigger (ETR). + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPSC_OFF : ETRP Prescaler OFF. + * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. + * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. + * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. + * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * This parameter can be one of the following values: + * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. + * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. + * @param ExtTRGFilter: External Trigger Filter. + * This parameter must be a value between 0x00 and 0x0F + * @retval None + */ +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, + uint32_t ExtTRGFilter) +{ + uint32_t tmpsmcr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); + assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); + assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); + + tmpsmcr = TIMx->SMCR; + + /* Reset the ETR Bits */ + tmpsmcr &= SMCR_ETR_MASK; + + /* Set the Prescaler, the Filter value and the Polarity */ + tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (uint32_t)(TIM_ExtTRGPolarity | (uint32_t)(ExtTRGFilter << (uint32_t)8))); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; +} + +/** + * @} + */ +/** + * @brief Configures the TIMx Encoder Interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. + * This parameter can be one of the following values: + * @arg TIM_EncoderMode_TI1 : counts up/down on TI2FP2 edge depending on TI1FP1 level. + * @arg TIM_EncoderMode_TI2 : counts up/down on TI1FP1 edge depending on TI2FP2 level. + * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending + * on the level of the other input. + * @param TIM_IC1Polarity: specifies the IC1 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising : IC Rising edge. + * @param TIM_IC2Polarity: specifies the IC2 Polarity + * This parmeter can be one of the following values: + * @arg TIM_ICPolarity_Falling: IC Falling edge. + * @arg TIM_ICPolarity_Rising : IC Rising edge. + * @retval None + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint32_t TIM_EncoderMode, + uint32_t TIM_IC1Polarity, uint32_t TIM_IC2Polarity) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); + + /* Get the TIMx SMCR register value */ + tmpsmcr = TIMx->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = TIMx->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = TIMx->CCER; + + /* Set the encoder Mode */ + tmpsmcr &= (uint32_t)(~((uint32_t)TIM_SMCR_SMS)); + tmpsmcr |= TIM_EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR1_CC1S)) & (uint32_t)(~((uint32_t)TIM_CCMR1_CC2S))); + tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint32_t)~((uint32_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint32_t)(TIM_IC1Polarity | (uint32_t)(TIM_IC2Polarity << (uint32_t)4)); + + /* Write to TIMx SMCR */ + TIMx->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + TIMx->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + TIMx->CCER = tmpccer; +} + +/** + * @brief Enables or disables the TIMx's Hall sensor interface. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param NewState: new state of the TIMx Hall sensor interface. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Set the TI1S Bit */ + TIMx->CR2 |= TIM_CR2_TI1S; + } + else + { + /* Reset the TI1S Bit */ + TIMx->CR2 &= (uint32_t)~((uint32_t)TIM_CR2_TI1S); + } +} + +/** + * @} + */ + +/** + * @brief Configures the TIM2 or TIM11 OR register Remapping input Capabilities. + * @param TIMx: where x can be 2 or 11 to select the TIM peripheral. + * @param TIM_Remap: specifies the TIM input reampping source. + * This parameter can be one of the following values: + * + * - For TIM2 + * @arg TIM2_ITR1ConnectTIM8Trgo: TIM8 TRGO is connected to TIM2_ITR1 input + * @arg TIM2_ITR1ConnectPTPTrgo : PTP TRGO is connected to TIM2_ITR1 input + * @arg TIM2_ITR1ConnectOTGFSSOF: OTG FS SOF is connected to TIM2_ITR1 input + * @arg TIM2_ITR1ConnectOTGHSSOF: OTG HS SOF is connected to TIM2_ITR1 input + * + * - For TIM11 + * @arg TIM11_IT1ConnectGPIO_0 : TIM11 GPIO is connected to TIM11_TI1 input + * @arg TIM11_IT1ConnectGPIO_1 : TIM11 GPIO is connected to TIM11_TI1 input + * @arg TIM11_IT1ConnectHSE_RTC: HSE RTC clock is connected to TIM11_TI1 input + * @arg TIM11_IT1ConnectGPIO_3 : TIM11 GPIO is connected to TIM11_TI1 input + * + * @retval None + */ +void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST7_PERIPH(TIMx)); + + /* Check the parameters - TIM_Remap */ + if (TIMx == TIM2) + { + assert_param(IS_TIM2_ITR1REMAP(TIM_Remap)); + } + else + { + assert_param(IS_TIM11_ITR1REMAP(TIM_Remap)); + } + + /* Clear the Timer ITR1_RMP or IT1_RMP remapping configuration */ + if (TIMx == TIM2) + { + TIMx->OR &= (uint32_t)(~(3 << (uint32_t)10)); + } + else + { + TIMx->OR &= (uint32_t)(~(3 << (uint32_t)0)); + } + + /* Set the Timer remapping configuration */ + if (TIMx == TIM2) + { + TIMx->OR = (uint32_t)(TIM_Remap << (uint32_t)10); + } + else + { + TIMx->OR = TIM_Remap; + } +} + +/** + * @brief Configures the TIMx ETRSEL[3:0] bits of AF1 register Remapping input Capabilities. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ETRSel_Remap: specifies the TIM etrsel input reampping source. + * This parameter can be one of the following values: + * + * - For TIM1 and TIM8 + * @arg TIM_ETR_GPIO : ETR input is connected to GPIO + * @arg TIM_ETR_COMP1 : ETR input is connected to COMP1_OUT + * @arg TIM_ETR_COMP2 : ETR input is connected to COMP2_OUT + * @arg TIM_ETR_COMP3 : ETR input is connected to COMP3_OUT + * @arg TIM_ETR_COMP4 : ETR input is connected to COMP4_OUT + * @arg TIM_ETR_COMP5 : ETR input is connected to COMP5_OUT + * @arg TIM_ETR_COMP6 : ETR input is connected to COMP6_OUT + * @arg TIM_ETR_ADC1_AWD1: ETR input is connected to ADC1 analog watchdog 1 + * @arg TIM_ETR_ADC1_AWD2: ETR input is connected to ADC1 analog watchdog 2 + * @arg TIM_ETR_ADC1_AWD3: ETR input is connected to ADC1 analog watchdog 3 + * @arg TIM_ETR_ADC2_AWD1: ETR input is connected to ADC2 analog watchdog 1 + * @arg TIM_ETR_ADC2_AWD2: ETR input is connected to ADC2 analog watchdog 2 + * @arg TIM_ETR_ADC2_AWD3: ETR input is connected to ADC2 analog watchdog 3 + * @arg TIM_ETR_ADC3_AWD1: ETR input is connected to ADC3 analog watchdog 1 + * @arg TIM_ETR_ADC3_AWD2: ETR input is connected to ADC3 analog watchdog 2 + * @arg TIM_ETR_ADC3_AWD3: ETR input is connected to ADC3 analog watchdog 3 + * + * - For TIM2, TIM3, TIM4 and TIM5 + * @arg TIM_ETR_GPIO: ETR input is connected to GPIO + * @arg TIM_ETR_1 : ETR input is connected to ETR[ 1] + * @arg TIM_ETR_2 : ETR input is connected to ETR[ 2] + * @arg TIM_ETR_3 : ETR input is connected to ETR[ 3] + * @arg TIM_ETR_4 : ETR input is connected to ETR[ 4] + * @arg TIM_ETR_5 : ETR input is connected to ETR[ 5] + * @arg TIM_ETR_6 : ETR input is connected to ETR[ 6] + * @arg TIM_ETR_7 : ETR input is connected to ETR[ 7] + * @arg TIM_ETR_8 : ETR input is connected to ETR[ 8] + * @arg TIM_ETR_9 : ETR input is connected to ETR[ 9] + * @arg TIM_ETR_10 : ETR input is connected to ETR[10] + * @arg TIM_ETR_11 : ETR input is connected to ETR[11] + * @arg TIM_ETR_12 : ETR input is connected to ETR[12] + * @arg TIM_ETR_13 : ETR input is connected to ETR[13] + * @arg TIM_ETR_14 : ETR input is connected to ETR[14] + * @arg TIM_ETR_15 : ETR input is connected to ETR[15] + * + * @retval None + */ +void TIM_ETRSelRemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_ETRSel_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Check the parameters - TIM_ETRSel_Remap */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_ETRSEL_LIST1_REMAP(TIM_ETRSel_Remap)); + } + else + { + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + assert_param(IS_TIM_ETRSEL_LIST2_REMAP(TIM_ETRSel_Remap)); + } + } + + /* Clear the Timer ETRSEL remapping configuration */ + TIMx->AF1 &= (uint32_t)(~TIM_AF1_ETRSEL); + + /* Set the Timer ETRSEL remapping configuration */ + TIMx->AF1 |= TIM_ETRSel_Remap; +} + +/** + * @brief Configures the TIMx OCRSEL[2:0] bits of AF2 register Remapping input Capabilities. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_OCRSel_Remap: specifies the TIM ocrsel input reampping source. + * This parameter can be one of the following values: + * + * - For TIM1 and TIM8 + * @arg TIM_OCR_COMP1: OCxref clear source select COMP1_OUT + * @arg TIM_OCR_COMP2: OCxref clear source select COMP2_OUT + * @arg TIM_OCR_COMP3: OCxref clear source select COMP3_OUT + * @arg TIM_OCR_COMP4: OCxref clear source select COMP4_OUT + * @arg TIM_OCR_COMP5: OCxref clear source select COMP5_OUT + * @arg TIM_OCR_COMP6: OCxref clear source select COMP6_OUT + * + * - For TIM2, TIM3, TIM4 and TIM5 + * @arg TIM_OCR_CLEAR_0: OCxref clear source select ocrefcr[0] + * @arg TIM_OCR_CLEAR_1: OCxref clear source select ocrefcr[1] + * @arg TIM_OCR_CLEAR_2: OCxref clear source select ocrefcr[2] + * @arg TIM_OCR_CLEAR_3: OCxref clear source select ocrefcr[3] + * @arg TIM_OCR_CLEAR_4: OCxref clear source select ocrefcr[4] + * @arg TIM_OCR_CLEAR_5: OCxref clear source select ocrefcr[5] + * @arg TIM_OCR_CLEAR_6: OCxref clear source select ocrefcr[6] + * @arg TIM_OCR_CLEAR_7: OCxref clear source select ocrefcr[7] + * + * @retval None + */ +void TIM_OCRSelRemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_OCRSel_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Check the parameters - TIM_OCRSel_Remap */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_OCRSEL_LIST1_REMAP(TIM_OCRSel_Remap)); + } + else + { + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + assert_param(IS_TIM_OCRSEL_LIST2_REMAP(TIM_OCRSel_Remap)); + } + } + + /* Clear the Timer OCRSEL remapping configuration */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + TIMx->AF2 &= (uint32_t)(~(7 << (uint32_t)0)); + } + else + { + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + TIMx->AF2 &= (uint32_t)(~(TIM_AF2_OCRSEL)); + } + } + + /* Set the Timer OCRSEL remapping configuration */ + TIMx->AF2 |= TIM_OCRSel_Remap; +} + +/** + * @brief Configures the TIMx TIxSEL[2:0] bits of TISEL register Remapping input Capabilities. + * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIxSEL: where x can be 1, 2, 3 or 4 to select the TIM TISEL. + * @param TIM_TISel_Channel: specifies the TIM tisel input channel select. + * This parameter can be one of the following values: + * + * - For TIM1 and TIM8 + * @arg TIM_TISel_Channel1 + * + * - For TIM2, TIM3, TIM4 and TIM5 + * @arg TIM_TISel_Channel1 + * @arg TIM_TISel_Channel2 + * @arg TIM_TISel_Channel3 + * @arg TIM_TISel_Channel4 + * + * @param TIM_TISel_Remap: specifies the TIM tisel input reampping source. + * This parameter can be one of the following values: + * + * - For TIM1 and TIM8 + * @arg TIM_TI1_CH1 : TIM_CH1 input select GPIO + * @arg TIM_TI1_COMP1: TIM_CH1 input select COMP1_OUT + * @arg TIM_TI1_COMP2: TIM_CH1 input select COMP2_OUT + * @arg TIM_TI1_COMP3: TIM_CH1 input select COMP3_OUT + * @arg TIM_TI1_COMP4: TIM_CH1 input select COMP4_OUT + * @arg TIM_TI1_COMP5: TIM_CH1 input select COMP5_OUT + * @arg TIM_TI1_COMP6: TIM_CH1 input select COMP6_OUT + * + * - For TIM2, TIM3, TIM4 and TIM5 + * @arg TIM_TI_CH : TIM_CH input select GPIO + * @arg TIM_TI_I1 : TIM_CH input select ti_i[ 1] + * @arg TIM_TI_I2 : TIM_CH input select ti_i[ 2] + * @arg TIM_TI_I3 : TIM_CH input select ti_i[ 3] + * @arg TIM_TI_I4 : TIM_CH input select ti_i[ 4] + * @arg TIM_TI_I5 : TIM_CH input select ti_i[ 5] + * @arg TIM_TI_I6 : TIM_CH input select ti_i[ 6] + * @arg TIM_TI_I7 : TIM_CH input select ti_i[ 7] + * @arg TIM_TI_I8 : TIM_CH input select ti_i[ 8] + * @arg TIM_TI_I9 : TIM_CH input select ti_i[ 9] + * @arg TIM_TI_I10: TIM_CH input select ti_i[10] + * @arg TIM_TI_I11: TIM_CH input select ti_i[11] + * @arg TIM_TI_I12: TIM_CH input select ti_i[12] + * @arg TIM_TI_I13: TIM_CH input select ti_i[13] + * @arg TIM_TI_I14: TIM_CH input select ti_i[14] + * @arg TIM_TI_I15: TIM_CH input select ti_i[15] + * + * @retval None + */ +void TIM_TISelRemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_TISel_Channel, uint32_t TIM_TISel_Remap) +{ + /* Check the parameters */ + assert_param(IS_TIM_LIST3_PERIPH(TIMx)); + + /* Check the parameters - TIM_TISel_Remap */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + assert_param(IS_TIM_TISEL_LIST1_REMAP(TIM_TISel_Remap)); + } + else + { + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + assert_param(IS_TIM_TISEL_LIST2_REMAP(TIM_TISel_Remap)); + } + } + + /* Clear the Timer TISEL remapping configuration */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + TIMx->TISEL &= (uint32_t)(~(7 << (uint32_t)TIM_TISel_Channel1)); + } + else + { + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + TIMx->TISEL &= (uint32_t)(~(TIM_TISEL_TI1SEL << TIM_TISel_Channel)); + } + } + + /* Set the Timer TIxSEL remapping configuration */ + if ((TIMx == TIM1) || (TIMx == TIM8)) + { + TIMx->TISEL |= (uint32_t)((TIM_TISel_Remap << (uint32_t)TIM_TISel_Channel1)); + } + else + { + if ((TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || (TIMx == TIM5)) + { + TIMx->TISEL |= (uint32_t)((TIM_TISel_Remap << TIM_TISel_Channel)); + } + } +} + +/** + * @} + */ + +/** + * @brief Configure the TI1 as Input. + * @param TIMx: where x can from 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 to select the TIM peripheral. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 1 is selected to be connected to IC1. + * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. + * @arg TIM_ICSelection_TRC : TIM Input 1 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI1_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0, tmpccer = 0; + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC1E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + + /* Select the Input and set the filter */ + tmpccmr1 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR1_CC1S)) & ((uint32_t)~((uint32_t)TIM_CCMR1_IC1F))); + tmpccmr1 |= (uint32_t)(TIM_ICSelection | (uint32_t)(TIM_ICFilter << (uint32_t)4)); + + /* Select the Polarity and set the CC1E Bit */ + tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); + tmpccer |= (uint32_t)(TIM_ICPolarity | (uint32_t)TIM_CCER_CC1E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI2 as Input. + * @param TIMx: where x can from 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 2 is selected to be connected to IC2. + * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. + * @arg TIM_ICSelection_TRC : TIM Input 2 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI2_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC2E); + tmpccmr1 = TIMx->CCMR1; + tmpccer = TIMx->CCER; + tmp = (uint32_t)(TIM_ICPolarity << 4); + + /* Select the Input and set the filter */ + tmpccmr1 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR1_CC2S)) & ((uint32_t)~((uint32_t)TIM_CCMR1_IC2F))); + tmpccmr1 |= (uint32_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint32_t)(TIM_ICSelection << 8); + + /* Select the Polarity and set the CC2E Bit */ + tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCER_CC2E); + + /* Write to TIMx CCMR1 and CCER registers */ + TIMx->CCMR1 = tmpccmr1 ; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI3 as Input. + * @param TIMx: where x can from 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 3 is selected to be connected to IC3. + * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. + * @arg TIM_ICSelection_TRC : TIM Input 3 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI3_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC3E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint32_t)(TIM_ICPolarity << 8); + + /* Select the Input and set the filter */ + tmpccmr2 &= (uint32_t)(((uint32_t)~((uint32_t)TIM_CCMR2_CC3S)) & ((uint32_t)~((uint32_t)TIM_CCMR2_IC3F))); + tmpccmr2 |= (uint32_t)(TIM_ICSelection | (uint32_t)(TIM_ICFilter << (uint32_t)4)); + + /* Select the Polarity and set the CC3E Bit */ + tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCER_CC3E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @brief Configure the TI4 as Input. + * @param TIMx: where x can from 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. + * @param TIM_ICPolarity: The Input Polarity. + * This parameter can be one of the following values: + * @arg TIM_ICPolarity_Rising + * @arg TIM_ICPolarity_Falling + * @param TIM_ICSelection: specifies the input to be used. + * This parameter can be one of the following values: + * @arg TIM_ICSelection_DirectTI : TIM Input 4 is selected to be connected to IC4. + * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. + * @arg TIM_ICSelection_TRC : TIM Input 4 is selected to be connected to TRC. + * @param TIM_ICFilter: Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * @retval None + */ +static void TI4_Config(TIM_TypeDef* TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, + uint32_t TIM_ICFilter) +{ + uint32_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~((uint32_t)TIM_CCER_CC4E); + tmpccmr2 = TIMx->CCMR2; + tmpccer = TIMx->CCER; + tmp = (uint32_t)(TIM_ICPolarity << 12); + + /* Select the Input and set the filter */ + tmpccmr2 &= (uint32_t)((uint32_t)(~(uint32_t)TIM_CCMR2_CC4S) & ((uint32_t)~((uint32_t)TIM_CCMR2_IC4F))); + tmpccmr2 |= (uint32_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint32_t)(TIM_ICFilter << 12); + + /* Select the Polarity and set the CC4E Bit */ + tmpccer &= (uint32_t)~((uint32_t)(TIM_CCER_CC4P)); + tmpccer |= (uint32_t)(tmp | (uint32_t)TIM_CCER_CC4E); + + /* Write to TIMx CCMR2 and CCER registers */ + TIMx->CCMR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_uart.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_uart.c new file mode 100644 index 00000000000..f30398bc1cd --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_uart.c @@ -0,0 +1,2391 @@ +/** + ****************************************************************************** + * @file ft32f4xx_uart.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter + * Peripheral (UART) and the Low-Power Universal Asynchronous Receiver + * Transmitter Peripheral (LPUART). + * + Initialization and de-initialization functions + * + Normal command and configuration functions + * + Fractional baudrate function + * + Break command functions + * + Receiver time-out and transmitter timeguard functions + * + Multidrop mode command function + * + IrDA mode function + * + LIN mode functions + * + Data transfers functions + * + DMA transfers management functions + * + Low-Power SLEEP and STOP wakeup management functions + * + Interrupts and flags management functions + * @version V1.0.0 + * @date 2025-03-28 + * + @verbatim + * + * [..] + * The functionalities supported by different UART and LPUART are listed in following: + * + * Table 1. UART / LPUART feature. + * +---------------------------------------------------------+ + * | Functionalities | UART4 | UART5 | UART7 | LPUART | + * |---------------------------------------------------------+ + * | DMA Communication | X | X | X | X | + * |---------------------------------------------------------+ + * | IrDA mode | X | X | X | - | + * |---------------------------------------------------------+ + * | Low-Power wakeup | X | X | X | X | + * |---------------------------------------------------------+ + * | LIN mode | X | X | X | - | + * |---------------------------------------------------------+ + * | Fractional baudrate | X | X | - | - | + * |---------------------------------------------------------+ + * | Timeguard and Time-out | X | X | X | - | + * |---------------------------------------------------------+ + * | Multidrop mode | X | X | X | X | + * |---------------------------------------------------------+ + * + * [+] X - Supported + * [+] - - Not supported + * [+] Low-Power wakeup: UART can wakeup from SLEEP mode. + * LPUART can wakeup from SLEEP and STOP mode. + * + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_uart.h" +#include "ft32f4xx_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +/*!< UART and LPUART CR register mode field Mask ((~(uint32_t)0xFFFFFF5F)) */ +#define CR_CLEAR_MODE_MASK ((uint32_t)(USART_CR_TXDIS | USART_CR_RXDIS)) /*!< UART CR mode fields of parameters set by UART_Init API */ + +/*!< UART and LPUART MR register normal Mask ((~(uint32_t)0xFF740100)) */ +#define MR_CLEAR_NORMAL_MASK ((uint32_t)(USART_MR_INVDATA | USART_MR_OVER | \ + USART_MR_MODE9 | \ + USART_MR_MSBF | USART_MR_CHMODE | \ + USART_MR_NBSTOP | USART_MR_PAR | \ + USART_MR_CHRL | \ + USART_MR_USCLKS | USART_MR_USART_MODE))/*!< UART MR normal fields of parameters set by UART_Init API */ + +/** + * @} + */ + +/** @defgroup UART and LPUAR init and de-init functions + * @brief None + * +@verbatim + =============================================================================== + ##### Init and DeInit Functions ##### + =============================================================================== + [..] This subsection provides a set of functions about UART and LPUART + initialization and de-initialization. + + [..] Most UART and LPUART configurations can be set in the UART_init() function. + However, After UART_Init() function, user can use others configurations + (cfg) functions to change UART and LPUART configurational. The command (Cmd) + functions can execute control operations under different configurations. + + [..] The configuration procedure of UART_Init() function is as follows: + (++) Check the parameters + (++) Enable UARTx and LPUART work clock and configuration clock. + (++) UART and LPUART CR configuration + (#) Configure the UART_Mode: + (-) transmitter disable + (-) transmitter enable + (-) receiver disable + (-) receiver enable + (++) UART and LPUART MR configuration + (#) Normal configuration: + (-) Inverted data + (-) Oversampling mode + (-) 9-bit character length + (-) Bit order + (-) channel mode + (-) Number of STOP bits + (-) Parity type + (-) Character length + (-) Clock selection + (-) UART mode of operation + (++) UART BRGR configuration except fractional part + (++) UART IF configuration + (++) UART LINMR configuration: + (-) Synchronization disable + (-) DMA mode + (-) Data length control + (-) Wakeup signal type + (-) Frame slot mode disable + (-) Data length mode + (-) Checksum type + (-) Checksum disable + (-) Parity disable + (-) LIN node action + + [..] + + (#) The UART and LPUART init API's : + (++) UART_Init() + + (#) The UART and LPUART Struct init API's : + (++) UART_StructInit() + + (#) The UART and LPUART de-init API's : + (++) UART_DeInit() +@endverbatim + * @{ + */ + +/** + * @brief Initialize the UART and LPUART peripheral according to the specified + * parameters in the UART_InitStruct. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_InitStruct: pointer to a UART_InitTypeDef structure that contains + * the configuration information for the specified UART peripheral. + * @retval None + */ +void UART_Init(USART_TypeDef* UARTx, UART_InitTypeDef* UART_InitStruct) +{ + uint32_t clock_divider = 0, frac_divider = 0, apbclock = 0, tmpreg = 0; + + RCC_ClocksTypeDef RCC_ClocksStatus; + + /*---------------------------- Check the Parameter -------------------------*/ + /* Check UART PERIPH */ + if ((UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_IrDA) || + (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_LIN_MASTER) || + (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_LIN_SLAVE)) + { + assert_param(IS_UART_457_PERIPH(UARTx)); + } + else if (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_NORMAL) + { + assert_param(IS_UART_ALL_PERIPH(UARTx)); + } + + if (UART_InitStruct->UART_INVData == UART_INVDATA_ENABLE) + { + assert_param(IS_UART_457_PERIPH(UARTx)); + } + else + { + assert_param(IS_UART_ALL_PERIPH(UARTx)); + } + + /* Check normal parameter*/ + assert_param(IS_UART_BAUDRATE(UART_InitStruct->UART_BaudRate)); + assert_param(IS_UART_CHAR_LENGTH(UART_InitStruct->UART_WordLength)); + assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits)); + assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity)); + assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode)); + assert_param(IS_UART_CLOCK_SELECT(UART_InitStruct->UART_CLKSelect)); + assert_param(IS_UART_MODE_OPERATION(UART_InitStruct->UART_OperationMode)); + assert_param(IS_UART_BIT_ORDER(UART_InitStruct->UART_BitOrder)); + assert_param(IS_UART_CHANNEL_MODE(UART_InitStruct->UART_ChannelMode)); + assert_param(IS_UART_OVERSAMPLING(UART_InitStruct->UART_OverSampling)); + assert_param(IS_UART_INVDATA(UART_InitStruct->UART_INVData)); + + /* Check IrDA mode parameter */ + if (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_IrDA) + { + assert_param(IS_UART_IF(UART_InitStruct->UART_IrDAFilter)); + assert_param(IS_UART_FIDIRATIO(UART_InitStruct->UART_FiDiRatio)); + } + + /* Check LIN mode parameter*/ + if ((UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_LIN_MASTER) || + (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_LIN_SLAVE)) + { + assert_param(IS_UART_SYNC_DISABLE(UART_InitStruct->UART_SYNCDisable)); + assert_param(IS_UART_PDC_MODE_LINMR(UART_InitStruct->UART_PDCMode)); + assert_param(IS_UART_DLC(UART_InitStruct->UART_DataLengthControl)); + assert_param(IS_UART_WKUP_TYPE(UART_InitStruct->UART_WkupType)); + assert_param(IS_UART_FRAME_SLOT_DISABLE(UART_InitStruct->UART_FrameSlotDisable)); + assert_param(IS_UART_DATA_LENGTH_MODE(UART_InitStruct->UART_DataLengthMode)); + assert_param(IS_UART_CHECKSUM_TYPE(UART_InitStruct->UART_CheckSumType)); + assert_param(IS_UART_CHECKSUM_DISABLE(UART_InitStruct->UART_CheckSumDisable)); + assert_param(IS_UART_PARITY_DISABLE(UART_InitStruct->UART_ParityDisable)); + assert_param(IS_UART_NODE_ACTIVE(UART_InitStruct->UART_NodeAction)); + } + + /*--------------------------- Enable The Peripheral ------------------------*/ + if (UARTx == UART4) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); + } + else if (UARTx == UART5) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); + } + else if (UARTx == UART7) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART7, ENABLE); + } + else if (UARTx == LPUART) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_LPUART, ENABLE); + } + + /*---------------------- UART and LPUART CR Configuration ------------------*/ + tmpreg = UARTx->CR; + + /* Configure the UART_Mode */ + /* Configure the TXDIS and RXDIS bits */ + UARTx->CR |= ((uint32_t)(CR_CLEAR_MODE_MASK)); + /* Configure the TXEN and RXEN bits */ + tmpreg |= UART_InitStruct->UART_Mode; + + /* Write to UART and LPUART CR */ + UARTx->CR = tmpreg; + + /*---------------------- UART and LPUART MR Configuration ------------------*/ + tmpreg = UARTx->MR; + + /* Normal configuration */ + /* Set the [23:23]_INVDATA ascording to UART_INVData value */ + /* Set the [19:19]_OVER ascording to UART_OverSampling value */ + /* Set the [17:17]_MODE9 ascording to UART_WordLength value */ + /* Set the [16:16]_MSBF ascording to UART_BitOrder value */ + /* Set the [15:14]_CHMODE ascording to UART_ChannelMode value */ + /* Set the [13:12]_NBSTOP ascording to UART_StopBits value */ + /* Set the [11: 9]_PAR ascording to UART_Parity value */ + /* Set the [ 7: 6]_CHRL ascording to UART_WordLength value */ + /* Set the [ 5: 4]_USCLKS ascording to UART_CLKSelect value */ + /* Set the [ 3: 0]_USART_MODE ascording to UART_OperationMode value */ + /* Clear the normal cfg bits */ + tmpreg &= (uint32_t)~((uint32_t)MR_CLEAR_NORMAL_MASK); + /* Configure the normal cfg bits */ + tmpreg |= (uint32_t)UART_InitStruct->UART_INVData | + UART_InitStruct->UART_OverSampling | + UART_InitStruct->UART_WordLength | + UART_InitStruct->UART_BitOrder | + UART_InitStruct->UART_ChannelMode | + UART_InitStruct->UART_StopBits | + UART_InitStruct->UART_Parity | + UART_InitStruct->UART_CLKSelect | + UART_InitStruct->UART_OperationMode ; + + /* Write to UART and LPUART MR */ + UARTx->MR = tmpreg; + + /*---------------------------- USART FIDI Configuration -----------------------*/ + if (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_IrDA) + { + UARTx->FIDI = (uint32_t)UART_InitStruct->UART_FiDiRatio; + } + + /*---------------------- UART and LPUART BRGR Configuration ----------------*/ + tmpreg = UARTx->BRGR; + + /* Configure the UART and LPUART Baud Rate */ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if (UARTx == UART4) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (UARTx == UART5) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (UARTx == UART7) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (UARTx == LPUART) + { + apbclock = RCC_ClocksStatus.LPUARTCLK_Frequency; + } + + /* Determine the integer part and fraction part disable (fractional part can configure in UART_FracDivider_Cfg()) */ + /* BaudRate not equal 0*/ + if ((UART_InitStruct->UART_BaudRate) > 0) + { + /* x16 Oversample in Async mode */ + if (UART_InitStruct->UART_OverSampling == UART_OVERSAMPLING_16) + { + clock_divider = (uint32_t)(((apbclock) / ((UART_InitStruct->UART_BaudRate) * 16))); + frac_divider = 0; + } + /* x8 Oversample in Async mode */ + else if (UART_InitStruct->UART_OverSampling == UART_OVERSAMPLING_8) + { + clock_divider = (uint32_t)(((apbclock) / ((UART_InitStruct->UART_BaudRate) * 8))); + frac_divider = 0; + } + } + /* BaudRate equal 0*/ + else if ((UART_InitStruct->UART_BaudRate) == 0) + { + clock_divider = 0; + frac_divider = 0; + } + + /* Write to UART and LPUART BRGR */ + UARTx->BRGR = (((uint32_t)(clock_divider)) | ((uint32_t)(frac_divider) << 16U)); + + /*---------------------- UART and LPUART IF Configuration -------------------*/ + /* Write to UART and LPUART IF in IrDA mode */ + if (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_IrDA) + { + UARTx->IF = (uint16_t)UART_InitStruct->UART_IrDAFilter; + } + + /*---------------------- UART and LPUART LINMR Configuration ----------------*/ + tmpreg = 0; + + if ((UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_LIN_MASTER) || + (UART_InitStruct->UART_OperationMode == UART_MODE_OPERATION_LIN_SLAVE)) + { + /* Set the [17:17]_SYNCDIS ascording to UART_SYNCDisable value */ + /* Set the [16:16]_PDCM ascording to UART_PDCMode value */ + /* Set the [15: 8]_DLC ascording to UART_DataLengthControl value */ + /* Set the [ 7: 7]_WKUPTYP ascording to UART_WkupType value */ + /* Set the [ 6: 6]_FSDIS ascording to UART_FrameSlotDisable value */ + /* Set the [ 5: 5]_DLM ascording to UART_DataLengthMode value */ + /* Set the [ 4: 4]_CHKTYP ascording to UART_CheckSumType value */ + /* Set the [ 3: 3]_CHKDIS ascording to UART_CheckSumDisable value */ + /* Set the [ 2: 2]_PARDIS ascording to UART_ParityDisable value */ + /* Set the [ 1: 0]_NACT ascording to UART_NodeAction value */ + tmpreg |= (uint32_t)UART_InitStruct-> UART_SYNCDisable | + UART_InitStruct-> UART_PDCMode | + ((UART_InitStruct-> UART_DataLengthControl << (uint32_t)8)) | + UART_InitStruct-> UART_WkupType | + UART_InitStruct-> UART_FrameSlotDisable | + UART_InitStruct-> UART_DataLengthMode | + UART_InitStruct-> UART_CheckSumType | + UART_InitStruct-> UART_CheckSumDisable | + UART_InitStruct-> UART_ParityDisable | + ((UART_InitStruct-> UART_NodeAction << (uint32_t)0)) ; + + /* Write to UART and LPUART LINMR*/ + UARTx->LINMR = tmpreg; + } +} + +/** + * @brief Configure each UART_InitStruct member with its default value. + * @param UART_InitStruct: pointer to a UART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void UART_StructInit(UART_InitTypeDef* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->UART_BaudRate = 9600 ; + UART_InitStruct->UART_FiDiRatio = 174 ; + UART_InitStruct->UART_IrDAFilter = 0 ; + UART_InitStruct->UART_WordLength = UART_CHAR_LENGTH_8BIT ; + UART_InitStruct->UART_StopBits = UART_STOPBITS_1 ; + UART_InitStruct->UART_Parity = UART_PARITY_NONE ; + UART_InitStruct->UART_Mode = UART_MODE_TX | UART_MODE_RX ; + UART_InitStruct->UART_CLKSelect = UART_CLOCK_SELECT_MCK ; + UART_InitStruct->UART_OperationMode = UART_MODE_OPERATION_NORMAL ; + UART_InitStruct->UART_BitOrder = UART_BIT_ORDER_LSBF ; + UART_InitStruct->UART_ChannelMode = UART_CHANNEL_MODE_NORMAL ; + UART_InitStruct->UART_OverSampling = UART_OVERSAMPLING_16 ; + UART_InitStruct->UART_INVData = UART_INVDATA_DISABLE ; + UART_InitStruct->UART_SYNCDisable = UART_SYNC_DISABLE_NONE ; + UART_InitStruct->UART_PDCMode = UART_PDC_MODE_LINMR_NOTWRITE ; + UART_InitStruct->UART_DataLengthControl = 0 ; + UART_InitStruct->UART_WkupType = UART_WKUP_TYPE_LIN_2_0 ; + UART_InitStruct->UART_FrameSlotDisable = UART_FRAME_SLOT_DISABLE_NONE ; + UART_InitStruct->UART_DataLengthMode = UART_DATA_LENGTH_MODE_DLC ; + UART_InitStruct->UART_CheckSumType = UART_CHECKSUM_TYPE_ENHANCED ; + UART_InitStruct->UART_CheckSumDisable = UART_CHECKSUM_DISABLE_NONE ; + UART_InitStruct->UART_ParityDisable = UART_PARITY_DISABLE_NONE ; + UART_InitStruct->UART_NodeAction = UART_NODE_ACTIVE_PUBLISH ; +} + +/** + * @brief De-Initialize the UARTx peripheral to their default reset value. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @retval None + */ +void UART_DeInit(USART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + /* UARTx reset operation */ + if (UARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if (UARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if (UARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); + } + else if (UARTx == LPUART) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_LPUART, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_LPUART, DISABLE); + } +} + +/** + * @} + */ + +/** @defgroup UART and LPUART normal cmd and cfg functions + * @brief UART and LPUART normal command and configuration functions + * +@verbatim + =============================================================================== + ##### Normal Command And Configuration Functions ##### + =============================================================================== + [..] This subsection provides a set of normal command and configuration + function. + + [..] + + (#) The Normal cmd API's : + (++) UART_Cmd() + (++) UART_RSTSTA_Cmd() + (++) UART_TXDIS_Cmd() + (++) UART_TXEN_Cmd() + (++) UART_RXDIS_Cmd() + (++) UART_RXEN_Cmd() + (++) UART_RSTTX_Cmd() + (++) UART_RSTRX_Cmd() + + (#) The Normal cfg API's : + (++) UART_InvData_Cfg() + (++) UART_OverSampling8_Cfg() + (++) UART_DataLength9_Cfg() + (++) UART_MSBFirst_Cfg() + (++) UART_ChannelMode_Cfg() + (++) UART_StopBit_Cfg() + (++) UART_Parity_Cfg() + (++) UART_DataLength_Cfg() + (++) UART_CLKSelect_Cfg() + (++) UART_OperationMode_Cfg() + + (#) The Normal read API's : + (++) None +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified UART peripheral. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void UART_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected UART by setting the UARTxEN bit in the RCC_APB1ENR register */ + if (UARTx == UART4) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, ENABLE); + } + else if (UARTx == UART5) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); + } + else if (UARTx == UART7) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART7, ENABLE); + } + else if (UARTx == LPUART) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_LPUART, ENABLE); + } + } + else + { + /* Disable the selected UART by clearing the UARTxEN bit in the RCC_APB1ENR register */ + if (UARTx == UART4) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if (UARTx == UART5) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if (UARTx == UART7) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART7, DISABLE); + } + else if (UARTx == LPUART) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_LPUART, DISABLE); + } + } +} + +/** + * @brief Reset status bits. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx reset status bits. + * This parameter can be: + * @arg ENABLE : Resets the status bits PARE, FRAME, OVER, LINBE, + * LINISFE, LINIPE, LINCE, LINSNRE, LINSTE, LINHTE, + * LINID, LINTC, LINBK and RXBRK in US_CSR. + * @arg DISABLE: No effect + * @retval None + */ +void UART_RSTSTA_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The status bits reset by setting RSTSTA bit in the CR register */ + UARTx->CR |= USART_CR_RSTSTA; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTSTA); + } +} + +/** + * @brief Transmitter disable. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx transmitter disable. + * This parameter can be: + * @arg ENABLE : Disable the transmitter. + * @arg DISABLE: No effect + * @retval None + */ +void UART_TXDIS_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The transmitter disable by setting TXDIS bit in the CR register */ + UARTx->CR |= USART_CR_TXDIS; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_TXDIS); + } +} + +/** + * @brief Transmitter enable. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx transmitter enable. + * This parameter can be: + * @arg ENABLE : Enable the transmitter if TXDIS is 0. + * @arg DISABLE: No effect + * @retval None + */ +void UART_TXEN_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The transmitter enable by setting TXEN bit in the CR register */ + UARTx->CR |= USART_CR_TXEN; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_TXEN); + } +} + +/** + * @brief Receiver disable. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx receiver disable. + * This parameter can be: + * @arg ENABLE : Disable the receiver. + * @arg DISABLE: No effect + * @retval None + */ +void UART_RXDIS_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The receiver disable by setting RXDIS bit in the CR register */ + UARTx->CR |= USART_CR_RXDIS; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RXDIS); + } +} + +/** + * @brief Receiver enable. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx receiver enable. + * This parameter can be: + * @arg ENABLE : Enable the receiver if RXDIS is 0. + * @arg DISABLE: No effect + * @retval None + */ +void UART_RXEN_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The receiver enable by setting RXEN bit in the CR register */ + UARTx->CR |= USART_CR_RXEN; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RXEN); + } +} + +/** + * @brief Reset transmitter + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx reset transmitter. + * This parameter can be: + * @arg ENABLE : Resets the transmitter. + * @arg DISABLE: No effect + * @retval None + */ +void UART_RSTTX_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The transmitter reset by setting RSTTX bit in the CR register */ + UARTx->CR |= USART_CR_RSTTX; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTTX); + } +} + +/** + * @brief Reset receiver + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx reset receiver. + * This parameter can be: + * @arg ENABLE : Resets the receiver. + * @arg DISABLE: No effect + * @retval None + */ +void UART_RSTRX_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The receiver reset by setting RSTRX bit in the CR register */ + UARTx->CR |= USART_CR_RSTRX; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTRX); + } +} + +/** + * @brief Inverted data + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx inverted data. + * This parameter can be: + * @arg ENABLE : The data field transmitted on TXD line is inverted + * compared to the value writted on US_THR register or + * the content read in US_RHR is inverted compared to + * what is received on TXD line. + * @arg DISABLE: The data field transmitted on TXD line is the same + * as one written in US_THR register or content read in + * US_RHR is the same as RXD line. Normal mode of operation. + * @retval None + */ +void UART_InvData_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the invert data function by setting INVDATA bit in the MR register */ + UARTx->MR |= USART_MR_INVDATA; + } + else + { + /* Disable the invert data function by clearing INVDATA bit in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_INVDATA); + } +} + +/** + * @brief Oversampling mode + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx oversampling mode. + * This parameter can be: + * @arg ENABLE : 8x oversampling. + * @arg DISABLE: 16x oversampling. + * @retval None + */ +void UART_OverSampling8_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x oversampling function by setting OVER bit in the MR register */ + UARTx->MR |= USART_MR_OVER; + } + else + { + /* Disable the 8x oversampling function by clearing OVER bit in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_OVER); + } +} + +/** + * @brief 9-bit character length + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx 9-bit character length. + * This parameter can be: + * @arg ENABLE : 9-bit character length. + * @arg DISABLE: UART_Char_Length defines character length. + * @retval None + */ +void UART_DataLength9_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 9-bit character length by setting MODE9 bit in the MR register */ + UARTx->MR |= USART_MR_MODE9; + } + else + { + /* Disable 9-bit character length by clearing MODE9 bit in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_MODE9); + } +} + +/** + * @brief Bit order + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx bit order. + * This parameter can be: + * @arg ENABLE : Most significant bit is sent/received first. + * @arg DISABLE: Least significant bit is sent/received first. + * @retval None + */ +void UART_MSBFirst_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable most significant bit is sent/received by setting MSBF bit in the MR register */ + UARTx->MR |= USART_MR_MSBF; + } + else + { + /* Enable least significant bit is sent/received by setting MSBF bit in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_MSBF); + } +} + +/** + * @brief Channel mode + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_ChannelMode: channel mode; + * This parameter can be one of the following values: + * UART_CHANNEL_MODE_NORMAL - Normal mode + * UART_CHANNEL_MODE_AUTOMATIC - Automatic mode + * UART_CHANNEL_MODE_LOCAL_LOOPBACK - Local loopback mode + * UART_CHANNEL_MODE_REMOTE_LOOPBACK - Remote loopbak mode + * @retval None + */ +void UART_ChannelMode_Cfg(USART_TypeDef* UARTx, uint32_t UART_ChannelMode) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CHANNEL_MODE(UART_ChannelMode)); + + /* Clear the channel mode by clearing the CHMODE[15:14] bits in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_CHMODE); + + /* Set the channel mode by setting the CHMODE[15:14] bits in the MR register */ + UARTx->MR |= (uint32_t)((uint32_t)UART_ChannelMode); +} + +/** + * @brief Number of stop bits + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_StopBits: number of stop bits, + * This parameter can be one of the following values: + * UART_STOPBITS_1 - 1 stop bit + * UART_STOPBITS_1_5 - 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + * UART_STOPBITS_2 - 2 stop bits + * @retval None + */ +void UART_StopBit_Cfg(USART_TypeDef* UARTx, uint32_t UART_StopBits) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_STOPBITS(UART_StopBits)); + + /* Clear the number of stop bits by clearing the NBSTOP[13:12] bits in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_NBSTOP); + + /* Set the number of stop bits by setting the NBSTOP[13:12] bits in the MR register */ + UARTx->MR |= (uint32_t)((uint32_t)UART_StopBits); +} + +/** + * @brief Parity type + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_Parity: Parity type + * This parameter can be one of the following values: + * UART_PARITY_EVEN - Even parity + * UART_PARITY_ODD - Odd parity + * UART_PARITY_SPACE - Parity forced to 0 (space) + * UART_PARITY_MARK - Parity forced to 1 (mark) + * UART_PARITY_NONE - No parity + * UART_PARITY_MULTIDROP - Multidrop mode + * @retval None + */ +void UART_Parity_Cfg(USART_TypeDef* UARTx, uint32_t UART_Parity) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_PARITY(UART_Parity)); + + /* Clear the parity type by clearing the PAR[11:9] bits in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_PAR); + + /* Set the parity type by setting the PAR[11:9] bits in the MR register */ + UARTx->MR |= (uint32_t)((uint32_t)UART_Parity); +} + +/** + * @brief Character length + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_WordLength: character length + * This parameter can be one of the following values: + * UART_CHAR_LENGTH_5BIT - character length is 5 bits + * UART_CHAR_LENGTH_6BIT - character length is 6 bits + * UART_CHAR_LENGTH_7BIT - character length is 7 bits + * UART_CHAR_LENGTH_8BIT - character length is 8 bits + * @retval None + */ +void UART_DataLength_Cfg(USART_TypeDef* UARTx, uint32_t UART_WordLength) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CHAR_LENGTH(UART_WordLength)); + + /* Clear the character length by clearing the CHRL[7:6] bits in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_CHRL); + + /* Set the character length by setting the CHRL[7:6] bits in the MR register */ + UARTx->MR |= (uint32_t)((uint32_t)UART_WordLength); +} + +/** + * @brief Clock selection + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_CLKSelect: clock selection + * This parameter can be one of the following values: + * UART_CLOCK_SELECT_MCK - MCK + * UART_CLOCK_SELECT_MCKDIV8 - MCK / 8 + * @retval None + */ +void UART_CLKSelect_Cfg(USART_TypeDef* UARTx, uint32_t UART_CLKSelect) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLOCK_SELECT(UART_CLKSelect)); + + /* Clear the clock select by clearing the USCLKS[5:4] bits in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_USCLKS); + + /* Set the clock select by setting the USCLKS[5:4] bits in the MR register */ + UARTx->MR |= (uint32_t)((uint32_t)UART_CLKSelect); +} + +/** + * @brief UART mode of operation + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_OperationMode: UART mode of operation + * This parameter can be one of the following values: + * UART_MODE_OPERATION_NORMAL - Normal mode + * UART_MODE_OPERATION_IrDA - IrDA + * UART_MODE_OPERATION_LIN_MASTER - LIN master + * UART_MODE_OPERATION_LIN_SLAVE - LIN slave + * @retval None + */ +void UART_OperationMode_Cfg(USART_TypeDef* UARTx, uint32_t UART_OperationMode) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_MODE_OPERATION(UART_OperationMode)); + + /* Clear the UART mode of operation by clearing the USART_MODE[3:0] bits in the MR register */ + UARTx->MR &= (uint32_t)~((uint32_t)USART_MR_USART_MODE); + + /* Set the UART mode of operation by setting the USART_MODE[3:0] bits in the MR register */ + UARTx->MR |= (uint32_t)((uint32_t)UART_OperationMode); +} + +/** + * @} + */ + +/** @defgroup UART fractional baudrate function + * @brief UART fractional part of baudrate function + * +@verbatim + =============================================================================== + ##### Fractional Baudrate Functions ##### + =============================================================================== + [..] This subsection provides a function, which can configure fractional part + of baudrate. + + [..] + + (#) The fractional part of baudrate API's : + (++) UART_FracDivider_Cfg() +@endverbatim + * @{ + */ + +/** + * @brief UART fractional part of BaudRate + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param UART_BaudRate: user confige baudrate + * @note This function has to be called after calling UART_Init() function + * in order to have correct fractional part baudrate Divider value. + * @retval None + */ +void UART_FracDivider_Cfg(USART_TypeDef* UARTx, uint32_t UART_BaudRate) +{ + double clock_divider = 0, frac_divider = 0, apbclock = 0; + + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_UART_BAUDRATE(UART_BaudRate)); + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + /* Get UARTx work clock*/ + apbclock = RCC_ClocksStatus.PCLK_Frequency; + + /* BaudRate not equal 0*/ + if (UART_BaudRate > 0) + { + /* Async mode x16 Oversample*/ + if (((UARTx->MR)&USART_MR_OVER) == UART_OVERSAMPLING_16) + { + clock_divider = (uint32_t)(((apbclock) / ((UART_BaudRate) * 16))); + frac_divider = (uint32_t)(((apbclock) / ((UART_BaudRate) * 16) - clock_divider) * 8); + } + /* Async mode x8 Oversample*/ + if (((UARTx->MR)&USART_MR_OVER) == UART_OVERSAMPLING_8) + { + clock_divider = (uint32_t)(((apbclock) / ((UART_BaudRate) * 8))); + frac_divider = (uint32_t)(((apbclock) / ((UART_BaudRate) * 8) - clock_divider) * 8); + } + } + + /* Clear the UART fractional part by clearing the FP[18:16] bits in the BRGR register */ + UARTx->BRGR &= (uint32_t)~((uint32_t)USART_BRGR_FP); + + /* Set the UART fractional part by setting the FP[18:16] bits in the BRGR register */ + UARTx->BRGR |= (((uint32_t)frac_divider) << 16U); +} + +/** + * @} + */ + +/** @defgroup UART and LPUART BREAK command functions + * @brief None + * +@verbatim + =============================================================================== + ##### Break Command Functions ##### + =============================================================================== + [..] This subsection provides a set of BREAK command functions. + + [..] + + (#) The stop break command API's : + (++) UART_STPBRK_Cmd() + + (#) The start break command API's : + (++) UART_STTBRK_Cmd() +@endverbatim + * @{ + */ + +/** + * @brief Stop break. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx stop break. + * This parameter can be: + * @arg ENABLE : Stops transmission of break after a minimum of one character length and + * transmits a high level during 12-bit periods. + * @arg DISABLE: No effect + * @retval None + */ +void UART_STPBRK_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Stops transmission of break after a minimum of one character by setting + STPBRK bit in the CR register */ + UARTx->CR |= USART_CR_STPBRK; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_STPBRK); + } +} + +/** + * @brief Start break. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx start break. + * This parameter can be: + * @arg ENABLE : Starts transmission of break after the character present in US_THR and + * the transmit shift register have been transmitted. No effect if a break + * is already being transmitted. + * @arg DISABLE: No effect + * @retval None + */ +void UART_STTBRK_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Starts transmission of break after the characters present in US_THR and the transmit + shift register have been transmitted by setting STTBRK bit in the CR register */ + UARTx->CR |= USART_CR_STTBRK; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_STTBRK); + } +} + +/** + * @} + */ + +/** @defgroup UART receiver time-out and transmitter timeguard functions + * @brief Receiver time-out cfg and cmd functions. + * Transmitter timeguard cfg function. + * +@verbatim + =============================================================================== + ##### Receiver Time-out And Transmitter Timeguard Functions ##### + =============================================================================== + [..] This subsection provides a set of receiver time-out and transmitter + timeguard functions. + + [..] + + (#) The receiver time-out cfg API's : + (++) UART_Receiver_TimeOut_Cfg() + + (#) The receiver time-out cmd API's : + (++) UART_RETTO_After_Timeout_Cmd() + (++) UART_STTTO_After_Timeout_Cmd() + + (#) The transmitter timeguard cfg API's : + (++) UART_Transmitter_TimeGuard_Cfg() +@endverbatim + * @{ + */ + +/** + * @brief Receiver time-out value + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param UART_ReceiverTimeOut: Time-out value + * 0 : The receiver time-out is disabled. + * 1 - 65535 : The receiver time-out is enabled and time-out + * delay is TO * bit period. + * 1 - 131071: The receiver time-out is enabled and time-out + * delay is TO * bit period. + * @note This function has to be called before calling UART_Init() function + * in order to have correct receiver time-out value. + * @retval None + */ +void UART_Receiver_TimeOut_Cfg(USART_TypeDef* UARTx, uint32_t UART_ReceiverTimeOut) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_UART_TIMEOUT(UART_ReceiverTimeOut)); + + /* Clear the time-out value of receiver by clearing the TO[16:0] bits in the RTOR register */ + UARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_TO); + + /* Set the time-out value of receiver setting the TO[16:0] bits in the RTOR register */ + UARTx->RTOR |= (uint32_t)((uint32_t)UART_ReceiverTimeOut); +} + +/** + * @brief Rearm Time-out. + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx rearm Time-out. + * This parameter can be: + * @arg ENABLE : Restart Time-out + * @arg DISABLE: No effect + * @retval None + */ +void UART_RETTO_After_Timeout_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Restart time-out by setting RETTO bit in the CR register */ + UARTx->CR |= USART_CR_RETTO; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RETTO); + } +} + +/** + * @brief Start time-out. + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx start time-out. + * This parameter can be: + * @arg ENABLE : Starts waiting for a character before clocking the time-out counter. + * Resets the status bit TIMEOUT in US_CSR. + * @arg DISABLE: No effect + * @retval None + */ +void UART_STTTO_After_Timeout_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Starts waiting for a character before clocking the time-out counter by setting + STTTO bit in the CR register */ + UARTx->CR |= USART_CR_STTTO; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_STTTO); + } +} + +/** + * @brief Transmitter timeguard value + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param UART_TransmitterTimeGuard: timeguard value + * 0 : The transmitter timeguard value is disabled. + * 1 - 255: The transmitter timeguard is enabled and the + * timeguard delay is TG * bit period. + * @note This function has to be called before calling UART_Init() function + * in order to have correct transmitter timeguard value. + * @retval None + */ +void UART_Transmitter_TimeGuard_Cfg(USART_TypeDef* UARTx, uint32_t UART_TransmitterTimeGuard) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_UART_TIMGUARD(UART_TransmitterTimeGuard)); + + /* Clear the timeguard value of transmitter by clearing the TG[7:0] bits in the TTGR register */ + UARTx->TTGR &= (uint32_t)~((uint32_t)USART_TTGR_TG); + + /* Set the timeguard value of transmitter setting the TG[7:0] bits in the TTGR register */ + UARTx->TTGR |= (uint32_t)((uint32_t)UART_TransmitterTimeGuard); +} + +/** + * @} + */ + +/** @defgroup UART and LPUART multidrop mode cmd function + * @brief Multidrop mode command function. + * +@verbatim + =============================================================================== + ##### Multidrop Mode Command Function ##### + =============================================================================== + [..] This subsection provides the multidrop mode command function. + + [..] + + (#) The multidrop mode command API's : + (++) UART_SENDAInMultidropMode_Cmd() + +@endverbatim + * @{ + */ + +/** + * @brief Send address. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx send address. + * This parameter can be: + * @arg ENABLE : In multidrop mode only, the next character written to + * the US_THR is sent with address bit set. + * @arg DISABLE: No effect + * @retval None + */ +void UART_SENDAInMultidropMode_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* In multidrop mode only, the next character writted to the US_THR is sent with + address bit set by setting SENDA bit in the CR register */ + UARTx->CR |= USART_CR_SENDA; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_SENDA); + } +} + +/** + * @} + */ + +/** @defgroup UART IrDA mode cfg functions + * @brief UART IrDA mode mode configuration function + * +@verbatim + =============================================================================== + ##### IrDA Mode Functions ##### + =============================================================================== + [..] This subsection provides a IrDA mode function. + + [..] + + (#) The IrDA mode cfg API's : + (++) UART_IrDAFilter_Cfg() + +@endverbatim + * @{ + */ + +/** + * @brief IrDA Filter + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param UART_IrDAFilter: The IRDA_FILTER value must be defined to meet the + * following criteria: + * tMCK * (IDA_FILTER + 3) < 1.41us + * @retval None + */ +void UART_IrDAFilter_Cfg(USART_TypeDef* UARTx, uint32_t UART_IrDAFilter) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_UART_IF(UART_IrDAFilter)); + + /* Clear the IrDA filter value by clearing the IRDA_FILTER[7:0] bits in the IF register */ + UARTx->IF &= (uint32_t)~((uint32_t)USART_IF_IRDA_FILTER); + + /* Set the IrDA filter value by setting the IRDA_FILTER[7:0] bits in the IF register */ + UARTx->IF |= (uint32_t)((uint32_t)UART_IrDAFilter); +} + +/** + * @} + */ + +/** @defgroup UART LIN mode cmd, cfg, and read functions + * @brief UART LIN mode mode command, configuration and read functions + * +@verbatim + =============================================================================== + ##### LIN Mode Functions ##### + =============================================================================== + [..] This subsection provides a set of LIN mode functions. + + [..] + + (#) The LIN mode cmd API's : + (++) UART_LINWKUP_Cmd() + (++) UART_LINABT_Cmd() + + (#) The LIN mode cfg API's : + (++) UART_Write_LINIR_In_LIN_Master() + (++) UART_SYNCDisable_Cfg() + (++) UART_PDCMode_Cfg() + (++) UART_DataLengthControl_Cfg() + (++) UART_WkupType_Cfg() + (++) UART_FrameSlotDisable_Cfg() + (++) UART_DataLengthMode_Cfg() + (++) UART_CheckSumType_Cfg() + (++) UART_CheckSumDisable_Cfg() + (++) UART_ParityDisable_Cfg() + (++) UART_NodeAction_Cfg() + + (#) The LIN mode read API's : + (++) UART_Read_LINIR_In_LIN_Slave() + (++) UART_LINBaudRate() +@endverbatim + * @{ + */ + +/** + * @brief Send LIN Wakeup Signal. + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx send LIN wakeup signal. + * This parameter can be: + * @arg ENABLE : Sends a wakeup signal on LIN bus + * @arg DISABLE: No effect + * @retval None + */ +void UART_LINWKUP_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Send a wakeup signal on LIN bus by setting LINWKUP bit in the CR register */ + UARTx->CR |= USART_CR_LINWKUP; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_LINWKUP); + } +} + +/** + * @brief Abort LIN Transmission. + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx abort LIN transmission. + * This parameter can be: + * @arg ENABLE : Abort LIN transmission + * @arg DISABLE: No effect + * @retval None + */ +void UART_LINABT_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Abort LIN transmission by setting LINABT bit in the CR register */ + UARTx->CR |= USART_CR_LINABT; + } + else + { + /* No effect */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_LINABT); + } +} + +/** + * @brief Write identifier character in LIN master mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param UART_LINIR_Data: if UART_OperationMode = 0xA (Master node configure), + * UART_LINIR_Data is read-write and its value is the + * identifier character to be transmitted. + * @note This function has to be called after calling UART_Init() function + * in order to have correct identifer value in LIN master mode. + * @retval None + */ +void UART_Write_LINIR_In_LIN_Master(USART_TypeDef* UARTx, uint32_t UART_LINIR_Data) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_UART_LINIR_WR(UART_LINIR_Data)); + + /* Clear the identifier value to be transmitted in LIN master node by clearing + the IDCHR[7:0] bits in the LINIR register */ + UARTx->LINIR &= (uint32_t)~((uint32_t)USART_LINIR_IDCHR); + + /* Set the identifier value to be transmitted in LIN master node by setting + the IDCHR[7:0] bits in the LINIR register */ + UARTx->LINIR |= (uint32_t)((uint32_t)UART_LINIR_Data); +} + +/** + * @brief Synchronization disable in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN synchronization disable, + * applicable if UART operates in LIN mode. + * This parameter can be: + * @arg ENABLE : The synchronization procedure is not performed in LIN + * slave node configure. + * @arg DISABLE: The synchronization procedure is performed in LIN + * slave node configure. + * @retval None + */ +void UART_SYNCDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the synchronization procedure's disable by setting SYNCDIS bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_SYNCDIS; + } + else + { + /* Disable the synchronization procedure's disable by clearing SYNCDIS bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_SYNCDIS); + } +} + +/** + * @brief DMA mode in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN DMA mode, applicable if UART + * operates in LIN mode. + * This parameter can be: + * @arg ENABLE : The LIN mode register US_LINMR (excepting that flag) + * is written by the DMA. + * @arg DISABLE: The LIN mode register US_LINMR is not written by the DMA. + * @retval None + */ +void UART_PDCMode_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA written of LINMR by setting PDCM bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_PDCM; + } + else + { + /* Disable the DMA written of LINMR by clearing PDCM bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_PDCM); + } +} + +/** + * @brief Data length control in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param UART_DataLengthControl: (0 - 255) Defines the response data length + * if UART_DataLengthMode = 0, in that case + * the response data length is equal to + * UART_DataLengthControl + 1 bytes; + * @retval None + */ +void UART_DataLengthControl_Cfg(USART_TypeDef* UARTx, uint32_t UART_DataLengthControl) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_UART_DLC(UART_DataLengthControl)); + + /* Clear the response data length value of LIN mode (UART_DataLengthMode = 0) + by clearing the DLC[15:8] bits in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_DLC); + + /* Set the response data length value of LIN mode (UART_DataLengthMode = 0) + by setting the DLC[15:8] bits in the LINMR register */ + UARTx->LINMR |= (uint32_t)((uint32_t)UART_DataLengthControl << 8U); +} + +/** + * @brief Wakeup signal type in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN wakeup signal type. + * This parameter can be: + * @arg ENABLE : Setting the bit LINWKUP in the control register send + * a LIN 1.3 wakeup signal. + * @arg DISABLE: Setting the bit LINWKUP in the control register send + * a LIN 2.0 wakeup signal. + * @retval None + */ +void UART_WkupType_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN 1.3 wakeup signal as the wakeup type to send by setting WKUPTYP + bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_WKUPTYP; + } + else + { + /* Disable the LIN 1.3 wakeup signal as the wakeup type to send by clearing WKUPTYP + bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_WKUPTYP); + } +} + +/** + * @brief Frame slot mode disable in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN frame slot mode disable. + * This parameter can be: + * @arg ENABLE : The frame slot mode is disabled. + * @arg DISABLE: The frame slot mode is enabled. + * @retval None + */ +void UART_FrameSlotDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the frame slot mode's disable by setting FSDIS bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_FSDIS; + } + else + { + /* Disable the frame slot mode's disable by clearing FSDIS bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_FSDIS); + } +} + +/** + * @brief Data length mode in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN data length mode. + * This parameter can be: + * @arg ENABLE : The response data length is defined by the bits 5 + * and 6 of the identifier (IDCHR in US_LINIR). + * @arg DISABLE: The response data length is defined by the field + * DLC of US_LINMR register. + * @retval None + */ +void UART_DataLengthMode_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the response data length is defined by the bits 5 and 6 of the identifier + (IDCHR in US_LINIR) by setting DLM bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_DLM; + } + else + { + /* Disable the response data length is defined by the bits 5 and 6 of the identifier + (IDCHR in US_LINIR) by clearing DLM bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_DLM); + } +} + +/** + * @brief Checksum type in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN checksum type. + * This parameter can be: + * @arg ENABLE : LIN 1.3 "Classic" checksum. + * @arg DISABLE: LIN 2.0 "Enhanced" checksum. + * @retval None + */ +void UART_CheckSumType_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN 1.3 "Classic" checksum type by setting CHKTYP bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_CHKTYP; + } + else + { + /* Disable the LIN 1.3 "Classic" checksum type by clearing CHKTYP bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_CHKTYP); + } +} + +/** + * @brief Checksum disable in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN checksum disable. + * This parameter can be: + * @arg ENABLE : Whatever the node configuration is, the checksum is + * not computed/sent and it is not checked. + * @arg DISABLE: In Master node configuration, the cheksum is computed + * and sent automatically. In Slave node configure, the + * checksum is checked automatically. + * @retval None + */ +void UART_CheckSumDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the checksum's disable by setting CHKDIS bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_CHKDIS; + } + else + { + /* Disable the checksum's disable by clearing CHKDIS bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_CHKDIS); + } +} + +/** + * @brief Parity disable in LIN mode + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param NewState: new state of the UARTx LIN parity disable. + * This parameter can be: + * @arg ENABLE : Whatever the node configuration is, the identifier + * parity is not computed/sent and it is not checked. + * @arg DISABLE: In Master node configuration, the identifier parity + * is computed and sent automatically. In Master node + * and Slave node configuration, the parity is checked + * automatically. + * @retval None + */ +void UART_ParityDisable_Cfg(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the identifier parity's disable by setting PARDIS bit in the LINMR register */ + UARTx->LINMR |= USART_LINMR_PARDIS; + } + else + { + /* Disable the identifier parity's disable by clearing PARDIS bit in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_PARDIS); + } +} + +/** + * @brief LIN node action + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @param UART_NodeAction: LIN node action + * This parameter can be one of the following values: + * UART_NODE_ACTIVE_PUBLISH - PUBLISH ; The UART transmits the response. + * UART_NODE_ACTIVE_SUBSCRIBE - SUBSCRIBE; The UART receives the response. + * UART_NODE_ACTIVE_IGNORE - IGNORE ; The UART does not transmits and + * does not receives the response. + * @retval None + */ +void UART_NodeAction_Cfg(USART_TypeDef* UARTx, uint32_t UART_NodeAction) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + assert_param(IS_UART_NODE_ACTIVE(UART_NodeAction)); + + /* Clear the LIN node action by clearing the NACT[1:0] bits in the LINMR register */ + UARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_NACT); + + /* Set the LIN node action by setting the NACT[1:0] bits in the LINMR register */ + UARTx->LINMR |= (uint32_t)((uint32_t)UART_NodeAction); +} + +/** + * @brief Returns the identifier character by the UARTx peripheral. + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @note If UART_OperationMode = 0xB (Slave node configuration), IDCHR[7:0] + * in US_LINIR is read-only and its value is the last identifier character + * that has been received. + * @retval The last identifier character. + */ +uint32_t UART_Read_LINIR_In_LIN_Slave(USART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + + /* Return the last identifier character if operation in slave node configuration*/ + return (uint32_t)((UARTx->LINIR)); +} + +/** + * @brief Returns the baud rate value after the synchronization process completion + * by the UARTx peripheral. + * @param UARTx: Select UART peripheral from among UART4, UART5 and UART7 (Except LPUART). + * @note The return value [18:16] bits is LINFP[18:16], which means fractional part + * after synchronization. + * @note The return value [15: 0] bits is LINCD[15: 0], which means clock driver + * after synchronization. + * @retval The baud rate value after the synchronization process completion. + */ +uint32_t UART_LINBaudRate(USART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_457_PERIPH(UARTx)); + + /* Return the baud rate value after the synchronization process completion */ + return (uint32_t)((UARTx->LINBRR)); +} + +/** + * @} + */ + +/** @defgroup UART and LPUART Transfers functions + * @brief UART and LPUART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### Data Transfers Functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART + and LPUART data transfers. + + [..] + + (#) The UART and LPUART data transmit API's : + (++) UART_Transmit() + + (#) The UART and LPUART data receive API's : + (++) UART_Receive() +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the UARTx peripheral. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param Data: the data to transmit. + * @retval None + */ +void UART_Transmit(USART_TypeDef* UARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_DATA(Data)); + + /* Transmit Data */ + UARTx->THR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the UARTx peripheral. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @retval The received data. + */ +uint16_t UART_Receive(USART_TypeDef* UARTx) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + + /* Received Data */ + return (uint16_t)(UARTx->RHR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup UART and LPUART DMA Transfers functions + * @brief UART and LPUART DMA Transmit and Receive enable functions + * +@verbatim + =============================================================================== + ##### DMA Transfer Management Functions ##### + =============================================================================== + [..] This subsection provides a set of functions about DMA Tx/Rx enable functions. + + [..] + + (#) The UART and LPUART DMA enable transmitter API's : + (++) UART_DMATxEnable_Cmd() + + (#) The UART and LPUART DMA enable receiver API's : + (++) UART_DMARxEnable_Cmd() +@endverbatim + * @{ + */ + +/** + * @brief DMA enable transmitter + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx DMA enable transmitter. + * This parameter can be: + * @arg ENABLE : DMA mode is enable for transmission. + * @arg DISABLE: DMA mode is disable for transmission. + * @retval None + */ +void UART_DMATxEnable_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the transmission function of DMA mode by setting DMAT bit in the CR register */ + UARTx->CR |= USART_CR_DMAT_EN; + } + else + { + /* Disable the transmission function of DMA mode by clearing DMAT bit in the CR register */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_DMAT_EN); + } +} + +/** + * @brief DMA enable receiver + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx DMA enable receiver. + * This parameter can be: + * @arg ENABLE : DMA mode is enable for reception. + * @arg DISABLE: DMA mode is disable for reception. + * @retval None + */ +void UART_DMARxEnable_Cmd(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the reception function of DMA mode by setting DMAR bit in the CR register */ + UARTx->CR |= USART_CR_DMAR_EN; + } + else + { + /* Disable the reception function of DMA mode by clearing DMAR bit in the CR register */ + UARTx->CR &= (uint32_t)~((uint32_t)USART_CR_DMAR_EN); + } +} + +/** + * @} + */ + +/** @defgroup UART and LPUART low-power management functions + * @brief UART low-power sleep wakeup functions + * LPUART low-power sleep or stop wakeup functions + * +@verbatim + =============================================================================== + ##### Low-Power SLEEP and STOP Wakeup Management Functions ##### + =============================================================================== + [..] This subsection provides a set of functions about UART and LPUART + low-power wakeup management functions. + + [..] + + (#) The UART and LPUART Low-Power SLEEP wakeup configurations API's : + (++) UART_LowPowerSleepWkupConfig() + + (#) The LPUART Low-Power STOP wakeup configurations API's : + (++) LPUART_LowPowerStopWkupConfig() +@endverbatim + * @{ + */ + +/** + * @brief UART and LPUART Low-Power SLEEP wakeup configurations + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param NewState: new state of the UARTx Low-Power SLEEP wakeup configurations. + * This parameter can be: + * @arg ENABLE : Enable UARTx module clock in SLEEP mode. + * @arg DISABLE: Disable UARTx module clock in SLEEP mode. + * @retval None + */ +void UART_LowPowerSleepWkupConfig(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (UARTx == UART4) + { + if (NewState != DISABLE) + { + /* Enable the UART4 module clock in SLEEP mode by setting UART4LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART4, ENABLE); + } + else + { + /* Disable the UART4 module clock in SLEEP mode by clearing UART4LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART4, DISABLE); + } + } + else if (UARTx == UART5) + { + if (NewState != DISABLE) + { + /* Enable the UART5 module clock in SLEEP mode by setting UART5LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART5, ENABLE); + } + else + { + /* Disable the UART5 module clock in SLEEP mode by clearing UART5LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART5, DISABLE); + } + } + else if (UARTx == UART7) + { + if (NewState != DISABLE) + { + /* Enable the UART7 module clock in SLEEP mode by setting UART7LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART7, ENABLE); + } + else + { + /* Disable the UART7 module clock in SLEEP mode by clearing UART7LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART7, DISABLE); + } + } + else if (UARTx == LPUART) + { + if (NewState != DISABLE) + { + /* Enable the LPUART module clock in SLEEP mode by setting LPUARTLPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_LPUART, ENABLE); + } + else + { + /* Disable the LPUART module clock in SLEEP mode by clearing LPUARTLPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_LPUART, DISABLE); + } + } +} + +/** + * @brief LPUART Low-Power STOP wakeup configurations + * @param UARTx: UART peripheral only for LPUART. + * @param NewState: new state of the LPUART Low-Power STOP wakeup configurations. + * This parameter can be: + * @arg ENABLE : LSE as LPUART clock in STOP mode. + * @arg DISABLE: PCLK as LPUART clock in STOP mode. + * @retval None + */ +void LPUART_LowPowerStopWkupConfig(USART_TypeDef* UARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_LP_PERIPH(UARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* LSE as LPUART clock in STOP mode by setting LPUARTSEL bit in the RCC_CCIPR register */ + RCC_LPUARTCLKConfig(RCC_LPUARTCLK_LSE); + } + else + { + /* PCLK as LPUART clock in STOP mode by clearing LPUARTSEL bit in the RCC_CCIPR register */ + RCC_LPUARTCLKConfig(RCC_LPUARTCLK_PCLK); + } +} + +/** + * @} + */ + +/** @defgroup UART and LPUART Transfers functions + * @brief UART and LPUART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### Interrupts And Flags Management Functions ##### + =============================================================================== + [..] This subsection provides a set of functions, which is about the UART + and LPUART interrupts and the flags management. + + [..] + + (#) The UART and LPUART interrupts enable API's : + (++) UART_ITConfig() + + (#) The UART and LPUART flags status check API's : + (++) UART_GetFlagStatus() + + (#) The UART and LPUART flags clear API's : + (++) UART_ClearFlag() + + (#) The UART and LPUART interrupt mask check API's : + (++) UART_GetITStatus() + + (#) The UART and LPUART interrupt disable API's : + (++) UART_ITDisableConfig() +@endverbatim + * @{ + */ + +/** + * @brief Enables the specified UART and LPUART interrupts. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_IT: specifies the UART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg UART_IT_TXEMPTY: UART transmitter empty interruption + * @arg UART_IT_TIMEOUT: UART receiver time-out interruption + * @arg UART_IT_PARE : UART parity error interruption + * @arg UART_IT_FRAME : UART framing error interruption + * @arg UART_IT_OVER : UART overrun error interruption + * @arg UART_IT_RXBRK : UART break receive/end of break interruption + * @arg UART_IT_TXRDY : UART transmitter ready interruption + * @arg UART_IT_RXRDY : UART receiver ready interruption + * @arg UART_IT_LINHTE : UART LIN header timeout error interruption + * @arg UART_IT_LINSTE : UART LIN synch tolerance eror interruption + * @arg UART_IT_LINSNRE: UART LIN slave not response error interruption + * @arg UART_IT_LINCE : UART LIN checksum error interruption + * @arg UART_IT_LINIPE : UART LIN identifier parity error interruption + * @arg UART_IT_LINISFE: UART LIN inconsistent synch field error interruption + * @arg UART_IT_LINBE : UART LIN bit error interruption + * @arg UART_IT_LINTC : UART LIN transfer completed interruption + * @arg UART_IT_LINID : UART LIN identifier sent or LIN identifier received interruption + * @arg UART_IT_LINBK : UART LIN break sent or LIN break received interruption + * The following values are only available for UART4, UART5 and UART7, not for LPUART: + * @arg UART_IT_TIMEOUT + * @arg UART_IT_LINHTE + * @arg UART_IT_LINSTE + * @arg UART_IT_LINSNRE + * @arg UART_IT_LINCE + * @arg UART_IT_LINIPE + * @arg UART_IT_LINISFE + * @arg UART_IT_LINBE + * @arg UART_IT_LINTC + * @arg UART_IT_LINID + * @arg UART_IT_LINBK + * @param NewState: new state of the specified UARTx interrupts. + * This parameter can be: + * @arg ENABLE : Enable corresponding interrupt. + * @arg DISABLE: No effect. + * @retval None + * @retval None + */ +void UART_ITConfig(USART_TypeDef* UARTx, uint32_t UART_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_ENABLE_IT(UART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + UARTx->IER |= (uint32_t)((uint32_t)UART_IT); + } + else + { + UARTx->IER &= (uint32_t)~((uint32_t)UART_IT); + } +} + +/** + * @brief Checks whether the specified UART flag is set or not. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg UART_FLAG_TXEMPTY: transmitter empty + * @arg UART_FLAG_TIMEOUT: receiver time-out + * @arg UART_FLAG_PARE : parity error + * @arg UART_FLAG_FRAME : framing error + * @arg UART_FLAG_OVER : overrun error + * @arg UART_FLAG_RXBRK : break receive/end of break + * @arg UART_FLAG_TXRDY : transmitter ready + * @arg UART_FLAG_RXRDY : receiver ready + * @arg UART_FLAG_LINHTE : LIN header timeout error + * @arg UART_FLAG_LINSTE : LIN synch tolerance eror + * @arg UART_FLAG_LINSNRE: LIN slave not response error + * @arg UART_FLAG_LINCE : LIN checksum error + * @arg UART_FLAG_LINIPE : LIN identifier parity error + * @arg UART_FLAG_LINISFE: LIN inconsistent synch field error + * @arg UART_FLAG_LINBE : LIN bit error + * @arg UART_FLAG_LINBLS : LIN bus line status + * @arg UART_FLAG_LINTC : LIN transfer completed + * @arg UART_FLAG_LINID : LIN identifier sent or LIN identifier received + * @arg UART_FLAG_LINBK : LIN break sent or LIN break received + * The following values are only available for UART4, UART5 and UART7, not for LPUART: + * @arg UART_FLAG_TIMEOUT + * @arg UART_FLAG_LINHTE + * @arg UART_FLAG_LINSTE + * @arg UART_FLAG_LINSNRE + * @arg UART_FLAG_LINCE + * @arg UART_FLAG_LINIPE + * @arg UART_FLAG_LINISFE + * @arg UART_FLAG_LINBE + * @arg UART_FLAG_LINBLS + * @arg UART_FLAG_LINTC + * @arg UART_FLAG_LINID + * @arg UART_FLAG_LINBK + * @retval The new state of UART_FLAG (SET or RESET). + */ +FlagStatus UART_GetFlagStatus(USART_TypeDef* UARTx, uint32_t UART_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_GET_FLAG(UART_FLAG)); + + if ((UARTx->CSR & UART_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the UARTx's pending flags. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg UART_CLEAR_TXEMPTY: transmitter empty interrupt clear + * @arg UART_CLEAR_TIMEOUT: receiver time-out interrupt clear + * @arg UART_CLEAR_PARE : parity error interrupt clear + * @arg UART_CLEAR_FRAME : framing error interrupt clear + * @arg UART_CLEAR_OVER : overrun error interrupt clear + * @arg UART_CLEAR_RXBRK : break receive/end of break interrupt clear + * @arg UART_CLEAR_TXRDY : transmitter ready interrupt clear + * @arg UART_CLEAR_RXRDY : receiver ready interrupt clear + * @arg UART_CLEAR_LINHTE : LIN header timeout error interrupt clear + * @arg UART_CLEAR_LINSTE : LIN synch tolerance eror interrupt clear + * @arg UART_CLEAR_LINSNRE: LIN slave not response error interrupt clear + * @arg UART_CLEAR_LINCE : LIN checksum error interrupt clear + * @arg UART_CLEAR_LINIPE : LIN identifier parity error interrupt clear + * @arg UART_CLEAR_LINISFE: LIN inconsistent synch field error interrupt clear + * @arg UART_CLEAR_LINBE : LIN bit error interrupt clear + * @arg UART_CLEAR_LINTC : LIN transfer completed interrupt clear + * @arg UART_CLEAR_LINID : LIN identifier sent or LIN identifier received interrupt clear + * @arg UART_CLEAR_LINBK : LIN break sent or LIN break received interrupt clear + * The following values are only available for UART4, UART5 and UART7, not for LPUART: + * @arg UART_CLEAR_TIMEOUT + * @arg UART_CLEAR_LINHTE + * @arg UART_CLEAR_LINSTE + * @arg UART_CLEAR_LINSNRE + * @arg UART_CLEAR_LINCE + * @arg UART_CLEAR_LINIPE + * @arg UART_CLEAR_LINISFE + * @arg UART_CLEAR_LINBE + * @arg UART_CLEAR_LINTC + * @arg UART_CLEAR_LINID + * @arg UART_CLEAR_LINBK + * @note LINBLS LIN bus line status bit is cleared when LINRX pin is 0. + * @note TXEMPTY flag bit also can be cleared by a write to the US_THR register (UART_Transmit()). + * @note TXRDY flag bit also can be cleared by a write to the US_THR register (UART_Transmit()). + * @note RXRDY flag bit also can be cleared by a read to the US_RHR register (UART_Receive()). + * @retval None + */ +void UART_ClearFlag(USART_TypeDef* UARTx, uint32_t UART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLEAR_FLAG(UART_FLAG)); + + UARTx->CR |= (uint32_t)UART_FLAG; +} + +/** + * @brief Checks whether the specified UART interrupt has enabled or disabled. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_IT: specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg UART_MASK_TXEMPTY: transmitter empty interrupt mask + * @arg UART_MASK_TIMEOUT: receiver time-out interrupt mask + * @arg UART_MASK_PARE : parity error interrupt mask + * @arg UART_MASK_FRAME : framing error interrupt mask + * @arg UART_MASK_OVER : overrun error interrupt mask + * @arg UART_MASK_RXBRK : break receive/end of break interrupt mask + * @arg UART_MASK_TXRDY : transmitter ready interrupt mask + * @arg UART_MASK_RXRDY : receiver ready interrupt mask + * @arg UART_MASK_LINHTE : LIN header timeout error interrupt mask + * @arg UART_MASK_LINSTE : LIN synch tolerance eror interrupt mask + * @arg UART_MASK_LINSNRE: LIN slave not response error interrupt mask + * @arg UART_MASK_LINCE : LIN checksum error interrupt mask + * @arg UART_MASK_LINIPE : LIN identifier parity error interrupt mask + * @arg UART_MASK_LINISFE: LIN inconsistent synch field error interrupt mask + * @arg UART_MASK_LINBE : LIN bit error interrupt mask + * @arg UART_MASK_LINTC : LIN transfer completed interrupt mask + * @arg UART_MASK_LINID : LIN identifier sent or LIN identifier received interrupt mask + * @arg UART_MASK_LINBK : LIN break sent or LIN break received interrupt mask + * The following values are only available for UART4, UART5 and UART7, not for LPUART: + * @arg UART_MASK_TIMEOUT + * @arg UART_MASK_LINHTE + * @arg UART_MASK_LINSTE + * @arg UART_MASK_LINSNRE + * @arg UART_MASK_LINCE + * @arg UART_MASK_LINIPE + * @arg UART_MASK_LINISFE + * @arg UART_MASK_LINBE + * @arg UART_MASK_LINTC + * @arg UART_MASK_LINID + * @arg UART_MASK_LINBK + * @retval The new state of UART_IT (SET or RESET). + */ +ITStatus UART_GetITStatus(USART_TypeDef* UARTx, uint32_t UART_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_GET_IT(UART_IT)); + + if ((UARTx->IMR & UART_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief UARTx's interrupt disable configure. + * @param UARTx: Select UART peripheral from among UART4, UART5, UART7 and LPUART. + * @param UART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg UART_DIS_TXEMPTY: transmitter empty interrupt disable + * @arg UART_DIS_TIMEOUT: receiver time-out interrupt disable + * @arg UART_DIS_PARE : parity error interrupt disable + * @arg UART_DIS_FRAME : framing error interrupt disable + * @arg UART_DIS_OVER : overrun error interrupt disable + * @arg UART_DIS_RXBRK : break receive/end of break interrupt disable + * @arg UART_DIS_TXRDY : transmitter ready interrupt disable + * @arg UART_DIS_RXRDY : receiver ready interrupt disable + * @arg UART_DIS_LINHTE : LIN header timeout error interrupt disable + * @arg UART_DIS_LINSTE : LIN synch tolerance eror interrupt disable + * @arg UART_DIS_LINSNRE: LIN slave not response error interrupt disable + * @arg UART_DIS_LINCE : LIN checksum error interrupt disable + * @arg UART_DIS_LINIPE : LIN identifier parity error interrupt disable + * @arg UART_DIS_LINISFE: LIN inconsistent synch field error interrupt disable + * @arg UART_DIS_LINBE : LIN bit error interrupt disable + * @arg UART_DIS_LINTC : LIN transfer completed interrupt disable + * @arg UART_DIS_LINID : LIN identifier sent or LIN identifier received interrupt disable + * @arg UART_DIS_LINBK : LIN break sent or LIN break received interrupt disable + * The following values are only available for UART4, UART5 and UART7, not for LPUART: + * @arg UART_DIS_TIMEOUT + * @arg UART_DIS_LINHTE + * @arg UART_DIS_LINSTE + * @arg UART_DIS_LINSNRE + * @arg UART_DIS_LINCE + * @arg UART_DIS_LINIPE + * @arg UART_DIS_LINISFE + * @arg UART_DIS_LINBE + * @arg UART_DIS_LINTC + * @arg UART_DIS_LINID + * @arg UART_DIS_LINBK + * @param NewState: new state of the specified UARTx interrupts. + * This parameter can be: + * @arg ENABLE : Disable corresponding interrupt. + * @arg DISABLE: No effect. + * @retval None + */ +void UART_ITDisableConfig(USART_TypeDef* UARTx, uint32_t UART_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_UART_ALL_PERIPH(UARTx)); + assert_param(IS_UART_CLEAR_IT(UART_IT)); + + if (NewState != DISABLE) + { + UARTx->IDR |= (uint32_t)((uint32_t)UART_IT); + } + else + { + UARTx->IDR &= (uint32_t)~((uint32_t)UART_IT); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usart.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usart.c new file mode 100644 index 00000000000..aab557cf412 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usart.c @@ -0,0 +1,3188 @@ +/** + ****************************************************************************** + * @file ft32f4xx_usart.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter + * Peripheral (USART). + * + Initialization and de-initialization functions + * + Normal command and configuration functions + * + Fractional baudrate function + * + Break command functions + * + Receiver time-out and transmitter timeguard functions + * + Multidrop mode command function + * + RS485 mode + * + MODEM mode + * + SPI mode functions + * + ISO7816 mode functions + * + IrDA mode function + * + LIN mode functions + * + Write protection register mode functions + * + Data transfers functions + * + DMA transfers management functions + * + Low-Power SLEEP wakeup management function + * + Interrupts and flags management functions + * @version V1.0.0 + * @date 2025-03-21 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_usart.h" +#include "ft32f4xx_rcc.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup USART_Private_Constants USART Private Constants + * @{ + */ +/*!< USART CR register mode field Mask ((~(uint32_t)0xFFFFFF5F)) */ +#define CR_CLEAR_MODE_MASK ((uint32_t)(USART_CR_TXDIS | USART_CR_RXDIS)) /*!< USART CR mode fields of parameters set by USART_Init API */ + +/*!< USART CR register hardware field Mask ((~(uint32_t)0xFFF9FFFF)) */ +#define CR_CLEAR_HARDWARE_MASK ((uint32_t)(USART_CR_RTSDIS | USART_CR_DTRDIS)) /*!< USART CR hardware fields of parameters set by USART_Init API */ + +/*!< USART MR register SPI mode Mask ((~(uint32_t)0xFFEEFEFF)) */ +#define MR_CLEAR_SPI_MASK ((uint32_t)(USART_MR_WRDBT | USART_MR_CPOL | \ + USART_MR_CPHA)) /*!< USART MR SPI mode fields of parameters set by USART_Init API */ + +/*!< USART MR register ISO7816 mode Mask ((~(uint32_t)0xF8CFFFFF)) */ +#define MR_CLEAR_ISO7816_MASK ((uint32_t)(USART_MR_MAX_ITERATION | USART_MR_DSNACK | \ + USART_MR_INACK)) /*!< USART MR ISO7816 mode fields of parameters set by USART_Init API */ + +/*!< USART MR register normal Mask ((~(uint32_t)0xFF700000)) */ +#define MR_CLEAR_NORMAL_MASK ((uint32_t)(USART_MR_INVDATA | USART_MR_OVER | \ + USART_MR_CLKO | USART_MR_MODE9 | \ + USART_MR_MSBF | USART_MR_CHMODE | \ + USART_MR_NBSTOP | USART_MR_PAR | \ + USART_MR_SYNC | USART_MR_CHRL | \ + USART_MR_USCLKS | USART_MR_USART_MODE))/*!< USART MR normal fields of parameters set by USART_Init API */ + +/** + * @} + */ + +/** @defgroup USART init and de-init functions + * @brief None + * +@verbatim + =============================================================================== + ##### Init and DeInit Functions ##### + =============================================================================== + [..] This subsection provides a set of functions about USART initialization + and de-initialization. + + [..] Most USART configurations can be set in the USART_init() function. + However, After USART_Init() function, user can use others configurations + (cfg) functions to change USART configurational. The command (Cmd) + functions can execute control operations under different configurations. + + [..] The configuration procedure of USART_Init() function is as follows: + (++) Check the parameters + (++) Enable USARTx work clock and configuration clock. + (++) USART CR configuration + (#) Configure the USART_Mode: + (-) transmitter disable + (-) transmitter enable + (-) receiver disable + (-) receiver enable + (#) Configure the USART RTS and DTR pins in RS485, MODEM and SPI mode: + (-) Request to send disable + (-) Request to send enable + (-) Data teriminal ready disable + (-) Data teriminal ready enable + (++) USART MR configuration + (#) Special configuration for SPI mode: + (-) Wait read data before transfer + (-) SPI clock polarity + (-) SPI clock phase + (#) Special configuration for ISO7816 protocol T = 0 mode: + (-) Maximum number of automatic iteration + (-) Disable successive NACK + (-) Inhibit non acknowledge + (#) Normal configuration: + (-) Inverted data + (-) Oversampling mode + (-) Clock output select + (-) 9-bit character length + (-) Bit order + (-) channel mode + (-) Number of STOP bits + (-) Parity type + (-) Synchronous mode select + (-) Character length + (-) Clock selection + (-) USART mode of operation + (++) USART FIDI configuration + (++) USART BRGR configuration except fractional part + (++) USART IF configuration + (++) USART LINMR configuration: + (-) Synchronization disable + (-) DMA mode + (-) Data length control + (-) Wakeup signal type + (-) Frame slot mode disable + (-) Data length mode + (-) Checksum type + (-) Checksum disable + (-) Parity disable + (-) LIN node action + + [..] + + (#) The USART init API's : + (++) USART_Init() + + (#) The USART Struct init API's : + (++) USART_StructInit() + + (#) The USART de-init API's : + (++) USART_DeInit() +@endverbatim + * @{ + */ + +/** + * @brief Initialize the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains + * the configuration information for the specified USART peripheral. + * @retval None + */ +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct) +{ + uint32_t clock_divider = 0, frac_divider = 0, apbclock = 0, tmpreg = 0; + + RCC_ClocksTypeDef RCC_ClocksStatus; + + /*------------------------------ Check The Parameter ------------------------*/ + /* Check the normal parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if ((USARTx == USART1) || (USARTx == USART6)) + { + assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate)); + } + else if ((USARTx == USART2) || (USARTx == USART3)) + { + assert_param(IS_USART_BAUDRATE_APB1(USART_InitStruct->USART_BaudRate)); + } + + assert_param(IS_USART_CHAR_LENGTH(USART_InitStruct->USART_WordLength)); + assert_param(IS_USART_CLOCK_OUTPUT(USART_InitStruct->USART_ClockOutput)); + assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits)); + assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity)); + assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode)); + assert_param(IS_USART_CLOCK_SELECT(USART_InitStruct->USART_CLKSelect)); + assert_param(IS_USART_MODE_OPERATION(USART_InitStruct->USART_OperationMode)); + assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl)); + assert_param(IS_USART_SYNC_MODE(USART_InitStruct->USART_Sync)); + assert_param(IS_USART_BIT_ORDER(USART_InitStruct->USART_BitOrder)); + assert_param(IS_USART_CHANNEL_MODE(USART_InitStruct->USART_ChannelMode)); + assert_param(IS_USART_OVERSAMPLING(USART_InitStruct->USART_OverSampling)); + assert_param(IS_USART_INVDATA(USART_InitStruct->USART_INVData)); + + /* Check ISO7816 mode special parameter */ + if ((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_0) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_1)) + { + assert_param(IS_USART_FIDIRATIO(USART_InitStruct->USART_FiDiRatio)); + assert_param(IS_USART_ISO7816_T0_INACK(USART_InitStruct->USART_InhibitNACK)); + assert_param(IS_USART_ISO7816_T0_DSNACK(USART_InitStruct->USART_DisSuccessiveNACK)); + assert_param(IS_USART_ISO7816_T0_MAX_ITERATION(USART_InitStruct->USART_MAXIteration)); + } + + /* Check IrDA mode special parameter */ + if (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_IrDA) + { + assert_param(IS_USART_IF(USART_InitStruct->USART_IrDAFilter)); + assert_param(IS_USART_FIDIRATIO(USART_InitStruct->USART_FiDiRatio)); + } + + /* Check SPI mode special parameter */ + if ((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_MASTER) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_SLAVE)) + { + assert_param(IS_USART_WRDBT(USART_InitStruct->USART_WRDBT)); + assert_param(IS_USART_POLARITY(USART_InitStruct->USART_CLKPolarity)); + assert_param(IS_USART_PHASE(USART_InitStruct->USART_CLKPhase)); + } + + /* Check LIN mode special parameter */ + if ((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_LIN_MASTER) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_LIN_SLAVE)) + { + assert_param(IS_USART_SYNC_DISABLE(USART_InitStruct->USART_SYNCDisable)); + assert_param(IS_USART_PDC_MODE_LINMR(USART_InitStruct->USART_PDCMode)); + assert_param(IS_USART_DLC(USART_InitStruct->USART_DataLengthControl)); + assert_param(IS_USART_WKUP_TYPE(USART_InitStruct->USART_WkupType)); + assert_param(IS_USART_FRAME_SLOT_DISABLE(USART_InitStruct->USART_FrameSlotDisable)); + assert_param(IS_USART_DATA_LENGTH_MODE(USART_InitStruct->USART_DataLengthMode)); + assert_param(IS_USART_CHECKSUM_TYPE(USART_InitStruct->USART_CheckSumType)); + assert_param(IS_USART_CHECKSUM_DISABLE(USART_InitStruct->USART_CheckSumDisable)); + assert_param(IS_USART_PARITY_DISABLE(USART_InitStruct->USART_ParityDisable)); + assert_param(IS_USART_NODE_ACTIVE(USART_InitStruct->USART_NodeAction)); + } + + /*----------------------------- Enable The Peripheral -----------------------*/ + if (USARTx == USART1) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART3, ENABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); + } + + /*---------------------------- USART CR Configuration -----------------------*/ + tmpreg = USARTx->CR; + + /* Configure the USART_Mode */ + /* Configure the TXDIS and RXDIS bits */ + USARTx->CR |= ((uint32_t)(CR_CLEAR_MODE_MASK)); + /* Configure the TXEN and RXEN bits */ + tmpreg |= USART_InitStruct->USART_Mode; + + /* Configure the USART RTS in SPI mode and DTR in MODEM mode */ + if ((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_MODEM) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_MASTER) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_SLAVE)) + { + /* Configure the hardware flow control bits RTSDIS and DTRDIS */ + USARTx->CR |= ((uint32_t)(CR_CLEAR_HARDWARE_MASK)); + /* Configure the hardware flow control bits RTSEN and DTREN */ + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + } + + /* Write to USART CR */ + USARTx->CR = tmpreg; + + /*---------------------------- USART MR Configuration -----------------------*/ + tmpreg = USARTx->MR; + + /* Normal configuration */ + /* Set the [23:23]_INVDATA ascording to USART_INVData value */ + /* Set the [19:19]_OVER ascording to USART_OverSampling value */ + /* Set the [18:18]_CLKO ascording to USART_ClockOutput value */ + /* Set the [17:17]_MODE9 ascording to USART_WordLength value */ + /* Set the [16:16]_MSBF ascording to USART_BitOrder value */ + /* Set the [15:14]_CHMODE ascording to USART_ChannelMode value */ + /* Set the [13:12]_NBSTOP ascording to USART_StopBits value */ + /* Set the [11: 9]_PAR ascording to USART_Parity value */ + /* Set the [ 8: 8]_SYNC ascording to USART_Sync value */ + /* Set the [ 7: 6]_CHRL ascording to USART_WordLength value */ + /* Set the [ 5: 4]_USCLKS ascording to USART_CLKSelect value */ + /* Set the [ 3: 0]_USART_MODE ascording to USART_OperationMode value */ + /* Clear the normal cfg bits */ + tmpreg &= (uint32_t)~((uint32_t)MR_CLEAR_NORMAL_MASK); + /* Configure the normal cfg bits */ + tmpreg |= (uint32_t)USART_InitStruct->USART_INVData | + USART_InitStruct->USART_OverSampling | + USART_InitStruct->USART_ClockOutput | + USART_InitStruct->USART_WordLength | + USART_InitStruct->USART_BitOrder | + USART_InitStruct->USART_ChannelMode | + USART_InitStruct->USART_StopBits | + USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Sync | + USART_InitStruct->USART_CLKSelect | + USART_InitStruct->USART_OperationMode ; + + /* Special configuration for SPI mode */ + /* Set the [20:20]_WRDBT(SPI) ascording to USART_WRDBT value */ + /* Set the [16:16]_CPOL(SPI) ascording to USART_CLKPolarity value */ + /* Set the [ 8: 8]_CPHA(SPI) ascording to USART_CLKPhase value */ + if ((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_MASTER) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_SLAVE)) + { + /* Clear the SPI mode cfg bits WRDBT, CPOL and CPHA bits */ + tmpreg &= (uint32_t)~((uint32_t)MR_CLEAR_SPI_MASK); + /* Configure the SPI mode cfg bits WRDBT, CPOL and CPHA bits */ + tmpreg |= (uint32_t)USART_InitStruct->USART_WRDBT | + USART_InitStruct->USART_CLKPolarity | + USART_InitStruct->USART_CLKPhase ; + } + + /* Special configuration for ISO7816 protocol T = 0 mode */ + /* Set the [26:24]_MAX_ITERATION ascording to USART_MAXIteration value */ + /* Set the [21:21]_DSNACK ascording to USART_DisSuccessiveNACK value */ + /* Set the [20:20]_INACK ascording to USART_InhibitNACK value */ + if (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_0) + { + /* Clear the ISO7816 mode cfg bits MAX_ITERATION, DSNACK and INACK bits */ + tmpreg &= (uint32_t)~((uint32_t)MR_CLEAR_ISO7816_MASK); + /* Configure the ISO7816 mode cfg bits MAX_ITERATION, DSNACK and INACK bits */ + tmpreg |= (uint32_t)USART_InitStruct->USART_MAXIteration | + USART_InitStruct->USART_DisSuccessiveNACK | + USART_InitStruct->USART_InhibitNACK ; + } + + /* Write to USART MR */ + USARTx->MR = tmpreg; + + /*---------------------------- USART FIDI Configuration -----------------------*/ + if ((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_0) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_1) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_IrDA)) + { + USARTx->FIDI = (uint32_t)USART_InitStruct->USART_FiDiRatio; + } + + /*---------------------------- USART BRGR Configuration -----------------------*/ + tmpreg = USARTx->BRGR; + + /* Configure the USART Baud Rate */ + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if (USARTx == USART1) + { + apbclock = RCC_ClocksStatus.P2CLK_Frequency; + } + else if (USARTx == USART2) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (USARTx == USART3) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (USARTx == USART6) + { + apbclock = RCC_ClocksStatus.P2CLK_Frequency; + } + + /* Determine the integer part and fraction part disable (fractional part can configure in USART_FracDivider_Cfg()) */ + /* BaudRate not equal 0*/ + if ((USART_InitStruct->USART_BaudRate) > 0) + { + /* Non ISO7816 Mode*/ + if (!((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_0) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_1))) + { + /* Async mode*/ + if (!((USART_InitStruct->USART_Sync == USART_SYNC_MODE_SYNC) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_MASTER) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_SLAVE))) + { + /* x16 Oversample*/ + if (USART_InitStruct->USART_OverSampling == USART_OVERSAMPLING_16) + { + clock_divider = (uint32_t)(((apbclock) / ((USART_InitStruct->USART_BaudRate) * 16))); + frac_divider = 0; + } + /* x8 Oversample*/ + else if (USART_InitStruct->USART_OverSampling == USART_OVERSAMPLING_8) + { + clock_divider = (uint32_t)(((apbclock) / ((USART_InitStruct->USART_BaudRate) * 8))); + frac_divider = 0; + } + } + /* Sync mode or SPI mode*/ + else if ((USART_InitStruct->USART_Sync == USART_SYNC_MODE_SYNC) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_MASTER) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_SPI_SLAVE)) + { + clock_divider = (uint32_t)((apbclock) / ((USART_InitStruct->USART_BaudRate))); + } + } + /* ISO7816 Mode*/ + else if (((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_0) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_ISO7816_T_1))) + { + clock_divider = (uint32_t)((apbclock) / ((USART_InitStruct->USART_BaudRate) * + (USART_InitStruct->USART_FiDiRatio))); + } + } + /* BaudRate equal 0*/ + else if ((USART_InitStruct->USART_BaudRate) == 0) + { + clock_divider = 0; + frac_divider = 0; + } + + /* Write to USART BRGR */ + USARTx->BRGR = (((uint32_t)(clock_divider)) | ((uint32_t)(frac_divider) << 16U)); + + /*---------------------------- USART IF Configuration -----------------------*/ + /* Write to USART IF in IrDA mode */ + if (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_IrDA) + { + USARTx->IF = (uint16_t)USART_InitStruct->USART_IrDAFilter; + } + + /*---------------------------- USART LINMR Configuration --------------------*/ + tmpreg = 0; + + if ((USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_LIN_MASTER) || + (USART_InitStruct->USART_OperationMode == USART_MODE_OPERATION_LIN_SLAVE)) + { + /* Set the [17:17]_SYNCDIS ascording to USART_SYNCDisable value */ + /* Set the [16:16]_PDCM ascording to USART_PDCMode value */ + /* Set the [15: 8]_DLC ascording to USART_DataLengthControl value */ + /* Set the [ 7: 7]_WKUPTYP ascording to USART_WkupType value */ + /* Set the [ 6: 6]_FSDIS ascording to USART_FrameSlotDisable value */ + /* Set the [ 5: 5]_DLM ascording to USART_DataLengthMode value */ + /* Set the [ 4: 4]_CHKTYP ascording to USART_CheckSumType value */ + /* Set the [ 3: 3]_CHKDIS ascording to USART_CheckSumDisable value */ + /* Set the [ 2: 2]_PARDIS ascording to USART_ParityDisable value */ + /* Set the [ 1: 0]_NACT ascording to USART_NodeAction value */ + tmpreg |= (uint32_t)USART_InitStruct-> USART_SYNCDisable | + USART_InitStruct-> USART_PDCMode | + ((USART_InitStruct-> USART_DataLengthControl << (uint32_t)8)) | + USART_InitStruct-> USART_WkupType | + USART_InitStruct-> USART_FrameSlotDisable | + USART_InitStruct-> USART_DataLengthMode | + USART_InitStruct-> USART_CheckSumType | + USART_InitStruct-> USART_CheckSumDisable | + USART_InitStruct-> USART_ParityDisable | + ((USART_InitStruct-> USART_NodeAction << (uint32_t)0)) ; + + /* Write to USART LINMR*/ + USARTx->LINMR = tmpreg; + } +} + +/** + * @brief Configure each USART_InitStruct member with its default value. + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * @retval None + */ +void USART_StructInit(USART_InitTypeDef* USART_InitStruct) +{ + /* USART_InitStruct members default value */ + USART_InitStruct->USART_BaudRate = 9600 ; + USART_InitStruct->USART_FiDiRatio = 174 ; + USART_InitStruct->USART_IrDAFilter = 0 ; + USART_InitStruct->USART_WordLength = USART_CHAR_LENGTH_8BIT ; + USART_InitStruct->USART_ClockOutput = USART_CLOCK_OUTPUT_DISABLE ; + USART_InitStruct->USART_StopBits = USART_STOPBITS_1 ; + USART_InitStruct->USART_Parity = USART_PARITY_NONE ; + USART_InitStruct->USART_Mode = USART_MODE_TX | USART_MODE_RX ; + USART_InitStruct->USART_CLKSelect = USART_CLOCK_SELECT_MCK ; + USART_InitStruct->USART_OperationMode = USART_MODE_OPERATION_NORMAL ; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None ; + USART_InitStruct->USART_Sync = USART_SYNC_MODE_ASYNC ; + USART_InitStruct->USART_BitOrder = USART_BIT_ORDER_LSBF ; + USART_InitStruct->USART_ChannelMode = USART_CHANNEL_MODE_NORMAL ; + USART_InitStruct->USART_WRDBT = USART_WRDBT_DISABLE ; + USART_InitStruct->USART_OverSampling = USART_OVERSAMPLING_16 ; + USART_InitStruct->USART_CLKPolarity = USART_POLARITY_LOW ; + USART_InitStruct->USART_CLKPhase = USART_PHASE_2EDGE ; + USART_InitStruct->USART_INVData = USART_INVDATA_DISABLE ; + USART_InitStruct->USART_InhibitNACK = USART_ISO7816_T0_INACK_DISABLE ; + USART_InitStruct->USART_DisSuccessiveNACK = USART_ISO7816_T0_DSNACK_DISABLE ; + USART_InitStruct->USART_MAXIteration = USART_ISO7816_T0_MAX_ITERATION_0; + USART_InitStruct->USART_SYNCDisable = USART_SYNC_DISABLE_NONE ; + USART_InitStruct->USART_PDCMode = USART_PDC_MODE_LINMR_NOTWRITE ; + USART_InitStruct->USART_DataLengthControl = 0 ; + USART_InitStruct->USART_WkupType = USART_WKUP_TYPE_LIN_2_0 ; + USART_InitStruct->USART_FrameSlotDisable = USART_FRAME_SLOT_DISABLE_NONE ; + USART_InitStruct->USART_DataLengthMode = USART_DATA_LENGTH_MODE_DLC ; + USART_InitStruct->USART_CheckSumType = USART_CHECKSUM_TYPE_ENHANCED ; + USART_InitStruct->USART_CheckSumDisable = USART_CHECKSUM_DISABLE_NONE ; + USART_InitStruct->USART_ParityDisable = USART_PARITY_DISABLE_NONE ; + USART_InitStruct->USART_NodeAction = USART_NODE_ACTIVE_PUBLISH ; +} + +/** + * @brief De-Initialize the USARTx peripheral to their default reset value. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @retval None + */ +void USART_DeInit(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* USARTx reset operation */ + if (USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART3, DISABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE); + } +} + +/** + * @} + */ + +/** @defgroup USART normal cmd and cfg functions + * @brief USART normal command and configuration functions + * +@verbatim + =============================================================================== + ##### Normal Command And Configuration Functions ##### + =============================================================================== + [..] This subsection provides a set of normal command and configuration + function. + + [..] + + (#) The Normal cmd API's : + (++) USART_Cmd() + (++) USART_RTSDIS_Cmd() + (++) USART_RTSEN_Cmd() + (++) USART_DTRDIS_Cmd() + (++) USART_DTREN_Cmd() + (++) USART_RSTSTA_Cmd() + (++) USART_TXDIS_Cmd() + (++) USART_TXEN_Cmd() + (++) USART_RXDIS_Cmd() + (++) USART_RXEN_Cmd() + (++) USART_RSTTX_Cmd() + (++) USART_RSTRX_Cmd() + + (#) The Normal cfg API's : + (++) USART_InvData_Cfg() + (++) USART_OverSampling8_Cfg() + (++) USART_ClkOutput_Cfg() + (++) USART_DataLength9_Cfg() + (++) USART_MSBFirst_Cfg() + (++) USART_ChannelMode_Cfg() + (++) USART_StopBit_Cfg() + (++) USART_Parity_Cfg() + (++) USART_SYNCMode_Cfg() + (++) USART_DataLength_Cfg() + (++) USART_CLKSelect_Cfg() + (++) USART_OperationMode_Cfg() + + (#) The Normal read API's : + (++) None +@endverbatim + * @{ + */ + +/** + * @brief Enables or disables the specified USART peripheral. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx peripheral. + * This parameter can be: ENABLE or DISABLE. + * @retval None + */ +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the selected USART by setting the USARTxEN bit in the RCC_APB1ENR/APB2ENR register */ + if (USARTx == USART1) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, ENABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART3, ENABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE); + } + } + else + { + /* Disable the selected USART by clearing the USARTxEN bit in the RCC_APB1ENR/APB2ENR register */ + if (USARTx == USART1) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if (USARTx == USART2) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART2, DISABLE); + } + else if (USARTx == USART3) + { + RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART3, DISABLE); + } + else if (USARTx == USART6) + { + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, DISABLE); + } + } +} + +/** + * @brief Request to send disable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx request to send disable. + * This parameter can be: + * @arg ENABLE : Drives the pin RTS to 1 + * @arg DISABLE: No effect + * @retval None + */ +void USART_RTSDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Request to send disable by setting RTSDIS bit in the CR register */ + USARTx->CR |= USART_CR_RTSDIS; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RTSDIS); + } +} + +/** + * @brief Request to send enable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx request to send enable. + * This parameter can be: + * @arg ENABLE : Drives the pin RTS to 0 + * @arg DISABLE: No effect + * @retval None + */ +void USART_RTSEN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Request to send enable by setting RTSEN bit in the CR register */ + USARTx->CR |= USART_CR_RTSEN; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RTSEN); + } +} + +/** + * @brief Data terminal ready disable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx data terminal ready disable. + * This parameter can be: + * @arg ENABLE : Drives the pin DTR to 1 + * @arg DISABLE: No effect + * @retval None + */ +void USART_DTRDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Data terminal ready disable by setting DTRDIS bit in the CR register */ + USARTx->CR |= USART_CR_DTRDIS; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_DTRDIS); + } +} + +/** + * @brief Data terminal ready enable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx data terminal ready enable. + * This parameter can be: + * @arg ENABLE : Drives the pin DTR to 0 + * @arg DISABLE: No effect + * @retval None + */ +void USART_DTREN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Data terminal ready enable by setting DTREN bit in the CR register */ + USARTx->CR |= USART_CR_DTREN; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_DTREN); + } +} + +/** + * @brief Reset status bits. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx reset status bits. + * This parameter can be: + * @arg ENABLE : Resets the status bits PARE, FRAME, OVER, LINBE, + * LINISFE, LINIPE, LINCE, LINSNRE, LINSTE, LINHTE, + * LINID, LINTC, LINBK and RXBRK in US_CSR. + * @arg DISABLE: No effect + * @retval None + */ +void USART_RSTSTA_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The status bits reset by setting RSTSTA bit in the CR register */ + USARTx->CR |= USART_CR_RSTSTA; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTSTA); + } +} + +/** + * @brief Transmitter disable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx transmitter disable. + * This parameter can be: + * @arg ENABLE : Disable the transmitter. + * @arg DISABLE: No effect + * @retval None + */ +void USART_TXDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The transmitter disable by setting TXDIS bit in the CR register */ + USARTx->CR |= USART_CR_TXDIS; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_TXDIS); + } +} + +/** + * @brief Transmitter enable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx transmitter enable. + * This parameter can be: + * @arg ENABLE : Enable the transmitter if TXDIS is 0. + * @arg DISABLE: No effect + * @retval None + */ +void USART_TXEN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The transmitter enable by setting TXEN bit in the CR register */ + USARTx->CR |= USART_CR_TXEN; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_TXEN); + } +} + +/** + * @brief Receiver disable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx receiver disable. + * This parameter can be: + * @arg ENABLE : Disable the receiver. + * @arg DISABLE: No effect + * @retval None + */ +void USART_RXDIS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The receiver disable by setting RXDIS bit in the CR register */ + USARTx->CR |= USART_CR_RXDIS; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RXDIS); + } +} + +/** + * @brief Receiver enable. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx receiver enable. + * This parameter can be: + * @arg ENABLE : Enable the receiver if RXDIS is 0. + * @arg DISABLE: No effect + * @retval None + */ +void USART_RXEN_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The receiver enable by setting RXEN bit in the CR register */ + USARTx->CR |= USART_CR_RXEN; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RXEN); + } +} + +/** + * @brief Reset transmitter + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx reset transmitter. + * This parameter can be: + * @arg ENABLE : Resets the transmitter. + * @arg DISABLE: No effect + * @retval None + */ +void USART_RSTTX_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The transmitter reset by setting RSTTX bit in the CR register */ + USARTx->CR |= USART_CR_RSTTX; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTTX); + } +} + +/** + * @brief Reset receiver + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx reset receiver. + * This parameter can be: + * @arg ENABLE : Resets the receiver. + * @arg DISABLE: No effect + * @retval None + */ +void USART_RSTRX_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* The receiver reset by setting RSTRX bit in the CR register */ + USARTx->CR |= USART_CR_RSTRX; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTRX); + } +} + +/** + * @brief Inverted data + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx inverted data. + * This parameter can be: + * @arg ENABLE : The data field transmitted on TXD line is inverted + * compared to the value writted on US_THR register or + * the content read in US_RHR is inverted compared to + * what is received on TXD line (or ISO7816 IO line). + * @arg DISABLE: The data field transmitted on TXD line is the same + * as one written in US_THR register or content read in + * US_RHR is the same as RXD line. Normal mode of operation. + * @retval None + */ +void USART_InvData_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the invert data function by setting INVDATA bit in the MR register */ + USARTx->MR |= USART_MR_INVDATA; + } + else + { + /* Disable the invert data function by clearing INVDATA bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_INVDATA); + } +} + +/** + * @brief Oversampling mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx oversampling mode. + * This parameter can be: + * @arg ENABLE : 8x oversampling. + * @arg DISABLE: 16x oversampling. + * @retval None + */ +void USART_OverSampling8_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the 8x oversampling function by setting OVER bit in the MR register */ + USARTx->MR |= USART_MR_OVER; + } + else + { + /* Disable the 8x oversampling function by clearing OVER bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_OVER); + } +} + +/** + * @brief Clock output select + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx clock output select. + * This parameter can be: + * @arg ENABLE : The USART drives the SCK pin if USART_CLKSelect does + * not select the external clock SCK. + * @arg DISABLE: The USART does not drive the SCK pin. + * @retval None + */ +void USART_ClkOutput_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART drives the SCK pin if USART_CLKSelect does not select the + external clock SCK by setting CLKO bit in the MR register */ + USARTx->MR |= USART_MR_CLKO; + } + else + { + /* Disable the USART drives the SCK pin if USART_CLKSelect does not select the + external clock SCK by clearing CLKO bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_CLKO); + } +} + +/** + * @brief 9-bit character length + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx 9-bit character length. + * This parameter can be: + * @arg ENABLE : 9-bit character length. + * @arg DISABLE: USART_Char_Length defines character length. + * @retval None + */ +void USART_DataLength9_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable 9-bit character length by setting MODE9 bit in the MR register */ + USARTx->MR |= USART_MR_MODE9; + } + else + { + /* Disable 9-bit character length by clearing MODE9 bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_MODE9); + } +} + +/** + * @brief Bit order + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx bit order. + * This parameter can be: + * @arg ENABLE : Most significant bit is sent/received first. + * @arg DISABLE: Least significant bit is sent/received first. + * @retval None + */ +void USART_MSBFirst_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable most significant bit is sent/received by setting MSBF bit in the MR register */ + USARTx->MR |= USART_MR_MSBF; + } + else + { + /* Enable least significant bit is sent/received by setting MSBF bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_MSBF); + } +} + +/** + * @brief Channel mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_ChannelMode: channel mode + * This parameter can be one of the following values: + * USART_CHANNEL_MODE_NORMAL - Normal mode + * USART_CHANNEL_MODE_AUTOMATIC - Automatic mode + * USART_CHANNEL_MODE_LOCAL_LOOPBACK - Local loopback mode + * USART_CHANNEL_MODE_REMOTE_LOOPBACK - Remote loopbak mode + * @retval None + */ +void USART_ChannelMode_Cfg(USART_TypeDef* USARTx, uint32_t USART_ChannelMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CHANNEL_MODE(USART_ChannelMode)); + + /* Clear the channel mode by clearing the CHMODE[15:14] bits in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_CHMODE); + + /* Set the channel mode by setting the CHMODE[15:14] bits in the MR register */ + USARTx->MR |= (uint32_t)((uint32_t)USART_ChannelMode); +} + +/** + * @brief Number of stop bits + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_StopBits: number of stop bits, + * This parameter can be one of the following values: + * USART_STOPBITS_1 - 1 stop bit + * USART_STOPBITS_1_5 - 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) + * USART_STOPBITS_2 - 2 stop bits + * @retval None + */ +void USART_StopBit_Cfg(USART_TypeDef* USARTx, uint32_t USART_StopBits) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_STOPBITS(USART_StopBits)); + + /* Clear the number of stop bits by clearing the NBSTOP[13:12] bits in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_NBSTOP); + + /* Set the number of stop bits by setting the NBSTOP[13:12] bits in the MR register */ + USARTx->MR |= (uint32_t)((uint32_t)USART_StopBits); +} + +/** + * @brief Parity type + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_Parity: Parity type + * This parameter can be one of the following values: + * USART_PARITY_EVEN - Even parity + * USART_PARITY_ODD - Odd parity + * USART_PARITY_SPACE - Parity forced to 0 (space) + * USART_PARITY_MARK - Parity forced to 1 (mark) + * USART_PARITY_NONE - No parity + * USART_PARITY_MULTIDROP - Multidrop mode + * @retval None + */ +void USART_Parity_Cfg(USART_TypeDef* USARTx, uint32_t USART_Parity) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_PARITY(USART_Parity)); + + /* Clear the parity type by clearing the PAR[11:9] bits in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_PAR); + + /* Set the parity type by setting the PAR[11:9] bits in the MR register */ + USARTx->MR |= (uint32_t)((uint32_t)USART_Parity); +} + +/** + * @brief Synchronous mode select + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx synchronous mode select. + * This parameter can be: + * @arg ENABLE : USART operates in synchronous mode. + * @arg DISABLE: USART operated in asynchronous mode. + * @retval None + */ +void USART_SYNCMode_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the USART operates in sync mode by setting SYNC bit in the MR register */ + USARTx->MR |= USART_MR_SYNC; + } + else + { + /* Disable the USART operates in sync mode by clearing SYNC bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_SYNC); + } +} + +/** + * @brief Character length + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_WordLength: character length + * This parameter can be one of the following values: + * USART_CHAR_LENGTH_5BIT - character length is 5 bits + * USART_CHAR_LENGTH_6BIT - character length is 6 bits + * USART_CHAR_LENGTH_7BIT - character length is 7 bits + * USART_CHAR_LENGTH_8BIT - character length is 8 bits + * @retval None + */ +void USART_DataLength_Cfg(USART_TypeDef* USARTx, uint32_t USART_WordLength) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CHAR_LENGTH(USART_WordLength)); + + /* Clear the character length by clearing the CHRL[7:6] bits in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_CHRL); + + /* Set the character length by setting the CHRL[7:6] bits in the MR register */ + USARTx->MR |= (uint32_t)((uint32_t)USART_WordLength); +} + +/** + * @brief Clock selection + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_CLKSelect: clock selection + * This parameter can be one of the following values: + * USART_CLOCK_SELECT_MCK - MCK + * USART_CLOCK_SELECT_MCKDIV8 - MCK / 8 + * USART_CLOCK_SELECT_SCK - SCK + * @retval None + */ +void USART_CLKSelect_Cfg(USART_TypeDef* USARTx, uint32_t USART_CLKSelect) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLOCK_SELECT(USART_CLKSelect)); + + /* Clear the clock select by clearing the USCLKS[5:4] bits in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_USCLKS); + + /* Set the clock select by setting the USCLKS[5:4] bits in the MR register */ + USARTx->MR |= (uint32_t)((uint32_t)USART_CLKSelect); +} + +/** + * @brief USART mode of operation + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_OperationMode: USART mode of operation + * This parameter can be one of the following values: + * USART_MODE_OPERATION_NORMAL - Normal mode + * USART_MODE_OPERATION_RS485 - RS485 mode + * USART_MODE_OPERATION_MODEM - Modem mode + * USART_MODE_OPERATION_ISO7816_T_0 - ISO7816 protocol: T = 0 + * USART_MODE_OPERATION_ISO7816_T_1 - ISO7816 protocol: T = 1 + * USART_MODE_OPERATION_IrDA - IrDA + * USART_MODE_OPERATION_LIN_MASTER - LIN master + * USART_MODE_OPERATION_LIN_SLAVE - LIN slave + * USART_MODE_OPERATION_SPI_MASTER - SPI master + * USART_MODE_OPERATION_SPI_SLAVE - SPI slave + * + * @retval None + */ +void USART_OperationMode_Cfg(USART_TypeDef* USARTx, uint32_t USART_OperationMode) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_MODE_OPERATION(USART_OperationMode)); + + /* Clear the USART mode of operation by clearing the USART_MODE[3:0] bits in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_USART_MODE); + + /* Set the USART mode of operation by setting the USART_MODE[3:0] bits in the MR register */ + USARTx->MR |= (uint32_t)((uint32_t)USART_OperationMode); +} + +/** + * @} + */ + +/** @defgroup USART fractional baudrate function + * @brief USART fractional part of baudrate function + * +@verbatim + =============================================================================== + ##### Fractional Baudrate Functions ##### + =============================================================================== + [..] This subsection provides a function, which can configure fractional part + of baudrate. + + [..] + + (#) The fractional part of baudrate API's : + (++) USART_FracDivider_Cfg() +@endverbatim + * @{ + */ + +/** + * @brief USART fractional part of BaudRate + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_BaudRate: user confige baudrate + * @note This function has to be called after calling USART_Init() function + * in order to have correct fractional part baudrate Divider value. + * @retval None + */ +void USART_FracDivider_Cfg(USART_TypeDef* USARTx, uint32_t USART_BaudRate) +{ + double clock_divider = 0, frac_divider = 0, apbclock = 0; + + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if ((USARTx == USART1) || (USARTx == USART6)) + { + assert_param(IS_USART_BAUDRATE(USART_BaudRate)); + } + else if ((USARTx == USART2) || (USARTx == USART3)) + { + assert_param(IS_USART_BAUDRATE_APB1(USART_BaudRate)); + } + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + /* Get USARTx work clock*/ + if (USARTx == USART1) + { + apbclock = RCC_ClocksStatus.P2CLK_Frequency; + } + else if (USARTx == USART2) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (USARTx == USART3) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (USARTx == USART6) + { + apbclock = RCC_ClocksStatus.P2CLK_Frequency; + } + + /* BaudRate not equal 0*/ + if (USART_BaudRate > 0) + { + /* Non ISO7816 Mode*/ + if (!((((USARTx->MR)&USART_MR_USART_MODE) == USART_MODE_OPERATION_ISO7816_T_0) || + (((USARTx->MR)&USART_MR_USART_MODE) == USART_MODE_OPERATION_ISO7816_T_1))) + { + /* Async mode*/ + if (((USARTx->MR)&USART_MR_SYNC) == USART_SYNC_MODE_ASYNC) + { + /* x16 Oversample*/ + if (((USARTx->MR)&USART_MR_OVER) == USART_OVERSAMPLING_16) + { + clock_divider = (uint32_t)(((apbclock) / ((USART_BaudRate) * 16))); + frac_divider = (uint32_t)(((apbclock) / ((USART_BaudRate) * 16) - clock_divider) * 8); + } + /* x8 Oversample*/ + if (((USARTx->MR)&USART_MR_OVER) == USART_OVERSAMPLING_8) + { + clock_divider = (uint32_t)(((apbclock) / ((USART_BaudRate) * 8))); + frac_divider = (uint32_t)(((apbclock) / ((USART_BaudRate) * 8) - clock_divider) * 8); + } + } + } + } + + /* Clear the USART fractional part by clearing the FP[18:16] bits in the BRGR register */ + USARTx->BRGR &= (uint32_t)~((uint32_t)USART_BRGR_FP); + + /* Set the USART fractional part by setting the FP[18:16] bits in the BRGR register */ + USARTx->BRGR |= (((uint32_t)frac_divider) << 16U); +} + +/** + * @} + */ + +/** @defgroup USART BREAK command functions + * @brief None + * +@verbatim + =============================================================================== + ##### Break Command Functions ##### + =============================================================================== + [..] This subsection provides a set of BREAK command functions. + + [..] + + (#) The stop break command API's : + (++) USART_STPBRK_Cmd() + + (#) The start break command API's : + (++) USART_STTBRK_Cmd() +@endverbatim + * @{ + */ + +/** + * @brief Stop break. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx stop break. + * This parameter can be: + * @arg ENABLE : Stops transmission of break after a minimum of one character length and + * transmits a high level during 12-bit periods. + * @arg DISABLE: No effect + * @retval None + */ +void USART_STPBRK_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Stops transmission of break after a minimum of one character by setting STPBRK + bit in the CR register */ + USARTx->CR |= USART_CR_STPBRK; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_STPBRK); + } +} + +/** + * @brief Start break. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx start break. + * This parameter can be: + * @arg ENABLE : Starts transmission of break after the character present in US_THR and + * the transmit shift register have been transmitted. No effect if a break + * is already being transmitted. + * @arg DISABLE: No effect + * @retval None + */ +void USART_STTBRK_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Starts transmission of the break after the characters present in US_THR and the transmit + shift register have been transmitted by setting STTBRK bit in the CR register */ + USARTx->CR |= USART_CR_STTBRK; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_STTBRK); + } +} + +/** + * @} + */ + +/** @defgroup USART receiver time-out and transmitter timeguard functions + * @brief Receiver time-out cfg and cmd functions. + * Transmitter timeguard cfg function. + * +@verbatim + =============================================================================== + ##### Receiver Time-out And Transmitter Timeguard Functions ##### + =============================================================================== + [..] This subsection provides a set of receiver time-out and transmitter + timeguard functions. + + [..] + + (#) The receiver time-out cfg API's : + (++) USART_Receiver_TimeOut_Cfg() + + (#) The receiver time-out cmd API's : + (++) USART_RETTO_After_Timeout_Cmd() + (++) USART_STTTO_After_Timeout_Cmd() + + (#) The transmitter timeguard cfg API's : + (++) USART_Transmitter_TimeGuard_Cfg() +@endverbatim + * @{ + */ + +/** + * @brief Receiver time-out value + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_ReceiverTimeOut: Time-out value + * 0 : The receiver time-out is disabled. + * 1 - 65535 : The receiver time-out is enabled and time-out + * delay is TO * bit period. + * 1 - 131071: The receiver time-out is enabled and time-out + * delay is TO * bit period. + * @note This function has to be called before calling USART_Init() function + * in order to have correct receiver time-out value. + * @retval None + */ +void USART_Receiver_TimeOut_Cfg(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut)); + + /* Clear the time-out value of receiver by clearing the TO[16:0] bits in the RTOR register */ + USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_TO); + + /* Set the time-out value of receiver setting the TO[16:0] bits in the RTOR register */ + USARTx->RTOR |= (uint32_t)((uint32_t)USART_ReceiverTimeOut); +} + +/** + * @brief Rearm Time-out. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx rearm Time-out. + * This parameter can be: + * @arg ENABLE : Restart Time-out + * @arg DISABLE: No effect + * @retval None + */ +void USART_RETTO_After_Timeout_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Restart Time-out by setting RETTO bit in the CR register */ + USARTx->CR |= USART_CR_RETTO; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RETTO); + } +} + +/** + * @brief Start time-out. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx start time-out. + * This parameter can be: + * @arg ENABLE : Starts waiting for a character before clocking the time-out counter. + * Resets the status bit TIMEOUT in US_CSR. + * @arg DISABLE: No effect + * @retval None + */ +void USART_STTTO_After_Timeout_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Starts waiting for a character before clocking the time-out counter by setting + STTTO bit in the CR register */ + USARTx->CR |= USART_CR_STTTO; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_STTTO); + } +} + +/** + * @brief Transmitter timeguard value + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_TransmitterTimeGuard: timeguard value + * 0 : The transmitter timeguard value is disabled. + * 1 - 255: The transmitter timeguard is enabled and the + * timeguard delay is TG * bit period. + * @note This function has to be called before calling USART_Init() function + * in order to have correct transmitter timeguard value. + * @retval None + */ +void USART_Transmitter_TimeGuard_Cfg(USART_TypeDef* USARTx, uint32_t USART_TransmitterTimeGuard) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_TIMGUARD(USART_TransmitterTimeGuard)); + + /* Clear the timeguard value of transmitter by clearing the TG[7:0] bits in the TTGR register */ + USARTx->TTGR &= (uint32_t)~((uint32_t)USART_TTGR_TG); + + /* Set the timeguard value of transmitter setting the TG[7:0] bits in the TTGR register */ + USARTx->TTGR |= (uint32_t)((uint32_t)USART_TransmitterTimeGuard); +} + +/** + * @} + */ + +/** @defgroup USART multidrop mode cmd function + * @brief Multidrop mode command function. + * +@verbatim + =============================================================================== + ##### Multidrop Mode Command Function ##### + =============================================================================== + [..] This subsection provides the multidrop mode command function. + + [..] + + (#) The multidrop mode command API's : + (++) USART_SENDAInMultidropMode_Cmd() + +@endverbatim + * @{ + */ + +/** + * @brief Send address. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx send address. + * This parameter can be: + * @arg ENABLE : In multidrop mode only, the next character written to + * the US_THR is sent with address bit set. + * @arg DISABLE: No effect + * @retval None + */ +void USART_SENDAInMultidropMode_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* In multidrop mode only, the next character writted to the US_THR is sent + with the address bit set by setting SENDA bit in the CR register */ + USARTx->CR |= USART_CR_SENDA; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_SENDA); + } +} + +/** + * @} + */ + +/** @defgroup USART SPI mode cmd, cfg, and read functions + * @brief USART SPI mode mode command, configuration and read functions + * +@verbatim + =============================================================================== + ##### SPI Mode Functions ##### + =============================================================================== + [..] This subsection provides a set of SPI mode functions. + + [..] + + (#) The SPI mode cmd API's : + (++) USART_RCS_Cmd() + (++) USART_FCS_Cmd() + + (#) The SPI mode cfg API's : + (++) USART_WRDBT_Cfg() + (++) USART_CLKPolarity_Cfg() + (++) USART_CLKPhase_Cfg() + + (#) The SPI mode read API's : + (++) None +@endverbatim + * @{ + */ + +/** + * @brief Release SPI chip select + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx release SPI chip select. + * This parameter can be: + * @arg ENABLE : Releases the slave select lin NSS (RTS pin). + * Applicable if USARTx operates in SPI Master. + * @arg DISABLE: No effect + * @retval None + */ +void USART_RCS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Release the slave slect line (RTS pin) by setting RCS bit in + the CR(SPI_MODE) register */ + USARTx->CR |= USART_CR_RCS; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RCS); + } +} + +/** + * @brief Force SPI chip select + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx force SPI chip select. + * This parameter can be: + * @arg ENABLE : Forces the slave select lin NSS (RTS pin) to 0, + * even if USART is no transmitting, in order to + * address SPI slave devices supporting the CSAAT + * mode (Chip Select Active After Transfer). + * Applicable if USARTx operates in SPI Master. + * @arg DISABLE: No effect + * @retval None + */ +void USART_FCS_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Force the slave slect line (RTS pin) by setting FCS bit in the + CR(SPI_MODE) register */ + USARTx->CR |= USART_CR_FCS; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_FCS); + } +} + +/** + * @brief Wait read data before transfre + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx wait read data before transfer. + * This parameter can be: + * @arg ENABLE : The character transmission starts when a character + * is written and only if RXRDY flag is cleared (Receiver + * Holding register has been read). + * @arg DISABLE: The character transmission starts as soon as a character + * is written into US_THR register (assuming TXRDY was set). + * @retval None + */ +void USART_WRDBT_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the transmission after read data by setting WRDBT bit in the MR register */ + USARTx->MR |= USART_MR_WRDBT; + } + else + { + /* Disable the transmission after read data by clearing WRDBT bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_WRDBT); + } +} + +/** + * @brief SPI clock polarity + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx spi operates clock polarity, + * applicable if USART operates in SPI mode (slave or master). + * This parameter can be: + * @arg ENABLE : The inactive status value of SPCK is logic level one. + * @arg DISABLE: The inactive status value of SPCK is logic level zero. + * @retval None + */ +void USART_CLKPolarity_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the spi clock polarity by setting CPOL bit in the MR register */ + USARTx->MR |= USART_MR_CPOL; + } + else + { + /* Disable the spi clock polarity by clearing CPOL bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_CPOL); + } +} + +/** + * @brief SPI clock phase + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx spi operates clock phase, + * applicable if USART operates in SPI mode (slave or master). + * This parameter can be: + * @arg ENABLE : Data is captured on the leading edge of SPCK and + * changed on the following edge of SPCK. + * @arg DISABLE: Data is changeded on the leading edge of SPCK and + * captured on the following edge of SPCK. + * @retval None + */ +void USART_CLKPhase_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the spi clock phase by setting CPHA bit in the MR register */ + USARTx->MR |= USART_MR_CPHA; + } + else + { + /* Disable the spi clock phase by clearing CPHA bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_CPHA); + } +} + +/** + * @} + */ + +/** @defgroup USART ISO7816 mode cmd, cfg, and read functions + * @brief USART ISO7816 mode mode command, configuration and read functions + * +@verbatim + =============================================================================== + ##### ISO7816 Mode Functions ##### + =============================================================================== + [..] This subsection provides a set of ISO7816 mode functions. + + [..] + + (#) The ISO7816 mode cmd API's : + (++) USART_RSTNACK_Cmd() + (++) USART_RSTIT_Cmd() + + (#) The ISO7816 mode cfg API's : + (++) USART_MaxIteration_Cfg() + (++) USART_DsNack_Cfg() + (++) USART_INack_Cfg() + (++) USART_FiDiRatio_Cfg() + + (#) The ISO7816 mode read API's : + (++) USART_GetNumberOfError() +@endverbatim + * @{ + */ + +/** + * @brief Reset non acknowledge. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx reset non acknowledge. + * This parameter can be: + * @arg ENABLE : Reset NACK in US_CSR + * @arg DISABLE: No effect + * @retval None + */ +void USART_RSTNACK_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Reset the NACK in US_CSR by setting RSTNACK bit in the CR register */ + USARTx->CR |= USART_CR_RSTNACK; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTNACK); + } +} + +/** + * @brief Reset iterations. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx reset iterations. + * This parameter can be: + * @arg ENABLE : Reset ITERATION in US_CSR (No effect if the ISO7816 is not enabled). + * @arg DISABLE: No effect + * @retval None + */ +void USART_RSTIT_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Reset the ITERATION in US_CSR by setting RSTIT bit in the CR register */ + USARTx->CR |= USART_CR_RSTIT; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_RSTIT); + } +} + +/** + * @brief Maximum number of automatic iteration + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_MAXIteration: Defines the maximum number of iterations in mode ISO7816, + * protocol T = 0 + * This parameter can be one of the following values: + * USART_ISO7816_T0_MAX_ITERATION_0 - USART max_iteration with 0 times + * USART_ISO7816_T0_MAX_ITERATION_1 - USART max_iteration with 1 times + * USART_ISO7816_T0_MAX_ITERATION_2 - USART max_iteration with 2 times + * USART_ISO7816_T0_MAX_ITERATION_3 - USART max_iteration with 4 times + * USART_ISO7816_T0_MAX_ITERATION_5 - USART max_iteration with 5 times + * USART_ISO7816_T0_MAX_ITERATION_6 - USART max_iteration with 6 times + * USART_ISO7816_T0_MAX_ITERATION_7 - USART max_iteration with 7 times + * @retval None + */ +void USART_MaxIteration_Cfg(USART_TypeDef* USARTx, uint32_t USART_MAXIteration) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ISO7816_T0_MAX_ITERATION(USART_MAXIteration)); + + /* Clear the maximum number of automatic iteration value by clearing the MAX_ITERATION[26:24] + bits in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_MAX_ITERATION); + + /* Set the maximum number of automatic iteration value by setting the MAX_ITERATION[26:24] + bits in the MR register */ + USARTx->MR |= (uint32_t)((uint32_t)USART_MAXIteration); +} + +/** + * @brief Disable Successive NACK + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx disable successive NACK. + * This parameter can be: + * @arg ENABLE : Successive parity errors are counted up to the value + * specificed in the MAX_ITERATION field. + * @arg DISABLE: NACK is sent on the ISO line as soon as a parity error + * occurs in the received character (unless INACK is set). + * @retval None + */ +void USART_DsNack_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the disable successive NACK function by setting DSNACK bit in the MR register */ + USARTx->MR |= USART_MR_DSNACK; + } + else + { + /* Disable the disable successive NACK function by clearing DSNACK bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_DSNACK); + } +} + +/** + * @brief Inhibit non acknowledge + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx inhibit non acknowledge. + * This parameter can be: + * @arg ENABLE : The NACK is not generated. + * @arg DISABLE: The NACK is generated. + * @retval None + */ +void USART_INack_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the inhibit non acknowledge function by setting INACK bit in the MR register */ + USARTx->MR |= USART_MR_INACK; + } + else + { + /* Disable the inhibit non acknowledge function by clearing INACK bit in the MR register */ + USARTx->MR &= (uint32_t)~((uint32_t)USART_MR_INACK); + } +} + +/** + * @brief Fi over Di ratio value + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_FiDiRatio: user config Fi_Di_Ratio + * @param USART_BaudRate: user confige baudrate + * @note This function has to be called when user need to change Fi_Di_Ratio + * after USART_Init() function, CD fields of BRGR change as bellow: + * CD = MCK / (BaudRate * FiDiRatio). + * @retval None + */ +void USART_FiDiRatio_Cfg(USART_TypeDef* USARTx, uint32_t USART_FiDiRatio, uint32_t USART_BaudRate) +{ + uint32_t clock_divider = 0, apbclock = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + if ((USARTx == USART1) || (USARTx == USART6)) + { + assert_param(IS_USART_BAUDRATE(USART_BaudRate)); + } + else if ((USARTx == USART2) || (USARTx == USART3)) + { + assert_param(IS_USART_BAUDRATE_APB1(USART_BaudRate)); + } + + assert_param(IS_USART_FIDIRATIO(USART_FiDiRatio)); + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + /* Get USARTx work clock*/ + if (USARTx == USART1) + { + apbclock = RCC_ClocksStatus.P2CLK_Frequency; + } + else if (USARTx == USART2) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (USARTx == USART3) + { + apbclock = RCC_ClocksStatus.PCLK_Frequency ; + } + else if (USARTx == USART6) + { + apbclock = RCC_ClocksStatus.P2CLK_Frequency; + } + + /* BaudRate not equal 0*/ + if (USART_BaudRate > 0) + { + /* ISO7816 Mode*/ + if ((((USARTx->MR)&USART_MR_USART_MODE) == USART_MODE_OPERATION_ISO7816_T_0) || + (((USARTx->MR)&USART_MR_USART_MODE) == USART_MODE_OPERATION_ISO7816_T_1)) + { + clock_divider = (uint32_t)(((apbclock) / ((USART_BaudRate) * USART_FiDiRatio))); + } + } + + /* Clear the USART clock divider by clearing the CD[15:0] bits in the BRGR register */ + USARTx->BRGR &= (uint32_t)~((uint32_t)USART_BRGR_CD); + + /* Set the USART clock divider by setting the CD[15:0] bits in the BRGR register */ + USARTx->BRGR |= ((uint32_t)clock_divider); + + /* Clear the USART Fi_Di_Ration by clearing the FI_DI_RATIO[15:0] bits in the FIDI register */ + USARTx->FIDI &= (uint32_t)~((uint32_t)USART_FIDI_FI_DI_RATIO); + + /* Set the USART Fi_Di_Ration by setting the FI_DI_RATIO[15:0] bits in the FIDI register */ + USARTx->FIDI |= ((uint32_t)USART_FiDiRatio); +} + +/** + * @brief Returns the number of error by the USARTx peripheral. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @note Total number of errors that occurred during an ISO7816 transfer. + * This register automatically clears when read. + * @retval The number of error. + */ +uint32_t USART_GetNumberOfError(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Return the number of errors that occured during an ISO7816 transfer */ + return (uint32_t)((USARTx->NER)); +} + +/** + * @} + */ + +/** @defgroup USART IrDA mode cfg functions + * @brief USART IrDA mode mode configuration function + * +@verbatim + =============================================================================== + ##### IrDA Mode Functions ##### + =============================================================================== + [..] This subsection provides a IrDA mode function. + + [..] + + (#) The IrDA mode cfg API's : + (++) USART_IrDAFilter_Cfg() + +@endverbatim + * @{ + */ + +/** + * @brief IrDA Filter + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_IrDAFilter: The IRDA_FILTER value must be defined to meet the + * following criteria: + * tMCK * (IRDA_FILTER + 3) < 1.41us + * @retval None + */ +void USART_IrDAFilter_Cfg(USART_TypeDef* USARTx, uint32_t USART_IrDAFilter) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_IF(USART_IrDAFilter)); + + /* Clear the IrDA filter value by clearing the IRDA_FILTER[7:0] bits in the IF register */ + USARTx->IF &= (uint32_t)~((uint32_t)USART_IF_IRDA_FILTER); + + /* Set the IrDA filter value by setting the IRDA_FILTER[7:0] bits in the IF register */ + USARTx->IF |= (uint32_t)((uint32_t)USART_IrDAFilter); +} + +/** + * @} + */ + +/** @defgroup USART LIN mode cmd, cfg, and read functions + * @brief USART LIN mode mode command, configuration and read functions + * +@verbatim + =============================================================================== + ##### LIN Mode Functions ##### + =============================================================================== + [..] This subsection provides a set of LIN mode functions. + + [..] + + (#) The LIN mode cmd API's : + (++) USART_LINWKUP_Cmd() + (++) USART_LINABT_Cmd() + + (#) The LIN mode cfg API's : + (++) USART_Write_LINIR_In_LIN_Master() + (++) USART_SYNCDisable_Cfg() + (++) USART_PDCMode_Cfg() + (++) USART_DataLengthControl_Cfg() + (++) USART_WkupType_Cfg() + (++) USART_FrameSlotDisable_Cfg() + (++) USART_DataLengthMode_Cfg() + (++) USART_CheckSumType_Cfg() + (++) USART_CheckSumDisable_Cfg() + (++) USART_ParityDisable_Cfg() + (++) USART_NodeAction_Cfg() + + (#) The LIN mode read API's : + (++) USART_Read_LINIR_In_LIN_Slave() + (++) USART_LINBaudRate() +@endverbatim + * @{ + */ + +/** + * @brief Send LIN Wakeup Signal. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx send LIN wakeup signal. + * This parameter can be: + * @arg ENABLE : Sends a wakeup signal on LIN bus + * @arg DISABLE: No effect + * @retval None + */ +void USART_LINWKUP_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Sends a wakeup signal on LIN bus by setting LINWKUP bit in the CR register */ + USARTx->CR |= USART_CR_LINWKUP; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_LINWKUP); + } +} + +/** + * @brief Abort LIN Transmission. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx abort LIN transmission. + * This parameter can be: + * @arg ENABLE : Abort LIN transmission + * @arg DISABLE: No effect + * @retval None + */ +void USART_LINABT_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Abort the LIN transmission by setting LINABT bit in the CR register */ + USARTx->CR |= USART_CR_LINABT; + } + else + { + /* No effect */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_LINABT); + } +} + +/** + * @brief Write identifier character in LIN master mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_LINIR_Data: if USART_OperationMode = 0xA (Master node configure), + * USART_LINIR_Data is read-write and its value is the + * identifier character to be transmitted. + * @note This function has to be called after calling USART_Init() function + * in order to have correct identifer value in LIN master mode. + * @retval None + */ +void USART_Write_LINIR_In_LIN_Master(USART_TypeDef* USARTx, uint32_t USART_LINIR_Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_LINIR_WR(USART_LINIR_Data)); + + /* Clear the identifier value to be transmitted in LIN master node by clearing + the IDCHR[7:0] bits in the LINIR register */ + USARTx->LINIR &= (uint32_t)~((uint32_t)USART_LINIR_IDCHR); + + /* Set the identifier value to be transmitted in LIN master node by setting + the IDCHR[7:0] bits in the LINIR register */ + USARTx->LINIR |= (uint32_t)((uint32_t)USART_LINIR_Data); +} + +/** + * @brief Synchronization disable in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN synchronization disable, + * applicable if USART operates in LIN mode. + * This parameter can be: + * @arg ENABLE : The synchronization procedure is not performed in LIN + * slave node configure. + * @arg DISABLE: The synchronization procedure is performed in LIN + * slave node configure. + * @retval None + */ +void USART_SYNCDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the synchronization procedure's disable by setting SYNCDIS bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_SYNCDIS; + } + else + { + /* Disable the synchronization procedure's disable by clearing SYNCDIS bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_SYNCDIS); + } +} + +/** + * @brief DMA mode in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN DMA mode, + * applicable if USART operates in LIN mode. + * This parameter can be: + * @arg ENABLE : The LIN mode register US_LINMR (excepting that flag) + * is written by the DMA. + * @arg DISABLE: The LIN mode register US_LINMR is not written by the DMA. + * @retval None + */ +void USART_PDCMode_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the DMA written of LINMR by setting PDCM bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_PDCM; + } + else + { + /* Disable the DMA written of LINMR by clearing PDCM bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_PDCM); + } +} + +/** + * @brief Data length control in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_DataLengthControl: (0 - 255) Defines the response data length + * if USART_DataLengthMode = 0, in that case + * the response data length is equal to + * USART_DataLengthControl + 1 bytes; + * @retval None + */ +void USART_DataLengthControl_Cfg(USART_TypeDef* USARTx, uint32_t USART_DataLengthControl) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DLC(USART_DataLengthControl)); + + /* Clear the response data length value of LIN mode (USART_DataLengthMode = 0) + by clearing the DLC[15:8] bits in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_DLC); + + /* Set the response data length value of LIN mode (USART_DataLengthMode = 0) + by setting the DLC[15:8] bits in the LINMR register */ + USARTx->LINMR |= (uint32_t)((uint32_t)USART_DataLengthControl << 8U); +} + +/** + * @brief Wakeup signal type in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN wakeup signal type. + * This parameter can be: + * @arg ENABLE : Setting the bit LINWKUP in the control register send + * a LIN 1.3 wakeup signal. + * @arg DISABLE: Setting the bit LINWKUP in the control register send + * a LIN 2.0 wakeup signal. + * @retval None + */ +void USART_WkupType_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN 1.3 wakeup signal as the wakeup type to send by setting WKUPTYP + bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_WKUPTYP; + } + else + { + /* Disable the LIN 1.3 wakeup signal as the wakeup type to send by clearing WKUPTYP + bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_WKUPTYP); + } +} + +/** + * @brief Frame slot mode disable in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN frame slot mode disable. + * This parameter can be: + * @arg ENABLE : The frame slot mode is disabled. + * @arg DISABLE: The frame slot mode is enabled. + * @retval None + */ +void USART_FrameSlotDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the frame slot mode's disable by setting FSDIS bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_FSDIS; + } + else + { + /* Disable the frame slot mode's disable by clearing FSDIS bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_FSDIS); + } +} + +/** + * @brief Data length mode in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN data length mode. + * This parameter can be: + * @arg ENABLE : The response data length is defined by the bits 5 + * and 6 of the identifier (IDCHR in US_LINIR). + * @arg DISABLE: The response data length is defined by the field + * DLC of US_LINMR register. + * @retval None + */ +void USART_DataLengthMode_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the response data length is defined by the bits 5 and 6 of the identifier + (IDCHR in US_LINIR) by setting DLM bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_DLM; + } + else + { + /* Disable the response data length is defined by the bits 5 and 6 of the identifier + (IDCHR in US_LINIR) by clearing DLM bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_DLM); + } +} + +/** + * @brief Checksum type in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN checksum type. + * This parameter can be: + * @arg ENABLE : LIN 1.3 "Classic" checksum. + * @arg DISABLE: LIN 2.0 "Enhanced" checksum. + * @retval None + */ +void USART_CheckSumType_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the LIN 1.3 "Classic" checksum type by setting CHKTYP bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_CHKTYP; + } + else + { + /* Disable the LIN 1.3 "Classic" checksum type by clearing CHKTYP bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_CHKTYP); + } +} + +/** + * @brief Checksum disable in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN checksum disable. + * This parameter can be: + * @arg ENABLE : Whatever the node configuration is, the checksum is + * not computed/sent and it is not checked. + * @arg DISABLE: In Master node configuration, the cheksum is computed + * and sent automatically. In Slave node configure, the + * checksum is checked automatically. + * @retval None + */ +void USART_CheckSumDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the checksum's disable by setting CHKDIS bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_CHKDIS; + } + else + { + /* Disable the checksum's disable by clearing CHKDIS bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_CHKDIS); + } +} + +/** + * @brief Parity disable in LIN mode + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx LIN parity disable. + * This parameter can be: + * @arg ENABLE : Whatever the node configuration is, the identifier + * parity is not computed/sent and it is not checked. + * @arg DISABLE: In Master node configuration, the identifier parity + * is computed and sent automatically. In Master node + * and Slave node configuration, the parity is checked + * automatically. + * @retval None + */ +void USART_ParityDisable_Cfg(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the identifier parity's disable by setting PARDIS bit in the LINMR register */ + USARTx->LINMR |= USART_LINMR_PARDIS; + } + else + { + /* Disable the identifier parity's disable by clearing PARDIS bit in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_PARDIS); + } +} + +/** + * @brief LIN node action + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_NodeAction: LIN node action + * This parameter can be one of the following values: + * USART_NODE_ACTIVE_PUBLISH - PUBLISH ; The USART transmits the response. + * USART_NODE_ACTIVE_SUBSCRIBE - SUBSCRIBE; The USART receives the response. + * USART_NODE_ACTIVE_IGNORE - IGNORE ; The USART does not transmits and + * does not receives the response. + * @retval None + */ +void USART_NodeAction_Cfg(USART_TypeDef* USARTx, uint32_t USART_NodeAction) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_NODE_ACTIVE(USART_NodeAction)); + + /* Clear the LIN node action by clearing the NACT[1:0] bits in the LINMR register */ + USARTx->LINMR &= (uint32_t)~((uint32_t)USART_LINMR_NACT); + + /* Set the LIN node action by setting the NACT[1:0] bits in the LINMR register */ + USARTx->LINMR |= (uint32_t)((uint32_t)USART_NodeAction); +} + +/** + * @brief Returns the identifier character by the USARTx peripheral. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @note If USART_OperationMode = 0xB (Slave node configuration), IDCHR[7:0] + * in US_LINIR is read-only and its value is the last identifier character + * that has been received. + * @retval The last identifier character. + */ +uint32_t USART_Read_LINIR_In_LIN_Slave(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Return the last identifier character if operation in slave node configuration*/ + return (uint32_t)((USARTx->LINIR)); +} + +/** + * @brief Returns the baud rate value after the synchronization process completion + * by the USARTx peripheral. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @note The return value [18:16] bits is LINFP[18:16], which means fractional part + * after synchronization. + * @note The return value [15: 0] bits is LINCD[15: 0], which means clock driver + * after synchronization. + * @retval The baud rate value after the synchronization process completion. + */ +uint32_t USART_LINBaudRate(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Return the baud rate value after the synchronization process completion */ + return (uint32_t)((USARTx->LINBRR)); +} + +/** + * @} + */ + +/** @defgroup USART write protection register functions + * @brief USART write protection register mode functions + * +@verbatim + =============================================================================== + ##### Write Protection Register Mode Functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to operate in write + protection register mode. + + [..] The protected register are: + (++) US_MR, which offset address is 0x0004 + (++) US_BRGR, which offset address is 0x0020 + (++) US_RTOR, which offset address is 0x0024 + (++) US_TTGR, which offset address is 0x0028 + (++) US_FIDI, which offset address is 0x0040 + (++) US_IF, which offset address is 0x004C + + [..] + + (#) The USART write protection register mode configure API's : + (++) USART_WriteProtectionRegisterConfig() + + (#) The USART write protection violation status (WPVS bit of US_WPSR) API's : + (++) USART_GetWriteProtectionRegisterStatus() + + (#) The USART get write protection violation source API's : + (++) USART_GetWriteProtectionRegisterSource() + + (#) The USART clear write protection register US_WPSR fields API's : + (++) USART_ClearWPSRField() +@endverbatim + * @{ + */ + +/** + * @brief Write protect enable + * @param USARTx_WP: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx write protect enable. + * This parameter can be: + * @arg ENABLE : Enables the write protect if WPKEY corresponds to 0x555341. + * @arg DISABLE: Disables the write protect if WPKEY corresponds to 0x555341. + * @retval None + */ +void USART_WriteProtectionRegisterConfig(USART_WP_TypeDef* USARTx_WP, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH_WP(USARTx_WP)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enables the write protect if WPKEY corresponds to 0x555341 by setting WPEN bit in the WPMR register */ + USARTx_WP->WPMR = (USART_WPMR_WPEN | (0x555341 << 8U)); + } + else + { + /* Disables the write protect if WPKEY corresponds to 0x555341 by clearing WPEN bit in the WPMR register */ + USARTx_WP->WPMR = 0x55534100; + } +} + +/** + * @brief Checks whether the USART write protect violation is set or not. + * @param USARTx_WP: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @retval The new state of write protect violation status. + */ +FlagStatus USART_GetWriteProtectionRegisterStatus(USART_WP_TypeDef* USARTx_WP) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH_WP(USARTx_WP)); + + if ((USARTx_WP->WPSR & USART_WPSR_WPVS) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Returns the write protect violation source by the USARTx_WP peripheral. + * @param USARTx_WP: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @note When WPVS bit of WPSR register is active, this field indicates the + * write-protected register (through address offset or code) in which a + * write access has been attempted. + * @retval The write protect violation source. + */ +uint32_t USART_GetWriteProtectionRegisterSource(USART_WP_TypeDef* USARTx_WP) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH_WP(USARTx_WP)); + + /* Return the write protect violation source, which is WPVSRC[23:8] bits of US_WPSR */ + return (uint32_t)((USARTx_WP->WPSR) >> 8U); +} + +/** + * @brief Reading US_WPSR automatically clears all fields. + * @param USARTx_WP: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @retval US_WPSR value. + */ +uint32_t USART_ClearWPSRField(USART_WP_TypeDef* USARTx_WP) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH_WP(USARTx_WP)); + + /* Reading US_WPSR automatically clears all fields */ + return (uint32_t)(USARTx_WP->WPSR); +} + +/** + * @} + */ + +/** @defgroup USART Transfers functions + * @brief USART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### Data Transfers Functions ##### + =============================================================================== + [..] This subsection provides a set of functions allowing to manage the USART data transfers. + + [..] + + (#) The USART data transmit API's : + (++) USART_Transmit() + + (#) The USART data receive API's : + (++) USART_Receive() +@endverbatim + * @{ + */ + +/** + * @brief Transmits single data through the USARTx peripheral. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param Data: the data to transmit. + * @retval None + */ +void USART_Transmit(USART_TypeDef* USARTx, uint16_t Data) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_DATA(Data)); + + /* Transmit Data */ + USARTx->THR = (Data & (uint16_t)0x01FF); +} + +/** + * @brief Returns the most recent received data by the USARTx peripheral. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @retval The received data. + */ +uint16_t USART_Receive(USART_TypeDef* USARTx) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + + /* Received Data */ + return (uint16_t)(USARTx->RHR & (uint16_t)0x01FF); +} + +/** + * @} + */ + +/** @defgroup USART DMA Transfers functions + * @brief USART DMA Transmit and Receive enable functions + * +@verbatim + =============================================================================== + ##### DMA Transfer Management Functions ##### + =============================================================================== + [..] This subsection provides a set of functions about DMA Tx/Rx enable functions. + + [..] + + (#) The USART DMA enable transmitter API's : + (++) USART_DMATxEnable_Cmd() + + (#) The USART DMA enable receiver API's : + (++) USART_DMARxEnable_Cmd() +@endverbatim + * @{ + */ + +/** + * @brief DMA enable transmitter + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx DMA enable transmitter. + * This parameter can be: + * @arg ENABLE : DMA mode is enable for transmission. + * @arg DISABLE: DMA mode is disable for transmission. + * @retval None + */ +void USART_DMATxEnable_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the transmission function of DMA mode by setting DMAT bit in the CR register */ + USARTx->CR |= USART_CR_DMAT_EN; + } + else + { + /* Disable the transmission function of DMA mode by clearing DMAT bit in the CR register */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_DMAT_EN); + } +} + +/** + * @brief DMA enable receiver + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx DMA enable receiver. + * This parameter can be: + * @arg ENABLE : DMA mode is enable for reception. + * @arg DISABLE: DMA mode is disable for reception. + * @retval None + */ +void USART_DMARxEnable_Cmd(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + /* Enable the reception function of DMA mode by setting DMAR bit in the CR register */ + USARTx->CR |= USART_CR_DMAR_EN; + } + else + { + /* Disable the reception function of DMA mode by clearing DMAR bit in the CR register */ + USARTx->CR &= (uint32_t)~((uint32_t)USART_CR_DMAR_EN); + } +} + +/** + * @} + */ + +/** @defgroup USART low-power management functions + * @brief USART low-power sleep wakeup functions + * +@verbatim + =============================================================================== + ##### Low-Power SLEEP Wakeup Management Functions ##### + =============================================================================== + [..] This subsection provides a set of functions about USART low-power wakeup + management functions. + + [..] + + (#) The USART Low-Power SLEEP wakeup configurations API's : + (++) USART_LowPowerSleepWkupConfig() +@endverbatim + * @{ + */ + +/** + * @brief USART Low-Power SLEEP wakeup configurations + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param NewState: new state of the USARTx Low-Power SLEEP wakeup configurations. + * This parameter can be: + * @arg ENABLE : Enable USARTx module clock in SLEEP mode. + * @arg DISABLE: Disable USARTx module clock in SLEEP mode. + * @retval None + */ +void USART_LowPowerSleepWkupConfig(USART_TypeDef* USARTx, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (USARTx == USART1) + { + if (NewState != DISABLE) + { + /* Enable the USART1 module clock in SLEEP mode by setting USART1LPEN bit in the + RCC_APB2LPENR register */ + RCC_APB2PeriphLpenCmd(RCC_APB2PeriphLpen_USART1, ENABLE); + } + else + { + /* Disable the USART1 module clock in SLEEP mode by clearing USART1LPEN bit in the + RCC_APB2LPENR register */ + RCC_APB2PeriphLpenCmd(RCC_APB2PeriphLpen_USART1, DISABLE); + } + } + else if (USARTx == USART2) + { + if (NewState != DISABLE) + { + /* Enable the USART2 module clock in SLEEP mode by setting USART2LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART2, ENABLE); + } + else + { + /* Disable the USART2 module clock in SLEEP mode by clearing USART2LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART2, DISABLE); + } + } + else if (USARTx == USART3) + { + if (NewState != DISABLE) + { + /* Enable the USART3 module clock in SLEEP mode by setting UART3LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART3, ENABLE); + } + else + { + /* Disable the USART3 module clock in SLEEP mode by clearing UART3LPEN bit in the + RCC_APB1LPENR register */ + RCC_APB1PeriphLpenCmd(RCC_APB1PeriphLpen_UART3, DISABLE); + } + } + else if (USARTx == USART6) + { + if (NewState != DISABLE) + { + /* Enable the USART6 module clock in SLEEP mode by setting USART6LPEN bit in the + RCC_APB2LPENR register */ + RCC_APB2PeriphLpenCmd(RCC_APB2PeriphLpen_USART6, ENABLE); + } + else + { + /* Disable the USART6 module clock in SLEEP mode by clearing USART6LPEN bit in the + RCC_APB2LPENR register */ + RCC_APB2PeriphLpenCmd(RCC_APB2PeriphLpen_USART6, DISABLE); + } + } +} + +/** + * @} + */ + +/** @defgroup USART Transfers functions + * @brief USART Transmit and Receive functions + * +@verbatim + =============================================================================== + ##### Interrupts And Flags Management Functions ##### + =============================================================================== + [..] This subsection provides a set of functions, which is about the USART + interrupts and the flags management. + + [..] + + (#) The USART interrupts enable API's : + (++) USART_ITConfig() + + (#) The USART flags status check API's : + (++) USART_GetFlagStatus() + + (#) The USART flags clear API's : + (++) USART_ClearFlag() + + (#) The USART interrupt mask check API's : + (++) USART_GetITStatus() + + (#) The USART interrupt disable API's : + (++) USART_ITDisableConfig() +@endverbatim + * @{ + */ + +/** + * @brief Enables the specified USART interrupts. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled. + * This parameter can be one of the following values: + * @arg USART_IT_CTSIC : USART Clear to Send input interruption + * @arg USART_IT_DSRIC : USART Data Set Ready input change interruption + * @arg USART_IT_NACK : USART non acknowledge interruption + * @arg USART_IT_ITER : USART max number of repetitions reached interruption + * @arg USART_IT_TXEMPTY: USART transmitter empty interruption + * @arg USART_IT_TIMEOUT: USART receiver time-out interruption + * @arg USART_IT_PARE : USART parity error interruption + * @arg USART_IT_FRAME : USART framing error interruption + * @arg USART_IT_OVER : USART overrun error interruption + * @arg USART_IT_RXBRK : USART break receive/end of break interruption + * @arg USART_IT_TXRDY : USART transmitter ready interruption + * @arg USART_IT_RXRDY : USART receiver ready interruption + * @arg USART_IT_UNRE : USART LIN header timeout error interruption + * @arg USART_IT_LINHTE : USART LIN header timeout error interruption + * @arg USART_IT_LINSTE : USART LIN synch tolerance eror interruption + * @arg USART_IT_LINSNRE: USART LIN slave not response error interruption + * @arg USART_IT_LINCE : USART LIN checksum error interruption + * @arg USART_IT_LINIPE : USART LIN identifier parity error interruption + * @arg USART_IT_LINISFE: USART LIN inconsistent synch field error interruption + * @arg USART_IT_LINBE : USART LIN bit error interruption + * @arg USART_IT_LINTC : USART LIN transfer completed interruption + * @arg USART_IT_LINID : USART LIN identifier sent or LIN identifier received interruption + * @arg USART_IT_LINBK : USART LIN break sent or LIN break received interruption + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: + * @arg ENABLE : Enable corresponding interrupt. + * @arg DISABLE: No effect. + * @retval None + * @retval None + */ +void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_ENABLE_IT(USART_IT)); + assert_param(IS_FUNCTIONAL_STATE(NewState)); + + if (NewState != DISABLE) + { + USARTx->IER |= (uint32_t)((uint32_t)USART_IT); + } + else + { + USARTx->IER &= (uint32_t)~((uint32_t)USART_IT); + } +} + +/** + * @brief Checks whether the specified USART flag is set or not. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_FLAG: specifies the flag to check. + * This parameter can be one of the following values: + * @arg USART_FLAG_CTS : image of CTS input + * @arg USART_FLAG_DSR : image of DSR input + * @arg USART_FLAG_CTSIC : Clear to Send input change flag + * @arg USART_FLAG_DSRIC : Data Set Ready input change flag + * @arg USART_FLAG_NACK : non acknowledge interrupt + * @arg USART_FLAG_ITER : max number of repetitions reached + * @arg USART_FLAG_TXEMPTY: transmitter empty + * @arg USART_FLAG_TIMEOUT: receiver time-out + * @arg USART_FLAG_PARE : parity error + * @arg USART_FLAG_FRAME : framing error + * @arg USART_FLAG_OVER : overrun error + * @arg USART_FLAG_RXBRK : break receive/end of break + * @arg USART_FLAG_TXRDY : transmitter ready + * @arg USART_FLAG_RXRDY : receiver ready + * @arg USART_FLAG_UNRE : underrun error + * @arg USART_FLAG_LINHTE : LIN header timeout error + * @arg USART_FLAG_LINSTE : LIN synch tolerance eror + * @arg USART_FLAG_LINSNRE: LIN slave not response error + * @arg USART_FLAG_LINCE : LIN checksum error + * @arg USART_FLAG_LINIPE : LIN identifier parity error + * @arg USART_FLAG_LINISFE: LIN inconsistent synch field error + * @arg USART_FLAG_LINBE : LIN bit error + * @arg USART_FLAG_LINBLS : LIN bus line status + * @arg USART_FLAG_LINTC : LIN transfer completed + * @arg USART_FLAG_LINID : LIN identifier sent or LIN identifier received + * @arg USART_FLAG_LINBK : LIN break sent or LIN break received + * @retval The new state of USART_FLAG (SET or RESET). + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_FLAG(USART_FLAG)); + + if ((USARTx->CSR & USART_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears the USARTx's pending flags. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_FLAG: specifies the flag to clear. + * This parameter can be any combination of the following values: + * @arg USART_CLEAR_CTSIC : Clear to Send input interrupt clear + * @arg USART_CLEAR_DSRIC : Data Set Ready input change clear + * @arg USART_CLEAR_NACK : non acknowledge interrupt clear + * @arg USART_CLEAR_ITER : max number of repetitions reached interrupt clear + * @arg USART_CLEAR_TXEMPTY: transmitter empty interrupt clear + * @arg USART_CLEAR_TIMEOUT: receiver time-out interrupt clear + * @arg USART_CLEAR_PARE : parity error interrupt clear + * @arg USART_CLEAR_FRAME : framing error interrupt clear + * @arg USART_CLEAR_OVER : overrun error interrupt clear + * @arg USART_CLEAR_RXBRK : break receive/end of break interrupt clear + * @arg USART_CLEAR_TXRDY : transmitter ready interrupt clear + * @arg USART_CLEAR_RXRDY : receiver ready interrupt clear + * @arg USART_CLEAR_UNRE : underrun error interrupt clear + * @arg USART_CLEAR_LINHTE : LIN header timeout error interrupt clear + * @arg USART_CLEAR_LINSTE : LIN synch tolerance eror interrupt clear + * @arg USART_CLEAR_LINSNRE: LIN slave not response error interrupt clear + * @arg USART_CLEAR_LINCE : LIN checksum error interrupt clear + * @arg USART_CLEAR_LINIPE : LIN identifier parity error interrupt clear + * @arg USART_CLEAR_LINISFE: LIN inconsistent synch field error interrupt clear + * @arg USART_CLEAR_LINBE : LIN bit error interrupt clear + * @arg USART_CLEAR_LINTC : LIN transfer completed interrupt clear + * @arg USART_CLEAR_LINID : LIN identifier sent or LIN identifier received interrupt clear + * @arg USART_CLEAR_LINBK : LIN break sent or LIN break received interrupt clear + * @note CTS image of CTS input bit is cleared when CTS pin is 0. + * @note DST image of DSR input bit is cleared when DSR pin is 0. + * @note LINBLS LIN bus line status bit is cleared when LINRX pin is 0. + * @note TXEMPTY flag bit also can be cleared by a write to the US_THR register (USART_Transmit()). + * @note TXRDY flag bit also can be cleared by a write to the US_THR register (USART_Transmit()). + * @note RXRDY flag bit also can be cleared by a read to the US_RHR register (USART_Receive()). + * @retval None + */ +void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_FLAG(USART_FLAG)); + + USARTx->CR |= (uint32_t)USART_FLAG; +} + +/** + * @brief Checks whether the specified USART interrupt has enabled or disabled. + * @param USARTx: where x can be [1, 2, 3, 6] to select the USART peripheral. + * @param USART_IT: specifies the USART interrupt source to check. + * This parameter can be one of the following values: + * @arg USART_MASK_CTSIC : mask to Send input interrupt mask + * @arg USART_MASK_DSRIC : Data Set Ready input change mask + * @arg USART_MASK_NACK : non acknowledge interrupt mask + * @arg USART_MASK_ITER : max number of repetitions reached interrupt mask + * @arg USART_MASK_TXEMPTY: transmitter empty interrupt mask + * @arg USART_MASK_TIMEOUT: receiver time-out interrupt mask + * @arg USART_MASK_PARE : parity error interrupt mask + * @arg USART_MASK_FRAME : framing error interrupt mask + * @arg USART_MASK_OVER : overrun error interrupt mask + * @arg USART_MASK_RXBRK : break receive/end of break interrupt mask + * @arg USART_MASK_TXRDY : transmitter ready interrupt mask + * @arg USART_MASK_RXRDY : receiver ready interrupt mask + * @arg USART_MASK_UNRE : underrun error interrupt mask + * @arg USART_MASK_LINHTE : LIN header timeout error interrupt mask + * @arg USART_MASK_LINSTE : LIN synch tolerance eror interrupt mask + * @arg USART_MASK_LINSNRE: LIN slave not response error interrupt mask + * @arg USART_MASK_LINCE : LIN checksum error interrupt mask + * @arg USART_MASK_LINIPE : LIN identifier parity error interrupt mask + * @arg USART_MASK_LINISFE: LIN inconsistent synch field error interrupt mask + * @arg USART_MASK_LINBE : LIN bit error interrupt mask + * @arg USART_MASK_LINTC : LIN transfer completed interrupt mask + * @arg USART_MASK_LINID : LIN identifier sent or LIN identifier received interrupt mask + * @arg USART_MASK_LINBK : LIN break sent or LIN break received interrupt mask + * @retval The new state of USART_IT (SET or RESET). + */ +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT) +{ + ITStatus bitstatus = RESET; + + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_GET_IT(USART_IT)); + + if ((USARTx->IMR & USART_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/** + * @brief USARTx's interrupt disable configure. + * @param USARTx: where x can be [1, 2. 3, 6] to select the USART peripheral. + * @param USART_IT: specifies the interrupt pending bit to clear. + * This parameter can be one of the following values: + * @arg USART_DIS_CTSIC : disable to Send input interrupt disable + * @arg USART_DIS_DSRIC : Data Set Ready input change disable + * @arg USART_DIS_NACK : non acknowledge interrupt disable + * @arg USART_DIS_ITER : max number of repetitions reached interrupt disable + * @arg USART_DIS_TXEMPTY: transmitter empty interrupt disable + * @arg USART_DIS_TIMEOUT: receiver time-out interrupt disable + * @arg USART_DIS_PARE : parity error interrupt disable + * @arg USART_DIS_FRAME : framing error interrupt disable + * @arg USART_DIS_OVER : overrun error interrupt disable + * @arg USART_DIS_RXBRK : break receive/end of break interrupt disable + * @arg USART_DIS_TXRDY : transmitter ready interrupt disable + * @arg USART_DIS_RXRDY : receiver ready interrupt disable + * @arg USART_DIS_UNRE : underrun error interrupt disable + * @arg USART_DIS_LINHTE : LIN header timeout error interrupt disable + * @arg USART_DIS_LINSTE : LIN synch tolerance eror interrupt disable + * @arg USART_DIS_LINSNRE: LIN slave not response error interrupt disable + * @arg USART_DIS_LINCE : LIN checksum error interrupt disable + * @arg USART_DIS_LINIPE : LIN identifier parity error interrupt disable + * @arg USART_DIS_LINISFE: LIN inconsistent synch field error interrupt disable + * @arg USART_DIS_LINBE : LIN bit error interrupt disable + * @arg USART_DIS_LINTC : LIN transfer completed interrupt disable + * @arg USART_DIS_LINID : LIN identifier sent or LIN identifier received interrupt disable + * @arg USART_DIS_LINBK : LIN break sent or LIN break received interrupt disable + * @param NewState: new state of the specified USARTx interrupts. + * This parameter can be: + * @arg ENABLE : Disable corresponding interrupt. + * @arg DISABLE: No effect. + * @retval None + */ +void USART_ITDisableConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState) +{ + /* Check the parameters */ + assert_param(IS_USART_ALL_PERIPH(USARTx)); + assert_param(IS_USART_CLEAR_IT(USART_IT)); + + if (NewState != DISABLE) + { + USARTx->IDR |= (uint32_t)((uint32_t)USART_IT); + } + else + { + USARTx->IDR &= (uint32_t)~((uint32_t)USART_IT); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usb_fs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usb_fs.c new file mode 100644 index 00000000000..c475e0bcffa --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usb_fs.c @@ -0,0 +1,1451 @@ +/** + ****************************************************************************** + * @file ft32f4xx_usb_fs.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * @version V1.0.0 + * @data 2025-05-28 + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + + (#) Call USB_FS_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HCD/PCD driver will call the right routines for its internal processes. + @endverbatim +****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "ft32f4xx_rcc.h" +#include "ft32f4xx_usb_fs.h" + +volatile uint32_t delayCount; + +/** @addtogroup FT32F4xx_USB_FS_DRIVER + * @{ + */ + +#if defined (PCD_FS_MODULE_ENABLED) || defined (HCD_FS_MODULE_ENABLED) +#if defined (USB_OTG_FS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_FS) +static USB_FS_StatusTypeDef USB_FS_CoreReset(void); + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_Exported_Functions USB OTG FS Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ + +void USB_FS_Delayms(uint32_t num) +{ + if(SysTick_Config(SystemCoreClock/1000)) + { + while (1); + } + uint32_t tickStart = delayCount; + while ((delayCount - tickStart) < num); +} + +/** + * @brief Initializes the USB OTG FS Core + * @param USB FS USB Instance + * @param cfg pointer to a USB_OTG_FS_CfgTypeDef structure that contains + * the configuration information for the specified USB_FS peripheral. + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_CoreInit(void) +{ + USB_FS_StatusTypeDef ret; + + + /* Init the UTMI interface */ + + /* Reset */ + ret = USB_FS_CoreReset(); + /* change srqxtune txvreftune otgtune compdistune */ + /* waiting for update */ + + return ret; +} + +/** + * @brief Reset the USB_FS Core + * @param USB_FS Selected device + * @retval USB_FS status + */ +static USB_FS_StatusTypeDef USB_FS_CoreReset(void) +{ + __IO uint32_t count = 0U; + + /* Core Soft Reset */ + count = 0U; + RCC_AHB2PeriphResetCmd(RCC_AHB2PeriphRst_USBOTGFS, ENABLE); + + USB_FS_Delayms(5U); /* update delay */ + + RCC_AHB2PeriphResetCmd(RCC_AHB2PeriphRst_USBOTGFS, DISABLE); + return USB_FS_OK; +} + + +/** + * @brief USB_FS_DevInit: Initializes the USB_OTG_FS controller registers + * for device mode + * @param USB_FS Selected device + * @param cfg pointer to a USB_OTG_FS_CfgTypeDef structure that contains + * the configuration information for the specified USB_FS peripheral. + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_DevInit(USB_OTG_FS_CfgTypeDef cfg) +{ + USB_FS_StatusTypeDef ret = USB_FS_OK ; + uint32_t i; + + for (i = 1U; i < cfg.endpoints; i++) + { + USB_FS->INDEX = i; + USB_FS->TXFIFO1 = 0U; + USB_FS->TXFIFO2 = 0U; + USB_FS->RXFIFO1 = 0U; + USB_FS->RXFIFO2 = 0U; + } + + /* initial ep0 */ + USB_FS_RstEP0Regs(); + + /* reset all ep register include flush fifo*/ + for (i = 1U; i < cfg.endpoints; i++) + { + if (USB_FS_RstEPRegs(i) != USB_FS_OK) + { + ret = USB_FS_ERROR; + } + } + + /* Clear all pending Device Interrupts */ + USB_FS_ClrEPInt(); + USB_FS->INTRTX1E = 0U; + USB_FS->INTRRX1E = 0U; + + USB_FS_ClrUSBInt(); + USB_FS->INTRUSBE = 0U; + + /* Enable the common interrupts */ + USB_FS_SetUSBInt(OTG_FS_INTRUSBE_SOFINTE | OTG_FS_INTRUSBE_RSTINTE | + OTG_FS_INTRUSBE_DISCINTE | OTG_FS_INTRUSBE_SREQINTE | + OTG_FS_INTRUSBE_VERRINTE); + + return ret; +} + +/** + * @brief USB_FS_IndexSel : select a endpoint + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_IndexSel(uint8_t epnum) +{ + uint8_t reg; + + reg = USB_FS->INDEX; + + if (reg != epnum) + { + USB_FS->INDEX = epnum; + + do + { + reg = USB_FS->INDEX; + } + while(reg != epnum); + } + + return USB_FS_OK; +} + +/** + * @brief USB_FS_RstEP0Regs : reset endpoint 0 registers + * @param none + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_RstEP0Regs(void) +{ + uint8_t reg; + + /* reset endpoint0 register */ + (void)USB_FS_FlushEp0Fifo(); + + USB_FS->CSR0 = 0U; + USB_FS->NAKLMT0 = 0U; + + return USB_FS_OK; +} + +/** + * @brief USB_FS_RstEPRegs : reset endpoint registers + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_RstEPRegs(uint8_t epnum) +{ + uint8_t reg; + + //USB_FS_IndexSel(epnum); + /* reset tx register */ + /* flush tx fifo */ + USB_FS_FlushTxFifo(epnum); + /* reset the data tog to 0 */ + USB_FS->TXCSR1 |= OTG_FS_TXCSR1_CLRDT; + /* clear autoset, iso, mode, frcdatatog */ + USB_FS->TXCSR2 = OTG_FS_TXCSR2_MODE; + /* config max tx endpoint data packet size */ + USB_FS->TXMAXP = USB_OTG_FS_MAX_PACKET_SIZE / 8; + + /* flush tx fifo */ + USB_FS_FlushRxFifo(epnum); + /* reset the data tog to 0 */ + USB_FS->RXCSR1 |= OTG_FS_RXCSR1_CLRDT; + /* clear autoclr, iso, autoreq */ + USB_FS->RXCSR2 = 0U; + /* config max rx endpoint data packet size */ + USB_FS->RXMAXP = USB_OTG_FS_MAX_PACKET_SIZE / 8; + + + return USB_FS_OK; +} +/** + * @brief USB_FS_Get_VBusStatus : + * get vbus stattus + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + * @retval USB_FS VBus status + */ +uint32_t USB_FS_Get_VBusStatus(void) +{ + uint8_t power; + + power = USB_FS->POWER; + + switch ((power & VBUS_MASK) >> 4) + { + case 0: + return VBUS_BELOW_SESSION_END; + + case 1: + return VBUS_ABOVE_SESSION_END; + + case 3: + return VBUS_ABOVE_AVALID; + + case 7: + return VBUS_ABOVE_VBUS_VALID; + } + + return (VBUS_ERROR); +} + +/** + * @brief USB_FS_Read_RxCount + * get received data size + * @param none + * @retval data size + */ +uint16_t USB_FS_Read_RxCount(void) +{ + uint16_t count = 0; + uint16_t count1 = 0; + uint16_t count2 = 0; + + count1 = USB_FS->RXCOUNT1; + count2 = USB_FS->RXCOUNT2; + + count = ((count2 << 8) | count1); + + return count; +} + +/** + * @brief USB_FS_Read_Count0 + * get received data size of endpoint0 + * @param none + @retval endpoint0 received data size + */ +uint8_t USB_FS_Read_Count0(void) +{ + uint8_t count = 0; + + count = USB_FS->COUNT0; + + return count; +} + + + +/** + * @brief USB_FS_GetCurrentFrame + * Return Host Current Frame number + * @param USB_FS Selected device + * @retval current frame number + */ +uint32_t USB_FS_GetCurrentFrame(void) +{ + uint32_t framel = 0U; + uint32_t frameh = 0U; + uint32_t frame = 0U; + + framel = USB_FS->FRAME1; + frameh = ((USB_FS->FRAME2) << 8); + frame = (framel | frameh); + + return frame; +} + +/** + * @brief USB_FS_Enable_EP + * enable endpoint transfer + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval none + */ +/* + * MGC_Enable_EP_DRC: + * Following a successful "SetConfig" operation, use MGC_Enable_EP_DRC + * to enable the endpoint registers in the DRC previosly bound by a + * ReturnEPMatch/SelectEP operation. Following this operation, live + * traffic can occur on the endpoint. Note that this can be called prior + * to "SetConfig". Either way, if SetConfig fails, the EPs previously + * bound must be released. + */ +void USB_FS_Enable_HEP(USB_OTG_FS_HEPTypeDef *hep) +{ + uint8_t epnum = (uint8_t)hep->epnum; + USB_FS_IndexSel(epnum); + + if (hep->ep_is_in == 1U) + { + if ((USB_FS->RXCSR1 & OTG_FS_RXCSR1_REQPKT) == 0U) + { + USB_FS->RXTYPE = (hep->epnum & 0x0f) | ((hep->ep_type & 0x03) << 4); /* set this endpoint */ + USB_FS->RXMAXP = (hep->max_packet / 8); + USB_FS->RXCSR1 = OTG_FS_RXCSR1_CLRDT; + } + } + else + { + if ((USB_FS->TXCSR1 & OTG_FS_TXCSR1_TXPKTRDY) == 0U) + { + USB_FS->TXTYPE = (hep->epnum & 0x0f) | ((hep->ep_type & 0x03) << 4); /* set this endpoint */ + USB_FS->TXMAXP = (hep->max_packet / 8); + USB_FS->TXCSR2 = OTG_FS_TXCSR2_MODE; + USB_FS->TXCSR1 = OTG_FS_TXCSR1_FFIFO; + USB_FS->TXCSR1 = OTG_FS_TXCSR1_FFIFO; + USB_FS->TXCSR1 = OTG_FS_TXCSR1_CLRDT; + } + } +} + + +void USB_FS_Enable_DEP(USB_OTG_FS_DEPTypeDef *dep) +{ + uint8_t epnum = (uint8_t)dep->num; + USB_FS_IndexSel(epnum); + + if (dep->is_in == 0U) + { + if ((USB_FS->RXCSR1 & OTG_FS_RXCSR1_REQPKT) == 0U) + { + USB_FS->RXTYPE = (dep->num & 0x0f) | ((dep->type & 0x03) << 4); /* set this endpoint */ + USB_FS->RXMAXP = (dep->maxpacket / 8); + + if (dep->type == EP_TYPE_ISOC) + { + USB_FS->RXCSR2 = OTG_FS_RXCSR2_AUTOCLR | OTG_FS_RXCSR2_ISO; + } + + USB_FS->RXCSR1 = OTG_FS_RXCSR1_CLRDT; + } + } + else + { + if ((USB_FS->TXCSR1 & OTG_FS_TXCSR1_TXPKTRDY) == 0U) + { + USB_FS->TXTYPE = (dep->num & 0x0f) | ((dep->type & 0x03) << 4); /* set this endpoint */ + USB_FS->RXMAXP = (dep->maxpacket / 8); + + if (dep->type == EP_TYPE_ISOC) + { + USB_FS->TXCSR2 = OTG_FS_TXCSR2_MODE | OTG_FS_TXCSR2_ISO; + } + else + { + USB_FS->TXCSR2 = OTG_FS_TXCSR2_MODE; + } + + USB_FS->TXCSR1 = OTG_FS_TXCSR1_FFIFO; + USB_FS->TXCSR1 = OTG_FS_TXCSR1_FFIFO; + USB_FS->TXCSR1 = OTG_FS_TXCSR1_CLRDT; + } + } +} + + + +/** + * @brief USB_FS_DEPStartXfer : setup and starts a transfer over an EP + * @param ep pointer to endpoint structure + * @retval none + */ +void USB_FS_DEPStartXfer(USB_OTG_FS_DEPTypeDef *dep) +{ + uint8_t epnum = (uint8_t)dep->num; + uint16_t pktcnt; + static uint8_t current_pid = 0; + USB_FS_IndexSel(epnum); + + /* tx endpoint */ + if (dep->is_in == 1U) + { + /* Zero Length Packet? */ + if (dep->xfer_len == 0U) + { + USB_FS->TXMAXP &= (~OTG_FS_TXMAXP_TXMAXPKT); + } + else + { + USB_FS->TXMAXP &= (~OTG_FS_TXMAXP_TXMAXPKT); + + USB_FS->TXMAXP = (OTG_FS_TXMAXP_TXMAXPKT & dep->xfer_len); + } + + if (current_pid == 0) + { + USB_FS->TXCSR1 = OTG_FS_TXCSR1_CLRDT; + current_pid = 1; + } + else + { + current_pid = 0; + } + + USB_FS_FIFOWrite(dep->xfer_buff, dep->num, (uint16_t)dep->xfer_len); + USB_FS->TXCSR1 = OTG_FS_TXCSR1_TXPKTRDY; + } + else /* rx endpoint */ + { + USB_FS->RXMAXP &= (~OTG_FS_RXMAXP_RXMAXPKT); + + if (dep->xfer_len > 0U) + { + dep->xfer_size = dep->xfer_len; + USB_FS->RXMAXP = (OTG_FS_RXMAXP_RXMAXPKT & dep->xfer_size); + } + + USB_FS->RXCSR1 = OTG_FS_RXCSR1_CLRDT; + } +} +/** + * @brief USB_FS_DEP0StartXfer : setup and starts a transfer over EP0 + * @param ep pointer to endpoint structure + * @retval none + */ +void USB_FS_DEP0StartXfer(USB_OTG_FS_DEPTypeDef *dep) +{ + USB_FS_IndexSel(0U); + uint32_t len = 0; + + /* tx endpoint */ + if (dep->is_in == 1U) + { + if (dep->xfer_len > dep->maxpacket) + { + dep->xfer_len = dep->maxpacket; + } + USB_FS_FIFOWrite(dep->xfer_buff, dep->num, (uint16_t)dep->xfer_len); + USB_FS->CSR0 |= OTG_FS_CSR0_TXPKTRDY; + + if (dep->xfer_len < 0x40U) + { + USB_FS->CSR0 |= OTG_FS_CSR0_DATAEND; + } + dep->xfer_buff += dep->xfer_len; + dep->xfer_count += dep->xfer_len; + } + else + { + dep->xfer_count = 0; + } +} + + +/** + * @brief USB_FS_FIFORead + * read receive fifo + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval none + */ + +/* + * Fifo_Read uses the endpoint object to ensure sole access to FIFO, + * then updates the object with # of bytes read. ***IMPORTANT***, we + * assume only thread of execution is BGD interrupt process, which has + * preselected the INDEX reg. eP->FifoRemain always represents the + * number of remaining bytes in the fifo following a recv packet interrupt. + * eP->BytesRequested - eP->BytesProcessed always represents the remaining + * bytes to fill from the APP (EP0 or user). We use the smaller of those + * two and move the bytes, updating all relevant counters. A new recv + * packet operation won't be initiated by the DRC until the fifo count + * has gone to 0. + */ +void USB_FS_FIFORead(uint8_t *dst, uint8_t ep_num, uint16_t len) +{ + uint16_t readcount; + uint32_t fifo_addr; + /* Take the smaller of what's requested versus what's in the fifo */ + readcount = len; + //MIN((eP->BytesRequested - eP->BytesProcessed), eP->FifoRemain); + + if (readcount <= 0) /* if none to read or blown tracking ... */ + { + return; + } + +// dst += eP->BytesProcessed; /* user buffer offset for current rd*/ +// eP->BytesProcessed += readcount; /* apps & stack can monitor progress */ +// eP->FifoRemain -= readcount; + fifo_addr = ADDR_FIFO_EP0 + (ep_num << 2); /* blds absolute fifo addrs */ +// fifo_addr = ADDR_FIFO_EP0 + ep_num; /* blds absolute fifo addrs */ + + while (readcount != 0U) + { + *dst++ = *((uint8_t *)fifo_addr); + readcount = readcount - 1U; + } + +} + +/** + * @brief USB_FS_FIFOWrite + * write data to tx fifo + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval USB_FS VBus status + */ +/* + * MGC_DRC_Fifo_Write uses the endpoint object to ensure sole access to FIFO, + * then updates the object with # of bytes written. MaxEPSize used to + * limit the write. MaxEPSize shall never be larger than the size of the + * configured fifo. + * + * 20-May-03: Setting eP->LastPacket universally for transmits. If + * a requested transmission is a multiple of the Max EP Size, then a 0-len + * packet is owed following the data packets. Otherwise, when processed + * = requested, we have a last-packet condition. + */ +void USB_FS_FIFOWrite(uint8_t *src, uint8_t ep_num, uint16_t len) +{ + uint16_t writecount; + uint32_t fifo_addr; + + writecount = len; + //MIN(eP->MaxEPSize, (eP->BytesRequested - eP->BytesProcessed)); + +// src += eP->BytesProcessed; /* user offset */ +// eP->BytesProcessed += writecount; /* apps & stack can monitor progress */ + +// if ((eP->BytesProcessed == eP->BytesRequested) & +// ((eP->BytesProcessed % eP->MaxEPSize) /* can't be a multiple */ +// || usb_pipebulk(eP->URBP->pipe) || +// (eP->Attr == 3) || (eP->Attr == 1))) +// { +// eP->LastPacket = 1; +// } + fifo_addr = ADDR_FIFO_EP0 + (ep_num << 2); /* blds absolute fifo addrs */ +// fifo_addr = ADDR_FIFO_EP0 + ep_num; /* blds absolute fifo addrs */ + + while (writecount) + { + *((uint8_t *)fifo_addr) = *src++; + writecount--; + } +} + + + +/** + * @brief USB_FS_SetEPInt + * unmask or mask endpoint interrupt + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + * @retval USB_FS status + */ +void USB_FS_SetEPInt(uint8_t cfg) +{ + uint8_t reg; + + /* Set INT enable registers */ + reg = cfg & 0xff; /* endpoints 0 .. 7 */ + USB_FS->INTRTX1E |= reg; + USB_FS->INTRRX1E |= reg; +} + +/** + * @brief USB_FS_SetUSBInt + * unmask or mask usb interrupt + * @param none + * @retval USB_FS status + */ +void USB_FS_SetUSBInt(uint8_t cfg) +{ + uint8_t reg; + + /* Set INT enable registers */ + reg = cfg & 0xff; + USB_FS->INTRUSBE = reg; +} +/** + * @brief USB_FS_ClrUSBInt + * clear usb interrupts + * @retval none + */ + +void USB_FS_ClrUSBInt(void) +{ + uint8_t temp; + + /* flush pending interrupts */ + temp = USB_FS->INTRUSB; +} +/** + * @brief USB_FS_ClrEPInt + * clear endpoint interrupts + * @retval none + */ + +void USB_FS_ClrEPInt(void) +{ + uint8_t temp; + + /* flush pending interrupts */ + temp = USB_FS->INTRTX1; + temp = USB_FS->INTRRX1; +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USB_FS Selected device + */ +void USB_FS_ActivateSetup(void) +{ + /* Set the MPS of the IN EP0 to 64 bytes */ + USB_FS->CSR0 |= (OTG_FS_CSR0_SETUPPKT | OTG_FS_TXCSR1_TXPKTRDY); +} + + +/** + * @brief Initialize a host transfer + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * @param interval : for iso/interrupt interval + * for bulk: nakmit + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * @retval USB_FS state + */ +USB_FS_StatusTypeDef USB_FS_HEP_Init(uint8_t epnum, uint8_t dev_address, + uint8_t ep_type, uint8_t interval, + uint16_t xfersize) +{ + USB_FS_StatusTypeDef ret = USB_FS_OK; + uint8_t HostCoreSpeed; + uint8_t ep_num; + uint8_t ep_dir; + + ep_num = epnum & 0x7FU; + + ret = USB_FS_IndexSel(ep_num); + /* Clear old interrupt conditions for this host channel. */ + USB_FS_ClrUSBInt(); + USB_FS_ClrEPInt(); + USB_FS_SetEPInt(1 << ep_num); + + HostCoreSpeed = USB_FS_GetSpeed(); + + USB_FS_SetAddress(dev_address); + + if (ep_num != 0U) + { + if ((epnum & 0x80U) == 0x80U) /* in rx */ + { + USB_FS->RXTYPE = (ep_num | (ep_type << 4)); + USB_FS->RXINTERVAL = interval; + USB_FS->RXMAXP = (xfersize / 8); + } + else + { + USB_FS->TXTYPE = (ep_num | (ep_type << 4)); + USB_FS->TXINTERVAL = interval; + USB_FS->TXMAXP = (xfersize / 8); + } + } + + return ret; +} + + +/** + * @brief Start a transfer over a host endpoint + * @param endpoint pointer to host endpoint structure + * @retval none + */ +void USB_FS_HEP_StartXfer(USB_OTG_FS_HEPTypeDef *hep) +{ + uint8_t ep_num = (uint32_t)hep->epnum; + __IO uint32_t tmpreg; + uint16_t maxpacket = 0U; + + (void)USB_FS_IndexSel(ep_num); + + switch (hep->ep_type) + { + case EP_TYPE_BULK: + maxpacket = USB_OTG_FS_MAX_BULK_PACKET_SIZE; + break; + + case EP_TYPE_INTR: + if ((USB_FS->DEVCTL & 0x40U) != 0) + { + maxpacket = USB_OTG_FS_MAX_INTR_PACKET_SIZE; + } + else + { + maxpacket = USB_OTG_LS_MAX_INTR_PACKET_SIZE; + } + + break; + + case EP_TYPE_ISOC: + maxpacket = USB_OTG_FS_MAX_ISOC_PACKET_SIZE; + break; + + default: + break; + } + + if (hep->xfer_len > maxpacket) + { + hep->XferSize = maxpacket; + } + else + { + hep->XferSize = hep->xfer_len; + } + + if (hep->ep_is_in == 1U) /* in rx */ + { + USB_FS->RXTYPE = (ep_num | (hep->ep_type << 4)); + USB_FS->RXMAXP = ((maxpacket + 7U) / 8U); + USB_FS->RXCSR1 |= OTG_FS_RXCSR1_CLRDT; + USB_FS->RXCSR1 |= OTG_FS_RXCSR1_REQPKT; + } + else + { + USB_FS->TXTYPE = (ep_num | (hep->ep_type << 4)); + USB_FS->TXMAXP = ((maxpacket + 7U) / 8U);; + USB_FS->TXCSR1 |= OTG_FS_TXCSR1_CLRDT; + USB_FS->TXCSR2 |= OTG_FS_TXCSR2_MODE; + } + + if ((hep->ep_is_in == 0U) & (hep->xfer_len > 0U)) + { + /* Write packet into the Tx FIFO. */ + (void)USB_FS_FIFOWrite(hep->xfer_buff, ep_num, (uint16_t)hep->XferSize); + USB_FS->TXCSR1 = OTG_FS_TXCSR1_TXPKTRDY; + } +} + +/** + * @brief Start a transfer over a host endpoint 0 + * @param endpoint pointer to host endpoint structure + * @retval none + */ +void USB_FS_HEP0_StartXfer(USB_OTG_FS_HEPTypeDef *hep, uint8_t ctl_state) +{ + uint8_t ep_num = 0U; + + (void)USB_FS_IndexSel(ep_num); + + if (hep->data_pid == EP_PID_SETUP) + { + /* Write packet into the Tx FIFO. */ + (void)USB_FS_FIFOWrite(hep->xfer_buff, ep_num, (uint16_t)hep->xfer_len); + USB_FS->CSR0 = OTG_FS_CSR0_TXPKTRDY | OTG_FS_CSR0_SETUPPKT; + } + else if (ctl_state == CTRL_STATUS) + { + if (hep->ep_is_in == 0U) + { + USB_FS->CSR0 = OTG_FS_CSR0_TXPKTRDY | OTG_FS_CSR0_STATUSPKT; + } + else + { + USB_FS->CSR0 = OTG_FS_CSR0_REQPKT | OTG_FS_CSR0_STATUSPKT; + } + } + else if (ctl_state == CTRL_DATA) + { + if (hep->ep_is_in == 0U) + { + if (hep->xfer_len > 0U) + { + (void)USB_FS_FIFOWrite(hep->xfer_buff, ep_num, (uint16_t)hep->xfer_len); + } + + USB_FS->CSR0 = OTG_FS_CSR0_TXPKTRDY; + } + else + { + USB_FS->CSR0 = OTG_FS_CSR0_REQPKT; + } + } + else + { + /*...*/ + } +} + + +/** + * @brief USB_FS_FlushEp0Fifo : Flush EP0 FIFO + * @param none + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_FlushEp0Fifo(void) +{ + + /* Flush EP0 fifo */ + USB_FS->INDEX = 0U; + USB_FS->CSR02 = OTG_FS_CSR02_FFIFO; + + + return USB_FS_OK; +} + +/** + * @brief USB_FS_FlushTxFifo : Flush a Tx FIFO + * @param epnum endpoint number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_FlushTxFifo(uint8_t epnum) +{ + + /* Flush TX fifo */ + USB_FS->INDEX = epnum; + USB_FS->TXCSR1 |= OTG_FS_TXCSR1_FFIFO; + + + return USB_FS_OK; +} + +/** + * @brief USB_FS_FlushRxFifo : Flush Rx FIFO + * @param USB_FS Selected device + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_FlushRxFifo(uint8_t epnum) +{ + + /* Flush RX fifo */ + USB_FS->INDEX = epnum; + USB_FS->RXCSR1 |= OTG_FS_RXCSR1_FFIFO; + + return USB_FS_OK; +} + + +/** + * @brief Set Tx FIFO + * @param fifo The number of Tx fifo + * @param size Fifo size + * @retval none + */ +void USB_FS_SetTxFiFo(uint8_t epnum, uint8_t size, uint8_t address, uint8_t dpb) +{ + uint8_t fifo1, fifo2; + + /* + * usb_fs ram 1024bytes + * size and address are in the unit of 8 bytes + * max fifo size, 1024 bytes / 8 = 128 + * max address, 0x7ff8 / 8 = 0xfff (0x400-8) / 8 = 0x7F + */ + if ((size > 128) || (address > 0x7F)) + { + return; + } + + fifo1 = address; + fifo2 = ((dpb << 4 ) & (OTG_FS_TXFIFO2_TXDPB)); + fifo2 |= (usb_log2(size)) << 5; + + USB_FS->INDEX = (0x0F & epnum); + USB_FS->TXFIFO1 = fifo1; + USB_FS->TXFIFO2 = fifo2; + +} + +/** + * @brief Set Rx FIFO + * @param size Size of Rx fifo + * @retval none + */ +void USB_FS_SetRxFiFo(uint8_t epnum, uint8_t size, uint8_t address, uint8_t dpb) +{ + uint8_t fifo1, fifo2; + + /* + * usb_fs ram 1024bytes + * size and address are in the unit of 8 bytes + * max fifo size, 1024 bytes / 8 = 128 + * max address, 0x7ff8 / 8 = 0xfff (0x400-8) / 8 = 0x7F + */ + if ((size > 128) || (address > 0x7F)) + { + return; + } + + fifo1 = address; + fifo2 = ((dpb << 4 ) & (OTG_FS_TXFIFO2_TXDPB)); + fifo2 |= (usb_log2(size)) << 5; + + USB_FS->INDEX = (0x0F & epnum); + USB_FS->RXFIFO1 = fifo1; + USB_FS->RXFIFO2 = fifo2; + +} + +/** + * @brief Returns USB_FS core mode + * @param USB_FS Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 1 : Host + * 0 : Device + */ +uint8_t USB_FS_GetMode(void) +{ + return ((USB_FS->DEVCTL) & 0x4U); +} + +/** + * @brief Returns USB_FS core CID + * @retval return core ID : A-device or B-device + * This parameter can be one of these values: + * 0 : A-device + * 1 : B-device + */ +uint8_t USB_FS_GetCID(void) +{ + return ((USB_FS->DEVCTL) & 0x80U); +} + +/** + * @brief USB_FS_DrvSess : enabel or disable session + * @param state session state + * This parameter can be one of these values: + * 0 : disable session request + * 1 : enable session request + */ +void USB_FS_DrvSess(uint8_t state) +{ + __IO uint8_t session = 0U; + + session = USB_FS->DEVCTL; + + if (((session & OTG_FS_DEVCTL_SESSION) == 0U) & (state == 1U)) + { + USB_FS->DEVCTL = (OTG_FS_DEVCTL_SESSION | session); + } + + if (((session & OTG_FS_DEVCTL_SESSION) == OTG_FS_DEVCTL_SESSION) & (state == 0U)) + { + USB_FS->DEVCTL = ((~OTG_FS_DEVCTL_SESSION) & session); + } +} + +/** + * @brief Return Host Core speed + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_FS_GetSpeed(void) +{ + __IO uint8_t spd = 0U; + uint32_t speed; + spd = USB_FS->DEVCTL; + + if ((spd & OTG_FS_DEVCTL_FSDEV) == OTG_FS_DEVCTL_FSDEV) + { + speed = USB_FS_SPEED; + } + else if ((spd & OTG_FS_DEVCTL_LSDEV) == OTG_FS_DEVCTL_LSDEV) + { + speed = USB_LS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + +/** + * @brief USB_FS_Set_Polling_Interval + * set polling interval value for iso or interrupt transfer. + * @param epdir endpoint transfer tx or rx + * 1: tx + * 0: rx + * @param interval: polling interval value + * @retval none + */ +void USB_FS_Set_Polling_Interval(uint8_t epdir, uint8_t interval) +{ + if ((epdir & 0x01) == FIFO_TX) + { + USB_FS->TXINTERVAL = (interval & 0xFF); + } + else + { + USB_FS->RXINTERVAL = (interval & 0xFF); + } +} + +/** + * @brief USB_FS_Set_NAKLMT + * set nak limit value + * @param epnum: endpoint number + * @param epdir endpoint transfer tx or rx + * 1: tx + * 0: rx + * @param interval: polling interval value + * @retval none + */ +void USB_FS_Set_NAKLMT(uint8_t epnum, uint8_t epdir, uint8_t naklmt) +{ + if (epnum != 0U) + { + if ((epdir & 0x01) == FIFO_TX) + { + USB_FS->TXINTERVAL = (naklmt & 0xFF); + } + else + { + USB_FS->RXINTERVAL = (naklmt & 0xFF); + } + } + else + { + USB_FS->NAKLMT0 = naklmt; + } +} + +/** + * @brief USB_FS_SetAddress : set device address + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + * @retval none + */ +void USB_FS_SetAddress(uint8_t address) +{ + USB_FS->FADDR &= ~(OTG_FS_FADDR_FUNADDR); + USB_FS->FADDR = (address & OTG_FS_FADDR_FUNADDR); +} + +/** + * @brief USB_FS_GetAddress : get device address + * @retval device address + */ +uint8_t USB_FS_GetAddress(void) +{ + uint8_t address; + address = 0U; + + address = USB_FS->FADDR; + return address; +} + +/** + * @brief USB_FS_SetPower : Set power register + * @param configured value + * @retval none */ +void USB_FS_SetPower(uint8_t powercfg) +{ + uint8_t reg_power; + uint8_t temp; + reg_power = USB_FS->POWER; + temp = (reg_power | powercfg); + + USB_FS->POWER = temp; +} + +/** + * @brief USB_FS_GetPower : get power register + * @param none + * @retval power register value + */ +uint8_t USB_FS_GetPower(void) +{ + uint8_t reg_power; + reg_power = USB_FS->POWER; + + return reg_power; +} + +/** + * @brief USB_FS_ClrPower : Clear power register + * @param configured value + * @retval none + */ +void USB_FS_ClrPower(uint8_t powercfg) +{ + uint8_t reg_power; + uint8_t temp; + reg_power = USB_FS->POWER; + temp = (reg_power & (~powercfg)); + + USB_FS->POWER = temp; +} + +/** + * @brief USB_FS_SetDevctl : Set devctl register + * @param configured value + * @retval none + */ +void USB_FS_SetDevctl(uint8_t cfg) +{ + uint8_t reg_devctl; + uint8_t temp; + reg_devctl = USB_FS->DEVCTL; + temp = (reg_devctl | cfg); + + USB_FS->DEVCTL = temp; +} + +/** + * @brief USB_FS_GetDevctl : get devctl register + * @param none + * @retval Devctl register value + */ +uint8_t USB_FS_GetrDevctl(void) +{ + uint8_t reg_devctl; + reg_devctl = USB_FS->DEVCTL; + + return reg_devctl; +} + +/** + * @brief USB_FS_ClrDevctl : Clear devctl register + * @param configured value + * @retval none + */ +void USB_FS_ClrDevctl(uint8_t cfg) +{ + uint8_t reg_devctl; + uint8_t temp; + reg_devctl = USB_FS->DEVCTL; + temp = (reg_devctl & (~cfg)); + + USB_FS->DEVCTL = temp; +} + +/** + * @brief USB_FS_Exiting_Host : exit host mode + * @param toOTG cp + * @retval status + */ +int8_t USB_FS_Exiting_Host(uint8_t toOTG, USB_OTG_FS_CfgTypeDef *cfg) +{ + if (toOTG == A_SUSPEND) /* A_SUSPEND itself is not exiting host */ + { + return(0); + } + else if (toOTG == A_PERIPHERAL) /* Only way here is from a host(suspend) */ + { + return(1); + } + else if ((cfg->OTGState == A_HOST) || (cfg->OTGState == B_HOST)) + { + return(1); + } + else + { + return(0); + } +} +/** + * @brief USB_FS_Activate_Resume : set resume + * @param none + * @retval none + */ +void USB_FS_Activate_Resume(void) +{ + if ((USB_FS_GetPower() & OTG_FS_POWER_SUSPEND) == OTG_FS_POWER_SUSPEND) + { + USB_FS_SetPower(OTG_FS_POWER_RESUME); /* sets the RESUME bit */ + } +} + +/** + * @brief USB_FS_DeActivate_Resume : exit host mode + * @param none + * @retval none + */ +void USB_FS_DeActivate_Resume(void) +{ + USB_FS_ClrPower(OTG_FS_POWER_RESUME); /* clear the RESUME bit */ +} + +/** + * @brief USB_FS_ResetPort : Reset Host Port + * @param USB_FS Selected device + * @note (1)The application must wait at least 20 ms + * before clearing the reset bit. + */ +void USB_FS_ResetPort(void) +{ + __IO uint8_t temp_reg = 0U; + __IO uint32_t num = 20; + + temp_reg = USB_FS->POWER; + + temp_reg |= OTG_FS_POWER_RESET; + USB_FS->POWER = temp_reg; + + while(num--) /* update delay 20ms */ + { + SysTick->LOAD = SystemCoreClock / 1000; + SysTick->VAL = 0x00; + SysTick->CTRL = 0x00000005; + + while(!(SysTick->CTRL & 0x00010000)); + + SysTick->CTRL = 0x00000004; + } +// USB_FS_Delayms(20U); + temp_reg &= (~OTG_FS_POWER_RESET); + USB_FS->POWER = temp_reg; +} + +int32_t usb_log2(int32_t x) +{ + int32_t i; + + for (i = 0; x > 1; i++) + { + x = x / 2 ; + } + + return i; +} + +/** + * @brief USB_FS_HostInit : Initializes the USB controller registers + * for Host mode + * @param USB_FS Selected device + * @param cfg pointer to a USB_OTG_FS_CfgTypeDef structure that contains + * the configuration information for the specified USB_FS peripheral. + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_HostInit(USB_OTG_FS_CfgTypeDef cfg) +{ + USB_FS_StatusTypeDef ret = USB_FS_OK; + uint32_t i; + + /* initial ep0 */ + (void)USB_FS_RstEP0Regs(); + + /* reset all ep register include flush fifo*/ + for (i = 1U; i < cfg.endpoints; i++) + { + if (USB_FS_RstEPRegs(i) != USB_FS_OK) + { + ret = USB_FS_ERROR; + } + } + + /* Clear all pending Interrupts */ + USB_FS_ClrEPInt(); + OTG_FS->INTRTX1E = 0U; + OTG_FS->INTRRX1E = 0U; + + USB_FS_ClrUSBInt(); + OTG_FS->INTRUSBE = 0U; + + /* Enable VBUS driving */ + USB_FS_SetUSBInt(OTG_FS_INTRUSBE_CONNINTE); + (void)USB_FS_DrvSess(1U); + USB_FS_Delayms(200U); /* update delay*/ + + /* Enable the common interrupts */ + USB_FS_SetUSBInt(OTG_FS_INTRUSBE_SOFINTE | OTG_FS_INTRUSBE_RSTINTE | + OTG_FS_INTRUSBE_DISCINTE | OTG_FS_INTRUSBE_SREQINTE | + OTG_FS_INTRUSBE_VERRINTE); + return ret; +} + +/** + * @brief USB_FS_ReadInterrupts: return the USB interrupt status + * @retval global interrupt register + */ +uint32_t USB_FS_ReadInterrupts(void) +{ + uint32_t tmpreg = 0; + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + uint32_t tmpreg3 = 0; + + tmpreg1 = USB_FS->INTRUSB; + tmpreg1 &= USB_FS->INTRUSBE; + + tmpreg2 = USB_FS->INTRTX1; + tmpreg2 &= USB_FS->INTRTX1E; + + tmpreg3 = USB_FS->INTRRX1; + tmpreg3 &= USB_FS->INTRRX1E; + + tmpreg = ((tmpreg1) | (tmpreg2 << 8) | (tmpreg3 << 16)); + + return tmpreg; +} + +/** + * @brief USB_FS_SendStall: send STALL handshake to the endpoint + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_SendStall(USB_OTG_FS_DEPTypeDef *dep) +{ + if (dep->num == 0) /* endpoint0 */ + { + USB_FS_IndexSel(0U); + USB_FS->CSR0 |= OTG_FS_CSR0_SDSTALL; + } + else + { + USB_FS_IndexSel(dep->num); + + if (dep->is_in) /* tx */ + { + USB_FS->TXCSR1 |= OTG_FS_TXCSR1_SDSTALL; + } + else /* rx */ + { + USB_FS->RXCSR1 |= OTG_FS_RXCSR1_SDSTALL; + } + } + + return USB_FS_OK; +} + +/** + * @brief USB_FS_ClrStall: clear send STALL handshake to the endpoint + * @retval USB_FS status + */ +USB_FS_StatusTypeDef USB_FS_ClrStall(USB_OTG_FS_DEPTypeDef *dep) +{ + USB_FS_IndexSel(dep->num); + + if (dep->is_in) /* tx */ + { + USB_FS->TXCSR1 &= (~OTG_FS_TXCSR1_SDSTALL); + } + else /* rx */ + { + USB_FS->RXCSR1 &= (~OTG_FS_RXCSR1_SDSTALL); + } + + return USB_FS_OK; +} +/** + * @brief USB_FS_Enable_Suspend: entry suspend mode + * @retval none + */ +void USB_FS_Enable_Suspend(void) +{ + if ((USB_FS->DEVCTL & OTG_FS_DEVCTL_HSTMD) == OTG_FS_DEVCTL_HSTMD) + { + USB_FS_SetPower(OTG_FS_POWER_SUSPEND); + } + else + { + USB_FS_SetPower(OTG_FS_POWER_SUSPENDEN); + } +} + +/** + * @brief USB_FS_Disable_Suspend: exit suspend mode + * @retval none + */ +void USB_FS_Disable_Suspend(void) +{ + if ((USB_FS->DEVCTL & OTG_FS_DEVCTL_HSTMD) == OTG_FS_DEVCTL_HSTMD) + { + USB_FS_ClrPower(OTG_FS_POWER_SUSPEND); + } + else + { + USB_FS_ClrPower(OTG_FS_POWER_SUSPENDEN); + } +} + + +#endif /* defined (USB_OTG_FS) */ + +#endif /* defined (USB_OTG_FS) */ + + +#endif /* defined (PCD_MODULE_ENABLED) || defined (HCD_MODULE_ENABLED) */ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usb_hs.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usb_hs.c new file mode 100644 index 00000000000..85fd1259f26 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_usb_hs.c @@ -0,0 +1,2128 @@ +/** + ****************************************************************************** + * @file ft32f4xx_usb_hs.c + * @author FMD XA + * @brief This file provides firmware functions to manage the following + * functionalities of the USB Peripheral Controller: + * + Initialization/de-initialization functions + * + Peripheral Control functions + * + Peripheral State functions + * @version V1.0.0 + * @data 2025-03-20 + @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure. + + (#) Call USB_HS_CoreInit() API to initialize the USB Core peripheral. + + (#) The upper HCD/PCD driver will call the right routines for its internal processes. + @endverbatim +****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" +#include "system_ft32f4xx.h" +#include "ft32f4xx_misc.h" +#include "ft32f4xx_usb_hs.h" + +/** @addtogroup FT32F4xx_USB_HS_DRIVER + * @{ + */ + +#if defined (PCD_MODULE_ENABLED) || defined (HCD_MODULE_ENABLED) +#if defined (USB_OTG_HS) +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ +#if defined (USB_OTG_HS) +static USB_HS_StatusTypeDef USB_HS_CoreReset(); + +volatile uint32_t delayCount_hs_ms; + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup USB_Exported_Functions USB OTG HS Low Layer Exported Functions + * @{ + */ + +/** @defgroup USB_Exported_Functions_Group1 Initialization/de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim + =============================================================================== + ##### Initialization/de-initialization functions ##### + =============================================================================== + +@endverbatim + * @{ + */ +void USB_HS_Delayms (uint32_t num) +{ + if(SysTick_Config(SystemCoreClock/1000)) + { + while (1); + } + uint32_t tickStart = delayCount_hs_ms; + while ((delayCount_hs_ms - tickStart) < num); +} +/** + * @brief Initializes the USB OTG HS Core + * @param USB HS USB Instance + * @param cfg pointer to a USB_OTG_HS_CfgTypeDef structure that contains + * the configuration information for the specified USB_HS peripheral. + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_CoreInit(USB_OTG_HS_CfgTypeDef cfg) +{ + USB_HS_StatusTypeDef ret; + #define W32_TRIM(ADDRESS) (*((volatile unsigned int *)(ADDRESS))) + uint32_t read_trim; + uint32_t otgtune; + uint32_t comptune; + uint32_t sqrxtune; + uint32_t txhstune; + uint32_t vregtune; + uint32_t txfslstune; + uint32_t txvreftune; + uint32_t txrisetune; + uint32_t txpretune; + + read_trim = W32_TRIM(0x1FFF0A24); + + otgtune = ((read_trim & 0x00000007) << 3); // bit5:3 + comptune = ((read_trim & 0x00000070) << 2); // bit8:6 + sqrxtune = ((read_trim & 0x00000700) << 1); // bit11:9 + txhstune = ((read_trim & 0x00003000) ); // bit13:12 + vregtune = ((read_trim & 0x00004000) ); // bit14 + txfslstune = ((read_trim & 0x000F0000) >> 1); // bit18:15 + txvreftune = ((read_trim & 0x00F00000) >> 1); // bit 22:19 + txrisetune = ((read_trim & 0x01000000) >> 1); // bit23 + txpretune = ((read_trim & 0x02000000) >> 1); // bit24 + + /* Init the UTMI interface */ + USB_HS->GUSBCFG &= ~(OTG_HS_GUSBCFG_TSDPS); + + /* Reset */ + ret = USB_HS_CoreReset(); + /* change srqxtune txvreftune otgtune compdistune */ + /* waiting for update */ + USB_HS_PKEY = 0x5057 ; + USB_HS_PKEY = 0x5948 ; + +//USB_HS_PREG = 0x0041B723; + USB_HS_PREG = (otgtune | comptune | sqrxtune | + txhstune | vregtune | txfslstune | + txvreftune | txrisetune | txpretune | + 0x03); + + *(uint32_t*)(0x40040E1C) |= 0x2000000; + + USB_HS_PKEY = 0x0; + + + if (cfg.dma_enable == 1U) + { + USB_HS->GAHBCFG |= OTG_HS_GAHBCFG_HBSTLEN_2 ; // INCR4 + USB_HS->GAHBCFG |= OTG_HS_GAHBCFG_DMAEN ; // enable dma mode + } + return ret; +} + + +/** + * @brief Set the USB turnaround time + * @param USB HS Instance + * @param hlck: AHB clock frequency + * @retval USB HS turnaround time in PHY clock number + */ + +void USB_HS_SetTurnaroundTime(uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USBD_FS_SPEED) + { + if ((hclk >= 14200000U) && (hclk < 15000000U)) + { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } + else if ((hclk >= 15000000U) && (hclk < 16000000U)) + { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } + else if ((hclk >= 16000000U) && (hclk < 17200000U)) + { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } + else if ((hclk >= 17200000U) && (hclk < 18500000U)) + { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } + else if ((hclk >= 18500000U) && (hclk < 20000000U)) + { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } + else if ((hclk >= 20000000U) && (hclk < 21800000U)) + { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } + else if ((hclk >= 21800000U) && (hclk < 24000000U)) + { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } + else if ((hclk >= 24000000U) && (hclk < 27700000U)) + { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } + else if ((hclk >= 27700000U) && (hclk < 32000000U)) + { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } + else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } + else if (speed == USBD_HS_SPEED) + { + UsbTrd = USBD_HS_TRDT_VALUE; + } + else + { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USB_HS->GUSBCFG &= ~OTG_HS_GUSBCFG_TRDT; + USB_HS->GUSBCFG |= (uint32_t)((UsbTrd << 10) & OTG_HS_GUSBCFG_TRDT); + +} + + +/** + * @brief USB_HS_EnableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USB_HS Selected device + */ +void USB_HS_EnableGlobalInt(void) +{ + USB_HS->GAHBCFG |= OTG_HS_GAHBCFG_GINT; +} + +/** + * @brief USB_HS_DisableGlobalInt + * Enables the controller's Global Int in the AHB Config reg + * @param USB_HS Selected device + */ +void USB_HS_DisableGlobalInt(void) +{ + USB_HS->GAHBCFG &= ~OTG_HS_GAHBCFG_GINT; +} + +/** + * @brief USB_HS_SetCurrentMode Set functional mode + * @param USB_HS Selected device + * @param mode current core mode + * This parameter can be one of these values: + * @arg USB_DEVICE_MODE Peripheral mode + * @arg USB_HOST_MODE Host mode + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_SetCurrentMode(USB_ModeTypeDef mode) +{ + uint32_t ms = 0U; + + USB_HS->GUSBCFG &= ~(OTG_HS_GUSBCFG_FHMOD | OTG_HS_GUSBCFG_FDMOD); + + if (mode == USB_HOST_MODE) + { + USB_HS->GUSBCFG |= OTG_HS_GUSBCFG_FHMOD; + do + { + USB_HS_Delayms(10U); + ms += 10U; + }while ((USB_HS_GetMode() != (uint32_t)USB_HOST_MODE) && (ms < USB_HS_CURRENT_MODE_MAX_DELAY_MS)); + } + else if (mode == USB_DEVICE_MODE) + { + USB_HS->GUSBCFG |= OTG_HS_GUSBCFG_FDMOD; + do + { + USB_HS_Delayms(10U); + ms += 10U; + }while ((USB_HS_GetMode() != (uint32_t)USB_DEVICE_MODE) && (ms < USB_HS_CURRENT_MODE_MAX_DELAY_MS)); + } + else + { + return USB_HS_ERROR; + } + if (ms == USB_HS_CURRENT_MODE_MAX_DELAY_MS) + { + return USB_HS_ERROR; + } + return USB_HS_OK ; +} + + +/** + * @brief USB_HS_DevInit Initializes the USB_OTG_HS controller registers + * for device mode + * @param USB_HS Selected device + * @param cfg pointer to a USB_OTG_HS_CfgTypeDef structure that contains + * the configuration information for the specified USB_HS peripheral. + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_DevInit(USB_OTG_HS_CfgTypeDef cfg) +{ + USB_HS_StatusTypeDef ret = USB_HS_OK ; + uint32_t i; + + /* Device InEndpoint FIFO size Iintialize */ + for (i = 0U; i < 15U; i++) + { + USB_HS->DIEPTXF[i] = 0U; + } + + /* VBUS sensing setup */ + if (cfg.bvalid_override_enable == 1U) + { + USB_HS_DEVICE->DCTL |= OTG_HS_DCTL_SDIS; + + /* B-peripheral session valid override enable */ + USB_HS->GOTGCTL |= OTG_HS_GOTGCTL_BOVALEN; + USB_HS->GOTGCTL |= OTG_HS_GOTGCTL_BOVAL; + } + else + { + /* ... */ + } + + /* Restart the Phy Clock */ + USB_HS_PCGCCTL = 0U; + + /* Device mode configuration */ + USB_HS_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80; + + if(cfg.speed == USBD_HS_SPEED) + { + /* Set Core speed to High speed mode */ + (void)USB_HS_SetDevSpeed(USB_OTG_SPEED_HIGH); + } + else + { + /* Set Core speed to Full speed mode */ + (void)USB_HS_SetDevSpeed(USB_OTG_SPEED_HIGH_IN_FULL); + } + + /* Flush the FIFOs */ + if (USB_HS_FlushTxFifo(0x10U) != USB_HS_OK) /* all Tx FIFOs */ + { + ret = USB_HS_ERROR; + } + + if (USB_HS_FlushRxFifo() != USB_HS_OK) + { + ret = USB_HS_ERROR; + } + + /* Clear all pending Device Interrupts */ + USB_HS_DEVICE->DIEPMSK = 0U; + USB_HS_DEVICE->DOEPMSK = 0U; + USB_HS_DEVICE->DAINTMSK = 0U; + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USB_HS_INEP(i)->DIEPCTL & OTG_HS_DIEPCTL_EPENA) == OTG_HS_DIEPCTL_EPENA) + { + if (i == 0U) + { + USB_HS_INEP(i)->DIEPCTL = OTG_HS_DIEPCTL_SNAK; + } + else + { + USB_HS_INEP(i)->DIEPCTL = OTG_HS_DIEPCTL_EPDIS | OTG_HS_DIEPCTL_SNAK; + } + } + else + { + USB_HS_INEP(i)->DIEPCTL = 0U; + } + + USB_HS_INEP(i)->DIEPTSIZ = 0U; + USB_HS_INEP(i)->DIEPINT = 0xFB7FU; + } + + for (i = 0U; i < cfg.dev_endpoints; i++) + { + if ((USB_HS_OUTEP(i)->DOEPCTL & OTG_HS_DOEPCTL_EPENA) == OTG_HS_DOEPCTL_EPENA) + { + if (i == 0U) + { + USB_HS_OUTEP(i)->DOEPCTL = OTG_HS_DOEPCTL_SNAK; + } + else + { + USB_HS_OUTEP(i)->DOEPCTL = OTG_HS_DOEPCTL_EPDIS | OTG_HS_DOEPCTL_SNAK; + } + } + else + { + USB_HS_OUTEP(i)->DOEPCTL = 0U; + } + + USB_HS_OUTEP(i)->DOEPTSIZ = 0U; + USB_HS_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + USB_HS_DEVICE->DIEPMSK &= ~(OTG_HS_DIEPMSK_TXFURM); + + /* Disable all interrupts. */ + USB_HS->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USB_HS->GINTSTS = 0xBFFFFFFFU; + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USB_HS->GINTMSK |= OTG_HS_GINTMSK_RXFLVLM; + } + /* Enable interrupts matching to the Device mode ONLY */ + USB_HS->GINTMSK |= OTG_HS_GINTMSK_USBSUSPM | OTG_HS_GINTMSK_USBRSTM | + OTG_HS_GINTMSK_ENDNEM | OTG_HS_GINTMSK_IEPINTM | + OTG_HS_GINTMSK_OEPINTM | OTG_HS_GINTMSK_IISOIXFRM | + OTG_HS_GINTMSK_PXFRM_IISOOXFRM | OTG_HS_GINTMSK_WUIM | + OTG_HS_GINTMSK_SOFM | OTG_HS_GINTMSK_OTGINTM | + OTG_HS_GINTMSK_SRQIM ; + + return ret; +} + +/** + * @brief USB_HS_FlushTxFifo : Flush a Tx FIFO + * @param USB_HS Selected device + * @param num FIFO number + * This parameter can be a value from 1 to 15 + 15 means Flush all Tx FIFOs + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_FlushTxFifo(uint32_t num) +{ + __IO uint32_t count = 0U; + + /* wait for AHB master IDLE state */ + do + { + count++; + if (count > USB_TIMEOUT) + { + return USB_HS_TIMEOUT; + } + } while ((USB_HS->GRSTCTL & OTG_HS_GRSTCTL_AHBIDL) == 0U); + + /* Flush TX fifo */ + count = 0U; + USB_HS->GRSTCTL = (OTG_HS_GRSTCTL_TXFFLSH | (num << 6)); + + do + { + count++; + if (count > USB_TIMEOUT) + { + return USB_HS_TIMEOUT; + } + } while ((USB_HS->GRSTCTL & OTG_HS_GRSTCTL_TXFFLSH) == OTG_HS_GRSTCTL_TXFFLSH); + + return USB_HS_OK; +} + +/** + * @brief USB_HS_FlushRxFifo : Flush Rx FIFO + * @param USB_HS Selected device + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_FlushRxFifo(void) +{ + __IO uint32_t count = 0U; + /* wait for AHB master IDLE state */ + do + { + count++; + if (count > USB_TIMEOUT) + { + return USB_HS_TIMEOUT; + } + } while ((USB_HS->GRSTCTL & OTG_HS_GRSTCTL_AHBIDL) == 0U); + + /* Flush RX fifo */ + count = 0U; + USB_HS->GRSTCTL = OTG_HS_GRSTCTL_RXFFLSH ; + + do + { + count++; + if (count > USB_TIMEOUT) + { + return USB_HS_TIMEOUT; + } + } while ((USB_HS->GRSTCTL & OTG_HS_GRSTCTL_RXFFLSH) == OTG_HS_GRSTCTL_RXFFLSH); + + return USB_HS_OK; +} + + +/** + * @brief USB_HS_SetDevSpeed Initializes the DevSpd field of DCFG register + * depending the PHY type and the enumeration speed of the device. + * @param USB_HS Selected device + * @param speed device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_HIGH: High speed mode + * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full speed mode + */ +void USB_HS_SetDevSpeed(uint8_t speed) +{ + USB_HS_DEVICE->DCFG |= speed; +} + +/** + * @brief USB_HS_GetDevSpeed Return the Dev Speed + * @param USB_HS Selected device + * @retval speed device speed + * This parameter can be one of these values: + * @arg PCD_SPEED_HIGH: High speed mode + * @arg PCD_SPEED_FULL: Full speed mode + */ +uint8_t USB_HS_GetDevSpeed(void) +{ + uint8_t speed; + uint32_t DevEnumSpeed = USB_HS_DEVICE->DSTS & OTG_HS_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_HS_SPEED; + } + else if (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) + { + speed = USBD_FS_SPEED; + } + else + { + speed = 0xFU; + } + + return speed; +} + + +/** + * @brief Activate and configure an endpoint + * @param USB_HS Selected device + * @param ep pointer to endpoint structure + */ +void USB_HS_ActivateEndpoint(USB_OTG_HS_EPTypeDef *ep) +{ + uint32_t epnum = (uint32_t)ep->num; + /* read DI/OEPCTLn register */ + if (ep->is_in == 1U) + { + USB_HS_DEVICE->DAINTMSK |= OTG_HS_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + + if ((USB_HS_INEP(epnum)->DIEPCTL & OTG_HS_DIEPCTL_USBAEP) == 0U) + { + USB_HS_INEP(epnum)->DIEPCTL |= (ep->maxpacket & OTG_HS_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + OTG_HS_DIEPCTL_SD0PID_SEVNFRM | + OTG_HS_DIEPCTL_USBAEP; + } + } + else + { + USB_HS_DEVICE->DAINTMSK |= OTG_HS_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); + + if (((USB_HS_OUTEP(epnum)->DOEPCTL) & OTG_HS_DOEPCTL_USBAEP) == 0U) + { + USB_HS_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & OTG_HS_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + OTG_HS_DOEPCTL_SD0PID_SEVNFRM | + OTG_HS_DOEPCTL_USBAEP; + } + } +} + + +/** + * @brief Activate and configure a dedicated endpoint + * @param USB_HS Selected device + * @param ep pointer to endpoint structure + */ +void USB_HS_ActivateDedicatedEndpoint(USB_OTG_HS_EPTypeDef *ep) +{ + uint32_t epnum = (uint32_t)ep->num; + /* read DI/OEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USB_HS_INEP(epnum)->DIEPCTL & OTG_HS_DIEPCTL_USBAEP) == 0U) + { + USB_HS_INEP(epnum)->DIEPCTL |= (ep->maxpacket & OTG_HS_DIEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | (epnum << 22) | + OTG_HS_DIEPCTL_SD0PID_SEVNFRM | + OTG_HS_DIEPCTL_USBAEP; + } + USB_HS_DEVICE->DEACHMSK |= OTG_HS_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); + } + else + { + if (((USB_HS_OUTEP(epnum)->DOEPCTL) & OTG_HS_DOEPCTL_USBAEP) == 0U) + { + USB_HS_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & OTG_HS_DOEPCTL_MPSIZ) | + ((uint32_t)ep->type << 18) | + OTG_HS_DOEPCTL_SD0PID_SEVNFRM | + OTG_HS_DOEPCTL_USBAEP; + } + USB_HS_DEVICE->DEACHMSK |= OTG_HS_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16 ); + } +} + +/** + * @brief De-activate and de-initialize an endpoint + * @param USB_HS Selected device + * @param ep pointer to endpoint structure + */ +void USB_HS_DeactivateEndpoint(USB_OTG_HS_EPTypeDef *ep) +{ + uint32_t epnum = (uint32_t)ep->num; + + /* Read DI/OEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USB_HS_INEP(epnum)->DIEPCTL & OTG_HS_DIEPCTL_EPENA) == OTG_HS_DIEPCTL_EPENA) + { + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_SNAK; + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_EPDIS; + } + + USB_HS_DEVICE->DEACHMSK &= ~(OTG_HS_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USB_HS_DEVICE->DAINTMSK &= ~(OTG_HS_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + USB_HS_INEP(epnum)->DIEPCTL &= ~(OTG_HS_DIEPCTL_USBAEP | + OTG_HS_DIEPCTL_MPSIZ | + OTG_HS_DIEPCTL_TXFNUM | + OTG_HS_DIEPCTL_SD0PID_SEVNFRM | + OTG_HS_DIEPCTL_EPTYP); + } + else + { + if ((USB_HS_OUTEP(epnum)->DOEPCTL & OTG_HS_DOEPCTL_EPENA) == OTG_HS_DOEPCTL_EPENA) + { + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_SNAK; + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_EPDIS; + } + + USB_HS_DEVICE->DEACHMSK &= ~(OTG_HS_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USB_HS_DEVICE->DAINTMSK &= ~(OTG_HS_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + USB_HS_OUTEP(epnum)->DOEPCTL &= ~(OTG_HS_DOEPCTL_USBAEP | + OTG_HS_DOEPCTL_MPSIZ | + OTG_HS_DOEPCTL_SD0PID_SEVNFRM | + OTG_HS_DOEPCTL_EPTYP); + } +} + +/** + * @brief De-activate and de-initialize a dedicated endpoint + * @param USB_HS Selected device + * @param ep pointer to endpoint structure + */ +void USB_HS_DeactivateDedicatedEndpoint(USB_OTG_HS_EPTypeDef *ep) +{ + uint32_t epnum = (uint32_t)ep->num; + + /* Read DI/OEPCTLn register */ + if (ep->is_in == 1U) + { + if ((USB_HS_INEP(epnum)->DIEPCTL & OTG_HS_DIEPCTL_EPENA) == OTG_HS_DIEPCTL_EPENA) + { + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_SNAK; + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_EPDIS; + } + + USB_HS_INEP(epnum)->DIEPCTL &= ~OTG_HS_DIEPCTL_USBAEP ; + USB_HS_DEVICE->DAINTMSK &= ~(OTG_HS_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); + } + else + { + if ((USB_HS_OUTEP(epnum)->DOEPCTL & OTG_HS_DOEPCTL_EPENA) == OTG_HS_DOEPCTL_EPENA) + { + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_SNAK; + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_EPDIS; + } + + USB_HS_OUTEP(epnum)->DOEPCTL &= ~OTG_HS_DOEPCTL_USBAEP ; + USB_HS_DEVICE->DAINTMSK &= ~(OTG_HS_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); + } +} + + +/** + * @brief USB_HS_EPStartXfer : setup and starts a transfer over an EP + * @param USB_HS Selected device + * @param ep pointer ro endpoint structure + * @param dma USB_HS enable or disable + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + */ +void USB_HS_EPStartXfer(USB_OTG_HS_EPTypeDef *ep, uint8_t dma) +{ + uint32_t epnum = (uint32_t)ep->num; + uint16_t pktcnt; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* Zero Length Packet? */ + if (ep->xfer_len == 0U) + { + USB_HS_INEP(epnum)->DIEPTSIZ &= ~(OTG_HS_DIEPTSIZ_PKTCNT); + USB_HS_INEP(epnum)->DIEPTSIZ |= (OTG_HS_DIEPTSIZ_PKTCNT & (1U << 19)); + USB_HS_INEP(epnum)->DIEPTSIZ &= ~(OTG_HS_DIEPTSIZ_XFRSIZ); + } + else + { + /* Program the transfer size and packet count + * as follows: xfersize = N * maxpacket + + * short_packet pktcnt = N + (short_packet + * exist ? 1 : 0) + */ + USB_HS_INEP(epnum)->DIEPTSIZ &= ~(OTG_HS_DIEPTSIZ_XFRSIZ); + USB_HS_INEP(epnum)->DIEPTSIZ &= ~(OTG_HS_DIEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > ep->maxpacket) + { + ep->xfer_len = ep->maxpacket; + } + + USB_HS_INEP(epnum)->DIEPTSIZ |= (OTG_HS_DIEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + USB_HS_INEP(epnum)->DIEPTSIZ |= (OTG_HS_DIEPTSIZ_PKTCNT & + (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); + } + + USB_HS_INEP(epnum)->DIEPTSIZ |= (OTG_HS_DIEPTSIZ_XFRSIZ & ep->xfer_len); + + if (ep->type == EP_TYPE_ISOC) + { + USB_HS_INEP(epnum)->DIEPTSIZ &= ~(OTG_HS_DIEPTSIZ_MULCNT); + USB_HS_INEP(epnum)->DIEPTSIZ |= (OTG_HS_DIEPTSIZ_MULCNT & (1U << 29)); + } + } + if (dma == 1U) + { + if ((uint32_t)ep->dma_addr != 0U) + { + USB_HS_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); + } + if (ep->type == EP_TYPE_ISOC) + { + /* SOF frame is odd or even */ + if ((USB_HS_DEVICE->DSTS & (1U << 8)) == 0U) + { + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_SODDFRM; + } + else + { + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable, IN data in FIFO */ + USB_HS_INEP(epnum)->DIEPCTL |= (OTG_HS_DIEPCTL_CNAK | OTG_HS_DIEPCTL_EPENA); + } + else + { + /* EP enable, IN data in FIFO */ + USB_HS_INEP(epnum)->DIEPCTL |= (OTG_HS_DIEPCTL_CNAK | OTG_HS_DIEPCTL_EPENA); + + if (ep->type != EP_TYPE_ISOC) + { + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (ep->xfer_len > 0U) + { + USB_HS_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); + } + } + else + { + if ((USB_HS_DEVICE->DSTS & (1U << 8)) == 0U) + { + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_SODDFRM; + } + else + { + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_SD0PID_SEVNFRM; + } + USB_HS_WritePacket(ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); + } + } + } + else /* OUT endpoint */ + { + /* Program the transfer size and packet count as follows: + * pktcnt = N + * xfersize = N * maxpacket + */ + USB_HS_OUTEP(epnum)->DOEPTSIZ &= ~(OTG_HS_DOEPTSIZ_XFRSIZ); + USB_HS_OUTEP(epnum)->DOEPTSIZ &= ~(OTG_HS_DOEPTSIZ_PKTCNT); + + if (epnum == 0U) + { + if (ep->xfer_len > 0U) + { + ep->xfer_len = ep->maxpacket; + } + + /* store transfer size, for EP0 this is equal to endpoint max packet size */ + ep->xfer_size = ep->maxpacket; + + USB_HS_OUTEP(epnum)->DOEPTSIZ |= (OTG_HS_DOEPTSIZ_XFRSIZ & ep->xfer_size); + USB_HS_OUTEP(epnum)->DOEPTSIZ |= (OTG_HS_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + if (ep->xfer_len == 0U) + { + USB_HS_OUTEP(epnum)->DOEPTSIZ |= (OTG_HS_DOEPTSIZ_XFRSIZ & ep->maxpacket); + USB_HS_OUTEP(epnum)->DOEPTSIZ |= (OTG_HS_DOEPTSIZ_PKTCNT & (1U << 19)); + } + else + { + pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); + ep->xfer_size = ep->maxpacket * pktcnt; + + USB_HS_OUTEP(epnum)->DOEPTSIZ |= OTG_HS_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); + USB_HS_OUTEP(epnum)->DOEPTSIZ |= OTG_HS_DOEPTSIZ_XFRSIZ & (ep->xfer_size); + } + } + + if (dma == 1U) + { + if ((uint32_t)ep->xfer_buff != 0U) + { + USB_HS_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); + } + } + if (ep->type == EP_TYPE_ISOC) + { + /* SOF frame is odd or even */ + if ((USB_HS_DEVICE->DSTS & (1U << 8)) == 0U) + { + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_SODDFRM; + } + else + { + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_SD0PID_SEVNFRM; + } + } + /* EP enable */ + USB_HS_OUTEP(epnum)->DOEPCTL |= (OTG_HS_DOEPCTL_CNAK | OTG_HS_DOEPCTL_EPENA); + } +} + +/** + * @brief USB_HS_EPStopXfer : Stop transfer on an EP + * @param USB_HS Selected device + * @param ep pointer to endpoint structure + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_EPStopXfer(USB_OTG_HS_EPTypeDef *ep) +{ + __IO uint32_t count = 0U; + USB_HS_StatusTypeDef ret = USB_HS_OK; + + /* IN endpoint */ + if (ep->is_in == 1U) + { + /* EP enable, IN data in FIFO */ + if (((USB_HS_INEP(ep->num)->DIEPCTL) & OTG_HS_DIEPCTL_EPENA) == OTG_HS_DIEPCTL_EPENA) + { + USB_HS_INEP(ep->num)->DIEPCTL |= (OTG_HS_DIEPCTL_SNAK); + USB_HS_INEP(ep->num)->DIEPCTL |= (OTG_HS_DIEPCTL_EPDIS); + + do + { + count++; + if (count > 10000U) + { + ret = USB_HS_ERROR; + break; + } + }while (((USB_HS_INEP(ep->num)->DIEPCTL) & OTG_HS_DIEPCTL_EPENA) == OTG_HS_DIEPCTL_EPENA); + } + } + else /* OUT endpoint */ + { + if (((USB_HS_OUTEP(ep->num)->DOEPCTL) & OTG_HS_DOEPCTL_EPENA) == OTG_HS_DOEPCTL_EPENA) + { + USB_HS_OUTEP(ep->num)->DOEPCTL |= (OTG_HS_DOEPCTL_SNAK); + USB_HS_OUTEP(ep->num)->DOEPCTL |= (OTG_HS_DOEPCTL_EPDIS); + + do + { + count++; + if (count > 10000U) + { + ret = USB_HS_ERROR; + break; + } + }while (((USB_HS_OUTEP(ep->num)->DOEPCTL) & OTG_HS_DOEPCTL_EPENA) == OTG_HS_DOEPCTL_EPENA); + } + } + return ret; +} + +/** + * @brief USB_HS_WritePacket : Writes a packet into the Tx FIFO associated + * with the EP/channel + * @param USB_HS Selected device + * @param src pointer to source buffer + * @param ch_ep_num endpoint or host channel number + * @param len Number of bytes to write + * @param dma USB dma enabled or disabled + * This parameter can be one of thes values: + * 0 : DMA feature not used + * 1 : DMA feature used + */ +void USB_HS_WritePacket(uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma) +{ + uint8_t *pSrc = src; + uint32_t count32b; + uint32_t i; + + if (dma == 0U) + { + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) + { + USB_HS_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + pSrc++; + pSrc++; + pSrc++; + } + } +} + + +/** + * @brief USB_HS_ReadPacket : read a packet from the RX FIFO + * @param USB_HS Selected device + * @param dest source pointer + * @param len Number of bytes to read + * @retval pointer to destination buffer + */ +void *USB_HS_ReadPacket(uint8_t *dest, uint16_t len) +{ + uint8_t *pDest = dest; + uint32_t pData; + uint32_t i; + uint32_t count32b = (uint32_t)len >> 2U; + uint16_t remaining_bytes = len % 4U; + + for (i = 0U; i < count32b; i++) + { + __UNALIGNED_UINT32_WRITE(pDest, USB_HS_DFIFO(0U)); + pDest++; + pDest++; + pDest++; + pDest++; + } + /* when number of data is not word aligned, read the remaining byte */ + if (remaining_bytes != 0U) + { + i = 0U; + __UNALIGNED_UINT32_WRITE(&pData, USB_HS_DFIFO(0U)); + + do + { + *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); + i++; + pDest++; + remaining_bytes--; + }while (remaining_bytes != 0U); + } + return ((void *)pDest); +} + + +/** + * @brief USB_HS_EPSetStall : set a stall condition over an EP + * @param USB_HS Selected device + * @param ep pointer to endpoint structure + */ +void USB_HS_EPSetStall(USB_OTG_HS_EPTypeDef *ep) +{ + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + if (((USB_HS_INEP(epnum)->DIEPCTL & OTG_HS_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USB_HS_INEP(epnum)->DIEPCTL &= ~(OTG_HS_DIEPCTL_EPDIS); + } + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_STALL; + } + else + { + if (((USB_HS_OUTEP(epnum)->DOEPCTL & OTG_HS_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) + { + USB_HS_OUTEP(epnum)->DOEPCTL &= ~(OTG_HS_DOEPCTL_EPDIS); + } + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_STALL; + } +} + +/** + * @brief USB_HS_EPClearStall : Clear a stall condition over an EP + * @param USB_HS Selected device + * @param ep pointer to endpoint structure + */ +void USB_HS_EPClearStall(USB_OTG_HS_EPTypeDef *ep) +{ + uint32_t epnum = (uint32_t)ep->num; + + if (ep->is_in == 1U) + { + USB_HS_INEP(epnum)->DIEPCTL &= ~OTG_HS_DIEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USB_HS_INEP(epnum)->DIEPCTL |= OTG_HS_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + else + { + USB_HS_OUTEP(epnum)->DOEPCTL &= ~OTG_HS_DOEPCTL_STALL; + if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) + { + USB_HS_OUTEP(epnum)->DOEPCTL |= OTG_HS_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } +} + + +/** + * @brief USB_HS_StopDevice : Stop the usb device mode + * @param USB_HS Selected device + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_StopDevice(void) +{ + USB_HS_StatusTypeDef ret; + uint32_t i; + + /* Clear Pending interrupt */ + for (i = 0U; i < 15U; i++) + { + USB_HS_INEP(i)->DIEPINT = 0xFB7FU; + USB_HS_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USB_HS_DEVICE->DIEPMSK = 0U; + USB_HS_DEVICE->DOEPMSK = 0U; + USB_HS_DEVICE->DAINTMSK = 0U; + + /* Flush the FIFO */ + ret = USB_HS_FlushRxFifo(); + if (ret != USB_HS_OK) + { + return ret; + } + + ret = USB_HS_FlushTxFifo(0x10U); + if (ret != USB_HS_OK) + { + return ret; + } + + return ret; +} + +/** + * @brief USB_HS_SetDevAddress : set device address + * @param USB_HS Selected device + * @param address new device address to be assigned + * This parameter can be a value from 0 to 255 + */ +void USB_HS_SetDevAddress(uint8_t address) +{ + USB_HS_DEVICE->DCFG &= ~(OTG_HS_DCFG_DAD); + USB_HS_DEVICE->DCFG |= ((uint32_t)address << 4) & OTG_HS_DCFG_DAD; +} + +/** + * @brief USB_HS_DevConnect : Connect the USB device by enabling Rpu + * @param USB_HS Selected device + */ +void USB_HS_DevConnect(void) +{ + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USB_HS_PCGCCTL &= ~(OTG_HS_PCGCCTL_STOPCLK | OTG_HS_PCGCCTL_GATECLK); + + /* disable software disconnect */ + USB_HS_DEVICE->DCTL &= ~OTG_HS_DCTL_SDIS; + +} + + +/** + * @brief USB_HS_DevDisconnect : Disconnect the USB device by disabling Rpu + * @param USB_HS Selected device + * @retval none + */ +void USB_HS_DevDisconnect(void) +{ + /* In case phy is stopped, ensure to ungate and restore the phy CLK */ + USB_HS_PCGCCTL &= ~(OTG_HS_PCGCCTL_STOPCLK | OTG_HS_PCGCCTL_GATECLK); + /* enable software disconnect */ + USB_HS_DEVICE->DCTL |= OTG_HS_DCTL_SDIS; + +} + +/** + * @brief USB_HS_ReadInterrupts: return the global USB interrupt status + * @param USB_HS Selected device + * @retval global interrupt register + */ +uint32_t USB_HS_ReadInterrupts(void) +{ + uint32_t tmpreg; + + tmpreg = USB_HS->GINTSTS; + tmpreg &= USB_HS->GINTMSK; + + return tmpreg; +} + +/** + * @brief USB_HS_ReadChInterrupts: return the USB channel interrupt status + * @param USB_HS Selected device + * @param chnum channel number + * @retval USB HS Channel interrupt register + */ +uint32_t USB_HS_ReadChInterrupts(uint8_t chnum) +{ + uint32_t tmpreg; + + tmpreg = USB_HS_HC(chnum)->HCINT; + tmpreg &= USB_HS_HC(chnum)->HCINTMSK; + + return tmpreg; +} + + +/** + * @brief USB_HS_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status + * @param USB_HS Selected device + * @retval USB Device OUT EP interrupt status + */ +uint32_t USB_HS_ReadDevAllOutEpInterrupt(void) +{ + uint32_t tmpreg; + + tmpreg = USB_HS_DEVICE->DAINT; + tmpreg &= USB_HS_DEVICE->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief USB_HS_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status + * @param USB_HS Selected device + * @retval USB Device IN EP interrupt status + */ +uint32_t USB_HS_ReadDevAllInEpInterrupt(void) +{ + uint32_t tmpreg; + + tmpreg = USB_HS_DEVICE->DAINT; + tmpreg &= USB_HS_DEVICE->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param USB_HS Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +uint32_t USB_HS_ReadDevOutEPInterrupt(uint8_t epnum) +{ + uint32_t tmpreg; + + tmpreg = USB_HS_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USB_HS_DEVICE->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param USB_HS Selected device + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +uint32_t USB_HS_ReadDevInEPInterrupt(uint8_t epnum) +{ + uint32_t tmpreg; + uint32_t msk; + uint32_t emp; + + msk = USB_HS_DEVICE->DIEPMSK; + emp = USB_HS_DEVICE->DIEPEMPMSK; + msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; + tmpreg = USB_HS_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +/** + * @brief USB_HS_ClearInterrupts: clear a USB interrupt + * @param USB_HS Selected device + * @param interrupt flag + * @retval None + */ +void USB_HS_ClearInterrupts(uint32_t interrupt) +{ + USB_HS->GINTSTS &= interrupt; +} + +/** + * @brief Returns USB_HS core mode + * @param USB_HS Selected device + * @retval return core mode : Host or Device + * This parameter can be one of these values: + * 0 : Host + * 1 : Device + */ +uint32_t USB_HS_GetMode(void) +{ + return ((USB_HS->GINTSTS) & 0x1U); +} + +/** + * @brief Activate EP0 for Setup transactions + * @param USB_HS Selected device + */ +void USB_HS_ActivateSetup(void) +{ + + /* Set the MPS of the IN EP0 to 64 bytes */ + USB_HS_INEP(0U)->DIEPCTL &= ~OTG_HS_DIEPCTL_MPSIZ; + + USB_HS_DEVICE->DCTL |= OTG_HS_DCTL_CGINAK; + +} + +/** + * @brief Prepare the EP0 to start the first control setup + * @param USB_HS Selected device + * @param dma USB_HS enabled or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA deature used + * @param psetup pointer to setup packet + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_EP0_OutStart(uint8_t dma, uint8_t *psetup) +{ + if ((USB_HS_OUTEP(0U)->DOEPCTL & OTG_HS_DOEPCTL_EPENA) == OTG_HS_DOEPCTL_EPENA) + { + return USB_HS_OK; + } + + USB_HS_OUTEP(0U)->DOEPTSIZ = 0U; + USB_HS_OUTEP(0U)->DOEPTSIZ |= (OTG_HS_DOEPTSIZ_PKTCNT & (1U << 19)); + USB_HS_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USB_HS_OUTEP(0U)->DOEPTSIZ |= OTG_HS_DOEPTSIZ_STUPCNT; + + if (dma == 1U) + { + USB_HS_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USB_HS_OUTEP(0U)->DOEPCTL |= (OTG_HS_DOEPCTL_EPENA | OTG_HS_DOEPCTL_USBAEP); + } + + return USB_HS_OK; +} + +/** + * @brief Reset the USB_HS Core (needed after USB clock settings change) + * @param USB_HS Selected device + * @retval USB_HS status + */ +static USB_HS_StatusTypeDef USB_HS_CoreReset(void) +{ + __IO uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do + { + count++; + + if (count > USB_TIMEOUT) + { + return USB_HS_TIMEOUT; + } + } while ((USB_HS->GRSTCTL & OTG_HS_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USB_HS->GRSTCTL |= OTG_HS_GRSTCTL_CSRST; + + do + { + count++; + + if (count > USB_TIMEOUT) + { + return USB_HS_TIMEOUT; + } + } while ((USB_HS->GRSTCTL & OTG_HS_GRSTCTL_CSRST) == OTG_HS_GRSTCTL_CSRST); + + return USB_HS_OK; +} + +/** + * @brief USB_HS_HostInit : Initializes the USB OTG controller registers + * for Host mode + * @param USB_HS Selected device + * @param cfg pointer to a USB_OTG_HS_CfgTypeDef structure that contains + * the configuration information for the specified USB_HS peripheral. + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_HostInit(USB_OTG_HS_CfgTypeDef cfg) +{ + USB_HS_StatusTypeDef ret = USB_HS_OK; + uint32_t i; + + /* Restart the Phy Clock */ + USB_HS_PCGCCTL = 0U; + + if ((USB_HS->GUSBCFG & OTG_HS_GUSBCFG_PHSEL) == 0U) + { + if (cfg.speed == USBH_FSLS_SPEED) + { + /* Force device enumeration to FS/LS mode only */ + USB_HS_HOST->HCFG |= OTG_HS_HCFG_FSLSS; + } + else + { + /* Set default Max speed support */ + USB_HS_HOST->HCFG &= ~(OTG_HS_HCFG_FSLSS); + } + } + else + { + ret = USB_HS_ERROR; + } + + /* Make sure the FIFOs are flushed. */ + if (USB_HS_FlushTxFifo(0x10U) != USB_HS_OK) /* all Tx FIFOs */ + { + ret = USB_HS_ERROR ; + } + if (USB_HS_FlushRxFifo() != USB_HS_OK) /* Rx FIFO */ + { + ret = USB_HS_ERROR ; + } + + /* Clear all pending HC Interrupts */ + for (i = 0U; i < cfg.Host_channels; i++) + { + USB_HS_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; + USB_HS_HC(i)->HCINTMSK = 0U; + } + + /* Enable VBUS driving */ +// (void)USB_HS_DriveVbus(1U); +// USB_HS_Delayms(200U); + + /* Disable all interrupts. */ + USB_HS->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USB_HS->GINTSTS = CLEAR_INTERRUPT_MASK; + + /* set Rx FIFO size */ + USB_HS->GRXFSIZ = 0x200U; + USB_HS->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & OTG_HS_HNPTXFSIZ_NPTXFD) | 0x200U); + USB_HS->HPTXFSIZ = (uint32_t)(((0xE0U << 16)& OTG_HS_HPTXFSIZ_PTXFD) | 0x300U); + + /* Enable the common interrupts */ + if (cfg.dma_enable == 0U) + { + USB_HS->GINTMSK |= OTG_HS_GINTMSK_RXFLVLM; + } + /* Enable interrupts matching to the Host mode ONLY */ + USB_HS->GINTMSK |= (OTG_HS_GINTMSK_PRTIM | OTG_HS_GINTMSK_HCIM | \ + OTG_HS_GINTMSK_SOFM | OTG_HS_GINTMSK_DISCINTM | \ + OTG_HS_GINTMSK_PXFRM_IISOOXFRM | OTG_HS_GINTMSK_WUIM ); + + return ret; +} + +/** + * @brief USB_HS_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the + * HCFG register on the PHY type and set the right frame interval + * @param USB_HS Selected device + * @param freq clock frequency + * This parameter can be one of these values: + * HCFG_48_MHZ : Full Speed 48 MHz Clock + * HCFG_6_MHZ : Low Speed 6 MHz Clock + * @retval USB_HS status + */ +USB_HS_StatusTypeDef USB_HS_InitFSLSPClkSel(uint8_t freq) +{ + + USB_HS_HOST->HCFG &= ~(OTG_HS_HCFG_FSLSPCS); + USB_HS_HOST->HCFG |= (uint32_t)freq & OTG_HS_HCFG_FSLSPCS; + + if (freq == HCFG_48_MHZ) + { + USB_HS_HOST->HFIR = 48000U; + } + else if (freq == HCFG_6_MHZ) + { + USB_HS_HOST->HFIR = 6000U; + } + else + { + return USB_HS_ERROR; + } + + return USB_HS_OK; + +} + +/** + * @brief USB_OTG_ResetPort : Reset Host Port + * @param USB_HS Selected device + * @note (1)The application must wait at least 10 ms + * before clearing the reset bit. + */ +void USB_HS_ResetPort(void) +{ + + __IO uint32_t hprt0 = 0U; + __IO uint32_t num = 100; + + hprt0 = USB_HS_HPRT0; + + hprt0 &= ~(OTG_HS_HPRT_PENA | OTG_HS_HPRT_PCDET | + OTG_HS_HPRT_PENCHNG | OTG_HS_HPRT_POCCHNG); + + USB_HS_HPRT0 = (OTG_HS_HPRT_PRST | hprt0); + while(num--) /* update delay 20ms */ + { + SysTick->LOAD = SystemCoreClock / 1000; + SysTick->VAL = 0x00; + SysTick->CTRL = 0x00000005; + + while(!(SysTick->CTRL & 0x00010000)); + + SysTick->CTRL = 0x00000004; + } /* See Note #1 */ + + USB_HS_HPRT0 = ((~OTG_HS_HPRT_PRST) & hprt0); + USB_HS_Delayms(10U); + +} + +/** + * @brief USB_HS_DriveVbus : activate or de-activate vbus + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate VBUS + * 1 : Activate VBUS + */ +void USB_HS_DriveVbus(uint8_t state) +{ + __IO uint32_t hprt0 = 0U; + + hprt0 = USB_HS_HPRT0; + + hprt0 &= ~(OTG_HS_HPRT_PENA | OTG_HS_HPRT_PCDET | + OTG_HS_HPRT_PENCHNG | OTG_HS_HPRT_POCCHNG); + + if (((hprt0 & OTG_HS_HPRT_PPWR) == 0U) && (state == 1U)) + { + USB_HS_HPRT0 = (OTG_HS_HPRT_PPWR | hprt0); + } + if (((hprt0 & OTG_HS_HPRT_PPWR) == OTG_HS_HPRT_PPWR) && (state == 0U)) + { + USB_HS_HPRT0 = ((~OTG_HS_HPRT_PPWR) & hprt0); + } +} + +/** + * @brief USB_HS_DriveID : activate or de-activate id + * @param state VBUS state + * This parameter can be one of these values: + * 0 : Deactivate ID + * 1 : Activate ID + * @note To use ID line detection, this function must be enabled; it is enabled by default. + * This function is connected to pin PB12. If PB12 is to use normal GPIO functions, + * this function must be disabled. + */ +void USB_HS_DriveID(uint8_t state) +{ + USB_HS_PKEY = 0x5057 ; + USB_HS_PKEY = 0x5948 ; + + *(uint32_t*)(0x40040E1C) |= (state << 25); + + USB_HS_PKEY = 0x0; +} + +/** + * @brief Return Host Core speed + * @param USB_HS Selected device + * @retval speed : Host speed + * This parameter can be one of these values: + * @arg HCD_SPEED_HIGH: Full speed mode + * @arg HCD_SPEED_FULL: Full speed mode + * @arg HCD_SPEED_LOW: Low speed mode + */ +uint32_t USB_HS_GetHostSpeed(void) +{ + __IO uint32_t hprt0 = 0U; + + hprt0 = USB_HS_HPRT0; + return ((hprt0 & OTG_HS_HPRT_PSPD) >> 17); +} + +/** + * @brief Return Host Current Frame number + * @param USB_HS Selected device + * @retval current frame number + */ +uint32_t USB_HS_GetCurrentFrame(void) +{ + return (USB_HS_HOST->HFNUM & OTG_HS_HFNUM_FRNUM); +} + +/** + * @brief Initialize a host channel + * @param USB_HS Selected device + * @param ch_num Channel number + * This parameter can be a value from 1 to 15 + * @param epnum Endpoint number + * This parameter can be a value from 1 to 15 + * @param dev_address Current device address + * This parameter can be a value from 0 to 255 + * @param speed Current device speed + * This parameter can be one of these values: + * @arg USB_OTG_SPEED_FULL: HIGH speed mode + * @arg USB_OTG_SPEED_FULL: Full speed mode + * @arg USB_OTG_SPEED_LOW: Low speed mode + * @param ep_type Endpoint Type + * This parameter can be one of these values: + * @arg EP_TYPE_CTRL: Control type + * @arg EP_TYPE_ISOC: Isochronous type + * @arg EP_TYPE_BULK: Bulk type + * @arg EP_TYPE_INTR: Interrupt type + * @param mps Max Packet Size + * This parameter can be a value from 0 to 32K + * @retval USB_HS state + */ +USB_HS_StatusTypeDef USB_HS_HC_Init(uint8_t ch_num, uint8_t epnum, uint8_t dev_address, + uint8_t speed, uint8_t ep_type, uint16_t mps) +{ + USB_HS_StatusTypeDef ret = USB_HS_OK; + uint32_t HCcharEpDir; + uint32_t HCcharLowSpeed; + uint32_t HostCoreSpeed; + + /* Clear old interrupt conditions for this host channel. */ + USB_HS_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; + + /* Enable channel interrupts required for this transfer. */ + switch (ep_type) + { + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + USB_HS_HC((uint32_t)ch_num)->HCINTMSK = OTG_HS_HCINTMSK_XFRCM | + OTG_HS_HCINTMSK_STALLM | + OTG_HS_HCINTMSK_TXERRM | + OTG_HS_HCINTMSK_DTERRM | + OTG_HS_HCINTMSK_AHBERRM | + OTG_HS_HCINTMSK_NAKM; + + if ((epnum & 0x80U) == 0x80U) + { + USB_HS_HC((uint32_t)ch_num)->HCINTMSK |= OTG_HS_HCINTMSK_BBERRM; + } + else + { + USB_HS_HC((uint32_t)ch_num)->HCINTMSK |= (OTG_HS_HCINTMSK_NYETM | OTG_HS_HCINTMSK_ACKM); + } + break; + + case EP_TYPE_INTR: + USB_HS_HC((uint32_t)ch_num)->HCINTMSK = OTG_HS_HCINTMSK_XFRCM | + OTG_HS_HCINTMSK_STALLM | + OTG_HS_HCINTMSK_TXERRM | + OTG_HS_HCINTMSK_DTERRM | + OTG_HS_HCINTMSK_NAKM | + OTG_HS_HCINTMSK_AHBERRM | + OTG_HS_HCINTMSK_FRMORM ; + + if ((epnum & 0x80U) == 0x80U) + { + USB_HS_HC((uint32_t)ch_num)->HCINTMSK |= OTG_HS_HCINTMSK_BBERRM; + } + + break; + + case EP_TYPE_ISOC: + USB_HS_HC((uint32_t)ch_num)->HCINTMSK = OTG_HS_HCINTMSK_XFRCM | + OTG_HS_HCINTMSK_ACKM | + OTG_HS_HCINTMSK_AHBERRM | + OTG_HS_HCINTMSK_FRMORM ; + + if ((epnum & 0x80U) == 0x80U) + { + USB_HS_HC((uint32_t)ch_num)->HCINTMSK |= (OTG_HS_HCINTMSK_TXERRM | OTG_HS_HCINTMSK_BBERRM); + } + break; + + default: + ret = USB_HS_ERROR; + break; + } + + /* Clear Hub Start Split transaction */ + USB_HS_HC((uint32_t)ch_num)->HCSPLT = 0U; + + /* Enable host channel Halt interrupt */ + USB_HS_HC((uint32_t)ch_num)->HCINTMSK |= OTG_HS_HCINTMSK_CHHM; + + /* Enable the top level host channel interrupt. */ + USB_HS_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + /* Make sure host channel interrupts are enabled. */ + USB_HS->GINTMSK |= OTG_HS_GINTMSK_HCIM; + + /* Program the HCCHAR register */ + if ((epnum & 0x80U) == 0x80U) + { + HCcharEpDir = (0x1U << 15) & OTG_HS_HCCHAR_EPDIR; + } + else + { + HCcharEpDir = 0U; + } + + HostCoreSpeed = USB_HS_GetHostSpeed(); + + /* LS device plugged to HUB */ + if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) + { + HCcharLowSpeed = (0x1U << 17) & OTG_HS_HCCHAR_LSDEV; + } + else + { + HCcharLowSpeed = 0U; + } + + USB_HS_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & OTG_HS_HCCHAR_DAD) | + ((((uint32_t)epnum & 0x7FU) << 11) & OTG_HS_HCCHAR_EPNUM) | + (((uint32_t)ep_type << 18) & OTG_HS_HCCHAR_EPTYP) | + ((uint32_t)mps & OTG_HS_HCCHAR_MPSIZ) | OTG_HS_HCCHAR_MEC_0 | + HCcharEpDir | HCcharLowSpeed; + + if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) + { + USB_HS_HC((uint32_t)ch_num)->HCCHAR |= OTG_HS_HCCHAR_ODDFRM ; + } + + return ret; +} + +/** + * @brief Start a transfer over a host channel + * @param USB_HS Selected device + * @param hc pointer to host channel structure + * @param dma USB_HS enable or disabled + * This parameter can be one of these values: + * 0 : DMA feature not used + * 1 : DMA feature used + */ +void USB_HS_HC_StartXfer(USB_OTG_HS_HCTypeDef *hc, uint8_t dma) +{ + uint32_t ch_num = (uint32_t)hc->ch_num; + __IO uint32_t tmpreg; + uint8_t is_oddframe; + uint16_t len_words; + uint16_t num_packets; + uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; + + if (dma == 1U) + { + if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) + { + USB_HS_HC((uint32_t)ch_num)->HCINTMSK &= ~( OTG_HS_HCINTMSK_NYETM | + OTG_HS_HCINTMSK_ACKM | + OTG_HS_HCINTMSK_NAKM ); + } + } + else + { + if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) + { + (void)USB_HS_DoPing(hc->ch_num); + + } + } + + if (hc->do_ssplit == 1U) + { + /* Set number of packet to 1 for Split transaction */ + num_packets = 1U; + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + if (hc->ep_type == EP_TYPE_ISOC) + { + if (hc->xfer_len > ISO_SPLT_MPS) + { + /* Isochrone Max Packet Size for Split mode */ + hc->XferSize = hc->max_packet; + hc->xfer_len = hc->XferSize; + + if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_MIDDLE; + } + else + { + hc->iso_splt_xactPos = HCSPLT_BEGIN; + } + } + else + { + hc->XferSize = hc->xfer_len; + + if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) + { + hc->iso_splt_xactPos = HCSPLT_FULL; + } + else + { + hc->iso_splt_xactPos = HCSPLT_END; + } + } + } + else + { + if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + } + } + else + { + /* Compute the expected number of packets associated to the transfer */ + if (hc->xfer_len > 0U) + { + num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); + + if (num_packets > max_hc_pkt_count) + { + num_packets = max_hc_pkt_count; + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + } + else + { + num_packets = 1U; + } + + /* + * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of + * max_packet size. + */ + if (hc->ep_is_in != 0U) + { + hc->XferSize = (uint32_t)num_packets * hc->max_packet; + } + else + { + hc->XferSize = hc->xfer_len; + } + } + + /* Initialize the HCTSIZn register */ + USB_HS_HC(ch_num)->HCTSIZ = (hc->XferSize & OTG_HS_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & OTG_HS_HCTSIZ_PKTCNT) | + (((uint32_t)hc->data_pid << 29) & OTG_HS_HCTSIZ_DPID); + + if (dma != 0U) + { + /* xfer_buff MUST be 32-bits aligned */ + USB_HS_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; + } + + is_oddframe = (((uint32_t)USB_HS_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USB_HS_HC(ch_num)->HCCHAR &= ~OTG_HS_HCCHAR_ODDFRM; + USB_HS_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + if (hc->do_ssplit == 1U) + { + /* Set Hub start Split transaction */ + USB_HS_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << OTG_HS_HCSPLT_HUBADDR_Pos) | + (uint32_t)hc->hub_port_nbr | OTG_HS_HCSPLT_SPLITEN; + /* unmask ack & nyet for IN/OUT transactions */ + USB_HS_HC((uint32_t)ch_num)->HCINTMSK |= (OTG_HS_HCINTMSK_ACKM | OTG_HS_HCINTMSK_NYETM); + + if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) + { + USB_HS_HC((uint32_t)ch_num)->HCSPLT |= OTG_HS_HCSPLT_COMPLSPLT; + USB_HS_HC((uint32_t)ch_num)->HCINTMSK |= OTG_HS_HCINTMSK_NYETM; + } + + if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && + (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) + { + USB_HS_HC((uint32_t)ch_num)->HCSPLT |= OTG_HS_HCSPLT_COMPLSPLT; + } + + /* Position management for iso out transaction on split mode */ + if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) + { + /* Set data payload position */ + switch(hc->iso_splt_xactPos) + { + case HCSPLT_BEGIN: + /* First data payload for OUT Transaction */ + USB_HS_HC((uint32_t)ch_num)->HCSPLT |= OTG_HS_HCSPLT_XACTPOS_1; + break; + + case HCSPLT_MIDDLE: + /* Middle data payload for OUT Transaction */ + USB_HS_HC((uint32_t)ch_num)->HCSPLT |= OTG_HS_HCSPLT_XACTPOS_Pos; + break; + + case HCSPLT_END: + /* End data payload for OUT Transaction */ + USB_HS_HC((uint32_t)ch_num)->HCSPLT |= OTG_HS_HCSPLT_XACTPOS_0; + break; + + case HCSPLT_FULL: + /* Entire data payload for OUT Transaction */ + USB_HS_HC((uint32_t)ch_num)->HCSPLT |= OTG_HS_HCSPLT_XACTPOS; + break; + + default: + break; + } + } + } + else + { + /* Clear Hub Start Split transaction */ + USB_HS_HC((uint32_t)ch_num)->HCSPLT = 0U; + } + + /* Set host channel enable */ + tmpreg = USB_HS_HC(ch_num)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + + /* make sure to set the correct ep direction */ + if (hc->ep_is_in != 0U) + { + tmpreg |= OTG_HS_HCCHAR_EPDIR; + } + else + { + tmpreg &= ~OTG_HS_HCCHAR_EPDIR; + } + + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(ch_num)->HCCHAR = tmpreg; + + if (dma != 0U) /*dma mode*/ + { + return ; + } + + if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) + { + switch (hc->ep_type) + { + /* Non periodic transfer */ + case EP_TYPE_CTRL: + case EP_TYPE_BULK: + + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + + /* check if there is enough space in FIFO space */ + if (len_words > (USB_HS->HNPTXSTS & 0xFFFFU)) + { + /* need to process data in nptxfempty interrupt */ + USB_HS->GINTMSK |= OTG_HS_GINTMSK_NPTXFEM; + } + break; + + /* Periodic transfer */ + case EP_TYPE_INTR: + case EP_TYPE_ISOC: + len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); + /* check if there is enough space in FIFO space */ + if (len_words > (USB_HS_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ + { + /* need to process data in ptxfempty interrupt */ + USB_HS->GINTMSK |= OTG_HS_GINTMSK_PTXFEM; + } + break; + + default: + break; + } + /* Write packet into the Tx FIFO. */ + (void)USB_HS_WritePacket(hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); + } +} + + +/** + * @brief Read all host channel interrupts status + * @param USB_HS Selected device + * @retval host channel interrupt state + */ +uint32_t USB_HS_HC_ReadInterrupt(void) +{ + return ((USB_HS_HOST->HAINT) & 0xFFFFU); +} + +/** + * @brief Halt a host channel + * @param USB_HS Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + */ +void USB_HS_HC_Halt(uint8_t hc_num) +{ + uint32_t hcnum = (uint32_t)hc_num; + uint32_t count = 0U; + uint32_t HcEpType = (USB_HS_HC(hcnum)->HCCHAR & OTG_HS_HCCHAR_EPTYP) >> 18; + uint32_t ChannelEna = (USB_HS_HC(hcnum)->HCCHAR & OTG_HS_HCCHAR_CHENA) >> 31; + uint32_t SplitEna = (USB_HS_HC(hcnum)->HCSPLT & OTG_HS_HCSPLT_SPLITEN) >> 31; + + if ((((USB_HS->GAHBCFG & OTG_HS_GAHBCFG_DMAEN) == OTG_HS_GAHBCFG_DMAEN) && (SplitEna == 0U)) && + ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) + { + return ; + } + + /* Check for space in the request queue to issue the halt. */ + if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) + { + USB_HS_HC(hcnum)->HCCHAR |= OTG_HS_HCCHAR_CHDIS; + + if ((USB_HS->GAHBCFG & OTG_HS_GAHBCFG_DMAEN) == 0U) + { + if ((USB_HS->HNPTXSTS & (0xFFU << 16)) == 0U) + { + USB_HS_HC(hcnum)->HCCHAR &= ~OTG_HS_HCCHAR_CHENA; + USB_HS_HC(hcnum)->HCCHAR |= OTG_HS_HCCHAR_CHENA; + do + { + count++; + if (count > 1000U) + { + break; + } + } while ((USB_HS_HC(hcnum)->HCCHAR & OTG_HS_HCCHAR_CHENA) == OTG_HS_HCCHAR_CHENA); + } + else + { + USB_HS_HC(hcnum)->HCCHAR |= OTG_HS_HCCHAR_CHENA; + } + } + else + { + USB_HS_HC(hcnum)->HCCHAR |= OTG_HS_HCCHAR_CHENA; + } + } + else + { + USB_HS_HC(hcnum)->HCCHAR |= OTG_HS_HCCHAR_CHDIS; + + if ((USB_HS_HOST->HPTXSTS & (0xFFU << 16)) == 0U) + { + USB_HS_HC(hcnum)->HCCHAR &= ~OTG_HS_HCCHAR_CHENA; + USB_HS_HC(hcnum)->HCCHAR |= OTG_HS_HCCHAR_CHENA; + do + { + count++; + if (count > 1000U) + { + break; + } + } while ((USB_HS_HC(hcnum)->HCCHAR & OTG_HS_HCCHAR_CHENA) == OTG_HS_HCCHAR_CHENA); + } + else + { + USB_HS_HC(hcnum)->HCCHAR |= OTG_HS_HCCHAR_CHENA; + } + } +} + +/** + * @brief Initiate Do Ping protocol + * @param USB_HS Selected device + * @param hc_num Host Channel number + * This parameter can be a value from 1 to 15 + */ +void USB_HS_DoPing(uint8_t ch_num) +{ + uint32_t chnum = (uint32_t)ch_num; + uint32_t num_packets = 1U; + uint32_t tmpreg; + + USB_HS_HC(chnum)->HCTSIZ = ((num_packets << 19) & OTG_HS_HCTSIZ_PKTCNT) | OTG_HS_HCTSIZ_DOPING; + + /* Set host channel enable */ + tmpreg = USB_HS_HC(chnum)->HCCHAR; + tmpreg &= ~OTG_HS_HCCHAR_CHDIS; + tmpreg |= OTG_HS_HCCHAR_CHENA; + USB_HS_HC(chnum)->HCCHAR = tmpreg; + +} + +/** + * @brief Stop Host Core + * @param USB_HS Selected device + * @retval USB_HS state + */ +USB_HS_StatusTypeDef USB_HS_StopHost(void) +{ + USB_HS_StatusTypeDef ret = USB_HS_OK; + __IO uint32_t count = 0U; + uint32_t value; + uint32_t i; + + USB_HS_DisableGlobalInt(); + + /* Flush FIFO */ + if (USB_HS_FlushTxFifo(0x10U) != USB_HS_OK) /* all Tx FIFOs */ + { + ret = USB_HS_ERROR; + } + if (USB_HS_FlushRxFifo() != USB_HS_OK) /* Rx FIFOs */ + { + ret = USB_HS_ERROR; + } + + /* Flush out any leftover queued requests. */ + for (i = 0U; i <= 15U; i++) + { + value = USB_HS_HC(i)->HCCHAR; + value |= OTG_HS_HCCHAR_CHDIS; + value &= ~OTG_HS_HCCHAR_CHENA; + value &= ~OTG_HS_HCCHAR_EPDIR; + USB_HS_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (i = 0U; i <= 15U; i++) + { + value = USB_HS_HC(i)->HCCHAR; + value |= OTG_HS_HCCHAR_CHDIS; + value |= OTG_HS_HCCHAR_CHENA; + value &= ~OTG_HS_HCCHAR_EPDIR; + USB_HS_HC(i)->HCCHAR = value; + + do + { + count++; + if (count > 1000U) + { + break; + } + } while ((USB_HS_HC(i)->HCCHAR & OTG_HS_HCCHAR_CHENA) == OTG_HS_HCCHAR_CHENA); + } + + /* Clear any pending Host interrupts */ + USB_HS_HOST->HAINT = CLEAR_INTERRUPT_MASK; + USB_HS->GINTSTS = CLEAR_INTERRUPT_MASK; + + (void)USB_HS_EnableGlobalInt(); + + return ret; +} + +/** + * @brief USB_HS_ActivateRemoteWakeup active remote wakeup signalling + * @param USB_HS Selected device + */ +void USB_HS_ActivateRemoteWakeup(void) +{ + + if ((USB_HS_DEVICE->DSTS & OTG_HS_DSTS_SUSPSTS) == OTG_HS_DSTS_SUSPSTS) + { + /* active Remote wakeup signalling */ + USB_HS_DEVICE->DCTL |= OTG_HS_DCTL_RWUSIG; + } + +} + +/** + * @brief USB_HS_DeActivateRemoteWakeup de-active remote wakeup signalling + * @param USB_HS Selected device + */ +void USB_HS_DeActivateRemoteWakeup(void) +{ + /* active Remote wakeup signalling */ + USB_HS_DEVICE->DCTL &= ~(OTG_HS_DCTL_RWUSIG); + +} +#endif /* defined (USB_OTG_HS) */ + +#endif /* defined (USB_OTG_HS) */ + + +#endif /* defined (PCD_MODULE_ENABLED) || defined (HCD_MODULE_ENABLED) */ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_wwdg.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_wwdg.c new file mode 100644 index 00000000000..6372f6e8c5d --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/src/ft32f4xx_wwdg.c @@ -0,0 +1,176 @@ +/** + ****************************************************************************** + * @file ft32f4xx_wwdg.c + * @author FMD AE + * @brief This file provides firmware functions to manage the following + * functionalities of the Window watchdog (WWDG) peripheral: + * + Prescaler, Refresh window and Counter configuration + * + WWDG activation + * + Interrupts and flags management + * @version V1.0.0 + * @data 2025-03-05 + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_wwdg.h" +#include "ft32f4xx_rcc.h" +/* --------------------- WWDG registers bit mask ---------------------------- */ +/* CFR register bit mask */ +#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) +#define CFR_W_MASK ((uint32_t)0xFFFFFF80) +#define BIT_MASK ((uint8_t)0x7F) + + +/** + * @brief Deinitializes the WWDG peripheral registers to their default reset values. + * @param None + * @retval None + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/** + * @brief Sets the WWDG Prescaler. + * @param WWDG_Prescaler: specifies the WWDG Prescaler. + * This parameter can be one of the following values: + * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 + * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 + * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 + * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 + * @retval None + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + /* Check the parameters */ + assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); + /* Clear WDGTB[1:0] bits */ + tmpreg = WWDG->CFR & CFR_WDGTB_MASK; + /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ + tmpreg |= WWDG_Prescaler; + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Sets the WWDG window value. + * @param WindowValue: specifies the window value to be compared to the downcounter. + * This parameter value must be lower than 0x80. + * @retval None + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); + /* Clear W[6:0] bits */ + + tmpreg = WWDG->CFR & CFR_W_MASK; + + /* Set W[6:0] bits according to WindowValue value */ + tmpreg |= WindowValue & (uint32_t) BIT_MASK; + + /* Store the new value */ + WWDG->CFR = tmpreg; +} + +/** + * @brief Enables the WWDG Early Wakeup interrupt(EWI). + * @note Once enabled this interrupt cannot be disabled except by a system reset. + * @param None + * @retval None + */ +void WWDG_EnableIT(void) +{ + WWDG->CFR |= WWDG_CFR_EWI; +} + +/** + * @brief Sets the WWDG counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent + * generating an immediate reset). + * @retval None + */ +void WWDG_SetCounter(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + /* Write to T[6:0] bits to configure the counter value, no need to do + a read-modify-write; writing a 0 to WDGA bit does nothing */ + WWDG->CR = Counter & BIT_MASK; +} + +/** + * @} + */ + +/** + * @brief Enables WWDG and load the counter value. + * @param Counter: specifies the watchdog counter value. + * This parameter must be a number between 0x40 and 0x7F (to prevent + * generating an immediate reset). + * @retval None + */ +void WWDG_Enable(uint8_t Counter) +{ + /* Check the parameters */ + assert_param(IS_WWDG_COUNTER(Counter)); + WWDG->CR = WWDG_CR_WDGA | Counter; +} +/** + * @} + */ + +/** + * @brief Checks whether the Early Wakeup interrupt flag is set or not. + * @param None + * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + FlagStatus bitstatus = RESET; + + if ((WWDG->SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/** + * @brief Clears Early Wakeup interrupt flag. + * @param None + * @retval None + */ +void WWDG_ClearFlag(void) +{ + WWDG->SR = (uint32_t)RESET; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT FMD *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/inc/FT32F4xx_it.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/inc/FT32F4xx_it.h new file mode 100644 index 00000000000..6ad4c5ee4e0 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/inc/FT32F4xx_it.h @@ -0,0 +1,54 @@ +/** + ****************************************************************************** + * @file ../ + * @author FMD AE + * @brief Main program body + * @version V1.0.0 + * @date 3-July-2025 + ****************************************************************************** + * @attention + * COPYRIGHT (C) 2025 Fremont Micro Devices (SZ) Corporation All rights reserved. + * This software is provided by the copyright holders and contributors,and the + * software is believed to be accurate and reliable. However, Fremont Micro + * Devices (SZ) Corporation assumes no responsibility for the consequences of + * use of such software or for any infringement of patents of other rights + * of third parties, which may result from its use. No license is granted by + * implication or otherwise under any patent rights of Fremont Micro Devices (SZ) + * Corporation. + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __FT32F4xx_IT_H +#define __FT32F4xx_IT_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __FT32F4xx_IT_H */ + + +/************************ (C) COPYRIGHT Fremont Micro Devices *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/inc/main.h b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/inc/main.h new file mode 100644 index 00000000000..bc283cc4375 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/inc/main.h @@ -0,0 +1,36 @@ +/** + ****************************************************************************** + * @file ../ + * @author FMD AE + * @brief Main program body + * @version V1.0.0 + * @date 3-July-2025 + ****************************************************************************** + * @attention + * COPYRIGHT (C) 2025 Fremont Micro Devices (SZ) Corporation All rights reserved. + * This software is provided by the copyright holders and contributors,and the + * software is believed to be accurate and reliable. However, Fremont Micro + * Devices (SZ) Corporation assumes no responsibility for the consequences of + * use of such software or for any infringement of patents of other rights + * of third parties, which may result from its use. No license is granted by + * implication or otherwise under any patent rights of Fremont Micro Devices (SZ) + * Corporation. + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx.h" + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions ------------------------------------------------------- */ + +void ADC_IRQHandler(void); + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT Fremont Micro Devices *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/src/FT32F4xx_it.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/src/FT32F4xx_it.c new file mode 100644 index 00000000000..860bc4ae893 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/src/FT32F4xx_it.c @@ -0,0 +1,162 @@ +/** + ****************************************************************************** + * @file ../ + * @author FMD AE + * @brief Main program body + * @version V1.0.0 + * @date 3-July-2025 + ****************************************************************************** + * @attention + * COPYRIGHT (C) 2025 Fremont Micro Devices (SZ) Corporation All rights reserved. + * This software is provided by the copyright holders and contributors,and the + * software is believed to be accurate and reliable. However, Fremont Micro + * Devices (SZ) Corporation assumes no responsibility for the consequences of + * use of such software or for any infringement of patents of other rights + * of third parties, which may result from its use. No license is granted by + * implication or otherwise under any patent rights of Fremont Micro Devices (SZ) + * Corporation. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "ft32f4xx_it.h" + +/** @addtogroup FT32F4xx_StdPeriph_Template + * @{ + */ + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M4 Processor Exceptions Handlers */ +/******************************************************************************/ + +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard Fault exception. + * @param None + * @retval None + */ +void HardFault_Handler(void) +{ + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) + { + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +#ifndef RTE_CMSIS_RTOS_RTX +void SVC_Handler(void) +{ +} +#endif + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ +} + +/** + * @brief This function handles PendSVC exception. + * @param None + * @retval None + */ +#ifndef RTE_CMSIS_RTOS_RTX +void PendSV_Handler(void) +{ +} +#endif + +/** + * @brief This function handles SysTick Handler. + * @param None + * @retval None + */ +#ifndef RTE_CMSIS_RTOS_RTX +void SysTick_Handler(void) +{ +} +#endif + +/******************************************************************************/ +/* FT32F4xx Peripherals Interrupt Handlers */ +/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ +/* available peripheral interrupt handler's name please refer to the startup */ +/* file (startup_FT32F4xx_xx.s). */ +/******************************************************************************/ + +/** + * @brief This function handles PPP interrupt request. + * @param None + * @retval None + */ +/*void PPP_IRQHandler(void) +{ +}*/ + +/** + * @} + */ + +/************************ (C) COPYRIGHT Fremont Micro Devices *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/src/main.c b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/src/main.c new file mode 100644 index 00000000000..de104913c70 --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/FT32F4xx_Driver/templates/src/main.c @@ -0,0 +1,73 @@ +/** + ****************************************************************************** + * @file ../ + * @author FMD AE + * @brief Main program body + * @version V1.0.0 + * @date 3-July-2025 + ****************************************************************************** + * @attention + * COPYRIGHT (C) 2025 Fremont Micro Devices (SZ) Corporation All rights reserved. + * This software is provided by the copyright holders and contributors,and the + * software is believed to be accurate and reliable. However, Fremont Micro + * Devices (SZ) Corporation assumes no responsibility for the consequences of + * use of such software or for any infringement of patents of other rights + * of third parties, which may result from its use. No license is granted by + * implication or otherwise under any patent rights of Fremont Micro Devices (SZ) + * Corporation. + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + +/** + * @brief Main program + * @param None + * @retval None + */ +int main(void) +{ + /* Main program loop */ + while(1) + { + } +} + +#ifdef USE_FULL_ASSERT + +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t* file, uint32_t line) +{ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + + while (1) + {} +} + +#endif + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT Fremont Micro Devices *****END OF FILE****/ diff --git a/bsp/ft32/libraries/FT32F4xx/SConscript b/bsp/ft32/libraries/FT32F4xx/SConscript new file mode 100644 index 00000000000..2e883833abd --- /dev/null +++ b/bsp/ft32/libraries/FT32F4xx/SConscript @@ -0,0 +1,97 @@ +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +CMSIS/FT32F4xx/source/system_ft32f4xx.c +FT32F4xx_Driver/src/ft32f4xx_comp.c +FT32F4xx_Driver/src/ft32f4xx_crc.c +FT32F4xx_Driver/src/ft32f4xx_crs.c +FT32F4xx_Driver/src/ft32f4xx_debug.c +FT32F4xx_Driver/src/ft32f4xx_dma.c +FT32F4xx_Driver/src/ft32f4xx_exti.c +FT32F4xx_Driver/src/ft32f4xx_gpio.c +FT32F4xx_Driver/src/ft32f4xx_iwdg.c +FT32F4xx_Driver/src/ft32f4xx_misc.c +FT32F4xx_Driver/src/ft32f4xx_opamp.c +FT32F4xx_Driver/src/ft32f4xx_pwr.c +FT32F4xx_Driver/src/ft32f4xx_rcc.c +FT32F4xx_Driver/src/ft32f4xx_syscfg.c +FT32F4xx_Driver/src/ft32f4xx_tim.c +""") + +if GetDepend(['RT_USING_ADC']): + src += ['FT32F4xx_Driver/src/ft32f4xx_adc.c'] + +if GetDepend(['RT_USING_DAC']): + src += ['FT32F4xx_Driver/src/ft32f4xx_dac.c'] + +if GetDepend(['RT_USING_ECAP']): + src += ['FT32F4xx_Driver/src/ft32f4xx_ecap.c'] + +if GetDepend(['RT_USING_EPWM']): + src += ['FT32F4xx_Driver/src/ft32f4xx_epwm.c'] + +if GetDepend(['RT_USING_EQEP']): + src += ['FT32F4xx_Driver/src/ft32f4xx_eqep.c'] + +if GetDepend(['RT_USING_FDCAN']): + src += ['FT32F4xx_Driver/src/ft32f4xx_fdcan.c'] + +if GetDepend(['RT_USING_FMC']): + src += ['FT32F4xx_Driver/src/ft32f4xx_fmc.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['FT32F4xx_Driver/src/ft32f4xx_usart.c'] + src += ['FT32F4xx_Driver/src/ft32f4xx_uart.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['FT32F4xx_Driver/src/ft32f4xx_i2c.c'] + +if GetDepend(['RT_USING_I2S']): + src += ['FT32F4xx_Driver/src/ft32f4xx_i2s.c'] + +if GetDepend(['RT_USING_LPTIM']): + src += ['FT32F4xx_Driver/src/ft32f4xx_lptim.c'] + +if GetDepend(['RT_USING_QSPI']): + src += ['FT32F4xx_Driver/src/ft32f4xx_qspi.c'] + +if GetDepend(['RT_USING_RNG']): + src += ['FT32F4xx_Driver/src/ft32f4xx_rng.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['FT32F4xx_Driver/src/ft32f4xx_spi.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['FT32F4xx_Driver/src/ft32f4xx_rtc.c'] + +if GetDepend(['RT_USING_SDIO']): + src += ['FT32F4xx_Driver/src/ft32f4xx_sdio.c'] + +if GetDepend(['RT_USING_SPDIF']): + src += ['FT32F4xx_Driver/src/ft32f4xx_spdif.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['FT32F4xx_Driver/src/ft32f4xx_wwdg.c'] + +if GetDepend(['RT_USING_SSI']): + src += ['FT32F4xx_Driver/src/ft32f4xx_ssi.c'] + +if GetDepend(['BSP_USING_ON_CHIP_FLASH']): + src += ['FT32F4xx_Driver/src/ft32f4xx_flash.c'] + +if GetDepend(['BSP_USING_ETH']): + src += ['FT32F4xx_Driver/src/ft32f4xx_eth.c'] + +path = [cwd + '/CMSIS/FT32F4xx/include', + cwd + '/FT32F4xx_Driver/inc', + cwd + '/FT32F4xx_Driver/templates/inc'] + +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path) + +Return('group') diff --git a/bsp/ft32/libraries/Kconfig b/bsp/ft32/libraries/Kconfig index afdd0fb83f0..6c690ec86f3 100644 --- a/bsp/ft32/libraries/Kconfig +++ b/bsp/ft32/libraries/Kconfig @@ -6,5 +6,8 @@ config SOC_SERIES_FT32F0 select ARCH_ARM_CORTEX_M0 select SOC_FAMILY_FT32 - +config SOC_SERIES_FT32F4 + bool + select ARCH_ARM_CORTEX_M4 + select SOC_FAMILY_FT32