diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 273c997e8eb..ca5934b4f3f 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -16,6 +16,8 @@ if rtconfig.CPU in common64_arch : else : group += SConscript(os.path.join('common', 'SConscript')) +group += SConscript(os.path.join('vector', 'SConscript')) + # cpu porting code files if 'VENDOR' in vars(rtconfig) and rtconfig.VENDOR != '': group = group + SConscript(os.path.join(rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) diff --git a/libcpu/risc-v/t-head/c908/SConscript b/libcpu/risc-v/t-head/c908/SConscript index 1f56051d1d4..0e2b4366234 100644 --- a/libcpu/risc-v/t-head/c908/SConscript +++ b/libcpu/risc-v/t-head/c908/SConscript @@ -5,9 +5,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -if GetDepend('ARCH_RISCV_VECTOR'): - CPPPATH += [cwd + '/../../vector/rvv-1.0'] - group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/risc-v/vector/SConscript b/libcpu/risc-v/vector/SConscript new file mode 100644 index 00000000000..69e8318e5ca --- /dev/null +++ b/libcpu/risc-v/vector/SConscript @@ -0,0 +1,12 @@ +# RT-Thread building script for component + +from building import * +cwd = GetCurrentDir() +src = [] +CPPPATH = [] + +CPPPATH += [cwd + '/rvv-1.0'] + +group = DefineGroup('libcpu', src, depend = ['ARCH_RISCV_VECTOR'], CPPPATH = CPPPATH) + +Return('group') diff --git a/libcpu/risc-v/virt64/SConscript b/libcpu/risc-v/virt64/SConscript index 0cfbd3cd6a3..0e2b4366234 100644 --- a/libcpu/risc-v/virt64/SConscript +++ b/libcpu/risc-v/virt64/SConscript @@ -5,9 +5,6 @@ cwd = GetCurrentDir() src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S') CPPPATH = [cwd] -if not GetDepend('ARCH_RISCV_VECTOR'): - SrcRemove(src, ['vector_gcc.S']) - group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH) Return('group') diff --git a/libcpu/risc-v/virt64/rvv_context.h b/libcpu/risc-v/virt64/rvv_context.h deleted file mode 100644 index a416396b1ea..00000000000 --- a/libcpu/risc-v/virt64/rvv_context.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2006-2024, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-10-10 RT-Thread the first version, - * compatible to riscv-v-spec-1.0 - */ -#ifndef __RVV_CONTEXT_H__ -#define __RVV_CONTEXT_H__ - -#include "cpuport.h" -#include "encoding.h" - -#if defined(ARCH_VECTOR_VLEN_128) - #define CTX_VECTOR_REGS 64 -#elif defined(ARCH_VECTOR_VLEN_256) - #define CTX_VECTOR_REGS 128 -#else -#error "No supported VLEN" -#endif /* VLEN */ - -#define CTX_VECTOR_REG_NR (CTX_VECTOR_REGS + 4) - -/** - * ================================== - * VECTOR EXTENSION - * ================================== - */ - -#define VEC_FRAME_VSTART (0 * REGBYTES) -#define VEC_FRAME_VTYPE (1 * REGBYTES) -#define VEC_FRAME_VL (2 * REGBYTES) -#define VEC_FRAME_VCSR (3 * REGBYTES) -#define VEC_FRAME_V0 (4 * REGBYTES) - -.macro GET_VEC_FRAME_LEN, xreg - csrr \xreg, vlenb - slli \xreg, \xreg, 5 - addi \xreg, \xreg, 4 * REGBYTES -.endm - -/** - * @brief save vector extension hardware state - * - * @param dst register storing bottom of storage block - * - */ -.macro SAVE_VECTOR, dst - mv t1, \dst - - csrr t0, vstart - STORE t0, VEC_FRAME_VSTART(t1) - csrr t0, vtype - STORE t0, VEC_FRAME_VTYPE(t1) - csrr t0, vl - STORE t0, VEC_FRAME_VL(t1) - csrr t0, vcsr - STORE t0, VEC_FRAME_VCSR(t1) - - addi t1, t1, VEC_FRAME_V0 - - // config vector setting, - // t2 is updated to length of a vector group in bytes - VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8) - - vse8.v v0, (t1) - add t1, t1, t2 - vse8.v v8, (t1) - add t1, t1, t2 - vse8.v v16, (t1) - add t1, t1, t2 - vse8.v v24, (t1) -.endm - -/** - * @brief restore vector extension hardware states - * - * @param dst register storing bottom of storage block - * - */ -.macro RESTORE_VECTOR, dst - // restore vector registers first since it will modify vector states - mv t0, \dst - addi t1, t0, VEC_FRAME_V0 - - VEC_CONFIG_SETVLI(t2, x0, VEC_IMM_SEW_8, VEC_IMM_LMUL_8) - - vle8.v v0, (t1) - add t1, t1, t2 - vle8.v v8, (t1) - add t1, t1, t2 - vle8.v v16, (t1) - add t1, t1, t2 - vle8.v v24, (t1) - - mv t1, t0 - - LOAD t0, VEC_FRAME_VSTART(t1) - csrw vstart, t0 - LOAD t0, VEC_FRAME_VCSR(t1) - csrw vcsr, t0 - - LOAD t0, VEC_FRAME_VTYPE(t1) - LOAD t3, VEC_FRAME_VL(t1) - VEC_CONFIG_SET_VL_VTYPE(t3, t0) -.endm - -#endif /* __RVV_CONTEXT_H__ */ diff --git a/libcpu/risc-v/virt64/vector_encoding.h b/libcpu/risc-v/virt64/vector_encoding.h deleted file mode 100644 index 26c2c86f4c8..00000000000 --- a/libcpu/risc-v/virt64/vector_encoding.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006-2022, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022-10-10 RT-Thread the first version, - * compatible to riscv-v-spec-1.0 - */ - -#ifndef __VECTOR_ENCODING_H__ -#define __VECTOR_ENCODING_H__ - -/* mstatus/sstatus */ -#define MSTATUS_VS 0x00000600 -#define SSTATUS_VS 0x00000600 /* Vector Status */ -#define SSTATUS_VS_INITIAL 0x00000200 -#define SSTATUS_VS_CLEAN 0x00000400 -#define SSTATUS_VS_DIRTY 0x00000600 - -/** - * assembler names used for vset{i}vli vtypei immediate - */ - -#define VEC_IMM_SEW_8 e8 -#define VEC_IMM_SEW_16 e16 -#define VEC_IMM_SEW_32 e32 -#define VEC_IMM_SEW_64 e64 -/* group setting, encoding by multiplier */ -#define VEC_IMM_LMUL_F8 mf8 -#define VEC_IMM_LMUL_F4 mf4 -#define VEC_IMM_LMUL_F2 mf2 -#define VEC_IMM_LMUL_1 m1 -#define VEC_IMM_LMUL_2 m2 -#define VEC_IMM_LMUL_4 m4 -#define VEC_IMM_LMUL_8 m8 -/* TAIL & MASK agnostic bits */ -#define VEC_IMM_TAIL_AGNOSTIC ta -#define VEC_IMM_MASK_AGNOSTIC ma -#define VEC_IMM_TAMA VEC_IMM_TAIL_AGNOSTIC, VEC_IMM_MASK_AGNOSTIC -#define VEC_IMM_TAMU VEC_IMM_TAIL_AGNOSTIC -#define VEC_IMM_TUMA VEC_IMM_MASK_AGNOSTIC - -/** - * configuration setting instruction - */ -#define VEC_CONFIG_SETVLI(xVl, xAvl, vtype...) vsetvli xVl, xAvl, ##vtype -#define VEC_CONFIG_SET_VL_VTYPE(xVl, xVtype) vsetvl x0, xVl, xVtype - -#endif /* __VECTOR_ENCODING_H__ */ \ No newline at end of file diff --git a/libcpu/risc-v/virt64/vector_gcc.S b/libcpu/risc-v/virt64/vector_gcc.S deleted file mode 100644 index 5c9047ec2e4..00000000000 --- a/libcpu/risc-v/virt64/vector_gcc.S +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2006-2024, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2018/10/28 Bernard The unify RISC-V porting implementation - * 2018/12/27 Jesven Add SMP support - * 2021/02/02 lizhirui Add userspace support - * 2022/10/22 Shell Support User mode RVV; - * Trimming process switch context - * 2024/09/01 Shell Separated vector ctx from the generic - */ - -#include "cpuport.h" -#include "stackframe.h" - -/** - * @param a0 pointer to frame bottom - */ -.global rt_hw_vector_ctx_save -rt_hw_vector_ctx_save: - SAVE_VECTOR a0 - ret - -/** - * @param a0 pointer to frame bottom - */ -.global rt_hw_vector_ctx_restore -rt_hw_vector_ctx_restore: - RESTORE_VECTOR a0 - ret - -.global rt_hw_disable_vector -rt_hw_disable_vector: - li t0, SSTATUS_VS - csrc sstatus, t0 - ret - -.global rt_hw_enable_vector -rt_hw_enable_vector: - li t0, SSTATUS_VS - csrs sstatus, t0 - ret