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RahixRahix
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treewide: Apply changes for new svd2rust API
As avr-device is upgrading to use svd2rust version 0.33.1, there are some significant changes in the generated API. We have to adapt the HAL code to use the new API whereever relevant. This commit was mostly generated using the following command, which adds the parentheses behind each register access to change it from struct-field access to method call. cargo build --message-format json 2>/dev/null \ | jq '.message.children[].spans[] | {file: .file_name, line: .line_start, col: (.text[0].highlight_start - 1), insert: .suggested_replacement}' 2>/dev/null \ | jq -r '"sed -ri '"'"'" + (.line | tostring) + "s/^(.{" + (.col | tostring) + "})/\\1" + .insert + "/'"'"' $(cd ../..; realpath " + .file + ")"' \ | sort | uniq | bash Shell magic for the win :) Beyond this, .bits() had to be converted to .set() where safe accesses are performed.
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-385
lines changed

25 files changed

+387
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lines changed

‎avr-hal-generic/src/adc.rs‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -250,17 +250,17 @@ macro_rules! impl_adc {
250250

251251
#[inline]
252252
fn raw_read_adc(&self) -> u16 {
253-
self.adc.read().bits()
253+
self.adc().read().bits()
254254
}
255255

256256
#[inline]
257257
fn raw_is_converting(&self) -> bool {
258-
self.adcsra.read().adsc().bit_is_set()
258+
self.adcsra().read().adsc().bit_is_set()
259259
}
260260

261261
#[inline]
262262
fn raw_start_conversion(&mut self) {
263-
self.adcsra.modify(|_, w| w.adsc().set_bit());
263+
self.adcsra().modify(|_, w| w.adsc().set_bit());
264264
}
265265

266266
#[inline]
@@ -276,7 +276,7 @@ macro_rules! impl_adc {
276276
match channel {
277277
$(
278278
x if x == $pin_channel => {
279-
$(self.$didr.modify(|_, w| w.$didr_method().set_bit());)?
279+
$(self.$didr().modify(|_, w| w.$didr_method().set_bit());)?
280280
}
281281
)+
282282
_ => unreachable!(),
@@ -288,7 +288,7 @@ macro_rules! impl_adc {
288288
match channel {
289289
$(
290290
x if x == $pin_channel => {
291-
$(self.$didr.modify(|_, w| w.$didr_method().clear_bit());)?
291+
$(self.$didr().modify(|_, w| w.$didr_method().clear_bit());)?
292292
}
293293
)+
294294
_ => unreachable!(),

‎avr-hal-generic/src/eeprom.rs‎

Lines changed: 25 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -159,8 +159,8 @@ macro_rules! impl_eeprom_common {
159159
$set_address
160160
}
161161

162-
self.eecr.write(|w| w.eere().set_bit());
163-
self.eedr.read().bits()
162+
self.eecr().write(|w| w.eere().set_bit());
163+
self.eedr().read().bits()
164164
}
165165
}
166166

@@ -173,8 +173,8 @@ macro_rules! impl_eeprom_common {
173173
}
174174

175175
//Start EEPROM read operation
176-
self.eecr.write(|w| w.eere().set_bit());
177-
let old_value = self.eedr.read().bits();
176+
self.eecr().write(|w| w.eere().set_bit());
177+
let old_value = self.eedr().read().bits();
178178
let diff_mask = old_value ^ data;
179179

180180
// Check if any bits are changed to '1' in the new value.
@@ -184,33 +184,33 @@ macro_rules! impl_eeprom_common {
184184
// Check if any bits in the new value are '0'.
185185
if data != 0xff {
186186
// Now we know that some bits need to be programmed to '0' also.
187-
self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
187+
self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.
188188

189189
{
190190
let $periph_ewmode_var = &self;
191191
$set_erasewrite_mode
192192
}
193-
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
193+
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
194194
} else {
195195
// Now we know that all bits should be erased.
196196
{
197197
let $periph_emode_var = &self;
198198
$set_erase_mode
199199
}
200-
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
200+
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
201201
}
202202
}
203203
//Now we know that _no_ bits need to be erased to '1'.
204204
else {
205205
// Check if any bits are changed from '1' in the old value.
206206
if diff_mask != 0 {
207207
// Now we know that _some_ bits need to the programmed to '0'.
208-
self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
208+
self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.
209209
{
210210
let $periph_wmode_var = &self;
211211
$set_write_mode
212212
}
213-
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
213+
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
214214
}
215215
}
216216
}
@@ -229,7 +229,7 @@ macro_rules! impl_eeprom_common {
229229
$set_erase_mode
230230
}
231231
// Start Erase-only operation.
232-
self.eecr.modify(|_, w| w.eepe().set_bit());
232+
self.eecr().modify(|_, w| w.eepe().set_bit());
233233
}
234234
}
235235
}
@@ -249,7 +249,7 @@ macro_rules! impl_eeprom_atmega_old {
249249
#[inline]
250250
pub unsafe fn wait_read(regs: &$EEPROM) {
251251
//Wait for completion of previous write.
252-
while regs.eecr.read().eewe().bit_is_set() {}
252+
while regs.eecr().read().eewe().bit_is_set() {}
253253
}
254254

255255
#[inline]
@@ -268,8 +268,8 @@ macro_rules! impl_eeprom_atmega_old {
268268
unsafe {
269269
atmega_helper::set_address(&self, address);
270270
}
271-
self.eecr.write(|w| w.eere().set_bit());
272-
self.eedr.read().bits()
271+
self.eecr().write(|w| w.eere().set_bit());
272+
self.eedr().read().bits()
273273
}
274274

275275
fn raw_write_byte(&mut self, address: u16, data: u8) {
@@ -278,11 +278,12 @@ macro_rules! impl_eeprom_atmega_old {
278278
}
279279

280280
//Start EEPROM read operation
281-
self.eedr.write(|w| unsafe { w.bits(data) });
281+
self.eedr().write(|w| unsafe { w.bits(data) });
282282

283-
self.eecr.write(|w| w.eemwe().set_bit().eewe().clear_bit());
283+
self.eecr()
284+
.write(|w| w.eemwe().set_bit().eewe().clear_bit());
284285

285-
self.eecr.write(|w| w.eewe().set_bit());
286+
self.eecr().write(|w| w.eewe().set_bit());
286287
}
287288

288289
fn raw_erase_byte(&mut self, address: u16) {
@@ -305,7 +306,7 @@ macro_rules! impl_eeprom_atmega {
305306
#[inline]
306307
pub unsafe fn wait_read(regs: &$EEPROM) {
307308
//Wait for completion of previous write.
308-
while regs.eecr.read().eepe().bit_is_set() {}
309+
while regs.eecr().read().eepe().bit_is_set() {}
309310
}
310311
#[inline]
311312
pub unsafe fn set_address(regs: &$EEPROM, address: $addrwidth) {
@@ -316,21 +317,21 @@ macro_rules! impl_eeprom_atmega {
316317
}
317318
#[inline]
318319
pub unsafe fn set_erasewrite_mode(regs: &$EEPROM) {
319-
regs.eecr.write(|w| {
320+
regs.eecr().write(|w| {
320321
// Set Master Write Enable bit, and and Erase+Write mode mode..
321322
w.eempe().set_bit().eepm().val_0x00()
322323
})
323324
}
324325
#[inline]
325326
pub unsafe fn set_erase_mode(regs: &$EEPROM) {
326-
regs.eecr.write(|w| {
327+
regs.eecr().write(|w| {
327328
// Set Master Write Enable bit, and Erase-only mode..
328329
w.eempe().set_bit().eepm().val_0x01()
329330
});
330331
}
331332
#[inline]
332333
pub unsafe fn set_write_mode(regs: &$EEPROM) {
333-
regs.eecr.write(|w| {
334+
regs.eecr().write(|w| {
334335
// Set Master Write Enable bit, and Write-only mode..
335336
w.eempe().set_bit().eepm().val_0x02()
336337
});
@@ -362,7 +363,7 @@ macro_rules! impl_eeprom_attiny {
362363
mod attiny_helper {
363364
#[inline]
364365
pub unsafe fn wait_read(regs: &$EEPROM) {
365-
while regs.eecr.read().eepe().bit_is_set() {}
366+
while regs.eecr().read().eepe().bit_is_set() {}
366367
}
367368
#[inline]
368369
pub unsafe fn set_address(regs: &$EEPROM, address: $addrwidth) {
@@ -373,21 +374,21 @@ macro_rules! impl_eeprom_attiny {
373374
}
374375
#[inline]
375376
pub unsafe fn set_erasewrite_mode(regs: &$EEPROM) {
376-
regs.eecr.write(|w| {
377+
regs.eecr().write(|w| {
377378
// Set Master Write Enable bit...and and Erase+Write mode mode..
378379
w.eempe().set_bit().eepm().atomic()
379380
});
380381
}
381382
#[inline]
382383
pub unsafe fn set_erase_mode(regs: &$EEPROM) {
383-
regs.eecr.write(|w| {
384+
regs.eecr().write(|w| {
384385
// Set Master Write Enable bit, and Erase-only mode..
385386
w.eempe().set_bit().eepm().erase()
386387
});
387388
}
388389
#[inline]
389390
pub unsafe fn set_write_mode(regs: &$EEPROM) {
390-
regs.eecr.write(|w| {
391+
regs.eecr().write(|w| {
391392
// Set Master Write Enable bit, and Write-only mode..
392393
w.eempe().set_bit().eepm().write()
393394
});

‎avr-hal-generic/src/i2c.rs‎

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -478,23 +478,23 @@ macro_rules! impl_i2c_twi {
478478
fn raw_setup<CLOCK: $crate::clock::Clock>(&mut self, speed: u32) {
479479
// Calculate TWBR register value
480480
let twbr = ((CLOCK::FREQ / speed) - 16) / 2;
481-
self.twbr
481+
self.twbr()
482482
.write(|w| unsafe { w.bits(twbr.try_into().unwrap()) });
483483

484484
// Disable prescaler
485-
self.twsr.write(|w| w.twps().prescaler_1());
485+
self.twsr().write(|w| w.twps().prescaler_1());
486486
}
487487

488488
#[inline]
489489
fn raw_start(&mut self, address: u8, direction: Direction) -> Result<(), Error> {
490490
// Write start condition
491-
self.twcr
491+
self.twcr()
492492
.write(|w| w.twen().set_bit().twint().set_bit().twsta().set_bit());
493493
// wait()
494-
while self.twcr.read().twint().bit_is_clear() {}
494+
while self.twcr().read().twint().bit_is_clear() {}
495495

496496
// Validate status
497-
match self.twsr.read().tws().bits() {
497+
match self.twsr().read().tws().bits() {
498498
$crate::i2c::twi_status::TW_START | $crate::i2c::twi_status::TW_REP_START => (),
499499
$crate::i2c::twi_status::TW_MT_ARB_LOST
500500
| $crate::i2c::twi_status::TW_MR_ARB_LOST => {
@@ -515,13 +515,13 @@ macro_rules! impl_i2c_twi {
515515
0
516516
};
517517
let rawaddr = (address << 1) | dirbit;
518-
self.twdr.write(|w| unsafe { w.bits(rawaddr) });
518+
self.twdr().write(|w| unsafe { w.bits(rawaddr) });
519519
// transact()
520-
self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
521-
while self.twcr.read().twint().bit_is_clear() {}
520+
self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
521+
while self.twcr().read().twint().bit_is_clear() {}
522522

523523
// Check if the slave responded
524-
match self.twsr.read().tws().bits() {
524+
match self.twsr().read().tws().bits() {
525525
$crate::i2c::twi_status::TW_MT_SLA_ACK
526526
| $crate::i2c::twi_status::TW_MR_SLA_ACK => (),
527527
$crate::i2c::twi_status::TW_MT_SLA_NACK
@@ -548,12 +548,12 @@ macro_rules! impl_i2c_twi {
548548
#[inline]
549549
fn raw_write(&mut self, bytes: &[u8]) -> Result<(), Error> {
550550
for byte in bytes {
551-
self.twdr.write(|w| unsafe { w.bits(*byte) });
551+
self.twdr().write(|w| unsafe { w.bits(*byte) });
552552
// transact()
553-
self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
554-
while self.twcr.read().twint().bit_is_clear() {}
553+
self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
554+
while self.twcr().read().twint().bit_is_clear() {}
555555

556-
match self.twsr.read().tws().bits() {
556+
match self.twsr().read().tws().bits() {
557557
$crate::i2c::twi_status::TW_MT_DATA_ACK => (),
558558
$crate::i2c::twi_status::TW_MT_DATA_NACK => {
559559
self.raw_stop()?;
@@ -578,17 +578,17 @@ macro_rules! impl_i2c_twi {
578578
let last = buffer.len() - 1;
579579
for (i, byte) in buffer.iter_mut().enumerate() {
580580
if i != last || !last_read {
581-
self.twcr
581+
self.twcr()
582582
.write(|w| w.twint().set_bit().twen().set_bit().twea().set_bit());
583583
// wait()
584-
while self.twcr.read().twint().bit_is_clear() {}
584+
while self.twcr().read().twint().bit_is_clear() {}
585585
} else {
586-
self.twcr.write(|w| w.twint().set_bit().twen().set_bit());
586+
self.twcr().write(|w| w.twint().set_bit().twen().set_bit());
587587
// wait()
588-
while self.twcr.read().twint().bit_is_clear() {}
588+
while self.twcr().read().twint().bit_is_clear() {}
589589
}
590590

591-
match self.twsr.read().tws().bits() {
591+
match self.twsr().read().tws().bits() {
592592
$crate::i2c::twi_status::TW_MR_DATA_ACK
593593
| $crate::i2c::twi_status::TW_MR_DATA_NACK => (),
594594
$crate::i2c::twi_status::TW_MR_ARB_LOST => {
@@ -602,14 +602,14 @@ macro_rules! impl_i2c_twi {
602602
}
603603
}
604604

605-
*byte = self.twdr.read().bits();
605+
*byte = self.twdr().read().bits();
606606
}
607607
Ok(())
608608
}
609609

610610
#[inline]
611611
fn raw_stop(&mut self) -> Result<(), Error> {
612-
self.twcr
612+
self.twcr()
613613
.write(|w| w.twen().set_bit().twint().set_bit().twsto().set_bit());
614614
Ok(())
615615
}

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