feat(interrupts): 添加APIC中断注册表管理IRQ处理器

Author: moyanj

kernel/src/interrupts/apic/mod.rs

@@ -9,6 +9,7 @@ use spin::Mutex;
 use x86_64::registers::model_specific::Msr;
 
 pub mod ioapic;
+pub mod registry;
 
 const APIC_SIVR_ENABLE: u32 = 0x100;
 const APIC_BASE_ENABLE: u64 = 1 << 11;

kernel/src/interrupts/apic/registry.rs

@@ -0,0 +1,101 @@
+use crate::libs::time::time_since_boot;
+use spin::Mutex;
+use x86_64::structures::idt::InterruptStackFrame;
+
+pub static IRQ_REGISTRY: Mutex<IrqRegistry> = Mutex::new(IrqRegistry::new());
+
+pub type IrqHandler = for<'a> fn(IrqContext<'a>) -> IrqResult;
+
+pub struct IrqRegistry {
+    handlers: [Option<IrqHandler>; 256],
+    names: [Option<&'static str>; 256],
+    stats: [IrqStats; 256],
+}
+
+pub struct IrqContext<'a> {
+    pub vector: u8,
+    pub irq_number: Option<u8>, // None for exceptions
+    pub stack_frame: &'a InterruptStackFrame,
+    pub error_code: Option<u64>,
+}
+
+pub enum IrqResult {
+    /// Continue execution
+    Continue,
+    /// Interrupt is handled
+    Handled,
+}
+
+#[derive(Default, Clone, Copy, Debug)]
+pub struct IrqStats {
+    /// Number of interrupts
+    pub count: u64,
+    /// Time spent in last interrupt handler
+    pub last_time: u64,
+    /// Time of last interrupt
+    pub interrupt_time: u64,
+}
+
+impl IrqStats {
+    pub const fn new() -> Self {
+        Self {
+            count: 0,
+            last_time: 0,
+            interrupt_time: 0,
+        }
+    }
+}
+
+impl IrqRegistry {
+    pub const fn new() -> Self {
+        Self {
+            handlers: [None; 256],
+            names: [None; 256],
+            stats: [IrqStats::new(); 256],
+        }
+    }
+
+    pub fn register(
+        &mut self,
+        vector: u8,
+        name: &'static str,
+        handler: IrqHandler,
+    ) -> Result<(), &'static str> {
+        if self.handlers[vector as usize].is_some() {
+            return Err("Handler already registered");
+        }
+        self.handlers[vector as usize] = Some(handler);
+        self.names[vector as usize] = Some(name);
+        self.stats[vector as usize] = IrqStats::new();
+        Ok(())
+    }
+
+    pub fn unregister(&mut self, vector: u8) -> Result<(), &'static str> {
+        if self.handlers[vector as usize].is_none() {
+            return Err("Handler not registered");
+        }
+        self.handlers[vector as usize] = None;
+        self.names[vector as usize] = None;
+        self.stats[vector as usize] = IrqStats::new();
+        Ok(())
+    }
+
+    pub fn handle(&mut self, context: IrqContext) -> IrqResult {
+        let vector = context.vector as usize;
+        self.stats[vector].count += 1;
+        let st = time_since_boot();
+        self.stats[vector].interrupt_time = st as u64;
+        match self.handlers[vector] {
+            Some(handler) => {
+                let result = handler(context);
+                self.stats[vector].last_time = (time_since_boot() - st) as u64;
+                result
+            }
+            None => IrqResult::Continue,
+        }
+    }
+
+    pub fn get_stats(&self, vector: u8) -> IrqStats {
+        self.stats[vector as usize]
+    }
+}

kernel/src/interrupts/handler.rs

@@ -1,5 +1,7 @@
 #[allow(unused)]
 use crate::interrupts::apic;
+use crate::interrupts::apic::registry::{IrqContext, IRQ_REGISTRY};
+use crate::interrupts::idt::IRQ_BASE;
 use crate::panic::{ExceptionInfo, EXCEPTION_INFO};
 use crate::serial_println;
 use x86_64::{
@@ -150,42 +152,70 @@ pub extern "x86-interrupt" fn machine_check_handler(stack_frame: InterruptStackF
     panic!("CRITICAL: MACHINE CHECK");
 }
 
-pub extern "x86-interrupt" fn timer_interrupt_handler(_stack_frame: InterruptStackFrame) {
-    // APIC Timer interrupt
-    // For now just EOI
+pub extern "x86-interrupt" fn timer_interrupt_handler(stack_frame: InterruptStackFrame) {
+    let context = IrqContext {
+        vector: crate::interrupts::apic::TIMER_VECTOR,
+        irq_number: None, // APIC timer is not a standard ISA IRQ
+        stack_frame: &stack_frame,
+        error_code: None,
+    };
+
+    if let Some(mut registry) = IRQ_REGISTRY.try_lock() {
+        registry.handle(context);
+    }
+
     apic::end_of_interrupt();
 }
 
-macro_rules! pic_interrupt_handler {
+macro_rules! ioapic_interrupt_handler {
     ($name:ident, $irq_number:expr) => {
         #[allow(unused_variables)]
         pub extern "x86-interrupt" fn $name(stack_frame: InterruptStackFrame) {
-            if $irq_number == 1 {
-                let mut port = x86_64::instructions::port::Port::<u8>::new(0x60);
-                let scancode = unsafe { port.read() };
-                crate::drivers::input::keyboard::KEYBOARD.handle_scancode(scancode);
-            } else {
-                serial_println!("IRQ {} received!", $irq_number);
+            let vector = IRQ_BASE + $irq_number;
+            let context = IrqContext {
+                vector,
+                irq_number: Some($irq_number),
+                stack_frame: &stack_frame,
+                error_code: None,
+            };
+
+            let mut handled = false;
+            if let Some(mut registry) = IRQ_REGISTRY.try_lock() {
+                if let crate::interrupts::apic::registry::IrqResult::Handled =
+                    registry.handle(context)
+                {
+                    handled = true;
+                }
+            }
+
+            if !handled {
+                if $irq_number == 1 {
+                    let mut port = x86_64::instructions::port::Port::<u8>::new(0x60);
+                    let scancode = unsafe { port.read() };
+                    crate::drivers::input::keyboard::KEYBOARD.handle_scancode(scancode);
+                } else {
+                    serial_println!("IRQ {} received!", $irq_number);
+                }
             }
 
             apic::end_of_interrupt();
         }
     };
 }
 // 为所有 16 个 IRQ 定义处理函数
-pic_interrupt_handler!(pic_interrupt_handler_0, 0); // Timer Interrupt
-pic_interrupt_handler!(pic_interrupt_handler_1, 1); // Keyboard Interrupt
-pic_interrupt_handler!(pic_interrupt_handler_2, 2); // Cascade to PIC2
-pic_interrupt_handler!(pic_interrupt_handler_3, 3); // Serial COM2
-pic_interrupt_handler!(pic_interrupt_handler_4, 4); // Serial COM1
-pic_interrupt_handler!(pic_interrupt_handler_5, 5); // Parallel Port LPT2 / Sound Card
-pic_interrupt_handler!(pic_interrupt_handler_6, 6); // Floppy Disk Controller
-pic_interrupt_handler!(pic_interrupt_handler_7, 7); // Parallel Port LPT1 / Fake Interrupt
-pic_interrupt_handler!(pic_interrupt_handler_8, 8); // RTC Real Time Clock
-pic_interrupt_handler!(pic_interrupt_handler_9, 9); // Redirect IRQ2
-pic_interrupt_handler!(pic_interrupt_handler_10, 10); // Freed / SCSI / Netcard
-pic_interrupt_handler!(pic_interrupt_handler_11, 11); // Freed / SCSI / Netcard
-pic_interrupt_handler!(pic_interrupt_handler_12, 12); // PS/2 mouse
-pic_interrupt_handler!(pic_interrupt_handler_13, 13); // FPU / MPU
-pic_interrupt_handler!(pic_interrupt_handler_14, 14); // Primary IDE
-pic_interrupt_handler!(pic_interrupt_handler_15, 15); // Secondary IDE
+ioapic_interrupt_handler!(ioapic_interrupt_handler_0, 0); // Timer Interrupt
+ioapic_interrupt_handler!(ioapic_interrupt_handler_1, 1); // Keyboard Interrupt
+ioapic_interrupt_handler!(ioapic_interrupt_handler_2, 2); // Cascade to PIC2
+ioapic_interrupt_handler!(ioapic_interrupt_handler_3, 3); // Serial COM2
+ioapic_interrupt_handler!(ioapic_interrupt_handler_4, 4); // Serial COM1
+ioapic_interrupt_handler!(ioapic_interrupt_handler_5, 5); // Parallel Port LPT2 / Sound Card
+ioapic_interrupt_handler!(ioapic_interrupt_handler_6, 6); // Floppy Disk Controller
+ioapic_interrupt_handler!(ioapic_interrupt_handler_7, 7); // Parallel Port LPT1 / Fake Interrupt
+ioapic_interrupt_handler!(ioapic_interrupt_handler_8, 8); // RTC Real Time Clock
+ioapic_interrupt_handler!(ioapic_interrupt_handler_9, 9); // Redirect IRQ2
+ioapic_interrupt_handler!(ioapic_interrupt_handler_10, 10); // Freed / SCSI / Netcard
+ioapic_interrupt_handler!(ioapic_interrupt_handler_11, 11); // Freed / SCSI / Netcard
+ioapic_interrupt_handler!(ioapic_interrupt_handler_12, 12); // PS/2 mouse
+ioapic_interrupt_handler!(ioapic_interrupt_handler_13, 13); // FPU / MPU
+ioapic_interrupt_handler!(ioapic_interrupt_handler_14, 14); // Primary IDE
+ioapic_interrupt_handler!(ioapic_interrupt_handler_15, 15); // Secondary IDE

kernel/src/interrupts/idt.rs

@@ -44,22 +44,22 @@ lazy_static! {
         }
         // IOAPIC interrupt handlers
         // IRQ0 - Clock Interrupt, IRQ1 - Keyboard Interrupt
-        idt[IRQ_BASE].set_handler_fn(handler::pic_interrupt_handler_0); // IRQ0
-        idt[IRQ_BASE + 1].set_handler_fn(handler::pic_interrupt_handler_1); // IRQ1
-        idt[IRQ_BASE + 2].set_handler_fn(handler::pic_interrupt_handler_2); // IRQ2
-        idt[IRQ_BASE + 3].set_handler_fn(handler::pic_interrupt_handler_3); // IRQ3
-        idt[IRQ_BASE + 4].set_handler_fn(handler::pic_interrupt_handler_4); // IRQ4
-        idt[IRQ_BASE + 5].set_handler_fn(handler::pic_interrupt_handler_5); // IRQ5
-        idt[IRQ_BASE + 6].set_handler_fn(handler::pic_interrupt_handler_6); // IRQ6
-        idt[IRQ_BASE + 7].set_handler_fn(handler::pic_interrupt_handler_7); // IRQ7
-        idt[IRQ_BASE + 8].set_handler_fn(handler::pic_interrupt_handler_8);   // IRQ8
-        idt[IRQ_BASE + 9].set_handler_fn(handler::pic_interrupt_handler_9);   // IRQ9
-        idt[IRQ_BASE + 10].set_handler_fn(handler::pic_interrupt_handler_10);  // IRQ10
-        idt[IRQ_BASE + 11].set_handler_fn(handler::pic_interrupt_handler_11);  // IRQ11
-        idt[IRQ_BASE + 12].set_handler_fn(handler::pic_interrupt_handler_12);  // IRQ12
-        idt[IRQ_BASE + 13].set_handler_fn(handler::pic_interrupt_handler_13);  // IRQ13
-        idt[IRQ_BASE + 14].set_handler_fn(handler::pic_interrupt_handler_14);  // IRQ14
-        idt[IRQ_BASE + 15].set_handler_fn(handler::pic_interrupt_handler_15);  // IRQ15
+        idt[IRQ_BASE].set_handler_fn(handler::ioapic_interrupt_handler_0); // IRQ0
+        idt[IRQ_BASE + 1].set_handler_fn(handler::ioapic_interrupt_handler_1); // IRQ1
+        idt[IRQ_BASE + 2].set_handler_fn(handler::ioapic_interrupt_handler_2); // IRQ2
+        idt[IRQ_BASE + 3].set_handler_fn(handler::ioapic_interrupt_handler_3); // IRQ3
+        idt[IRQ_BASE + 4].set_handler_fn(handler::ioapic_interrupt_handler_4); // IRQ4
+        idt[IRQ_BASE + 5].set_handler_fn(handler::ioapic_interrupt_handler_5); // IRQ5
+        idt[IRQ_BASE + 6].set_handler_fn(handler::ioapic_interrupt_handler_6); // IRQ6
+        idt[IRQ_BASE + 7].set_handler_fn(handler::ioapic_interrupt_handler_7); // IRQ7
+        idt[IRQ_BASE + 8].set_handler_fn(handler::ioapic_interrupt_handler_8);   // IRQ8
+        idt[IRQ_BASE + 9].set_handler_fn(handler::ioapic_interrupt_handler_9);   // IRQ9
+        idt[IRQ_BASE + 10].set_handler_fn(handler::ioapic_interrupt_handler_10);  // IRQ10
+        idt[IRQ_BASE + 11].set_handler_fn(handler::ioapic_interrupt_handler_11);  // IRQ11
+        idt[IRQ_BASE + 12].set_handler_fn(handler::ioapic_interrupt_handler_12);  // IRQ12
+        idt[IRQ_BASE + 13].set_handler_fn(handler::ioapic_interrupt_handler_13);  // IRQ13
+        idt[IRQ_BASE + 14].set_handler_fn(handler::ioapic_interrupt_handler_14);  // IRQ14
+        idt[IRQ_BASE + 15].set_handler_fn(handler::ioapic_interrupt_handler_15);  // IRQ15
         idt
     };
 }

kernel/src/main.rs

@@ -49,6 +49,21 @@ pub extern "C" fn kernel_main() -> ! {
         0,
     );
 
+    // Register Keyboard Handler via Registry
+    proka_kernel::interrupts::apic::registry::IRQ_REGISTRY
+        .lock()
+        .register(
+            proka_kernel::interrupts::idt::IRQ_BASE + 1,
+            "Keyboard",
+            |_context| {
+                let mut port = x86_64::instructions::port::Port::<u8>::new(0x60);
+                let scancode = unsafe { port.read() };
+                proka_kernel::drivers::input::keyboard::KEYBOARD.handle_scancode(scancode);
+                proka_kernel::interrupts::apic::registry::IrqResult::Handled
+            },
+        )
+        .expect("Failed to register keyboard handler");
+
     proka_kernel::drivers::init_devices(); // Initialize devices
     proka_kernel::libs::time::init(); // Init time system