Bug in ahci_init ???

[macpacheco]

; -----------------------------------------------------------------------------
ahci_init:
	push rsi			; Used in init_storage
	push rdx			; RDX should already point to a supported device for os_bus_read/write

	mov al, 5			; Read BAR5
	call os_bus_read_bar
	mov [ahci_base], rax
	mov rsi, rax			; RSI holds the ABAR

	; Set PCI Status/Command values
	mov dl, 0x01			; Read Status/Command
	call os_bus_read
	bts eax, 10			; Set Interrupt Disable
	bts eax, 2			; Enable Bus Master
	bts eax, 1			; Enable Memory Space
	call os_bus_write		; Write updated Status/Command

	; Mark controller memory as un-cacheable
	shr rax, 18
	and al, 0b11111000		; Clear the last 3 bits
	mov rdi, 0x10000		; Base of low PDE
	add rdi, rax
	mov rax, [rdi]
	btc rax, 3			; Clear PWT to disable caching
	bts rax, 4			; Set PCD to disable caching
	mov [rdi], rax

---> shr rax,18 ; rax contains input to os_bus_write, with Status/Command register
I think you want ahci_base in there ?????

[IanSeyler]

Correct! That should be the base that gets shifted. I’ll get this fixed.

[IanSeyler]

This has been corrected - ReturnInfinity/BareMetal@c8f504a