@@ -99,24 +99,24 @@ net_ena_reset:
9999 ; Stop queues if they are running
100100
101101 ; Reset interface
102- mov eax , 1
102+ mov eax , 1 ; Set the bit for ENA_CTRL_RESET
103103 mov [ rsi + ENA_DEV_CTL ], eax
104104
105105 ; Wait for reset
106106net_ena_reset_wait:
107- mov eax , [ rsi + ENA_DEV_STS ]
108- bt eax , 3
109- jc net_ena_reset_wait
107+ mov eax , [ rsi + ENA_DEV_STS ] ; Read the current controller status
108+ bt eax , 3 ; Put bit 3 into carry flag
109+ jc net_ena_reset_wait ; Keep polling until carry is clear (reset completed)
110110
111111 ; Clear reset
112- xor eax , eax
112+ xor eax , eax ; Clear the ENA_CTRL_RESET bit we set earlier
113113 mov [ rsi + ENA_DEV_CTL ], eax
114114
115115 ; Wait for reset clear
116116net_ena_reset_wait_clear:
117- mov eax , [ rsi + ENA_DEV_STS ]
118- bt eax , 3
119- jnc net_ena_reset_wait_clear
117+ mov eax , [ rsi + ENA_DEV_STS ] ; Read the current controller status
118+ bt eax , 3 ; Put bit 3 into carry flag
119+ jnc net_ena_reset_wait_clear ; Keep polling until carry is set
120120
121121 ; Check ENA_DEV_STS.READY
122122 mov eax , [ rsi + ENA_DEV_STS ]
@@ -145,7 +145,7 @@ net_ena_reset_wait_clear:
145145 shr rax , 32
146146 mov [ rsi + ENA_AENQ_BASE_HI ], eax
147147
148- ; Create Admin Queue
148+ ; Create Admin Queues
149149 ; Admin Submission Queue (AQ)
150150 ; Admin Completion Queue (ACQ)
151151
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