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Ian Seyler
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Start of ENA driver
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‎build.sh‎

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@@ -12,6 +12,7 @@ BUILDFLAGS=""
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# -dNO_I8254X Remove i8254x Gigabit driver
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# -dNO_I8257X Remove i8257x Gigabit driver
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# -dNO_I8259X Remove i8259x 10-Gigabit driver
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# -dNO_ENA Remove ENA driver
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# HID
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# -dNO_XHCI Remove xHCI USB driver (hid)
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# -dNO_LFB Remove LFB text driver

‎src/drivers.asm‎

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@@ -50,6 +50,9 @@
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%ifndef NO_VIRTIO
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%include "drivers/net/virtio-net.asm"
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%endif
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%ifndef NO_ENA
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%include "drivers/net/ena.asm"
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%endif
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; %include "drivers/net/r8169.asm"
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; Video
@@ -158,6 +161,16 @@ dw 0x1572 ; X710 (SFP+)
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dw 0x0000
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%endif
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%ifndef NO_ENA
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dw 0x0EC2 ; Driver ID
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dw 0x1D0F ; Vendor ID (Amazon)
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dw 0x0EC2 ; ENA_PF
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dw 0x1EC2 ; ENA_LLQ_PF
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dw 0xEC20 ; ENA_VF
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dw 0xEC21 ; ENA_LLQ_VF
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dw 0x0000
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%endif
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; Realtek 816x/811x Gigabit Ethernet
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;dw 0x8169 ; Driver ID
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;dw 0x10EC ; Vendor ID

‎src/drivers/net/ena.asm‎

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@@ -0,0 +1,256 @@
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; =============================================================================
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; BareMetal -- a 64-bit OS written in Assembly for x86-64 systems
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; Copyright (C) 2008-2025 Return Infinity -- see LICENSE.TXT
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;
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; Elastic Network Adapter Driver
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; =============================================================================
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; -----------------------------------------------------------------------------
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; Initialize an ENA NIC
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; IN: RDX = Packed Bus address (as per syscalls/bus.asm)
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net_ena_init:
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push rdi
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push rsi
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push rdx
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push rcx
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push rax
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mov rdi, net_table
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xor eax, eax
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mov al, [os_net_icount]
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shl eax, 7 ; Quick multiply by 128
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add rdi, rax
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mov ax, 0x0EC2 ; Driver tag for ena
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mov [rdi+nt_ID], ax
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; Get the Base Memory Address of the device
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mov al, 0 ; Read BAR0
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call os_bus_read_bar
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mov [rdi+nt_base], rax ; Save the base
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push rax ; Save the base for gathering the MAC later
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; Set PCI Status/Command values
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mov dl, 0x01 ; Read Status/Command
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call os_bus_read
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bts eax, 10 ; Set Interrupt Disable
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bts eax, 2 ; Enable Bus Master
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bts eax, 1 ; Enable Memory Space
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call os_bus_write ; Write updated Status/Command
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; Usually the MAC would be read from the device MMIO here but ENA works differently
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; Set base addresses for TX and RX descriptors
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xor ecx, ecx
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mov cl, byte [os_net_icount]
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shl ecx, 15
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mov rax, os_tx_desc
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add rax, rcx
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mov [rdi+nt_tx_desc], rax
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mov rax, os_rx_desc
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add rax, rcx
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mov [rdi+nt_rx_desc], rax
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; Reset the device
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xor edx, edx
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mov dl, [os_net_icount]
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call net_ena_reset
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; Store call addresses
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mov rax, net_ena_config
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mov [rdi+nt_config], rax
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mov rax, net_ena_transmit
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mov [rdi+nt_transmit], rax
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mov rax, net_ena_poll
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mov [rdi+nt_poll], rax
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net_ena_init_error:
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pop rax
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pop rcx
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pop rdx
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pop rsi
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pop rdi
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ret
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; net_ena_reset - Reset an ENA NIC
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; IN: RDX = Interface ID
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; OUT: Nothing, all registers preserved
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net_ena_reset:
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push rdi
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push rsi
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push rax
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; Gather Base Address from net_table
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mov rsi, net_table
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xor eax, eax
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mov al, [os_net_icount]
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shl eax, 7 ; Quick multiply by 128
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add rsi, rax
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add rsi, 16
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mov rsi, [rsi]
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mov rdi, rsi
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; Stop queues if they are running
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; Check ENA_DEV_STS.READY
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mov eax, [rsi+ENA_DEV_STS]
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test eax, 1
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; poll bit with timeout
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; Check versions
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mov eax, [rsi+ENA_VERSION]
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mov eax, [rsi+ENA_CONTROLLER_VERSION]
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; Check capabilities
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mov eax, [rsi+ENA_CAPS]
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mov eax, [rsi+ENA_CAPS_EXT]
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; Set device memory
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mov rax, 0x600000
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mov [rsi+ENA_AQ_BASE_LO], eax
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shr rax, 32
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mov [rsi+ENA_AQ_BASE_HI], eax
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mov rax, 0x610000
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mov [rsi+ENA_ACQ_BASE_LO], eax
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shr rax, 32
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mov [rsi+ENA_ACQ_BASE_HI], eax
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mov rax, 0x620000
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mov [rsi+ENA_AENQ_BASE_LO], eax
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shr rax, 32
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mov [rsi+ENA_AENQ_BASE_HI], eax
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; Create Admin Queue
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; Admin Submission Queue (AQ)
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; Admin Completion Queue (ACQ)
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; Check ENA_DEV_STS.READY
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; Build an Admin command
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; opcode ENA_ADMIN_GET_FEATURE = 0x0009
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; feat_id ENA_ADMIN_DEVICE_ATTRIBUTES = 1
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; Put it in the queue
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; Wait for completion
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; Check head has changed
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; Verify command
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; Verify status (ENA_ADMIN_SUCCESS)
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; MAC Address at offset 0x0 of returned data
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pop rax
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pop rsi
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pop rdi
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ret
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; net_ena_config -
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; IN: RAX = Base address to store packets
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; RDX = Interface ID
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; OUT: Nothing
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net_ena_config:
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push rdi
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push rcx
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push rax
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pop rax
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pop rcx
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pop rdi
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ret
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; net_ena_transmit - Transmit a packet via an ENA NIC
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; IN: RSI = Location of packet
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; RDX = Interface ID
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; RCX = Length of packet
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; OUT: Nothing
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net_ena_transmit:
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push rdi
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push rbx
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push rax
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mov rdi, [rdx+nt_tx_desc] ; Transmit Descriptor Base Address
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pop rax
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pop rbx
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pop rdi
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ret
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; net_ena_poll - Polls the ENA NIC for a received packet
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; IN: RDX = Interface ID
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; OUT: RDI = Location of stored packet
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; RCX = Length of packet
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net_ena_poll:
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push rsi ; Used for the base MMIO of the NIC
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push rbx
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push rax
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mov rdi, [rdx+nt_rx_desc]
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mov rsi, [rdx+nt_base] ; Load the base MMIO of the NIC
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net_ena_poll_end:
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pop rax
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pop rbx
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pop rsi
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ret
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; -----------------------------------------------------------------------------
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; -----------------------------------------------------------------------------
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; net_ena_ack_int - Acknowledge an internal interrupt of the Intel 8254x NIC
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; IN: Nothing
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; OUT: RAX = Ethernet status
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;net_ena_ack_int:
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; push rdi
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;
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; pop rdi
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; ret
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; -----------------------------------------------------------------------------
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; Register list (All registers should be accessed as 32-bit values)
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; General Control Registers
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ENA_VERSION equ 0x00
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ENA_CONTROLLER_VERSION equ 0x04
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ENA_CAPS equ 0x08
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ENA_CAPS_EXT equ 0x0C
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ENA_AQ_BASE_LO equ 0x10
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ENA_AQ_BASE_HI equ 0x14
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ENA_AQ_CAPS equ 0x18
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ENA_ACQ_BASE_LO equ 0x20
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ENA_ACQ_BASE_HI equ 0x24
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ENA_ACQ_CAPS equ 0x28
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ENA_AQ_DB equ 0x2C
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ENA_ACQ_TAIL equ 0x30
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ENA_AENQ_CAPS equ 0x34
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ENA_AENQ_BASE_LO equ 0x38
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ENA_AENQ_BASE_HI equ 0x3C
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ENA_AENQ_HEAD_DB equ 0x40
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ENA_AENQ_TAIL equ 0x44
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ENA_INTR_MASK equ 0x4C
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ENA_DEV_CTL equ 0x54
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ENA_DEV_STS equ 0x58
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ENA_MMIO_REG_READ equ 0x5C
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ENA_MMIO_RESP_LO equ 0x60
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ENA_MMIO_RESP_HI equ 0x64
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ENA_RSS_IND_ENTRY_UPDATE equ 0x68
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; Register bits
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; =============================================================================
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; EOF

‎src/init/net.asm‎

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@@ -67,6 +67,11 @@ init_net_probe_found:
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cmp bx, 0x8259
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je init_net_probe_found_i8259x
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%endif
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%ifndef NO_ENA
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cmp bx, 0x0EC2
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je init_net_probe_found_ena
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%endif
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; cmp bx, 0x8169
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; je init_net_probe_found_r8169
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jmp init_net_probe_not_found
@@ -95,6 +100,12 @@ init_net_probe_found_i8259x:
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jmp init_net_probe_found_finish
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%endif
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%ifndef NO_ENA
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init_net_probe_found_ena:
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call net_ena_init
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jmp init_net_probe_found_finish
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%endif
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;init_net_probe_found_r8169:
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; call net_r8169_init
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; jmp init_net_probe_found_finish

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