Verified pending bit is set on receive

```
(qemu) xp /16bx 0xfebd1800
00000000febd1800: 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00
```

Author: Ian Seyler

src/drivers/msi.asm

@@ -23,6 +23,9 @@
 ; 00038411 <- Cap ID 0x11 (MSI-X), next ptr 0x84, message control 0x0003 - Table size is bits 10:0 so 3 (n-1 so table size is actually 4)
 ; 00000001 <- BIR (2:0) is 0x1 so BAR1, Table Offset (31:3) - 8-byte aligned so clear low 3 bits - 0x0 in this case
 ; 00000801 <- Pending Bit BIR (2:0) is 0x1 so BAR1 and Pending Bit Offset (31:3) is 0x800
+;
+; Resulting MSI-X table entry in memory should look similar to:
+; 0xXXXXXXXX: FEE00000 00000000 000040XX 00000000
 msix_init:
 	push r8
 	push rdi

src/drivers/net/virtio-net.asm

@@ -266,7 +266,7 @@ virtio_net_init_reset_wait:
 	; reading and possibly writing the device’s virtio configuration space
 	; population of virtqueues
 
-	mov ax, 0x0000
+	mov ax, 0xFFFF
 	mov [rsi+VIRTIO_CONFIG_MSIX_VECTOR], ax
 
 	; Set up Queue 0 (Receive)
@@ -290,9 +290,8 @@ virtio_net_init_reset_wait:
 	rol rax, 32
 	mov [rsi+VIRTIO_QUEUE_DEVICE+8], eax
 	rol rax, 32
-	mov ax, 0x0001
+	mov ax, 0x0000
 	mov [rsi+VIRTIO_QUEUE_MSIX_VECTOR], ax
-	mov ax, [rsi+VIRTIO_QUEUE_MSIX_VECTOR]
 	mov ax, 1
 	mov [rsi+VIRTIO_QUEUE_ENABLE], ax