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cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coord
The driver stores access_coordinate for host bridge in ->hb_coord and switch CDAT access_coordinate in ->sw_coord. Since neither of these access_coordinate clobber each other, the variable name can be consolidated into ->coord to simplify the code. Reviewed-by: Jonathan Cameron <[email protected]> Reviewed-by: Davidlohr Bueso <[email protected]> Reviewed-by: Dan Williams <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dave Jiang <[email protected]>
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6 files changed

+94
-48
lines changed

6 files changed

+94
-48
lines changed

‎drivers/cxl/acpi.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -529,7 +529,7 @@ static int get_genport_coordinates(struct device *dev, struct cxl_dport *dport)
529529
if (kstrtou32(acpi_device_uid(hb), 0, &uid))
530530
return -EINVAL;
531531

532-
return acpi_get_genport_coordinates(uid, dport->hb_coord);
532+
return acpi_get_genport_coordinates(uid, dport->coord);
533533
}
534534

535535
static int add_host_bridge_dport(struct device *match, void *arg)

‎drivers/cxl/core/cdat.c

Lines changed: 47 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@
1414
struct dsmas_entry {
1515
struct range dpa_range;
1616
u8 handle;
17-
struct access_coordinate coord;
17+
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
1818

1919
int entries;
2020
int qos_class;
@@ -88,8 +88,8 @@ static int cdat_dsmas_handler(union acpi_subtable_headers *header, void *arg,
8888
return 0;
8989
}
9090

91-
static void cxl_access_coordinate_set(struct access_coordinate *coord,
92-
int access, unsigned int val)
91+
static void __cxl_access_coordinate_set(struct access_coordinate *coord,
92+
int access, unsigned int val)
9393
{
9494
switch (access) {
9595
case ACPI_HMAT_ACCESS_LATENCY:
@@ -115,6 +115,13 @@ static void cxl_access_coordinate_set(struct access_coordinate *coord,
115115
}
116116
}
117117

118+
static void cxl_access_coordinate_set(struct access_coordinate *coord,
119+
int access, unsigned int val)
120+
{
121+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++)
122+
__cxl_access_coordinate_set(&coord[i], access, val);
123+
}
124+
118125
static int cdat_dslbis_handler(union acpi_subtable_headers *header, void *arg,
119126
const unsigned long end)
120127
{
@@ -156,7 +163,7 @@ static int cdat_dslbis_handler(union acpi_subtable_headers *header, void *arg,
156163
val = cdat_normalize(le16_to_cpu(le_val), le64_to_cpu(le_base),
157164
dslbis->data_type);
158165

159-
cxl_access_coordinate_set(&dent->coord, dslbis->data_type, val);
166+
cxl_access_coordinate_set(dent->coord, dslbis->data_type, val);
160167

161168
return 0;
162169
}
@@ -190,13 +197,13 @@ static int cxl_cdat_endpoint_process(struct cxl_port *port,
190197
static int cxl_port_perf_data_calculate(struct cxl_port *port,
191198
struct xarray *dsmas_xa)
192199
{
193-
struct access_coordinate ep_c;
200+
struct access_coordinate ep_c[ACCESS_COORDINATE_MAX];
194201
struct dsmas_entry *dent;
195202
int valid_entries = 0;
196203
unsigned long index;
197204
int rc;
198205

199-
rc = cxl_endpoint_get_perf_coordinates(port, &ep_c);
206+
rc = cxl_endpoint_get_perf_coordinates(port, ep_c);
200207
if (rc) {
201208
dev_dbg(&port->dev, "Failed to retrieve ep perf coordinates.\n");
202209
return rc;
@@ -213,10 +220,11 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
213220
xa_for_each(dsmas_xa, index, dent) {
214221
int qos_class;
215222

216-
cxl_coordinates_combine(&dent->coord, &dent->coord, &ep_c);
223+
cxl_coordinates_combine(dent->coord, dent->coord, ep_c);
217224
dent->entries = 1;
218-
rc = cxl_root->ops->qos_class(cxl_root, &dent->coord, 1,
219-
&qos_class);
225+
rc = cxl_root->ops->qos_class(cxl_root,
226+
&dent->coord[ACCESS_COORDINATE_CPU],
227+
1, &qos_class);
220228
if (rc != 1)
221229
continue;
222230

@@ -233,14 +241,17 @@ static int cxl_port_perf_data_calculate(struct cxl_port *port,
233241
static void update_perf_entry(struct device *dev, struct dsmas_entry *dent,
234242
struct cxl_dpa_perf *dpa_perf)
235243
{
244+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++)
245+
dpa_perf->coord[i] = dent->coord[i];
236246
dpa_perf->dpa_range = dent->dpa_range;
237-
dpa_perf->coord = dent->coord;
238247
dpa_perf->qos_class = dent->qos_class;
239248
dev_dbg(dev,
240249
"DSMAS: dpa: %#llx qos: %d read_bw: %d write_bw %d read_lat: %d write_lat: %d\n",
241250
dent->dpa_range.start, dpa_perf->qos_class,
242-
dent->coord.read_bandwidth, dent->coord.write_bandwidth,
243-
dent->coord.read_latency, dent->coord.write_latency);
251+
dent->coord[ACCESS_COORDINATE_CPU].read_bandwidth,
252+
dent->coord[ACCESS_COORDINATE_CPU].write_bandwidth,
253+
dent->coord[ACCESS_COORDINATE_CPU].read_latency,
254+
dent->coord[ACCESS_COORDINATE_CPU].write_latency);
244255
}
245256

246257
static void cxl_memdev_set_qos_class(struct cxl_dev_state *cxlds,
@@ -477,10 +488,11 @@ static int cdat_sslbis_handler(union acpi_subtable_headers *header, void *arg,
477488

478489
xa_for_each(&port->dports, index, dport) {
479490
if (dsp_id == ACPI_CDAT_SSLBIS_ANY_PORT ||
480-
dsp_id == dport->port_id)
481-
cxl_access_coordinate_set(&dport->sw_coord,
491+
dsp_id == dport->port_id) {
492+
cxl_access_coordinate_set(dport->coord,
482493
sslbis->data_type,
483494
val);
495+
}
484496
}
485497
}
486498

@@ -502,6 +514,21 @@ void cxl_switch_parse_cdat(struct cxl_port *port)
502514
}
503515
EXPORT_SYMBOL_NS_GPL(cxl_switch_parse_cdat, CXL);
504516

517+
static void __cxl_coordinates_combine(struct access_coordinate *out,
518+
struct access_coordinate *c1,
519+
struct access_coordinate *c2)
520+
{
521+
if (c1->write_bandwidth && c2->write_bandwidth)
522+
out->write_bandwidth = min(c1->write_bandwidth,
523+
c2->write_bandwidth);
524+
out->write_latency = c1->write_latency + c2->write_latency;
525+
526+
if (c1->read_bandwidth && c2->read_bandwidth)
527+
out->read_bandwidth = min(c1->read_bandwidth,
528+
c2->read_bandwidth);
529+
out->read_latency = c1->read_latency + c2->read_latency;
530+
}
531+
505532
/**
506533
* cxl_coordinates_combine - Combine the two input coordinates
507534
*
@@ -513,15 +540,8 @@ void cxl_coordinates_combine(struct access_coordinate *out,
513540
struct access_coordinate *c1,
514541
struct access_coordinate *c2)
515542
{
516-
if (c1->write_bandwidth && c2->write_bandwidth)
517-
out->write_bandwidth = min(c1->write_bandwidth,
518-
c2->write_bandwidth);
519-
out->write_latency = c1->write_latency + c2->write_latency;
520-
521-
if (c1->read_bandwidth && c2->read_bandwidth)
522-
out->read_bandwidth = min(c1->read_bandwidth,
523-
c2->read_bandwidth);
524-
out->read_latency = c1->read_latency + c2->read_latency;
543+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++)
544+
__cxl_coordinates_combine(&out[i], &c1[i], &c2[i]);
525545
}
526546

527547
MODULE_IMPORT_NS(CXL);
@@ -558,12 +578,12 @@ void cxl_region_perf_data_calculate(struct cxl_region *cxlr,
558578
/* Get total bandwidth and the worst latency for the cxl region */
559579
cxlr->coord[i].read_latency = max_t(unsigned int,
560580
cxlr->coord[i].read_latency,
561-
perf->coord.read_latency);
581+
perf->coord[i].read_latency);
562582
cxlr->coord[i].write_latency = max_t(unsigned int,
563583
cxlr->coord[i].write_latency,
564-
perf->coord.write_latency);
565-
cxlr->coord[i].read_bandwidth += perf->coord.read_bandwidth;
566-
cxlr->coord[i].write_bandwidth += perf->coord.write_bandwidth;
584+
perf->coord[i].write_latency);
585+
cxlr->coord[i].read_bandwidth += perf->coord[i].read_bandwidth;
586+
cxlr->coord[i].write_bandwidth += perf->coord[i].write_bandwidth;
567587
}
568588
}
569589

‎drivers/cxl/core/port.c

Lines changed: 37 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2133,6 +2133,29 @@ bool schedule_cxl_memdev_detach(struct cxl_memdev *cxlmd)
21332133
}
21342134
EXPORT_SYMBOL_NS_GPL(schedule_cxl_memdev_detach, CXL);
21352135

2136+
static void add_latency(struct access_coordinate *c, long latency)
2137+
{
2138+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
2139+
c[i].write_latency += latency;
2140+
c[i].read_latency += latency;
2141+
}
2142+
}
2143+
2144+
static void set_min_bandwidth(struct access_coordinate *c, unsigned int bw)
2145+
{
2146+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
2147+
c[i].write_bandwidth = min(c[i].write_bandwidth, bw);
2148+
c[i].read_bandwidth = min(c[i].read_bandwidth, bw);
2149+
}
2150+
}
2151+
2152+
static void set_access_coordinates(struct access_coordinate *out,
2153+
struct access_coordinate *in)
2154+
{
2155+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++)
2156+
out[i] = in[i];
2157+
}
2158+
21362159
static bool parent_port_is_cxl_root(struct cxl_port *port)
21372160
{
21382161
return is_cxl_root(to_cxl_port(port->dev.parent));
@@ -2149,9 +2172,15 @@ static bool parent_port_is_cxl_root(struct cxl_port *port)
21492172
int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
21502173
struct access_coordinate *coord)
21512174
{
2152-
struct access_coordinate c = {
2153-
.read_bandwidth = UINT_MAX,
2154-
.write_bandwidth = UINT_MAX,
2175+
struct access_coordinate c[] = {
2176+
{
2177+
.read_bandwidth = UINT_MAX,
2178+
.write_bandwidth = UINT_MAX,
2179+
},
2180+
{
2181+
.read_bandwidth = UINT_MAX,
2182+
.write_bandwidth = UINT_MAX,
2183+
},
21552184
};
21562185
struct cxl_port *iter = port;
21572186
struct cxl_dport *dport;
@@ -2178,14 +2207,13 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
21782207
* have CDAT and therefore needs to be skipped.
21792208
*/
21802209
if (!is_cxl_root)
2181-
cxl_coordinates_combine(&c, &c, &dport->sw_coord);
2182-
c.write_latency += dport->link_latency;
2183-
c.read_latency += dport->link_latency;
2210+
cxl_coordinates_combine(c, c, dport->coord);
2211+
add_latency(c, dport->link_latency);
21842212
} while (!is_cxl_root);
21852213

21862214
dport = iter->parent_dport;
21872215
/* Retrieve HB coords */
2188-
cxl_coordinates_combine(&c, &c, dport->hb_coord);
2216+
cxl_coordinates_combine(c, c, dport->coord);
21892217

21902218
/* Get the calculated PCI paths bandwidth */
21912219
pdev = to_pci_dev(port->uport_dev->parent);
@@ -2194,10 +2222,8 @@ int cxl_endpoint_get_perf_coordinates(struct cxl_port *port,
21942222
return -ENXIO;
21952223
bw /= BITS_PER_BYTE;
21962224

2197-
c.write_bandwidth = min(c.write_bandwidth, bw);
2198-
c.read_bandwidth = min(c.read_bandwidth, bw);
2199-
2200-
*coord = c;
2225+
set_min_bandwidth(c, bw);
2226+
set_access_coordinates(coord, c);
22012227

22022228
return 0;
22032229
}

‎drivers/cxl/cxl.h

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -663,8 +663,7 @@ struct cxl_rcrb_info {
663663
* @rch: Indicate whether this dport was enumerated in RCH or VH mode
664664
* @port: reference to cxl_port that contains this downstream port
665665
* @regs: Dport parsed register blocks
666-
* @sw_coord: access coordinates (performance) for switch from CDAT
667-
* @hb_coord: access coordinates (performance) from ACPI generic port (host bridge)
666+
* @coord: access coordinates (bandwidth and latency performance attributes)
668667
* @link_latency: calculated PCIe downstream latency
669668
*/
670669
struct cxl_dport {
@@ -675,8 +674,7 @@ struct cxl_dport {
675674
bool rch;
676675
struct cxl_port *port;
677676
struct cxl_regs regs;
678-
struct access_coordinate sw_coord;
679-
struct access_coordinate hb_coord[ACCESS_COORDINATE_MAX];
677+
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
680678
long link_latency;
681679
};
682680

‎drivers/cxl/cxlmem.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -401,7 +401,7 @@ enum cxl_devtype {
401401
*/
402402
struct cxl_dpa_perf {
403403
struct range dpa_range;
404-
struct access_coordinate coord;
404+
struct access_coordinate coord[ACCESS_COORDINATE_MAX];
405405
int qos_class;
406406
};
407407

‎tools/testing/cxl/test/cxl.c

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -986,10 +986,12 @@ static void dpa_perf_setup(struct cxl_port *endpoint, struct range *range,
986986
{
987987
dpa_perf->qos_class = FAKE_QTG_ID;
988988
dpa_perf->dpa_range = *range;
989-
dpa_perf->coord.read_latency = 500;
990-
dpa_perf->coord.write_latency = 500;
991-
dpa_perf->coord.read_bandwidth = 1000;
992-
dpa_perf->coord.write_bandwidth = 1000;
989+
for (int i = 0; i < ACCESS_COORDINATE_MAX; i++) {
990+
dpa_perf->coord[i].read_latency = 500;
991+
dpa_perf->coord[i].write_latency = 500;
992+
dpa_perf->coord[i].read_bandwidth = 1000;
993+
dpa_perf->coord[i].write_bandwidth = 1000;
994+
}
993995
}
994996

995997
static void mock_cxl_endpoint_parse_cdat(struct cxl_port *port)

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