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VDavid003krzk
VDavid003
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krzk
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clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS
Exynos7885 SoC has a DWC3 USB Controller with Exynos USB PHY which in theory supports USB3 SuperSpeed, but is only used as USB2 in all known devices. These clocks are needed for everything related to USB. While at it, also remove the CLK_SET_RATE_PARENT capability of CLK_MOUT_FSYS_USB30DRD_USER, since it's not actually needed. Signed-off-by: David Virag <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
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‎drivers/clk/samsung/clk-exynos7885.c

Lines changed: 57 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
#define CLKS_NR_TOP (CLK_MOUT_SHARED1_PLL + 1)
2121
#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
2222
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
23-
#define CLKS_NR_FSYS (CLK_MOUT_FSYS_USB30DRD_USER + 1)
23+
#define CLKS_NR_FSYS (CLK_FSYS_USB30DRD_REF_CLK + 1)
2424

2525
/* ---- CMU_TOP ------------------------------------------------------------- */
2626

@@ -686,30 +686,56 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
686686
/* ---- CMU_FSYS ------------------------------------------------------------ */
687687

688688
/* Register Offset definitions for CMU_FSYS (0x13400000) */
689-
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
690-
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
691-
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
692-
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
693-
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
694-
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
695-
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
696-
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
697-
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
698-
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
699-
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
689+
#define PLL_LOCKTIME_PLL_USB 0x0000
690+
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
691+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
692+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
693+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
694+
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
695+
#define PLL_CON0_PLL_USB 0x01a0
696+
#define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE 0x200c
697+
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
698+
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
699+
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
700+
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
701+
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
702+
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
703+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL 0x2068
704+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0 0x206c
705+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1 0x2070
706+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY 0x2074
707+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK 0x2078
700708

701709
static const unsigned long fsys_clk_regs[] __initconst = {
710+
PLL_LOCKTIME_PLL_USB,
702711
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
703712
PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
704713
PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
705714
PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
706715
PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
716+
PLL_CON0_PLL_USB,
717+
CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE,
707718
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
708719
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
709720
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
710721
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
711722
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
712723
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
724+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL,
725+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0,
726+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1,
727+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY,
728+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK,
729+
};
730+
731+
static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {
732+
PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),
733+
};
734+
735+
static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
736+
PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
737+
PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
738+
pll_usb_rate_table),
713739
};
714740

715741
/* List of parent clocks for Muxes in CMU_FSYS */
@@ -718,6 +744,7 @@ PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
718744
PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
719745
PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
720746
PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
747+
PNAME(mout_usb_pll_p) = { "oscclk", "fout_usb_pll" };
721748

722749
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
723750
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
@@ -731,12 +758,16 @@ static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
731758
MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
732759
mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
733760
4, 1, CLK_SET_RATE_PARENT, 0),
734-
MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
761+
MUX(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
735762
mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
736-
4, 1, CLK_SET_RATE_PARENT, 0),
763+
4, 1),
764+
nMUX_F(CLK_MOUT_USB_PLL, "mout_usb_pll", mout_usb_pll_p,
765+
PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),
737766
};
738767

739768
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
769+
GATE(CLK_FSYS_USB20PHY_CLKCORE, "clk_fsys_usb20phy_clkcore", "mout_usb_pll",
770+
CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),
740771
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
741772
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
742773
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
@@ -752,9 +783,21 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
752783
GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
753784
"mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
754785
21, CLK_SET_RATE_PARENT, 0),
786+
GATE(CLK_FSYS_USB30DRD_ACLK_20PHYCTRL, "clk_fsys_usb30drd_aclk_20phyctrl",
787+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),
788+
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0, "clk_fsys_usb30drd_aclk_30phyctrl_0",
789+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),
790+
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1, "clk_fsys_usb30drd_aclk_30phyctrl_1",
791+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),
792+
GATE(CLK_FSYS_USB30DRD_BUS_CLK_EARLY, "clk_fsys_usb30drd_bus_clk_early",
793+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),
794+
GATE(CLK_FSYS_USB30DRD_REF_CLK, "clk_fsys_usb30drd_ref_clk", "mout_fsys_usb30drd_user",
795+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),
755796
};
756797

757798
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
799+
.pll_clks = fsys_pll_clks,
800+
.nr_pll_clks = ARRAY_SIZE(fsys_pll_clks),
758801
.mux_clks = fsys_mux_clks,
759802
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
760803
.gate_clks = fsys_gate_clks,

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