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mmc: sdhci-of-dwcmshc: Add support for Sophgo CV1800B and SG2002
Add support for the mmc controller in the Sophgo CV1800B and SG2002 with corresponding new compatible strings. Implement custom sdhci_ops. Signed-off-by: Jisheng Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
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drivers/mmc/host/sdhci-of-dwcmshc.c

Lines changed: 66 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,20 @@
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#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */
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#define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */
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/* Sophgo CV18XX specific Registers */
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#define CV18XX_SDHCI_MSHC_CTRL 0x00
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#define CV18XX_EMMC_FUNC_EN BIT(0)
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#define CV18XX_LATANCY_1T BIT(1)
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#define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40
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#define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0)
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#define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8)
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#define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1
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#define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16)
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#define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24)
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#define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1
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#define CV18XX_SDHCI_PHY_CONFIG 0x4c
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#define CV18XX_PHY_TX_BPS BIT(0)
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/* Rockchip specific Registers */
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#define DWCMSHC_EMMC_DLL_CTRL 0x800
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#define DWCMSHC_EMMC_DLL_RXCLK 0x804
@@ -642,6 +656,35 @@ static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
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}
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}
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static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
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sdhci_reset(host, mask);
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if ((host->mmc->caps2 & emmc_caps) == emmc_caps) {
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val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
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val |= CV18XX_EMMC_FUNC_EN;
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sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
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}
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val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
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val |= CV18XX_LATANCY_1T;
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sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL);
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val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
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val |= CV18XX_PHY_TX_BPS;
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sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG);
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val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) |
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FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) |
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FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) |
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FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK));
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sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY);
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}
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static const struct sdhci_ops sdhci_dwcmshc_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
@@ -671,6 +714,15 @@ static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
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.platform_execute_tuning = &th1520_execute_tuning,
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};
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static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = dwcmshc_set_uhs_signaling,
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.get_max_clock = dwcmshc_get_max_clock,
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.reset = cv18xx_sdhci_reset,
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.adma_write_desc = dwcmshc_adma_write_desc,
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};
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static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
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.ops = &sdhci_dwcmshc_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
@@ -700,6 +752,12 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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};
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static const struct sdhci_pltfm_data sdhci_dwcmshc_cv18xx_pdata = {
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.ops = &sdhci_dwcmshc_cv18xx_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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};
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static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
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{
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int err;
@@ -768,6 +826,14 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
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.compatible = "snps,dwcmshc-sdhci",
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.data = &sdhci_dwcmshc_pdata,
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},
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{
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.compatible = "sophgo,cv1800b-dwcmshc",
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.data = &sdhci_dwcmshc_cv18xx_pdata,
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},
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{
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.compatible = "sophgo,sg2002-dwcmshc",
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.data = &sdhci_dwcmshc_cv18xx_pdata,
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},
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{
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.compatible = "thead,th1520-dwcmshc",
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.data = &sdhci_dwcmshc_th1520_pdata,

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