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52 | 52 | #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */
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53 | 53 | #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */
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54 | 54 |
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| 55 | +/* Sophgo CV18XX specific Registers */ |
| 56 | +#define CV18XX_SDHCI_MSHC_CTRL 0x00 |
| 57 | +#define CV18XX_EMMC_FUNC_EN BIT(0) |
| 58 | +#define CV18XX_LATANCY_1T BIT(1) |
| 59 | +#define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40 |
| 60 | +#define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0) |
| 61 | +#define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8) |
| 62 | +#define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1 |
| 63 | +#define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16) |
| 64 | +#define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24) |
| 65 | +#define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1 |
| 66 | +#define CV18XX_SDHCI_PHY_CONFIG 0x4c |
| 67 | +#define CV18XX_PHY_TX_BPS BIT(0) |
| 68 | + |
55 | 69 | /* Rockchip specific Registers */
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56 | 70 | #define DWCMSHC_EMMC_DLL_CTRL 0x800
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57 | 71 | #define DWCMSHC_EMMC_DLL_RXCLK 0x804
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@@ -642,6 +656,35 @@ static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask)
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642 | 656 | }
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643 | 657 | }
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644 | 658 |
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| 659 | +static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) |
| 660 | +{ |
| 661 | + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); |
| 662 | + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); |
| 663 | + u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; |
| 664 | + |
| 665 | + sdhci_reset(host, mask); |
| 666 | + |
| 667 | + if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { |
| 668 | + val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); |
| 669 | + val |= CV18XX_EMMC_FUNC_EN; |
| 670 | + sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); |
| 671 | + } |
| 672 | + |
| 673 | + val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); |
| 674 | + val |= CV18XX_LATANCY_1T; |
| 675 | + sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); |
| 676 | + |
| 677 | + val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); |
| 678 | + val |= CV18XX_PHY_TX_BPS; |
| 679 | + sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); |
| 680 | + |
| 681 | + val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | |
| 682 | + FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | |
| 683 | + FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) | |
| 684 | + FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK)); |
| 685 | + sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); |
| 686 | +} |
| 687 | + |
645 | 688 | static const struct sdhci_ops sdhci_dwcmshc_ops = {
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646 | 689 | .set_clock = sdhci_set_clock,
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647 | 690 | .set_bus_width = sdhci_set_bus_width,
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@@ -671,6 +714,15 @@ static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = {
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671 | 714 | .platform_execute_tuning = &th1520_execute_tuning,
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672 | 715 | };
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673 | 716 |
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| 717 | +static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { |
| 718 | + .set_clock = sdhci_set_clock, |
| 719 | + .set_bus_width = sdhci_set_bus_width, |
| 720 | + .set_uhs_signaling = dwcmshc_set_uhs_signaling, |
| 721 | + .get_max_clock = dwcmshc_get_max_clock, |
| 722 | + .reset = cv18xx_sdhci_reset, |
| 723 | + .adma_write_desc = dwcmshc_adma_write_desc, |
| 724 | +}; |
| 725 | + |
674 | 726 | static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
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675 | 727 | .ops = &sdhci_dwcmshc_ops,
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676 | 728 | .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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@@ -700,6 +752,12 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = {
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700 | 752 | .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
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701 | 753 | };
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702 | 754 |
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| 755 | +static const struct sdhci_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { |
| 756 | + .ops = &sdhci_dwcmshc_cv18xx_ops, |
| 757 | + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, |
| 758 | + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, |
| 759 | +}; |
| 760 | + |
703 | 761 | static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv)
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704 | 762 | {
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705 | 763 | int err;
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@@ -768,6 +826,14 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
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768 | 826 | .compatible = "snps,dwcmshc-sdhci",
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769 | 827 | .data = &sdhci_dwcmshc_pdata,
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770 | 828 | },
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| 829 | + { |
| 830 | + .compatible = "sophgo,cv1800b-dwcmshc", |
| 831 | + .data = &sdhci_dwcmshc_cv18xx_pdata, |
| 832 | + }, |
| 833 | + { |
| 834 | + .compatible = "sophgo,sg2002-dwcmshc", |
| 835 | + .data = &sdhci_dwcmshc_cv18xx_pdata, |
| 836 | + }, |
771 | 837 | {
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772 | 838 | .compatible = "thead,th1520-dwcmshc",
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773 | 839 | .data = &sdhci_dwcmshc_th1520_pdata,
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