@@ -4781,7 +4781,7 @@ static int gfx_v11_0_soft_reset(void *handle)
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int r , i , j , k ;
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struct amdgpu_device * adev = (struct amdgpu_device * )handle ;
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- gfx_v11_0_set_safe_mode (adev , 0 );
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+ amdgpu_gfx_rlc_enter_safe_mode (adev , 0 );
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tmp = RREG32_SOC15 (GC , 0 , regCP_INT_CNTL );
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tmp = REG_SET_FIELD (tmp , CP_INT_CNTL , CMP_BUSY_INT_ENABLE , 0 );
@@ -4900,7 +4900,7 @@ static int gfx_v11_0_soft_reset(void *handle)
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tmp = REG_SET_FIELD (tmp , CP_INT_CNTL , GFX_IDLE_INT_ENABLE , 1 );
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WREG32_SOC15 (GC , 0 , regCP_INT_CNTL , tmp );
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- gfx_v11_0_unset_safe_mode (adev , 0 );
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+ amdgpu_gfx_rlc_exit_safe_mode (adev , 0 );
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return gfx_v11_0_cp_resume (adev );
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}
@@ -6590,7 +6590,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
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if (amdgpu_sriov_vf (adev ))
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return - EINVAL ;
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- gfx_v11_0_set_safe_mode (adev , 0 );
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+ amdgpu_gfx_rlc_enter_safe_mode (adev , 0 );
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mutex_lock (& adev -> srbm_mutex );
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soc21_grbm_select (adev , ring -> me , ring -> pipe , ring -> queue , 0 );
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WREG32_SOC15 (GC , 0 , regCP_HQD_DEQUEUE_REQUEST , 0x2 );
@@ -6606,7 +6606,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid)
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r = - ETIMEDOUT ;
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soc21_grbm_select (adev , 0 , 0 , 0 , 0 );
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mutex_unlock (& adev -> srbm_mutex );
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- gfx_v11_0_unset_safe_mode (adev , 0 );
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+ amdgpu_gfx_rlc_exit_safe_mode (adev , 0 );
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if (r ) {
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dev_err (adev -> dev , "fail to wait on hqd deactivate\n" );
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return r ;
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