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Pratap Nirujogialexdeucher
Pratap Nirujogi
authored and
alexdeucher
committed
drm/amd/amdgpu: Map ISP interrupts as generic IRQs
Map ISP IH interrupts to Linux generic IRQ for ISP driver to handle the interrupts using MFD IORESOURCE_IRQ resource. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Pratap Nirujogi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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‎drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -466,7 +466,8 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev,
466466
} else if (src_id >= AMDGPU_MAX_IRQ_SRC_ID) {
467467
DRM_DEBUG("Invalid src_id in IV: %d\n", src_id);
468468

469-
} else if ((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) &&
469+
} else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) ||
470+
(client_id == SOC15_IH_CLIENTID_ISP)) &&
470471
adev->irq.virq[src_id]) {
471472
generic_handle_domain_irq(adev->irq.domain, src_id);
472473

‎drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c

Lines changed: 27 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,13 +31,26 @@
3131
#include "amdgpu.h"
3232
#include "amdgpu_isp.h"
3333

34+
#include "ivsrcid/isp/irqsrcs_isp_4_1.h"
35+
3436
#define mmDAGB0_WRCLI5_V4_1 0x6811C
3537
#define mmDAGB0_WRCLI9_V4_1 0x6812C
3638
#define mmDAGB0_WRCLI10_V4_1 0x68130
3739
#define mmDAGB0_WRCLI14_V4_1 0x68140
3840
#define mmDAGB0_WRCLI19_V4_1 0x68154
3941
#define mmDAGB0_WRCLI20_V4_1 0x68158
4042

43+
static const unsigned int isp_int_srcid[MAX_ISP_INT_SRC] = {
44+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9,
45+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10,
46+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11,
47+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12,
48+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13,
49+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14,
50+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15,
51+
ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16
52+
};
53+
4154
static int isp_sw_init(void *handle)
4255
{
4356
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
@@ -69,11 +82,12 @@ static int isp_sw_fini(void *handle)
6982
*/
7083
static int isp_hw_init(void *handle)
7184
{
72-
int r;
73-
u64 isp_base;
7485
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7586
const struct amdgpu_ip_block *ip_block =
7687
amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ISP);
88+
u64 isp_base;
89+
int int_idx;
90+
int r;
7791

7892
if (!ip_block)
7993
return -EINVAL;
@@ -90,7 +104,7 @@ static int isp_hw_init(void *handle)
90104
goto failure;
91105
}
92106

93-
adev->isp.isp_res = kcalloc(1, sizeof(struct resource), GFP_KERNEL);
107+
adev->isp.isp_res = kcalloc(9, sizeof(struct resource), GFP_KERNEL);
94108
if (!adev->isp.isp_res) {
95109
r = -ENOMEM;
96110
DRM_ERROR("%s: isp mfd res alloc failed\n", __func__);
@@ -114,8 +128,17 @@ static int isp_hw_init(void *handle)
114128
adev->isp.isp_res[0].start = isp_base;
115129
adev->isp.isp_res[0].end = isp_base + ISP_REGS_OFFSET_END;
116130

131+
for (int_idx = 0; int_idx < MAX_ISP_INT_SRC; int_idx++) {
132+
adev->isp.isp_res[int_idx + 1].name = "isp_irq";
133+
adev->isp.isp_res[int_idx + 1].flags = IORESOURCE_IRQ;
134+
adev->isp.isp_res[int_idx + 1].start =
135+
amdgpu_irq_create_mapping(adev, isp_int_srcid[int_idx]);
136+
adev->isp.isp_res[int_idx + 1].end =
137+
adev->isp.isp_res[int_idx + 1].start;
138+
}
139+
117140
adev->isp.isp_cell[0].name = "amd_isp_capture";
118-
adev->isp.isp_cell[0].num_resources = 1;
141+
adev->isp.isp_cell[0].num_resources = 9;
119142
adev->isp.isp_cell[0].resources = &adev->isp.isp_res[0];
120143
adev->isp.isp_cell[0].platform_data = adev->isp.isp_pdata;
121144
adev->isp.isp_cell[0].pdata_size = sizeof(struct isp_platform_data);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_isp.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -30,6 +30,8 @@
3030

3131
#define ISP_REGS_OFFSET_END 0x629A4
3232

33+
#define MAX_ISP_INT_SRC 8
34+
3335
struct isp_platform_data {
3436
void *adev;
3537
u32 asic_type;

‎drivers/gpu/drm/amd/amdgpu/ih_v6_1.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -535,6 +535,12 @@ static void ih_v6_1_set_self_irq_funcs(struct amdgpu_device *adev)
535535
static int ih_v6_1_early_init(void *handle)
536536
{
537537
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
538+
int ret;
539+
540+
ret = amdgpu_irq_add_domain(adev);
541+
if (ret) {
542+
return ret;
543+
}
538544

539545
ih_v6_1_set_interrupt_funcs(adev);
540546
ih_v6_1_set_self_irq_funcs(adev);

‎drivers/gpu/drm/amd/include/ivsrcid/isp/irqsrcs_isp_4_1.h

Lines changed: 62 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,62 @@
1+
/*
2+
* Copyright 2024 Advanced Micro Devices, Inc.
3+
*
4+
* Permission is hereby granted, free of charge, to any person obtaining a
5+
* copy of this software and associated documentation files (the "Software"),
6+
* to deal in the Software without restriction, including without limitation
7+
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
8+
* and/or sell copies of the Software, and to permit persons to whom the
9+
* Software is furnished to do so, subject to the following conditions:
10+
*
11+
* The above copyright notice and this permission notice shall be included in
12+
* all copies or substantial portions of the Software.
13+
*
14+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17+
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18+
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19+
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20+
* OTHER DEALINGS IN THE SOFTWARE.
21+
*
22+
*/
23+
#ifndef __IRQSRCS_ISP_4_1_H__
24+
#define __IRQSRCS_ISP_4_1_H__
25+
26+
27+
#define ISP_4_1__SRCID__ISP_SEMA_WAIT_FAIL_TIMEOUT 0x12 // Semaphore wait fail timeout
28+
#define ISP_4_1__SRCID__ISP_SEMA_WAIT_INCOMPLETE_TIMEOUT 0x13 // Semaphore wait incomplete timeout
29+
#define ISP_4_1__SRCID__ISP_SEMA_SIGNAL_INCOMPLETE_TIMEOUT 0x14 // Semaphore signal incomplete timeout
30+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE5_CHANGED 0x15 // Ringbuffer base5 address changed
31+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT5 0x16 // Ringbuffer write point 5 changed
32+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE6_CHANGED 0x17 // Ringbuffer base6 address changed
33+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT6 0x18 // Ringbuffer write point 6 changed
34+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE7_CHANGED 0x19 // Ringbuffer base7 address changed
35+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT7 0x1A // Ringbuffer write point 7 changed
36+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE8_CHANGED 0x1B // Ringbuffer base8 address changed
37+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT8 0x1C // Ringbuffer write point 8 changed
38+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE9_CHANGED 0x00 // Ringbuffer base9 address changed
39+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9 0x01 // Ringbuffer write point 9 changed
40+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE10_CHANGED 0x02 // Ringbuffer base10 address changed
41+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10 0x03 // Ringbuffer write point 10 changed
42+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE11_CHANGED 0x04 // Ringbuffer base11 address changed
43+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11 0x05 // Ringbuffer write point 11 changed
44+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE12_CHANGED 0x06 // Ringbuffer base12 address changed
45+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12 0x07 // Ringbuffer write point 12 changed
46+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE13_CHANGED 0x08 // Ringbuffer base13 address changed
47+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13 0x09 // Ringbuffer write point 13 changed
48+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE14_CHANGED 0x0A // Ringbuffer base14 address changed
49+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14 0x0B // Ringbuffer write point 14 changed
50+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE15_CHANGED 0x0C // Ringbuffer base15 address changed
51+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15 0x0D // Ringbuffer write point 15 changed
52+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_BASE16_CHANGED 0x0E // Ringbuffer base16 address changed
53+
#define ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16 0x0F // Ringbuffer write point 16 changed
54+
#define ISP_4_1__SRCID__ISP_MIPI0 0x29 // MIPI0 interrupt
55+
#define ISP_4_1__SRCID__ISP_MIPI1 0x2A // MIPI1 interrupt
56+
#define ISP_4_1__SRCID__ISP_I2C0 0x2B // I2C0 PAD interrupt
57+
#define ISP_4_1__SRCID__ISP_I2C1 0x2C // I2C1 PAD interrupt
58+
#define ISP_4_1__SRCID__ISP_FLASH0 0x2D // Flash0 interrupt
59+
#define ISP_4_1__SRCID__ISP_FLASH1 0x2E // Flash1 interrupt
60+
#define ISP_4_1__SRCID__ISP_DEBUG 0x2F // Debug information
61+
62+
#endif

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