|
109 | 109 | main_usbss0_pins_default: main_usbss0_pins_default {
|
110 | 110 | pinctrl-single,pins = <
|
111 | 111 | J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
|
| 112 | + J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */ |
112 | 113 | >;
|
113 | 114 | };
|
114 | 115 |
|
|
398 | 399 | status = "disabled";
|
399 | 400 | };
|
400 | 401 |
|
| 402 | +&usb_serdes_mux { |
| 403 | + idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */ |
| 404 | +}; |
| 405 | + |
| 406 | +&serdes_ln_ctrl { |
| 407 | + idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>, |
| 408 | + <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>, |
| 409 | + <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>, |
| 410 | + <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>, |
| 411 | + <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>; |
| 412 | +}; |
| 413 | + |
| 414 | +&serdes_wiz3 { |
| 415 | + typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>; |
| 416 | +}; |
| 417 | + |
| 418 | +&serdes3 { |
| 419 | + serdes3_usb_link: link@0 { |
| 420 | + reg = <0>; |
| 421 | + cdns,num-lanes = <2>; |
| 422 | + #phy-cells = <0>; |
| 423 | + cdns,phy-type = <PHY_TYPE_USB3>; |
| 424 | + resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>; |
| 425 | + }; |
| 426 | +}; |
| 427 | + |
401 | 428 | &usbss0 {
|
402 | 429 | pinctrl-names = "default";
|
403 | 430 | pinctrl-0 = <&main_usbss0_pins_default>;
|
404 |
| - ti,usb2-only; |
405 | 431 | ti,vbus-divider;
|
406 | 432 | };
|
407 | 433 |
|
408 | 434 | &usb0 {
|
409 | 435 | dr_mode = "otg";
|
410 |
| - maximum-speed = "high-speed"; |
| 436 | + maximum-speed = "super-speed"; |
| 437 | + phys = <&serdes3_usb_link>; |
| 438 | + phy-names = "cdns3,usb3-phy"; |
411 | 439 | };
|
412 | 440 |
|
413 | 441 | &usbss1 {
|
|
0 commit comments