|
2588 | 2588 | isp0: isp@fed00000 {
|
2589 | 2589 | compatible = "renesas,r8a779a0-isp",
|
2590 | 2590 | "renesas,rcar-gen4-isp";
|
2591 |
| - reg = <0 0xfed00000 0 0x10000>; |
2592 |
| - interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
2593 |
| - clocks = <&cpg CPG_MOD 612>; |
| 2591 | + reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>; |
| 2592 | + reg-names = "cs", "core"; |
| 2593 | + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, |
| 2594 | + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| 2595 | + interrupt-names = "cs", "core"; |
| 2596 | + clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>; |
| 2597 | + clock-names = "cs", "core"; |
2594 | 2598 | power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
2595 |
| - resets = <&cpg 612>; |
| 2599 | + resets = <&cpg 612>, <&cpg 16>; |
| 2600 | + reset-names = "cs", "core"; |
2596 | 2601 | status = "disabled";
|
2597 | 2602 |
|
| 2603 | + renesas,vspx = <&vspx0>; |
| 2604 | + |
2598 | 2605 | ports {
|
2599 | 2606 | #address-cells = <1>;
|
2600 | 2607 | #size-cells = <0>;
|
|
2672 | 2679 | isp1: isp@fed20000 {
|
2673 | 2680 | compatible = "renesas,r8a779a0-isp",
|
2674 | 2681 | "renesas,rcar-gen4-isp";
|
2675 |
| - reg = <0 0xfed20000 0 0x10000>; |
2676 |
| - interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
2677 |
| - clocks = <&cpg CPG_MOD 613>; |
| 2682 | + reg = <0 0xfed20000 0 0x10000>, <0 0xfee00000 0 0x100000>; |
| 2683 | + reg-names = "cs", "core"; |
| 2684 | + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, |
| 2685 | + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| 2686 | + interrupt-names = "cs", "core"; |
| 2687 | + clocks = <&cpg CPG_MOD 613>, <&cpg CPG_MOD 17>; |
| 2688 | + clock-names = "cs", "core"; |
2678 | 2689 | power-domains = <&sysc R8A779A0_PD_A3ISP01>;
|
2679 |
| - resets = <&cpg 613>; |
| 2690 | + resets = <&cpg 613>, <&cpg 17>; |
| 2691 | + reset-names = "cs", "core"; |
2680 | 2692 | status = "disabled";
|
2681 | 2693 |
|
| 2694 | + renesas,vspx = <&vspx1>; |
| 2695 | + |
2682 | 2696 | ports {
|
2683 | 2697 | #address-cells = <1>;
|
2684 | 2698 | #size-cells = <0>;
|
|
2756 | 2770 | isp2: isp@fed30000 {
|
2757 | 2771 | compatible = "renesas,r8a779a0-isp",
|
2758 | 2772 | "renesas,rcar-gen4-isp";
|
2759 |
| - reg = <0 0xfed30000 0 0x10000>; |
2760 |
| - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
2761 |
| - clocks = <&cpg CPG_MOD 614>; |
| 2773 | + reg = <0 0xfed30000 0 0x10000>, <0 0xfef00000 0 0x100000>; |
| 2774 | + reg-names = "cs", "core"; |
| 2775 | + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, |
| 2776 | + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
| 2777 | + interrupt-names = "cs", "core"; |
| 2778 | + clocks = <&cpg CPG_MOD 614>, <&cpg CPG_MOD 18>; |
| 2779 | + clock-names = "cs", "core"; |
2762 | 2780 | power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
2763 |
| - resets = <&cpg 614>; |
| 2781 | + resets = <&cpg 614>, <&cpg 18>; |
| 2782 | + reset-names = "cs", "core"; |
2764 | 2783 | status = "disabled";
|
2765 | 2784 |
|
| 2785 | + renesas,vspx = <&vspx2>; |
| 2786 | + |
2766 | 2787 | ports {
|
2767 | 2788 | #address-cells = <1>;
|
2768 | 2789 | #size-cells = <0>;
|
|
2840 | 2861 | isp3: isp@fed40000 {
|
2841 | 2862 | compatible = "renesas,r8a779a0-isp",
|
2842 | 2863 | "renesas,rcar-gen4-isp";
|
2843 |
| - reg = <0 0xfed40000 0 0x10000>; |
2844 |
| - interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
2845 |
| - clocks = <&cpg CPG_MOD 615>; |
| 2864 | + reg = <0 0xfed40000 0 0x10000>, <0 0xfe400000 0 0x100000>; |
| 2865 | + reg-names = "cs", "core"; |
| 2866 | + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, |
| 2867 | + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
| 2868 | + interrupt-names = "cs", "core"; |
| 2869 | + clocks = <&cpg CPG_MOD 615>, <&cpg CPG_MOD 19>; |
| 2870 | + clock-names = "cs", "core"; |
2846 | 2871 | power-domains = <&sysc R8A779A0_PD_A3ISP23>;
|
2847 |
| - resets = <&cpg 615>; |
| 2872 | + resets = <&cpg 615>, <&cpg 19>; |
| 2873 | + reset-names = "cs", "core"; |
2848 | 2874 | status = "disabled";
|
2849 | 2875 |
|
| 2876 | + renesas,vspx = <&vspx3>; |
| 2877 | + |
2850 | 2878 | ports {
|
2851 | 2879 | #address-cells = <1>;
|
2852 | 2880 | #size-cells = <0>;
|
|
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