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fltorobclark
flto
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robclark
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drm/msm/a6xx: update pdc/rscc GMU registers for A640/A650
Update the gmu_pdc registers for A640 and A650. Some of the RSCC registers on A650 are in a separate region. Note this also changes the address of these registers: RSCC_TCS1_DRV0_STATUS RSCC_TCS2_DRV0_STATUS RSCC_TCS3_DRV0_STATUS Based on the values in msm-4.14 and msm-4.19 kernels. v3: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Jordan Crouse <[email protected]> Signed-off-by: Rob Clark <[email protected]>
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-53
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3 files changed

+85
-53
lines changed

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c

Lines changed: 56 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -429,7 +429,7 @@ static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
429429
return ret;
430430
}
431431

432-
ret = gmu_poll_timeout(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
432+
ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
433433
!val, 100, 10000);
434434

435435
if (ret) {
@@ -455,7 +455,7 @@ static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
455455

456456
gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
457457

458-
ret = gmu_poll_timeout(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
458+
ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
459459
val, val & (1 << 16), 100, 10000);
460460
if (ret)
461461
DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
@@ -478,32 +478,48 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
478478
struct platform_device *pdev = to_platform_device(gmu->dev);
479479
void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
480480
void __iomem *seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
481+
uint32_t pdc_address_offset;
481482

482483
if (!pdcptr || !seqptr)
483484
goto err;
484485

486+
if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))
487+
pdc_address_offset = 0x30090;
488+
else if (adreno_is_a650(adreno_gpu))
489+
pdc_address_offset = 0x300a0;
490+
else
491+
pdc_address_offset = 0x30080;
492+
485493
/* Disable SDE clock gating */
486-
gmu_write(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
494+
gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
487495

488496
/* Setup RSC PDC handshake for sleep and wakeup */
489-
gmu_write(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
490-
gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
491-
gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
492-
gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
493-
gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
494-
gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
495-
gmu_write(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
496-
gmu_write(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
497-
gmu_write(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
498-
gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
499-
gmu_write(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
497+
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
498+
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
499+
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
500+
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
501+
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
502+
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
503+
gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
504+
gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
505+
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
506+
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
507+
gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
500508

501509
/* Load RSC sequencer uCode for sleep and wakeup */
502-
gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
503-
gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
504-
gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
505-
gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
506-
gmu_write(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
510+
if (adreno_is_a650(adreno_gpu)) {
511+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
512+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
513+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
514+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
515+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
516+
} else {
517+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
518+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
519+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
520+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
521+
gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
522+
}
507523

508524
/* Load PDC sequencer uCode for power up and power down sequence */
509525
pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
@@ -524,10 +540,7 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
524540
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
525541

526542
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
527-
if (adreno_is_a618(adreno_gpu))
528-
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30090);
529-
else
530-
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, 0x30080);
543+
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
531544
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
532545

533546
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
@@ -539,17 +552,12 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
539552

540553
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
541554
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
542-
if (adreno_is_a618(adreno_gpu))
555+
if (adreno_is_a618(adreno_gpu) || adreno_is_a650(adreno_gpu))
543556
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
544557
else
545558
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
546-
547-
548559
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
549-
if (adreno_is_a618(adreno_gpu))
550-
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30090);
551-
else
552-
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, 0x30080);
560+
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
553561
pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
554562

555563
/* Setup GPU PDC */
@@ -796,13 +804,13 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
796804
u32 val;
797805

798806
/* Make sure there are no outstanding RPMh votes */
799-
gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
807+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
800808
(val & 1), 100, 10000);
801-
gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
809+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
802810
(val & 1), 100, 10000);
803-
gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
811+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
804812
(val & 1), 100, 10000);
805-
gmu_poll_timeout(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
813+
gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
806814
(val & 1), 100, 1000);
807815
}
808816

@@ -1361,6 +1369,7 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
13611369
void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
13621370
{
13631371
struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1372+
struct platform_device *pdev = to_platform_device(gmu->dev);
13641373

13651374
if (!gmu->initialized)
13661375
return;
@@ -1373,7 +1382,10 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
13731382
}
13741383

13751384
iounmap(gmu->mmio);
1385+
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1386+
iounmap(gmu->rscc);
13761387
gmu->mmio = NULL;
1388+
gmu->rscc = NULL;
13771389

13781390
a6xx_gmu_memory_free(gmu);
13791391

@@ -1456,6 +1468,14 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
14561468
goto err_memory;
14571469
}
14581470

1471+
if (adreno_is_a650(adreno_gpu)) {
1472+
gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1473+
if (IS_ERR(gmu->rscc))
1474+
goto err_mmio;
1475+
} else {
1476+
gmu->rscc = gmu->mmio + 0x23000;
1477+
}
1478+
14591479
/* Get the HFI and GMU interrupts */
14601480
gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
14611481
gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
@@ -1481,6 +1501,8 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
14811501

14821502
err_mmio:
14831503
iounmap(gmu->mmio);
1504+
if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1505+
iounmap(gmu->rscc);
14841506
free_irq(gmu->gmu_irq, gmu);
14851507
free_irq(gmu->hfi_irq, gmu);
14861508

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.h

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ struct a6xx_gmu {
4747
struct msm_gem_address_space *aspace;
4848

4949
void * __iomem mmio;
50+
void * __iomem rscc;
5051

5152
int hfi_irq;
5253
int gmu_irq;
@@ -125,6 +126,15 @@ static inline u64 gmu_read64(struct a6xx_gmu *gmu, u32 lo, u32 hi)
125126
readl_poll_timeout((gmu)->mmio + ((addr) << 2), val, cond, \
126127
interval, timeout)
127128

129+
static inline void gmu_write_rscc(struct a6xx_gmu *gmu, u32 offset, u32 value)
130+
{
131+
return msm_writel(value, gmu->rscc + (offset << 2));
132+
}
133+
134+
#define gmu_poll_timeout_rscc(gmu, addr, val, cond, interval, timeout) \
135+
readl_poll_timeout((gmu)->rscc + ((addr) << 2), val, cond, \
136+
interval, timeout)
137+
128138
/*
129139
* These are the available OOB (out of band requests) to the GMU where "out of
130140
* band" means that the CPU talks to the GMU directly and not through HFI.

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -336,8 +336,6 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
336336

337337
#define REG_A6XX_GMU_AO_SPARE_CNTL 0x00009316
338338

339-
#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00008c04
340-
341339
#define REG_A6XX_GMU_RSCC_CONTROL_REQ 0x00009307
342340

343341
#define REG_A6XX_GMU_RSCC_CONTROL_ACK 0x00009308
@@ -350,39 +348,41 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val)
350348

351349
#define REG_A6XX_GPU_CC_GX_DOMAIN_MISC 0x00009d42
352350

353-
#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00008c08
351+
#define REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0 0x00000004
352+
353+
#define REG_A6XX_RSCC_PDC_SEQ_START_ADDR 0x00000008
354354

355-
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00008c09
355+
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_LO 0x00000009
356356

357-
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x00008c0a
357+
#define REG_A6XX_RSCC_PDC_MATCH_VALUE_HI 0x0000000a
358358

359-
#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x00008c0b
359+
#define REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0 0x0000000b
360360

361-
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x00008c0d
361+
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR 0x0000000d
362362

363-
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x00008c0e
363+
#define REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA 0x0000000e
364364

365-
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00008c82
365+
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0 0x00000082
366366

367-
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00008c83
367+
#define REG_A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0 0x00000083
368368

369-
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00008c89
369+
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0 0x00000089
370370

371-
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x00008c8c
371+
#define REG_A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0 0x0000008c
372372

373-
#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00008d00
373+
#define REG_A6XX_RSCC_OVERRIDE_START_ADDR 0x00000100
374374

375-
#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00008d01
375+
#define REG_A6XX_RSCC_SEQ_BUSY_DRV0 0x00000101
376376

377-
#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00008d80
377+
#define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180
378378

379-
#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00008f46
379+
#define REG_A6XX_RSCC_TCS0_DRV0_STATUS 0x00000346
380380

381-
#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000090ae
381+
#define REG_A6XX_RSCC_TCS1_DRV0_STATUS 0x000003ee
382382

383-
#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00009216
383+
#define REG_A6XX_RSCC_TCS2_DRV0_STATUS 0x00000496
384384

385-
#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000937e
385+
#define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e
386386

387387

388388
#endif /* A6XX_GMU_XML */

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