drm/i915: Don't set PIPE_CONTROL_FLUSH_L3 for aux inval

PIPE_CONTROL_FLUSH_L3 is not needed for aux invalidation
so don't set that.

Fixes: ad8ebf1 ("drm/i915/gt: Ensure memory quiesced before invalidation")
Cc: Jonathan Cavitt <[email protected]>
Cc: Andi Shyti <[email protected]>
Cc: <[email protected]> # v5.8+
Cc: Andrzej Hajda <[email protected]>
Cc: Tvrtko Ursulin <[email protected]>
Cc: Matt Roper <[email protected]>
Cc: Tejas Upadhyay <[email protected]>
Cc: Lucas De Marchi <[email protected]>
Cc: Prathap Kumar Valsan <[email protected]>
Cc: Tapani Pälli <[email protected]>
Cc: Mark Janes <[email protected]>
Cc: Rodrigo Vivi <[email protected]>
Signed-off-by: Nirmoy Das <[email protected]>
Acked-by: Matt Roper <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Tested-by: Tapani Pälli <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]

Author: nirmoy

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

@@ -271,8 +271,17 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
 		if (GRAPHICS_VER_FULL(rq->i915) >= IP_VER(12, 70))
 			bit_group_0 |= PIPE_CONTROL_CCS_FLUSH;
 
+		/*
+		 * L3 fabric flush is needed for AUX CCS invalidation
+		 * which happens as part of pipe-control so we can
+		 * ignore PIPE_CONTROL_FLUSH_L3. Also PIPE_CONTROL_FLUSH_L3
+		 * deals with Protected Memory which is not needed for
+		 * AUX CCS invalidation and lead to unwanted side effects.
+		 */
+		if (mode & EMIT_FLUSH)
+			bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
+
 		bit_group_1 |= PIPE_CONTROL_TILE_CACHE_FLUSH;
-		bit_group_1 |= PIPE_CONTROL_FLUSH_L3;
 		bit_group_1 |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 		bit_group_1 |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 		/* Wa_1409600907:tgl,adl-p */